1 /* $NetBSD: pcscp.c,v 1.34 2005/12/11 12:22:50 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center; Izumi Tsutsui. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * pcscp.c: device dependent code for AMD Am53c974 (PCscsi-PCI) 42 * written by Izumi Tsutsui <tsutsui@ceres.dti.ne.jp> 43 * 44 * Technical manual available at 45 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/19113.pdf 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: pcscp.c,v 1.34 2005/12/11 12:22:50 christos Exp $"); 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/device.h> 54 #include <sys/buf.h> 55 56 #include <machine/bus.h> 57 #include <machine/intr.h> 58 59 #include <uvm/uvm_extern.h> 60 61 #include <dev/scsipi/scsipi_all.h> 62 #include <dev/scsipi/scsi_all.h> 63 #include <dev/scsipi/scsiconf.h> 64 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcivar.h> 67 #include <dev/pci/pcidevs.h> 68 69 #include <dev/ic/ncr53c9xreg.h> 70 #include <dev/ic/ncr53c9xvar.h> 71 72 #include <dev/pci/pcscpreg.h> 73 74 #define IO_MAP_REG 0x10 75 76 struct pcscp_softc { 77 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 78 79 bus_space_tag_t sc_st; /* bus space tag */ 80 bus_space_handle_t sc_sh; /* bus space handle */ 81 void *sc_ih; /* interrupt cookie */ 82 83 bus_dma_tag_t sc_dmat; /* DMA tag */ 84 85 bus_dmamap_t sc_xfermap; /* DMA map for transfers */ 86 87 uint32_t *sc_mdladdr; /* MDL array */ 88 bus_dmamap_t sc_mdldmap; /* MDL DMA map */ 89 90 int sc_active; /* DMA state */ 91 int sc_datain; /* DMA Data Direction */ 92 size_t sc_dmasize; /* DMA size */ 93 char **sc_dmaaddr; /* DMA address */ 94 size_t *sc_dmalen; /* DMA length */ 95 }; 96 97 #define READ_DMAREG(sc, reg) \ 98 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 99 #define WRITE_DMAREG(sc, reg, var) \ 100 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (var)) 101 102 #define PCSCP_READ_REG(sc, reg) \ 103 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2) 104 #define PCSCP_WRITE_REG(sc, reg, val) \ 105 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2, (val)) 106 107 /* 108 * Functions and the switch for the MI code. 109 */ 110 111 static u_char pcscp_read_reg(struct ncr53c9x_softc *, int); 112 static void pcscp_write_reg(struct ncr53c9x_softc *, int, u_char); 113 static int pcscp_dma_isintr(struct ncr53c9x_softc *); 114 static void pcscp_dma_reset(struct ncr53c9x_softc *); 115 static int pcscp_dma_intr(struct ncr53c9x_softc *); 116 static int pcscp_dma_setup(struct ncr53c9x_softc *, caddr_t *, size_t *, 117 int, size_t *); 118 static void pcscp_dma_go(struct ncr53c9x_softc *); 119 static void pcscp_dma_stop(struct ncr53c9x_softc *); 120 static int pcscp_dma_isactive(struct ncr53c9x_softc *); 121 122 static struct ncr53c9x_glue pcscp_glue = { 123 pcscp_read_reg, 124 pcscp_write_reg, 125 pcscp_dma_isintr, 126 pcscp_dma_reset, 127 pcscp_dma_intr, 128 pcscp_dma_setup, 129 pcscp_dma_go, 130 pcscp_dma_stop, 131 pcscp_dma_isactive, 132 NULL, /* gl_clear_latched_intr */ 133 }; 134 135 static int 136 pcscp_match(struct device *parent, struct cfdata *match, void *aux) 137 { 138 struct pci_attach_args *pa = aux; 139 140 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 141 return 0; 142 143 switch (PCI_PRODUCT(pa->pa_id)) { 144 case PCI_PRODUCT_AMD_PCSCSI_PCI: 145 return 1; 146 } 147 return 0; 148 } 149 150 /* 151 * Attach this instance, and then all the sub-devices 152 */ 153 static void 154 pcscp_attach(struct device *parent, struct device *self, void *aux) 155 { 156 struct pci_attach_args *pa = aux; 157 struct pcscp_softc *esc = (void *)self; 158 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 159 bus_space_tag_t iot; 160 bus_space_handle_t ioh; 161 pci_intr_handle_t ih; 162 const char *intrstr; 163 pcireg_t csr; 164 bus_dma_segment_t seg; 165 int error, rseg; 166 char devinfo[256]; 167 168 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 169 printf(": %s\n", devinfo); 170 printf("%s", sc->sc_dev.dv_xname); 171 172 if (pci_mapreg_map(pa, IO_MAP_REG, PCI_MAPREG_TYPE_IO, 0, 173 &iot, &ioh, NULL, NULL)) { 174 printf(": unable to map registers\n"); 175 return; 176 } 177 178 sc->sc_glue = &pcscp_glue; 179 180 esc->sc_st = iot; 181 esc->sc_sh = ioh; 182 esc->sc_dmat = pa->pa_dmat; 183 184 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 185 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 186 csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE); 187 188 /* 189 * XXX More of this should be in ncr53c9x_attach(), but 190 * XXX should we really poke around the chip that much in 191 * XXX the MI code? Think about this more... 192 */ 193 194 /* 195 * Set up static configuration info. 196 */ 197 198 /* 199 * XXX should read configuration from EEPROM? 200 * 201 * MI ncr53c9x driver does not support configuration 202 * per each target device, though... 203 */ 204 sc->sc_id = 7; 205 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 206 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 207 sc->sc_cfg3 = NCRAMDCFG3_IDM | NCRAMDCFG3_FCLK; 208 sc->sc_cfg4 = NCRAMDCFG4_GE12NS | NCRAMDCFG4_RADE; 209 sc->sc_rev = NCR_VARIANT_AM53C974; 210 sc->sc_features = NCR_F_FASTSCSI; 211 sc->sc_cfg3_fscsi = NCRAMDCFG3_FSCSI; 212 sc->sc_freq = 40; /* MHz */ 213 214 /* 215 * XXX minsync and maxxfer _should_ be set up in MI code, 216 * XXX but it appears to have some dependency on what sort 217 * XXX of DMA we're hooked up to, etc. 218 */ 219 220 /* 221 * This is the value used to start sync negotiations 222 * Note that the NCR register "SYNCTP" is programmed 223 * in "clocks per byte", and has a minimum value of 4. 224 * The SCSI period used in negotiation is one-fourth 225 * of the time (in nanoseconds) needed to transfer one byte. 226 * Since the chip's clock is given in MHz, we have the following 227 * formula: 4 * period = (1000 / freq) * 4 228 */ 229 230 sc->sc_minsync = 1000 / sc->sc_freq; 231 232 /* Really no limit, but since we want to fit into the TCR... */ 233 sc->sc_maxxfer = 16 * 1024 * 1024; 234 235 /* 236 * Create the DMA maps for the data transfers. 237 */ 238 239 #define MDL_SEG_SIZE 0x1000 /* 4kbyte per segment */ 240 #define MDL_SEG_OFFSET 0x0FFF 241 #define MDL_SIZE (MAXPHYS / MDL_SEG_SIZE + 1) /* no hardware limit? */ 242 243 if (bus_dmamap_create(esc->sc_dmat, MAXPHYS, MDL_SIZE, MDL_SEG_SIZE, 244 MDL_SEG_SIZE, BUS_DMA_NOWAIT, &esc->sc_xfermap)) { 245 printf(": can't create DMA maps\n"); 246 return; 247 } 248 249 /* 250 * Allocate and map memory for the MDL. 251 */ 252 253 if ((error = bus_dmamem_alloc(esc->sc_dmat, 254 sizeof(uint32_t) * MDL_SIZE, PAGE_SIZE, 0, &seg, 1, &rseg, 255 BUS_DMA_NOWAIT)) != 0) { 256 printf(": unable to allocate memory for the MDL, error = %d\n", 257 error); 258 return; 259 } 260 if ((error = bus_dmamem_map(esc->sc_dmat, &seg, rseg, 261 sizeof(uint32_t) * MDL_SIZE , (caddr_t *)&esc->sc_mdladdr, 262 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 263 printf(": unable to map the MDL memory, error = %d\n", error); 264 return; 265 } 266 if ((error = bus_dmamap_create(esc->sc_dmat, 267 sizeof(uint32_t) * MDL_SIZE, 1, sizeof(uint32_t) * MDL_SIZE, 268 0, BUS_DMA_NOWAIT, &esc->sc_mdldmap)) != 0) { 269 printf(": unable to map_create for the MDL, error = %d\n", 270 error); 271 return; 272 } 273 if ((error = bus_dmamap_load(esc->sc_dmat, esc->sc_mdldmap, 274 esc->sc_mdladdr, sizeof(uint32_t) * MDL_SIZE, 275 NULL, BUS_DMA_NOWAIT)) != 0) { 276 printf(": unable to load for the MDL, error = %d\n", error); 277 return; 278 } 279 280 /* map and establish interrupt */ 281 if (pci_intr_map(pa, &ih)) { 282 printf(": couldn't map interrupt\n"); 283 return; 284 } 285 286 intrstr = pci_intr_string(pa->pa_pc, ih); 287 esc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 288 ncr53c9x_intr, esc); 289 if (esc->sc_ih == NULL) { 290 printf(": couldn't establish interrupt"); 291 if (intrstr != NULL) 292 printf(" at %s", intrstr); 293 printf("\n"); 294 return; 295 } 296 if (intrstr != NULL) 297 printf(": interrupting at %s\n", intrstr); 298 299 /* Do the common parts of attachment. */ 300 printf("%s", sc->sc_dev.dv_xname); 301 sc->sc_adapter.adapt_minphys = minphys; 302 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 303 ncr53c9x_attach(sc); 304 305 /* Turn on target selection using the `DMA' method */ 306 sc->sc_features |= NCR_F_DMASELECT; 307 } 308 309 CFATTACH_DECL(pcscp, sizeof(struct pcscp_softc), 310 pcscp_match, pcscp_attach, NULL, NULL); 311 312 /* 313 * Glue functions. 314 */ 315 316 static u_char 317 pcscp_read_reg(struct ncr53c9x_softc *sc, int reg) 318 { 319 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 320 321 return PCSCP_READ_REG(esc, reg); 322 } 323 324 static void 325 pcscp_write_reg(struct ncr53c9x_softc *sc, int reg, u_char v) 326 { 327 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 328 329 PCSCP_WRITE_REG(esc, reg, v); 330 } 331 332 static int 333 pcscp_dma_isintr(struct ncr53c9x_softc *sc) 334 { 335 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 336 337 return (PCSCP_READ_REG(esc, NCR_STAT) & NCRSTAT_INT) != 0; 338 } 339 340 static void 341 pcscp_dma_reset(struct ncr53c9x_softc *sc) 342 { 343 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 344 345 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE); 346 347 esc->sc_active = 0; 348 } 349 350 static int 351 pcscp_dma_intr(struct ncr53c9x_softc *sc) 352 { 353 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 354 int trans, resid, i; 355 bus_dmamap_t dmap = esc->sc_xfermap; 356 int datain = esc->sc_datain; 357 uint32_t dmastat; 358 char *p = NULL; 359 360 dmastat = READ_DMAREG(esc, DMA_STAT); 361 362 if (dmastat & DMASTAT_ERR) { 363 /* XXX not tested... */ 364 WRITE_DMAREG(esc, DMA_CMD, 365 DMACMD_ABORT | (datain ? DMACMD_DIR : 0)); 366 367 printf("%s: error: DMA error detected; Aborting.\n", 368 sc->sc_dev.dv_xname); 369 bus_dmamap_unload(esc->sc_dmat, dmap); 370 return -1; 371 } 372 373 if (dmastat & DMASTAT_ABT) { 374 /* XXX What should be done? */ 375 printf("%s: dma_intr: DMA aborted.\n", sc->sc_dev.dv_xname); 376 WRITE_DMAREG(esc, DMA_CMD, 377 DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 378 esc->sc_active = 0; 379 return 0; 380 } 381 382 #ifdef DIAGNOSTIC 383 /* This is an "assertion" :) */ 384 if (esc->sc_active == 0) 385 panic("pcscp dmaintr: DMA wasn't active"); 386 #endif 387 388 /* DMA has stopped */ 389 390 esc->sc_active = 0; 391 392 if (esc->sc_dmasize == 0) { 393 /* A "Transfer Pad" operation completed */ 394 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 395 PCSCP_READ_REG(esc, NCR_TCL) | 396 (PCSCP_READ_REG(esc, NCR_TCM) << 8), 397 PCSCP_READ_REG(esc, NCR_TCL), 398 PCSCP_READ_REG(esc, NCR_TCM))); 399 return 0; 400 } 401 402 resid = 0; 403 /* 404 * If a transfer onto the SCSI bus gets interrupted by the device 405 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 406 * as residual since the ESP counter registers get decremented as 407 * bytes are clocked into the FIFO. 408 */ 409 if (!datain && 410 (resid = (PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 411 NCR_DMA(("pcscp_dma_intr: empty esp FIFO of %d ", resid)); 412 } 413 414 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 415 /* 416 * `Terminal count' is off, so read the residue 417 * out of the ESP counter registers. 418 */ 419 if (datain) { 420 resid = PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF; 421 while (resid > 1) 422 resid = 423 PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF; 424 WRITE_DMAREG(esc, DMA_CMD, DMACMD_BLAST | DMACMD_MDL | 425 (datain ? DMACMD_DIR : 0)); 426 427 for (i = 0; i < 0x8000; i++) /* XXX 0x8000 ? */ 428 if (READ_DMAREG(esc, DMA_STAT) & DMASTAT_BCMP) 429 break; 430 431 /* See the below comments... */ 432 if (resid) 433 p = *esc->sc_dmaaddr; 434 } 435 436 resid += PCSCP_READ_REG(esc, NCR_TCL) | 437 (PCSCP_READ_REG(esc, NCR_TCM) << 8) | 438 (PCSCP_READ_REG(esc, NCR_TCH) << 16); 439 } else { 440 while ((dmastat & DMASTAT_DONE) == 0) 441 dmastat = READ_DMAREG(esc, DMA_STAT); 442 } 443 444 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 445 446 /* sync MDL */ 447 bus_dmamap_sync(esc->sc_dmat, esc->sc_mdldmap, 448 0, sizeof(uint32_t) * dmap->dm_nsegs, BUS_DMASYNC_POSTWRITE); 449 /* sync transfer buffer */ 450 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 451 datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 452 bus_dmamap_unload(esc->sc_dmat, dmap); 453 454 trans = esc->sc_dmasize - resid; 455 456 /* 457 * From the technical manual notes: 458 * 459 * `In some odd byte conditions, one residual byte will be left 460 * in the SCSI FIFO, and the FIFO flags will never count to 0. 461 * When this happens, the residual byte should be retrieved 462 * via PIO following completion of the BLAST operation.' 463 */ 464 465 if (p) { 466 p += trans; 467 *p = PCSCP_READ_REG(esc, NCR_FIFO); 468 trans++; 469 } 470 471 if (trans < 0) { /* transferred < 0 ? */ 472 #if 0 473 /* 474 * This situation can happen in perfectly normal operation 475 * if the ESP is reselected while using DMA to select 476 * another target. As such, don't print the warning. 477 */ 478 printf("%s: xfer (%d) > req (%d)\n", 479 sc->sc_dev.dv_xname, trans, esc->sc_dmasize); 480 #endif 481 trans = esc->sc_dmasize; 482 } 483 484 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 485 PCSCP_READ_REG(esc, NCR_TCL), 486 PCSCP_READ_REG(esc, NCR_TCM), 487 PCSCP_READ_REG(esc, NCR_TCH), 488 trans, resid)); 489 490 *esc->sc_dmalen -= trans; 491 *esc->sc_dmaaddr += trans; 492 493 return 0; 494 } 495 496 static int 497 pcscp_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 498 int datain, size_t *dmasize) 499 { 500 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 501 bus_dmamap_t dmap = esc->sc_xfermap; 502 uint32_t *mdl; 503 int error, nseg, seg; 504 bus_addr_t s_offset, s_addr; 505 506 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 507 508 esc->sc_dmaaddr = addr; 509 esc->sc_dmalen = len; 510 esc->sc_dmasize = *dmasize; 511 esc->sc_datain = datain; 512 513 #ifdef DIAGNOSTIC 514 if ((*dmasize / MDL_SEG_SIZE) > MDL_SIZE) 515 panic("pcscp: transfer size too large"); 516 #endif 517 518 /* 519 * No need to set up DMA in `Transfer Pad' operation. 520 * (case of *dmasize == 0) 521 */ 522 if (*dmasize == 0) 523 return 0; 524 525 error = bus_dmamap_load(esc->sc_dmat, dmap, *esc->sc_dmaaddr, 526 *esc->sc_dmalen, NULL, 527 ((sc->sc_nexus->xs->xs_control & XS_CTL_NOSLEEP) ? 528 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | 529 ((sc->sc_nexus->xs->xs_control & XS_CTL_DATA_IN) ? 530 BUS_DMA_READ : BUS_DMA_WRITE)); 531 if (error) { 532 printf("%s: unable to load dmamap, error = %d\n", 533 sc->sc_dev.dv_xname, error); 534 return error; 535 } 536 537 /* set transfer length */ 538 WRITE_DMAREG(esc, DMA_STC, *dmasize); 539 540 /* set up MDL */ 541 mdl = esc->sc_mdladdr; 542 nseg = dmap->dm_nsegs; 543 544 /* the first segment is possibly not aligned with 4k MDL boundary */ 545 s_addr = dmap->dm_segs[0].ds_addr; 546 s_offset = s_addr & MDL_SEG_OFFSET; 547 s_addr -= s_offset; 548 549 /* set the first MDL and offset */ 550 WRITE_DMAREG(esc, DMA_SPA, s_offset); 551 *mdl++ = htole32(s_addr); 552 553 /* the rest dmamap segments are aligned with 4k boundary */ 554 for (seg = 1; seg < nseg; seg++) 555 *mdl++ = htole32(dmap->dm_segs[seg].ds_addr); 556 557 return 0; 558 } 559 560 static void 561 pcscp_dma_go(struct ncr53c9x_softc *sc) 562 { 563 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 564 bus_dmamap_t dmap = esc->sc_xfermap, mdldmap = esc->sc_mdldmap; 565 int datain = esc->sc_datain; 566 567 /* No DMA transfer in Transfer Pad operation */ 568 if (esc->sc_dmasize == 0) 569 return; 570 571 /* sync transfer buffer */ 572 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 573 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 574 575 /* sync MDL */ 576 bus_dmamap_sync(esc->sc_dmat, mdldmap, 577 0, sizeof(uint32_t) * dmap->dm_nsegs, BUS_DMASYNC_PREWRITE); 578 579 /* set Starting MDL Address */ 580 WRITE_DMAREG(esc, DMA_SMDLA, mdldmap->dm_segs[0].ds_addr); 581 582 /* set DMA command register bits */ 583 /* XXX DMA Transfer Interrupt Enable bit is broken? */ 584 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | DMACMD_MDL | 585 /* DMACMD_INTE | */ 586 (datain ? DMACMD_DIR : 0)); 587 588 /* issue DMA start command */ 589 WRITE_DMAREG(esc, DMA_CMD, DMACMD_START | DMACMD_MDL | 590 /* DMACMD_INTE | */ 591 (datain ? DMACMD_DIR : 0)); 592 593 esc->sc_active = 1; 594 } 595 596 static void 597 pcscp_dma_stop(struct ncr53c9x_softc *sc) 598 { 599 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 600 601 /* DMA stop */ 602 /* XXX What should we do here ? */ 603 WRITE_DMAREG(esc, DMA_CMD, 604 DMACMD_ABORT | (esc->sc_datain ? DMACMD_DIR : 0)); 605 bus_dmamap_unload(esc->sc_dmat, esc->sc_xfermap); 606 607 esc->sc_active = 0; 608 } 609 610 static int 611 pcscp_dma_isactive(struct ncr53c9x_softc *sc) 612 { 613 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 614 615 /* XXX should check esc->sc_active? */ 616 if ((READ_DMAREG(esc, DMA_CMD) & DMACMD_CMD) != DMACMD_IDLE) 617 return 1; 618 return 0; 619 } 620