1 /* $NetBSD: pcscp.c,v 1.12 2000/12/28 22:59:15 sommerfeld Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center; Izumi Tsutsui. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * pcscp.c: device dependent code for AMD Am53c974 (PCscsi-PCI) 42 * written by Izumi Tsutsui <tsutsui@ceres.dti.ne.jp> 43 * 44 * Technical manual available at 45 * http://www.amd.com/products/npd/techdocs/techdocs.html 46 */ 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/device.h> 51 #include <sys/buf.h> 52 53 #include <machine/bus.h> 54 #include <machine/intr.h> 55 #include <machine/endian.h> 56 57 #include <uvm/uvm_extern.h> 58 59 #include <dev/scsipi/scsi_all.h> 60 #include <dev/scsipi/scsipi_all.h> 61 #include <dev/scsipi/scsiconf.h> 62 #include <dev/scsipi/scsi_message.h> 63 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcivar.h> 66 #include <dev/pci/pcidevs.h> 67 68 #include <dev/ic/ncr53c9xreg.h> 69 #include <dev/ic/ncr53c9xvar.h> 70 71 #include <dev/pci/pcscpreg.h> 72 73 #define IO_MAP_REG 0x10 74 #define MEM_MAP_REG 0x14 75 76 struct pcscp_softc { 77 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 78 79 bus_space_tag_t sc_st; /* bus space tag */ 80 bus_space_handle_t sc_sh; /* bus space handle */ 81 void *sc_ih; /* interrupt cookie */ 82 83 bus_dma_tag_t sc_dmat; /* DMA tag */ 84 85 bus_dmamap_t sc_xfermap; /* DMA map for transfers */ 86 87 u_int32_t *sc_mdladdr; /* MDL array */ 88 bus_dmamap_t sc_mdldmap; /* MDL DMA map */ 89 90 int sc_active; /* DMA state */ 91 int sc_datain; /* DMA Data Direction */ 92 size_t sc_dmasize; /* DMA size */ 93 char **sc_dmaaddr; /* DMA address */ 94 size_t *sc_dmalen; /* DMA length */ 95 }; 96 97 #define READ_DMAREG(sc, reg) \ 98 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 99 #define WRITE_DMAREG(sc, reg, var) \ 100 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (var)) 101 102 /* don't have to use MI defines in MD code... */ 103 #undef NCR_READ_REG 104 #define NCR_READ_REG(sc, reg) pcscp_read_reg((sc), (reg)) 105 #undef NCR_WRITE_REG 106 #define NCR_WRITE_REG(sc, reg, val) pcscp_write_reg((sc), (reg), (val)) 107 108 int pcscp_match __P((struct device *, struct cfdata *, void *)); 109 void pcscp_attach __P((struct device *, struct device *, void *)); 110 111 struct cfattach pcscp_ca = { 112 sizeof(struct pcscp_softc), pcscp_match, pcscp_attach 113 }; 114 115 /* 116 * Functions and the switch for the MI code. 117 */ 118 119 u_char pcscp_read_reg __P((struct ncr53c9x_softc *, int)); 120 void pcscp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 121 int pcscp_dma_isintr __P((struct ncr53c9x_softc *)); 122 void pcscp_dma_reset __P((struct ncr53c9x_softc *)); 123 int pcscp_dma_intr __P((struct ncr53c9x_softc *)); 124 int pcscp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 125 size_t *, int, size_t *)); 126 void pcscp_dma_go __P((struct ncr53c9x_softc *)); 127 void pcscp_dma_stop __P((struct ncr53c9x_softc *)); 128 int pcscp_dma_isactive __P((struct ncr53c9x_softc *)); 129 130 struct ncr53c9x_glue pcscp_glue = { 131 pcscp_read_reg, 132 pcscp_write_reg, 133 pcscp_dma_isintr, 134 pcscp_dma_reset, 135 pcscp_dma_intr, 136 pcscp_dma_setup, 137 pcscp_dma_go, 138 pcscp_dma_stop, 139 pcscp_dma_isactive, 140 NULL, /* gl_clear_latched_intr */ 141 }; 142 143 int 144 pcscp_match(parent, match, aux) 145 struct device *parent; 146 struct cfdata *match; 147 void *aux; 148 { 149 struct pci_attach_args *pa = aux; 150 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 151 return 0; 152 153 switch (PCI_PRODUCT(pa->pa_id)) { 154 case PCI_PRODUCT_AMD_PCSCSI_PCI: 155 #if 0 156 case PCI_PRODUCT_AMD_PCNETS_PCI: 157 #endif 158 return 1; 159 } 160 return 0; 161 } 162 163 /* 164 * Attach this instance, and then all the sub-devices 165 */ 166 void 167 pcscp_attach(parent, self, aux) 168 struct device *parent, *self; 169 void *aux; 170 { 171 struct pci_attach_args *pa = aux; 172 struct pcscp_softc *esc = (void *)self; 173 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 174 bus_space_tag_t st, iot, memt; 175 bus_space_handle_t sh, ioh, memh; 176 int ioh_valid, memh_valid; 177 pci_intr_handle_t ih; 178 const char *intrstr; 179 pcireg_t csr; 180 bus_dma_segment_t seg; 181 int error, rseg; 182 183 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG, 184 PCI_MAPREG_TYPE_IO, 0, 185 &iot, &ioh, NULL, NULL) == 0); 186 #if 0 /* XXX cannot use memory map? */ 187 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, 188 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 189 &memt, &memh, NULL, NULL) == 0); 190 #else 191 memh_valid = 0; 192 #endif 193 194 if (memh_valid) { 195 st = memt; 196 sh = memh; 197 } else if (ioh_valid) { 198 st = iot; 199 sh = ioh; 200 } else { 201 printf(": unable to map registers\n"); 202 return; 203 } 204 printf("\n"); 205 206 sc->sc_glue = &pcscp_glue; 207 208 esc->sc_st = st; 209 esc->sc_sh = sh; 210 esc->sc_dmat = pa->pa_dmat; 211 212 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 213 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 214 csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE); 215 216 /* 217 * XXX More of this should be in ncr53c9x_attach(), but 218 * XXX should we really poke around the chip that much in 219 * XXX the MI code? Think about this more... 220 */ 221 222 /* 223 * Set up static configuration info. 224 */ 225 226 /* 227 * XXX should read configuration from EEPROM? 228 * 229 * MI ncr53c9x driver does not support configuration 230 * per each target device, though... 231 */ 232 sc->sc_id = 7; 233 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 234 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 235 sc->sc_cfg3 = NCRAMDCFG3_IDM | NCRAMDCFG3_FCLK; 236 sc->sc_cfg4 = NCRAMDCFG4_GE12NS | NCRAMDCFG4_RADE; 237 sc->sc_rev = NCR_VARIANT_AM53C974; 238 sc->sc_features = NCR_F_FASTSCSI; 239 sc->sc_cfg3_fscsi = NCRAMDCFG3_FSCSI; 240 sc->sc_freq = 40; /* MHz */ 241 242 /* 243 * XXX minsync and maxxfer _should_ be set up in MI code, 244 * XXX but it appears to have some dependency on what sort 245 * XXX of DMA we're hooked up to, etc. 246 */ 247 248 /* 249 * This is the value used to start sync negotiations 250 * Note that the NCR register "SYNCTP" is programmed 251 * in "clocks per byte", and has a minimum value of 4. 252 * The SCSI period used in negotiation is one-fourth 253 * of the time (in nanoseconds) needed to transfer one byte. 254 * Since the chip's clock is given in MHz, we have the following 255 * formula: 4 * period = (1000 / freq) * 4 256 */ 257 258 sc->sc_minsync = 1000 / sc->sc_freq; 259 260 /* Really no limit, but since we want to fit into the TCR... */ 261 sc->sc_maxxfer = 16 * 1024 * 1024; 262 263 /* map and establish interrupt */ 264 if (pci_intr_map(pa, &ih)) { 265 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 266 return; 267 } 268 269 intrstr = pci_intr_string(pa->pa_pc, ih); 270 esc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 271 ncr53c9x_intr, esc); 272 if (esc->sc_ih == NULL) { 273 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 274 if (intrstr != NULL) 275 printf(" at %s", intrstr); 276 printf("\n"); 277 return; 278 } 279 if (intrstr != NULL) 280 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, 281 intrstr); 282 283 /* 284 * Create the DMA maps for the data transfers. 285 */ 286 287 #define MDL_SEG_SIZE 0x1000 /* 4kbyte per segment */ 288 #define MDL_SEG_OFFSET 0x0FFF 289 #define MDL_SIZE (MAXPHYS / MDL_SEG_SIZE + 1) /* no hardware limit? */ 290 291 if (bus_dmamap_create(esc->sc_dmat, MAXPHYS, MDL_SIZE, MAXPHYS, 0, 292 BUS_DMA_NOWAIT, &esc->sc_xfermap)) { 293 printf("%s: can't create dma maps\n", sc->sc_dev.dv_xname); 294 return; 295 } 296 297 /* 298 * Allocate and map memory for the MDL. 299 */ 300 301 if ((error = bus_dmamem_alloc(esc->sc_dmat, 302 sizeof(u_int32_t) * MDL_SIZE, PAGE_SIZE, 0, &seg, 1, &rseg, 303 BUS_DMA_NOWAIT)) != 0) { 304 printf("%s: unable to allocate memory for the MDL, " 305 "error = %d\n", sc->sc_dev.dv_xname, error); 306 return; 307 } 308 if ((error = bus_dmamem_map(esc->sc_dmat, &seg, rseg, 309 sizeof(u_int32_t) * MDL_SIZE , (caddr_t *)&esc->sc_mdladdr, 310 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 311 printf("%s: unable to map the MDL memory, error = %d\n", 312 sc->sc_dev.dv_xname, error); 313 return; 314 } 315 if ((error = bus_dmamap_create(esc->sc_dmat, 316 sizeof(u_int32_t) * MDL_SIZE, 1, sizeof(u_int32_t) * MDL_SIZE, 317 0, BUS_DMA_NOWAIT, &esc->sc_mdldmap)) != 0) { 318 printf("%s: unable to map_create for the MDL, error = %d\n", 319 sc->sc_dev.dv_xname, error); 320 return; 321 } 322 if ((error = bus_dmamap_load(esc->sc_dmat, esc->sc_mdldmap, 323 esc->sc_mdladdr, sizeof(u_int32_t) * MDL_SIZE, 324 NULL, BUS_DMA_NOWAIT)) != 0) { 325 printf("%s: unable to load for the MDL, error = %d\n", 326 sc->sc_dev.dv_xname, error); 327 return; 328 } 329 330 /* Do the common parts of attachment. */ 331 printf("%s", sc->sc_dev.dv_xname); 332 333 ncr53c9x_attach(sc, NULL, NULL); 334 335 /* Turn on target selection using the `dma' method */ 336 ncr53c9x_dmaselect = 1; 337 } 338 339 /* 340 * Glue functions. 341 */ 342 343 u_char 344 pcscp_read_reg(sc, reg) 345 struct ncr53c9x_softc *sc; 346 int reg; 347 { 348 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 349 350 return bus_space_read_1(esc->sc_st, esc->sc_sh, reg << 2); 351 } 352 353 void 354 pcscp_write_reg(sc, reg, v) 355 struct ncr53c9x_softc *sc; 356 int reg; 357 u_char v; 358 { 359 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 360 361 bus_space_write_1(esc->sc_st, esc->sc_sh, reg << 2, v); 362 } 363 364 int 365 pcscp_dma_isintr(sc) 366 struct ncr53c9x_softc *sc; 367 { 368 369 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 370 } 371 372 void 373 pcscp_dma_reset(sc) 374 struct ncr53c9x_softc *sc; 375 { 376 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 377 378 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE); 379 380 esc->sc_active = 0; 381 } 382 383 int 384 pcscp_dma_intr(sc) 385 struct ncr53c9x_softc *sc; 386 { 387 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 388 int trans, resid, i; 389 bus_dmamap_t dmap = esc->sc_xfermap; 390 int datain = esc->sc_datain; 391 u_int32_t dmastat; 392 char *p = NULL; 393 394 dmastat = READ_DMAREG(esc, DMA_STAT); 395 396 if (dmastat & DMASTAT_ERR) { 397 /* XXX not tested... */ 398 WRITE_DMAREG(esc, DMA_CMD, 399 DMACMD_ABORT | (datain ? DMACMD_DIR : 0)); 400 401 printf("%s: error: DMA error detected; Aborting.\n", 402 sc->sc_dev.dv_xname); 403 bus_dmamap_unload(esc->sc_dmat, dmap); 404 return -1; 405 } 406 407 if (dmastat & DMASTAT_ABT) { 408 /* XXX What should be done? */ 409 printf("%s: dma_intr: DMA aborted.\n", sc->sc_dev.dv_xname); 410 WRITE_DMAREG(esc, DMA_CMD, 411 DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 412 esc->sc_active = 0; 413 return 0; 414 } 415 416 /* This is an "assertion" :) */ 417 if (esc->sc_active == 0) 418 panic("pcscp dmaintr: DMA wasn't active"); 419 420 /* DMA has stopped */ 421 422 esc->sc_active = 0; 423 424 if (esc->sc_dmasize == 0) { 425 /* A "Transfer Pad" operation completed */ 426 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 427 NCR_READ_REG(sc, NCR_TCL) | 428 (NCR_READ_REG(sc, NCR_TCM) << 8), 429 NCR_READ_REG(sc, NCR_TCL), 430 NCR_READ_REG(sc, NCR_TCM))); 431 return 0; 432 } 433 434 resid = 0; 435 /* 436 * If a transfer onto the SCSI bus gets interrupted by the device 437 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 438 * as residual since the ESP counter registers get decremented as 439 * bytes are clocked into the FIFO. 440 */ 441 if (!datain && 442 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 443 NCR_DMA(("pcscp_dma_intr: empty esp FIFO of %d ", resid)); 444 } 445 446 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 447 /* 448 * `Terminal count' is off, so read the residue 449 * out of the ESP counter registers. 450 */ 451 if (datain) { 452 resid = NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF; 453 while (resid > 1) 454 resid = 455 NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF; 456 WRITE_DMAREG(esc, DMA_CMD, DMACMD_BLAST | DMACMD_MDL | 457 (datain ? DMACMD_DIR : 0)); 458 459 for (i = 0; i < 0x8000; i++) /* XXX 0x8000 ? */ 460 if (READ_DMAREG(esc, DMA_STAT) & DMASTAT_BCMP) 461 break; 462 463 /* See the below comments... */ 464 if (resid) 465 p = *esc->sc_dmaaddr; 466 } 467 468 resid += (NCR_READ_REG(sc, NCR_TCL) | 469 (NCR_READ_REG(sc, NCR_TCM) << 8) | 470 ((sc->sc_cfg2 & NCRCFG2_FE) 471 ? (NCR_READ_REG(sc, NCR_TCH) << 16) : 0)); 472 473 if (resid == 0 && esc->sc_dmasize == 65536 && 474 (sc->sc_cfg2 & NCRCFG2_FE) == 0) 475 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 476 resid = 65536; 477 } else { 478 while((dmastat & DMASTAT_DONE) == 0) 479 dmastat = READ_DMAREG(esc, DMA_STAT); 480 } 481 482 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 483 484 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 485 datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 486 bus_dmamap_unload(esc->sc_dmat, dmap); 487 488 trans = esc->sc_dmasize - resid; 489 490 /* 491 * From the technical manual notes: 492 * 493 * `In some odd byte conditions, one residual byte will be left 494 * in the SCSI FIFO, and the FIFO flags will never count to 0. 495 * When this happens, the residual byte should be retrieved 496 * via PIO following completion of the BLAST operation.' 497 */ 498 499 if (p) { 500 p += trans; 501 *p = NCR_READ_REG(sc, NCR_FIFO); 502 trans++; 503 } 504 505 if (trans < 0) { /* transferred < 0 ? */ 506 #if 0 507 /* 508 * This situation can happen in perfectly normal operation 509 * if the ESP is reselected while using DMA to select 510 * another target. As such, don't print the warning. 511 */ 512 printf("%s: xfer (%d) > req (%d)\n", 513 sc->sc_dev.dv_xname, trans, esc->sc_dmasize); 514 #endif 515 trans = esc->sc_dmasize; 516 } 517 518 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 519 NCR_READ_REG(sc, NCR_TCL), 520 NCR_READ_REG(sc, NCR_TCM), 521 (sc->sc_cfg2 & NCRCFG2_FE) ? NCR_READ_REG(sc, NCR_TCH) : 0, 522 trans, resid)); 523 524 *esc->sc_dmalen -= trans; 525 *esc->sc_dmaaddr += trans; 526 527 return 0; 528 } 529 530 int 531 pcscp_dma_setup(sc, addr, len, datain, dmasize) 532 struct ncr53c9x_softc *sc; 533 caddr_t *addr; 534 size_t *len; 535 int datain; 536 size_t *dmasize; 537 { 538 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 539 bus_dmamap_t dmap = esc->sc_xfermap; 540 u_int32_t *mdl; 541 int error, nseg, seg; 542 bus_addr_t s_offset, s_addr; 543 long rest, count; 544 545 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 546 547 esc->sc_dmaaddr = addr; 548 esc->sc_dmalen = len; 549 esc->sc_dmasize = *dmasize; 550 esc->sc_datain = datain; 551 552 #ifdef DIAGNOSTIC 553 if ((*dmasize / MDL_SEG_SIZE) > MDL_SIZE) 554 panic("pcscp: transfer size too large"); 555 #endif 556 557 /* 558 * No need to set up DMA in `Transfer Pad' operation. 559 * (case of *dmasize == 0) 560 */ 561 if (*dmasize == 0) 562 return 0; 563 564 error = bus_dmamap_load(esc->sc_dmat, dmap, *esc->sc_dmaaddr, 565 *esc->sc_dmalen, NULL, 566 sc->sc_nexus->xs->xs_control & XS_CTL_NOSLEEP ? 567 BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 568 if (error) { 569 printf("%s: unable to load dmamap, error = %d\n", 570 sc->sc_dev.dv_xname, error); 571 return error; 572 } 573 574 /* set transfer length */ 575 WRITE_DMAREG(esc, DMA_STC, *dmasize); 576 577 /* set up MDL */ 578 mdl = esc->sc_mdladdr; 579 nseg = dmap->dm_nsegs; 580 581 /* the first segment is possibly not aligned with 4k MDL boundary */ 582 count = dmap->dm_segs[0].ds_len; 583 s_addr = dmap->dm_segs[0].ds_addr; 584 s_offset = s_addr & MDL_SEG_OFFSET; 585 s_addr -= s_offset; 586 rest = MDL_SEG_SIZE - s_offset; 587 588 /* set the first MDL and offset */ 589 WRITE_DMAREG(esc, DMA_SPA, s_offset); 590 *mdl++ = htole32(s_addr); 591 count -= rest; 592 593 /* rests of the first dmamap segment */ 594 while (count > 0) { 595 s_addr += MDL_SEG_SIZE; 596 *mdl++ = htole32(s_addr); 597 count -= MDL_SEG_SIZE; 598 } 599 600 /* the rest dmamap segments are aligned with 4k boundary */ 601 for (seg = 1; seg < nseg; seg++) { 602 count = dmap->dm_segs[seg].ds_len; 603 s_addr = dmap->dm_segs[seg].ds_addr; 604 605 /* first 4kbyte of each dmamap segment */ 606 *mdl++ = htole32(s_addr); 607 count -= MDL_SEG_SIZE; 608 609 /* trailing contiguous 4k frames of each dmamap segments */ 610 while (count > 0) { 611 s_addr += MDL_SEG_SIZE; 612 *mdl++ = htole32(s_addr); 613 count -= MDL_SEG_SIZE; 614 } 615 } 616 617 return 0; 618 } 619 620 void 621 pcscp_dma_go(sc) 622 struct ncr53c9x_softc *sc; 623 { 624 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 625 bus_dmamap_t dmap = esc->sc_xfermap, mdldmap = esc->sc_mdldmap; 626 int datain = esc->sc_datain; 627 628 /* No DMA transfer in Transfer Pad operation */ 629 if (esc->sc_dmasize == 0) 630 return; 631 632 /* sync transfer buffer */ 633 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 634 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 635 636 /* sync MDL */ 637 bus_dmamap_sync(esc->sc_dmat, mdldmap, 0, mdldmap->dm_mapsize, 638 BUS_DMASYNC_PREWRITE); 639 640 /* set Starting MDL Address */ 641 WRITE_DMAREG(esc, DMA_SMDLA, mdldmap->dm_segs[0].ds_addr); 642 643 /* set DMA command register bits */ 644 /* XXX DMA Transfer Interrupt Enable bit is broken? */ 645 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | DMACMD_MDL | 646 /* DMACMD_INTE | */ 647 (datain ? DMACMD_DIR : 0)); 648 649 /* issue DMA start command */ 650 WRITE_DMAREG(esc, DMA_CMD, DMACMD_START | DMACMD_MDL | 651 /* DMACMD_INTE | */ 652 (datain ? DMACMD_DIR : 0)); 653 654 esc->sc_active = 1; 655 } 656 657 void 658 pcscp_dma_stop(sc) 659 struct ncr53c9x_softc *sc; 660 { 661 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 662 663 /* dma stop */ 664 /* XXX What should we do here ? */ 665 WRITE_DMAREG(esc, DMA_CMD, 666 DMACMD_ABORT | (esc->sc_datain ? DMACMD_DIR : 0)); 667 668 esc->sc_active = 0; 669 } 670 671 int 672 pcscp_dma_isactive(sc) 673 struct ncr53c9x_softc *sc; 674 { 675 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 676 677 /* XXX should check esc->sc_active? */ 678 if ((READ_DMAREG(esc, DMA_CMD) & DMACMD_CMD) != DMACMD_IDLE) 679 return 1; 680 return 0; 681 } 682