1 /* $NetBSD: pcscp.c,v 1.44 2008/08/28 16:47:10 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center; Izumi Tsutsui. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * pcscp.c: device dependent code for AMD Am53c974 (PCscsi-PCI) 35 * written by Izumi Tsutsui <tsutsui@NetBSD.org> 36 * 37 * Technical manual available at 38 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/19113.pdf 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: pcscp.c,v 1.44 2008/08/28 16:47:10 tsutsui Exp $"); 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/buf.h> 48 49 #include <sys/bus.h> 50 #include <sys/intr.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <dev/scsipi/scsipi_all.h> 55 #include <dev/scsipi/scsi_all.h> 56 #include <dev/scsipi/scsiconf.h> 57 58 #include <dev/pci/pcireg.h> 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcidevs.h> 61 62 #include <dev/ic/ncr53c9xreg.h> 63 #include <dev/ic/ncr53c9xvar.h> 64 65 #include <dev/pci/pcscpreg.h> 66 67 #define IO_MAP_REG 0x10 68 69 struct pcscp_softc { 70 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 71 72 bus_space_tag_t sc_st; /* bus space tag */ 73 bus_space_handle_t sc_sh; /* bus space handle */ 74 void *sc_ih; /* interrupt cookie */ 75 76 bus_dma_tag_t sc_dmat; /* DMA tag */ 77 78 bus_dmamap_t sc_xfermap; /* DMA map for transfers */ 79 80 uint32_t *sc_mdladdr; /* MDL array */ 81 bus_dmamap_t sc_mdldmap; /* MDL DMA map */ 82 83 int sc_active; /* DMA state */ 84 int sc_datain; /* DMA Data Direction */ 85 size_t sc_dmasize; /* DMA size */ 86 uint8_t **sc_dmaaddr; /* DMA address */ 87 size_t *sc_dmalen; /* DMA length */ 88 }; 89 90 #define READ_DMAREG(sc, reg) \ 91 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 92 #define WRITE_DMAREG(sc, reg, var) \ 93 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (var)) 94 95 #define PCSCP_READ_REG(sc, reg) \ 96 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2) 97 #define PCSCP_WRITE_REG(sc, reg, val) \ 98 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2, (val)) 99 100 101 static int pcscp_match(device_t, cfdata_t, void *); 102 static void pcscp_attach(device_t, device_t, void *); 103 104 CFATTACH_DECL_NEW(pcscp, sizeof(struct pcscp_softc), 105 pcscp_match, pcscp_attach, NULL, NULL); 106 107 /* 108 * Functions and the switch for the MI code. 109 */ 110 111 static uint8_t pcscp_read_reg(struct ncr53c9x_softc *, int); 112 static void pcscp_write_reg(struct ncr53c9x_softc *, int, uint8_t); 113 static int pcscp_dma_isintr(struct ncr53c9x_softc *); 114 static void pcscp_dma_reset(struct ncr53c9x_softc *); 115 static int pcscp_dma_intr(struct ncr53c9x_softc *); 116 static int pcscp_dma_setup(struct ncr53c9x_softc *, uint8_t **, size_t *, 117 int, size_t *); 118 static void pcscp_dma_go(struct ncr53c9x_softc *); 119 static void pcscp_dma_stop(struct ncr53c9x_softc *); 120 static int pcscp_dma_isactive(struct ncr53c9x_softc *); 121 122 static struct ncr53c9x_glue pcscp_glue = { 123 pcscp_read_reg, 124 pcscp_write_reg, 125 pcscp_dma_isintr, 126 pcscp_dma_reset, 127 pcscp_dma_intr, 128 pcscp_dma_setup, 129 pcscp_dma_go, 130 pcscp_dma_stop, 131 pcscp_dma_isactive, 132 NULL, /* gl_clear_latched_intr */ 133 }; 134 135 static int 136 pcscp_match(device_t parent, cfdata_t cf, void *aux) 137 { 138 struct pci_attach_args *pa = aux; 139 140 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 141 return 0; 142 143 switch (PCI_PRODUCT(pa->pa_id)) { 144 case PCI_PRODUCT_AMD_PCSCSI_PCI: 145 return 1; 146 } 147 return 0; 148 } 149 150 /* 151 * Attach this instance, and then all the sub-devices 152 */ 153 static void 154 pcscp_attach(device_t parent, device_t self, void *aux) 155 { 156 struct pcscp_softc *esc = device_private(self); 157 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 158 struct pci_attach_args *pa = aux; 159 bus_space_tag_t iot; 160 bus_space_handle_t ioh; 161 pci_intr_handle_t ih; 162 const char *intrstr; 163 pcireg_t csr; 164 bus_dma_segment_t seg; 165 int error, rseg; 166 char devinfo[256]; 167 168 sc->sc_dev = self; 169 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 170 aprint_normal(": %s\n", devinfo); 171 aprint_normal("%s", device_xname(sc->sc_dev)); 172 173 if (pci_mapreg_map(pa, IO_MAP_REG, PCI_MAPREG_TYPE_IO, 0, 174 &iot, &ioh, NULL, NULL)) { 175 aprint_error(": unable to map registers\n"); 176 return; 177 } 178 179 sc->sc_glue = &pcscp_glue; 180 181 esc->sc_st = iot; 182 esc->sc_sh = ioh; 183 esc->sc_dmat = pa->pa_dmat; 184 185 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 186 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 187 csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE); 188 189 /* 190 * XXX More of this should be in ncr53c9x_attach(), but 191 * XXX should we really poke around the chip that much in 192 * XXX the MI code? Think about this more... 193 */ 194 195 /* 196 * Set up static configuration info. 197 */ 198 199 /* 200 * XXX should read configuration from EEPROM? 201 * 202 * MI ncr53c9x driver does not support configuration 203 * per each target device, though... 204 */ 205 sc->sc_id = 7; 206 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 207 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 208 sc->sc_cfg3 = NCRAMDCFG3_IDM | NCRAMDCFG3_FCLK; 209 sc->sc_cfg4 = NCRAMDCFG4_GE12NS | NCRAMDCFG4_RADE; 210 sc->sc_rev = NCR_VARIANT_AM53C974; 211 sc->sc_features = NCR_F_FASTSCSI; 212 sc->sc_cfg3_fscsi = NCRAMDCFG3_FSCSI; 213 sc->sc_freq = 40; /* MHz */ 214 215 /* 216 * XXX minsync and maxxfer _should_ be set up in MI code, 217 * XXX but it appears to have some dependency on what sort 218 * XXX of DMA we're hooked up to, etc. 219 */ 220 221 /* 222 * This is the value used to start sync negotiations 223 * Note that the NCR register "SYNCTP" is programmed 224 * in "clocks per byte", and has a minimum value of 4. 225 * The SCSI period used in negotiation is one-fourth 226 * of the time (in nanoseconds) needed to transfer one byte. 227 * Since the chip's clock is given in MHz, we have the following 228 * formula: 4 * period = (1000 / freq) * 4 229 */ 230 231 sc->sc_minsync = 1000 / sc->sc_freq; 232 233 /* Really no limit, but since we want to fit into the TCR... */ 234 sc->sc_maxxfer = 16 * 1024 * 1024; 235 236 /* 237 * Create the DMA maps for the data transfers. 238 */ 239 240 #define MDL_SEG_SIZE 0x1000 /* 4kbyte per segment */ 241 #define MDL_SEG_OFFSET 0x0FFF 242 #define MDL_SIZE (MAXPHYS / MDL_SEG_SIZE + 1) /* no hardware limit? */ 243 244 if (bus_dmamap_create(esc->sc_dmat, MAXPHYS, MDL_SIZE, MDL_SEG_SIZE, 245 MDL_SEG_SIZE, BUS_DMA_NOWAIT, &esc->sc_xfermap)) { 246 aprint_error(": can't create DMA maps\n"); 247 return; 248 } 249 250 /* 251 * Allocate and map memory for the MDL. 252 */ 253 254 if ((error = bus_dmamem_alloc(esc->sc_dmat, 255 sizeof(uint32_t) * MDL_SIZE, PAGE_SIZE, 0, &seg, 1, &rseg, 256 BUS_DMA_NOWAIT)) != 0) { 257 aprint_error(": unable to allocate memory for the MDL," 258 " error = %d\n", error); 259 goto fail_0; 260 } 261 if ((error = bus_dmamem_map(esc->sc_dmat, &seg, rseg, 262 sizeof(uint32_t) * MDL_SIZE , (void **)&esc->sc_mdladdr, 263 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 264 aprint_error(": unable to map the MDL memory, error = %d\n", 265 error); 266 goto fail_1; 267 } 268 if ((error = bus_dmamap_create(esc->sc_dmat, 269 sizeof(uint32_t) * MDL_SIZE, 1, sizeof(uint32_t) * MDL_SIZE, 270 0, BUS_DMA_NOWAIT, &esc->sc_mdldmap)) != 0) { 271 aprint_error(": unable to map_create for the MDL, error = %d\n", 272 error); 273 goto fail_2; 274 } 275 if ((error = bus_dmamap_load(esc->sc_dmat, esc->sc_mdldmap, 276 esc->sc_mdladdr, sizeof(uint32_t) * MDL_SIZE, 277 NULL, BUS_DMA_NOWAIT)) != 0) { 278 aprint_error(": unable to load for the MDL, error = %d\n", 279 error); 280 goto fail_3; 281 } 282 283 /* map and establish interrupt */ 284 if (pci_intr_map(pa, &ih)) { 285 aprint_error(": couldn't map interrupt\n"); 286 goto fail_4; 287 } 288 289 intrstr = pci_intr_string(pa->pa_pc, ih); 290 esc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 291 ncr53c9x_intr, esc); 292 if (esc->sc_ih == NULL) { 293 aprint_error(": couldn't establish interrupt"); 294 if (intrstr != NULL) 295 aprint_error(" at %s", intrstr); 296 aprint_error("\n"); 297 goto fail_4; 298 } 299 if (intrstr != NULL) { 300 aprint_normal(": interrupting at %s\n", intrstr); 301 aprint_normal("%s", device_xname(sc->sc_dev)); 302 } 303 304 /* Do the common parts of attachment. */ 305 sc->sc_adapter.adapt_minphys = minphys; 306 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 307 ncr53c9x_attach(sc); 308 309 /* Turn on target selection using the `DMA' method */ 310 sc->sc_features |= NCR_F_DMASELECT; 311 312 return; 313 314 fail_4: 315 bus_dmamap_unload(esc->sc_dmat, esc->sc_mdldmap); 316 fail_3: 317 bus_dmamap_destroy(esc->sc_dmat, esc->sc_mdldmap); 318 fail_2: 319 bus_dmamem_unmap(esc->sc_dmat, (void *)esc->sc_mdldmap, 320 sizeof(uint32_t) * MDL_SIZE); 321 fail_1: 322 bus_dmamem_free(esc->sc_dmat, &seg, rseg); 323 fail_0: 324 bus_dmamap_destroy(esc->sc_dmat, esc->sc_xfermap); 325 } 326 327 /* 328 * Glue functions. 329 */ 330 331 static uint8_t 332 pcscp_read_reg(struct ncr53c9x_softc *sc, int reg) 333 { 334 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 335 336 return PCSCP_READ_REG(esc, reg); 337 } 338 339 static void 340 pcscp_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t v) 341 { 342 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 343 344 PCSCP_WRITE_REG(esc, reg, v); 345 } 346 347 static int 348 pcscp_dma_isintr(struct ncr53c9x_softc *sc) 349 { 350 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 351 352 return (PCSCP_READ_REG(esc, NCR_STAT) & NCRSTAT_INT) != 0; 353 } 354 355 static void 356 pcscp_dma_reset(struct ncr53c9x_softc *sc) 357 { 358 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 359 360 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE); 361 362 esc->sc_active = 0; 363 } 364 365 static int 366 pcscp_dma_intr(struct ncr53c9x_softc *sc) 367 { 368 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 369 int trans, resid, i; 370 bus_dmamap_t dmap = esc->sc_xfermap; 371 int datain = esc->sc_datain; 372 uint32_t dmastat; 373 uint8_t *p = NULL; 374 375 dmastat = READ_DMAREG(esc, DMA_STAT); 376 377 if (dmastat & DMASTAT_ERR) { 378 /* XXX not tested... */ 379 WRITE_DMAREG(esc, DMA_CMD, 380 DMACMD_ABORT | (datain ? DMACMD_DIR : 0)); 381 382 printf("%s: error: DMA error detected; Aborting.\n", 383 device_xname(sc->sc_dev)); 384 bus_dmamap_unload(esc->sc_dmat, dmap); 385 return -1; 386 } 387 388 if (dmastat & DMASTAT_ABT) { 389 /* XXX What should be done? */ 390 printf("%s: %s: DMA aborted.\n", 391 device_xname(sc->sc_dev), __func__); 392 WRITE_DMAREG(esc, DMA_CMD, 393 DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 394 esc->sc_active = 0; 395 return 0; 396 } 397 398 #ifdef DIAGNOSTIC 399 /* This is an "assertion" :) */ 400 if (esc->sc_active == 0) 401 panic("%s: %s: DMA wasn't active", 402 device_xname(sc->sc_dev), __func__); 403 #endif 404 405 /* DMA has stopped */ 406 407 esc->sc_active = 0; 408 409 if (esc->sc_dmasize == 0) { 410 /* A "Transfer Pad" operation completed */ 411 NCR_DMA(("%s: discarded %d bytes (tcl=%d, tcm=%d)\n", 412 __func__, 413 PCSCP_READ_REG(esc, NCR_TCL) | 414 (PCSCP_READ_REG(esc, NCR_TCM) << 8), 415 PCSCP_READ_REG(esc, NCR_TCL), 416 PCSCP_READ_REG(esc, NCR_TCM))); 417 return 0; 418 } 419 420 resid = 0; 421 /* 422 * If a transfer onto the SCSI bus gets interrupted by the device 423 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 424 * as residual since the ESP counter registers get decremented as 425 * bytes are clocked into the FIFO. 426 */ 427 if (!datain && 428 (resid = (PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 429 NCR_DMA(("%s: empty esp FIFO of %d ", __func__, resid)); 430 } 431 432 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 433 /* 434 * `Terminal count' is off, so read the residue 435 * out of the ESP counter registers. 436 */ 437 if (datain) { 438 resid = PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF; 439 while (resid > 1) 440 resid = 441 PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF; 442 WRITE_DMAREG(esc, DMA_CMD, DMACMD_BLAST | DMACMD_MDL | 443 (datain ? DMACMD_DIR : 0)); 444 445 for (i = 0; i < 1000; i++) { /* XXX */ 446 if (READ_DMAREG(esc, DMA_STAT) & DMASTAT_BCMP) 447 break; 448 DELAY(1); 449 } 450 451 /* See the below comments... */ 452 if (resid) 453 p = *esc->sc_dmaaddr; 454 } 455 456 resid += PCSCP_READ_REG(esc, NCR_TCL) | 457 (PCSCP_READ_REG(esc, NCR_TCM) << 8) | 458 (PCSCP_READ_REG(esc, NCR_TCH) << 16); 459 } else { 460 while ((dmastat & DMASTAT_DONE) == 0) 461 dmastat = READ_DMAREG(esc, DMA_STAT); 462 } 463 464 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 465 466 /* sync MDL */ 467 bus_dmamap_sync(esc->sc_dmat, esc->sc_mdldmap, 468 0, sizeof(uint32_t) * dmap->dm_nsegs, BUS_DMASYNC_POSTWRITE); 469 /* sync transfer buffer */ 470 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 471 datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 472 bus_dmamap_unload(esc->sc_dmat, dmap); 473 474 trans = esc->sc_dmasize - resid; 475 476 /* 477 * From the technical manual notes: 478 * 479 * `In some odd byte conditions, one residual byte will be left 480 * in the SCSI FIFO, and the FIFO flags will never count to 0. 481 * When this happens, the residual byte should be retrieved 482 * via PIO following completion of the BLAST operation.' 483 */ 484 485 if (p) { 486 p += trans; 487 *p = PCSCP_READ_REG(esc, NCR_FIFO); 488 trans++; 489 } 490 491 if (trans < 0) { /* transferred < 0 ? */ 492 #if 0 493 /* 494 * This situation can happen in perfectly normal operation 495 * if the ESP is reselected while using DMA to select 496 * another target. As such, don't print the warning. 497 */ 498 printf("%s: xfer (%d) > req (%d)\n", 499 device_xname(sc->sc_dev), trans, esc->sc_dmasize); 500 #endif 501 trans = esc->sc_dmasize; 502 } 503 504 NCR_DMA(("%s: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 505 __func__, 506 PCSCP_READ_REG(esc, NCR_TCL), 507 PCSCP_READ_REG(esc, NCR_TCM), 508 PCSCP_READ_REG(esc, NCR_TCH), 509 trans, resid)); 510 511 *esc->sc_dmalen -= trans; 512 *esc->sc_dmaaddr += trans; 513 514 return 0; 515 } 516 517 static int 518 pcscp_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len, 519 int datain, size_t *dmasize) 520 { 521 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 522 bus_dmamap_t dmap = esc->sc_xfermap; 523 uint32_t *mdl; 524 int error, nseg, seg; 525 bus_addr_t s_offset, s_addr; 526 527 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 528 529 esc->sc_dmaaddr = addr; 530 esc->sc_dmalen = len; 531 esc->sc_dmasize = *dmasize; 532 esc->sc_datain = datain; 533 534 #ifdef DIAGNOSTIC 535 if ((*dmasize / MDL_SEG_SIZE) > MDL_SIZE) 536 panic("%s: transfer size too large", device_xname(sc->sc_dev)); 537 #endif 538 539 /* 540 * No need to set up DMA in `Transfer Pad' operation. 541 * (case of *dmasize == 0) 542 */ 543 if (*dmasize == 0) 544 return 0; 545 546 error = bus_dmamap_load(esc->sc_dmat, dmap, *esc->sc_dmaaddr, 547 *esc->sc_dmalen, NULL, 548 ((sc->sc_nexus->xs->xs_control & XS_CTL_NOSLEEP) ? 549 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | 550 ((sc->sc_nexus->xs->xs_control & XS_CTL_DATA_IN) ? 551 BUS_DMA_READ : BUS_DMA_WRITE)); 552 if (error) { 553 printf("%s: unable to load dmamap, error = %d\n", 554 device_xname(sc->sc_dev), error); 555 return error; 556 } 557 558 /* set transfer length */ 559 WRITE_DMAREG(esc, DMA_STC, *dmasize); 560 561 /* set up MDL */ 562 mdl = esc->sc_mdladdr; 563 nseg = dmap->dm_nsegs; 564 565 /* the first segment is possibly not aligned with 4k MDL boundary */ 566 s_addr = dmap->dm_segs[0].ds_addr; 567 s_offset = s_addr & MDL_SEG_OFFSET; 568 s_addr -= s_offset; 569 570 /* set the first MDL and offset */ 571 WRITE_DMAREG(esc, DMA_SPA, s_offset); 572 *mdl++ = htole32(s_addr); 573 574 /* the rest dmamap segments are aligned with 4k boundary */ 575 for (seg = 1; seg < nseg; seg++) 576 *mdl++ = htole32(dmap->dm_segs[seg].ds_addr); 577 578 return 0; 579 } 580 581 static void 582 pcscp_dma_go(struct ncr53c9x_softc *sc) 583 { 584 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 585 bus_dmamap_t dmap = esc->sc_xfermap, mdldmap = esc->sc_mdldmap; 586 int datain = esc->sc_datain; 587 588 /* No DMA transfer in Transfer Pad operation */ 589 if (esc->sc_dmasize == 0) 590 return; 591 592 /* sync transfer buffer */ 593 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 594 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 595 596 /* sync MDL */ 597 bus_dmamap_sync(esc->sc_dmat, mdldmap, 598 0, sizeof(uint32_t) * dmap->dm_nsegs, BUS_DMASYNC_PREWRITE); 599 600 /* set Starting MDL Address */ 601 WRITE_DMAREG(esc, DMA_SMDLA, mdldmap->dm_segs[0].ds_addr); 602 603 /* set DMA command register bits */ 604 /* XXX DMA Transfer Interrupt Enable bit is broken? */ 605 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | DMACMD_MDL | 606 /* DMACMD_INTE | */ 607 (datain ? DMACMD_DIR : 0)); 608 609 /* issue DMA start command */ 610 WRITE_DMAREG(esc, DMA_CMD, DMACMD_START | DMACMD_MDL | 611 /* DMACMD_INTE | */ 612 (datain ? DMACMD_DIR : 0)); 613 614 esc->sc_active = 1; 615 } 616 617 static void 618 pcscp_dma_stop(struct ncr53c9x_softc *sc) 619 { 620 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 621 622 /* DMA stop */ 623 /* XXX What should we do here ? */ 624 WRITE_DMAREG(esc, DMA_CMD, 625 DMACMD_ABORT | (esc->sc_datain ? DMACMD_DIR : 0)); 626 bus_dmamap_unload(esc->sc_dmat, esc->sc_xfermap); 627 628 esc->sc_active = 0; 629 } 630 631 static int 632 pcscp_dma_isactive(struct ncr53c9x_softc *sc) 633 { 634 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 635 636 /* XXX should check esc->sc_active? */ 637 if ((READ_DMAREG(esc, DMA_CMD) & DMACMD_CMD) != DMACMD_IDLE) 638 return 1; 639 return 0; 640 } 641