1 /* $NetBSD: pcscp.c,v 1.40 2007/10/19 12:00:54 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center; Izumi Tsutsui. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * pcscp.c: device dependent code for AMD Am53c974 (PCscsi-PCI) 42 * written by Izumi Tsutsui <tsutsui@ceres.dti.ne.jp> 43 * 44 * Technical manual available at 45 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/19113.pdf 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: pcscp.c,v 1.40 2007/10/19 12:00:54 ad Exp $"); 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/device.h> 54 #include <sys/buf.h> 55 56 #include <sys/bus.h> 57 #include <sys/intr.h> 58 59 #include <uvm/uvm_extern.h> 60 61 #include <dev/scsipi/scsipi_all.h> 62 #include <dev/scsipi/scsi_all.h> 63 #include <dev/scsipi/scsiconf.h> 64 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcivar.h> 67 #include <dev/pci/pcidevs.h> 68 69 #include <dev/ic/ncr53c9xreg.h> 70 #include <dev/ic/ncr53c9xvar.h> 71 72 #include <dev/pci/pcscpreg.h> 73 74 #define IO_MAP_REG 0x10 75 76 struct pcscp_softc { 77 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 78 79 bus_space_tag_t sc_st; /* bus space tag */ 80 bus_space_handle_t sc_sh; /* bus space handle */ 81 void *sc_ih; /* interrupt cookie */ 82 83 bus_dma_tag_t sc_dmat; /* DMA tag */ 84 85 bus_dmamap_t sc_xfermap; /* DMA map for transfers */ 86 87 uint32_t *sc_mdladdr; /* MDL array */ 88 bus_dmamap_t sc_mdldmap; /* MDL DMA map */ 89 90 int sc_active; /* DMA state */ 91 int sc_datain; /* DMA Data Direction */ 92 size_t sc_dmasize; /* DMA size */ 93 char **sc_dmaaddr; /* DMA address */ 94 size_t *sc_dmalen; /* DMA length */ 95 }; 96 97 #define READ_DMAREG(sc, reg) \ 98 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 99 #define WRITE_DMAREG(sc, reg, var) \ 100 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (var)) 101 102 #define PCSCP_READ_REG(sc, reg) \ 103 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2) 104 #define PCSCP_WRITE_REG(sc, reg, val) \ 105 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2, (val)) 106 107 /* 108 * Functions and the switch for the MI code. 109 */ 110 111 static u_char pcscp_read_reg(struct ncr53c9x_softc *, int); 112 static void pcscp_write_reg(struct ncr53c9x_softc *, int, u_char); 113 static int pcscp_dma_isintr(struct ncr53c9x_softc *); 114 static void pcscp_dma_reset(struct ncr53c9x_softc *); 115 static int pcscp_dma_intr(struct ncr53c9x_softc *); 116 static int pcscp_dma_setup(struct ncr53c9x_softc *, void **, size_t *, 117 int, size_t *); 118 static void pcscp_dma_go(struct ncr53c9x_softc *); 119 static void pcscp_dma_stop(struct ncr53c9x_softc *); 120 static int pcscp_dma_isactive(struct ncr53c9x_softc *); 121 122 static struct ncr53c9x_glue pcscp_glue = { 123 pcscp_read_reg, 124 pcscp_write_reg, 125 pcscp_dma_isintr, 126 pcscp_dma_reset, 127 pcscp_dma_intr, 128 pcscp_dma_setup, 129 pcscp_dma_go, 130 pcscp_dma_stop, 131 pcscp_dma_isactive, 132 NULL, /* gl_clear_latched_intr */ 133 }; 134 135 static int 136 pcscp_match(struct device *parent, struct cfdata *match, 137 void *aux) 138 { 139 struct pci_attach_args *pa = aux; 140 141 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 142 return 0; 143 144 switch (PCI_PRODUCT(pa->pa_id)) { 145 case PCI_PRODUCT_AMD_PCSCSI_PCI: 146 return 1; 147 } 148 return 0; 149 } 150 151 /* 152 * Attach this instance, and then all the sub-devices 153 */ 154 static void 155 pcscp_attach(struct device *parent, struct device *self, void *aux) 156 { 157 struct pci_attach_args *pa = aux; 158 struct pcscp_softc *esc = (void *)self; 159 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 160 bus_space_tag_t iot; 161 bus_space_handle_t ioh; 162 pci_intr_handle_t ih; 163 const char *intrstr; 164 pcireg_t csr; 165 bus_dma_segment_t seg; 166 int error, rseg; 167 char devinfo[256]; 168 169 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 170 printf(": %s\n", devinfo); 171 printf("%s", sc->sc_dev.dv_xname); 172 173 if (pci_mapreg_map(pa, IO_MAP_REG, PCI_MAPREG_TYPE_IO, 0, 174 &iot, &ioh, NULL, NULL)) { 175 printf(": unable to map registers\n"); 176 return; 177 } 178 179 sc->sc_glue = &pcscp_glue; 180 181 esc->sc_st = iot; 182 esc->sc_sh = ioh; 183 esc->sc_dmat = pa->pa_dmat; 184 185 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 186 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 187 csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE); 188 189 /* 190 * XXX More of this should be in ncr53c9x_attach(), but 191 * XXX should we really poke around the chip that much in 192 * XXX the MI code? Think about this more... 193 */ 194 195 /* 196 * Set up static configuration info. 197 */ 198 199 /* 200 * XXX should read configuration from EEPROM? 201 * 202 * MI ncr53c9x driver does not support configuration 203 * per each target device, though... 204 */ 205 sc->sc_id = 7; 206 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 207 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 208 sc->sc_cfg3 = NCRAMDCFG3_IDM | NCRAMDCFG3_FCLK; 209 sc->sc_cfg4 = NCRAMDCFG4_GE12NS | NCRAMDCFG4_RADE; 210 sc->sc_rev = NCR_VARIANT_AM53C974; 211 sc->sc_features = NCR_F_FASTSCSI; 212 sc->sc_cfg3_fscsi = NCRAMDCFG3_FSCSI; 213 sc->sc_freq = 40; /* MHz */ 214 215 /* 216 * XXX minsync and maxxfer _should_ be set up in MI code, 217 * XXX but it appears to have some dependency on what sort 218 * XXX of DMA we're hooked up to, etc. 219 */ 220 221 /* 222 * This is the value used to start sync negotiations 223 * Note that the NCR register "SYNCTP" is programmed 224 * in "clocks per byte", and has a minimum value of 4. 225 * The SCSI period used in negotiation is one-fourth 226 * of the time (in nanoseconds) needed to transfer one byte. 227 * Since the chip's clock is given in MHz, we have the following 228 * formula: 4 * period = (1000 / freq) * 4 229 */ 230 231 sc->sc_minsync = 1000 / sc->sc_freq; 232 233 /* Really no limit, but since we want to fit into the TCR... */ 234 sc->sc_maxxfer = 16 * 1024 * 1024; 235 236 /* 237 * Create the DMA maps for the data transfers. 238 */ 239 240 #define MDL_SEG_SIZE 0x1000 /* 4kbyte per segment */ 241 #define MDL_SEG_OFFSET 0x0FFF 242 #define MDL_SIZE (MAXPHYS / MDL_SEG_SIZE + 1) /* no hardware limit? */ 243 244 if (bus_dmamap_create(esc->sc_dmat, MAXPHYS, MDL_SIZE, MDL_SEG_SIZE, 245 MDL_SEG_SIZE, BUS_DMA_NOWAIT, &esc->sc_xfermap)) { 246 printf(": can't create DMA maps\n"); 247 return; 248 } 249 250 /* 251 * Allocate and map memory for the MDL. 252 */ 253 254 if ((error = bus_dmamem_alloc(esc->sc_dmat, 255 sizeof(uint32_t) * MDL_SIZE, PAGE_SIZE, 0, &seg, 1, &rseg, 256 BUS_DMA_NOWAIT)) != 0) { 257 printf(": unable to allocate memory for the MDL, error = %d\n", 258 error); 259 goto fail_0; 260 } 261 if ((error = bus_dmamem_map(esc->sc_dmat, &seg, rseg, 262 sizeof(uint32_t) * MDL_SIZE , (void **)&esc->sc_mdladdr, 263 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 264 printf(": unable to map the MDL memory, error = %d\n", error); 265 goto fail_1; 266 } 267 if ((error = bus_dmamap_create(esc->sc_dmat, 268 sizeof(uint32_t) * MDL_SIZE, 1, sizeof(uint32_t) * MDL_SIZE, 269 0, BUS_DMA_NOWAIT, &esc->sc_mdldmap)) != 0) { 270 printf(": unable to map_create for the MDL, error = %d\n", 271 error); 272 goto fail_2; 273 } 274 if ((error = bus_dmamap_load(esc->sc_dmat, esc->sc_mdldmap, 275 esc->sc_mdladdr, sizeof(uint32_t) * MDL_SIZE, 276 NULL, BUS_DMA_NOWAIT)) != 0) { 277 printf(": unable to load for the MDL, error = %d\n", error); 278 goto fail_3; 279 } 280 281 /* map and establish interrupt */ 282 if (pci_intr_map(pa, &ih)) { 283 printf(": couldn't map interrupt\n"); 284 goto fail_4; 285 } 286 287 intrstr = pci_intr_string(pa->pa_pc, ih); 288 esc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 289 ncr53c9x_intr, esc); 290 if (esc->sc_ih == NULL) { 291 printf(": couldn't establish interrupt"); 292 if (intrstr != NULL) 293 printf(" at %s", intrstr); 294 printf("\n"); 295 goto fail_4; 296 } 297 if (intrstr != NULL) 298 printf(": interrupting at %s\n", intrstr); 299 300 /* Do the common parts of attachment. */ 301 printf("%s", sc->sc_dev.dv_xname); 302 sc->sc_adapter.adapt_minphys = minphys; 303 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 304 ncr53c9x_attach(sc); 305 306 /* Turn on target selection using the `DMA' method */ 307 sc->sc_features |= NCR_F_DMASELECT; 308 309 return; 310 311 fail_4: 312 bus_dmamap_unload(esc->sc_dmat, esc->sc_mdldmap); 313 fail_3: 314 bus_dmamap_destroy(esc->sc_dmat, esc->sc_mdldmap); 315 fail_2: 316 bus_dmamem_unmap(esc->sc_dmat, (void *)esc->sc_mdldmap, 317 sizeof(uint32_t) * MDL_SIZE); 318 fail_1: 319 bus_dmamem_free(esc->sc_dmat, &seg, rseg); 320 fail_0: 321 bus_dmamap_destroy(esc->sc_dmat, esc->sc_xfermap); 322 } 323 324 CFATTACH_DECL(pcscp, sizeof(struct pcscp_softc), 325 pcscp_match, pcscp_attach, NULL, NULL); 326 327 /* 328 * Glue functions. 329 */ 330 331 static u_char 332 pcscp_read_reg(struct ncr53c9x_softc *sc, int reg) 333 { 334 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 335 336 return PCSCP_READ_REG(esc, reg); 337 } 338 339 static void 340 pcscp_write_reg(struct ncr53c9x_softc *sc, int reg, u_char v) 341 { 342 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 343 344 PCSCP_WRITE_REG(esc, reg, v); 345 } 346 347 static int 348 pcscp_dma_isintr(struct ncr53c9x_softc *sc) 349 { 350 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 351 352 return (PCSCP_READ_REG(esc, NCR_STAT) & NCRSTAT_INT) != 0; 353 } 354 355 static void 356 pcscp_dma_reset(struct ncr53c9x_softc *sc) 357 { 358 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 359 360 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE); 361 362 esc->sc_active = 0; 363 } 364 365 static int 366 pcscp_dma_intr(struct ncr53c9x_softc *sc) 367 { 368 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 369 int trans, resid, i; 370 bus_dmamap_t dmap = esc->sc_xfermap; 371 int datain = esc->sc_datain; 372 uint32_t dmastat; 373 char *p = NULL; 374 375 dmastat = READ_DMAREG(esc, DMA_STAT); 376 377 if (dmastat & DMASTAT_ERR) { 378 /* XXX not tested... */ 379 WRITE_DMAREG(esc, DMA_CMD, 380 DMACMD_ABORT | (datain ? DMACMD_DIR : 0)); 381 382 printf("%s: error: DMA error detected; Aborting.\n", 383 sc->sc_dev.dv_xname); 384 bus_dmamap_unload(esc->sc_dmat, dmap); 385 return -1; 386 } 387 388 if (dmastat & DMASTAT_ABT) { 389 /* XXX What should be done? */ 390 printf("%s: dma_intr: DMA aborted.\n", sc->sc_dev.dv_xname); 391 WRITE_DMAREG(esc, DMA_CMD, 392 DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 393 esc->sc_active = 0; 394 return 0; 395 } 396 397 #ifdef DIAGNOSTIC 398 /* This is an "assertion" :) */ 399 if (esc->sc_active == 0) 400 panic("pcscp dmaintr: DMA wasn't active"); 401 #endif 402 403 /* DMA has stopped */ 404 405 esc->sc_active = 0; 406 407 if (esc->sc_dmasize == 0) { 408 /* A "Transfer Pad" operation completed */ 409 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 410 PCSCP_READ_REG(esc, NCR_TCL) | 411 (PCSCP_READ_REG(esc, NCR_TCM) << 8), 412 PCSCP_READ_REG(esc, NCR_TCL), 413 PCSCP_READ_REG(esc, NCR_TCM))); 414 return 0; 415 } 416 417 resid = 0; 418 /* 419 * If a transfer onto the SCSI bus gets interrupted by the device 420 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 421 * as residual since the ESP counter registers get decremented as 422 * bytes are clocked into the FIFO. 423 */ 424 if (!datain && 425 (resid = (PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 426 NCR_DMA(("pcscp_dma_intr: empty esp FIFO of %d ", resid)); 427 } 428 429 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 430 /* 431 * `Terminal count' is off, so read the residue 432 * out of the ESP counter registers. 433 */ 434 if (datain) { 435 resid = PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF; 436 while (resid > 1) 437 resid = 438 PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF; 439 WRITE_DMAREG(esc, DMA_CMD, DMACMD_BLAST | DMACMD_MDL | 440 (datain ? DMACMD_DIR : 0)); 441 442 for (i = 0; i < 0x8000; i++) /* XXX 0x8000 ? */ 443 if (READ_DMAREG(esc, DMA_STAT) & DMASTAT_BCMP) 444 break; 445 446 /* See the below comments... */ 447 if (resid) 448 p = *esc->sc_dmaaddr; 449 } 450 451 resid += PCSCP_READ_REG(esc, NCR_TCL) | 452 (PCSCP_READ_REG(esc, NCR_TCM) << 8) | 453 (PCSCP_READ_REG(esc, NCR_TCH) << 16); 454 } else { 455 while ((dmastat & DMASTAT_DONE) == 0) 456 dmastat = READ_DMAREG(esc, DMA_STAT); 457 } 458 459 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 460 461 /* sync MDL */ 462 bus_dmamap_sync(esc->sc_dmat, esc->sc_mdldmap, 463 0, sizeof(uint32_t) * dmap->dm_nsegs, BUS_DMASYNC_POSTWRITE); 464 /* sync transfer buffer */ 465 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 466 datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 467 bus_dmamap_unload(esc->sc_dmat, dmap); 468 469 trans = esc->sc_dmasize - resid; 470 471 /* 472 * From the technical manual notes: 473 * 474 * `In some odd byte conditions, one residual byte will be left 475 * in the SCSI FIFO, and the FIFO flags will never count to 0. 476 * When this happens, the residual byte should be retrieved 477 * via PIO following completion of the BLAST operation.' 478 */ 479 480 if (p) { 481 p += trans; 482 *p = PCSCP_READ_REG(esc, NCR_FIFO); 483 trans++; 484 } 485 486 if (trans < 0) { /* transferred < 0 ? */ 487 #if 0 488 /* 489 * This situation can happen in perfectly normal operation 490 * if the ESP is reselected while using DMA to select 491 * another target. As such, don't print the warning. 492 */ 493 printf("%s: xfer (%d) > req (%d)\n", 494 sc->sc_dev.dv_xname, trans, esc->sc_dmasize); 495 #endif 496 trans = esc->sc_dmasize; 497 } 498 499 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 500 PCSCP_READ_REG(esc, NCR_TCL), 501 PCSCP_READ_REG(esc, NCR_TCM), 502 PCSCP_READ_REG(esc, NCR_TCH), 503 trans, resid)); 504 505 *esc->sc_dmalen -= trans; 506 *esc->sc_dmaaddr += trans; 507 508 return 0; 509 } 510 511 static int 512 pcscp_dma_setup(struct ncr53c9x_softc *sc, void **addr, size_t *len, 513 int datain, size_t *dmasize) 514 { 515 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 516 bus_dmamap_t dmap = esc->sc_xfermap; 517 uint32_t *mdl; 518 int error, nseg, seg; 519 bus_addr_t s_offset, s_addr; 520 521 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 522 523 esc->sc_dmaaddr = (void *)addr; 524 esc->sc_dmalen = len; 525 esc->sc_dmasize = *dmasize; 526 esc->sc_datain = datain; 527 528 #ifdef DIAGNOSTIC 529 if ((*dmasize / MDL_SEG_SIZE) > MDL_SIZE) 530 panic("pcscp: transfer size too large"); 531 #endif 532 533 /* 534 * No need to set up DMA in `Transfer Pad' operation. 535 * (case of *dmasize == 0) 536 */ 537 if (*dmasize == 0) 538 return 0; 539 540 error = bus_dmamap_load(esc->sc_dmat, dmap, *esc->sc_dmaaddr, 541 *esc->sc_dmalen, NULL, 542 ((sc->sc_nexus->xs->xs_control & XS_CTL_NOSLEEP) ? 543 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | 544 ((sc->sc_nexus->xs->xs_control & XS_CTL_DATA_IN) ? 545 BUS_DMA_READ : BUS_DMA_WRITE)); 546 if (error) { 547 printf("%s: unable to load dmamap, error = %d\n", 548 sc->sc_dev.dv_xname, error); 549 return error; 550 } 551 552 /* set transfer length */ 553 WRITE_DMAREG(esc, DMA_STC, *dmasize); 554 555 /* set up MDL */ 556 mdl = esc->sc_mdladdr; 557 nseg = dmap->dm_nsegs; 558 559 /* the first segment is possibly not aligned with 4k MDL boundary */ 560 s_addr = dmap->dm_segs[0].ds_addr; 561 s_offset = s_addr & MDL_SEG_OFFSET; 562 s_addr -= s_offset; 563 564 /* set the first MDL and offset */ 565 WRITE_DMAREG(esc, DMA_SPA, s_offset); 566 *mdl++ = htole32(s_addr); 567 568 /* the rest dmamap segments are aligned with 4k boundary */ 569 for (seg = 1; seg < nseg; seg++) 570 *mdl++ = htole32(dmap->dm_segs[seg].ds_addr); 571 572 return 0; 573 } 574 575 static void 576 pcscp_dma_go(struct ncr53c9x_softc *sc) 577 { 578 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 579 bus_dmamap_t dmap = esc->sc_xfermap, mdldmap = esc->sc_mdldmap; 580 int datain = esc->sc_datain; 581 582 /* No DMA transfer in Transfer Pad operation */ 583 if (esc->sc_dmasize == 0) 584 return; 585 586 /* sync transfer buffer */ 587 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 588 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 589 590 /* sync MDL */ 591 bus_dmamap_sync(esc->sc_dmat, mdldmap, 592 0, sizeof(uint32_t) * dmap->dm_nsegs, BUS_DMASYNC_PREWRITE); 593 594 /* set Starting MDL Address */ 595 WRITE_DMAREG(esc, DMA_SMDLA, mdldmap->dm_segs[0].ds_addr); 596 597 /* set DMA command register bits */ 598 /* XXX DMA Transfer Interrupt Enable bit is broken? */ 599 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | DMACMD_MDL | 600 /* DMACMD_INTE | */ 601 (datain ? DMACMD_DIR : 0)); 602 603 /* issue DMA start command */ 604 WRITE_DMAREG(esc, DMA_CMD, DMACMD_START | DMACMD_MDL | 605 /* DMACMD_INTE | */ 606 (datain ? DMACMD_DIR : 0)); 607 608 esc->sc_active = 1; 609 } 610 611 static void 612 pcscp_dma_stop(struct ncr53c9x_softc *sc) 613 { 614 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 615 616 /* DMA stop */ 617 /* XXX What should we do here ? */ 618 WRITE_DMAREG(esc, DMA_CMD, 619 DMACMD_ABORT | (esc->sc_datain ? DMACMD_DIR : 0)); 620 bus_dmamap_unload(esc->sc_dmat, esc->sc_xfermap); 621 622 esc->sc_active = 0; 623 } 624 625 static int 626 pcscp_dma_isactive(struct ncr53c9x_softc *sc) 627 { 628 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 629 630 /* XXX should check esc->sc_active? */ 631 if ((READ_DMAREG(esc, DMA_CMD) & DMACMD_CMD) != DMACMD_IDLE) 632 return 1; 633 return 0; 634 } 635