1 /* $NetBSD: pcscp.c,v 1.42 2008/04/13 04:55:53 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center; Izumi Tsutsui. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * pcscp.c: device dependent code for AMD Am53c974 (PCscsi-PCI) 42 * written by Izumi Tsutsui <tsutsui@NetBSD.org> 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: pcscp.c,v 1.42 2008/04/13 04:55:53 tsutsui Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/device.h> 51 #include <sys/buf.h> 52 53 #include <sys/bus.h> 54 #include <sys/intr.h> 55 56 #include <uvm/uvm_extern.h> 57 58 #include <dev/scsipi/scsipi_all.h> 59 #include <dev/scsipi/scsi_all.h> 60 #include <dev/scsipi/scsiconf.h> 61 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcidevs.h> 65 66 #include <dev/ic/ncr53c9xreg.h> 67 #include <dev/ic/ncr53c9xvar.h> 68 69 #include <dev/pci/pcscpreg.h> 70 71 #define IO_MAP_REG 0x10 72 73 struct pcscp_softc { 74 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 75 76 bus_space_tag_t sc_st; /* bus space tag */ 77 bus_space_handle_t sc_sh; /* bus space handle */ 78 void *sc_ih; /* interrupt cookie */ 79 80 bus_dma_tag_t sc_dmat; /* DMA tag */ 81 82 bus_dmamap_t sc_xfermap; /* DMA map for transfers */ 83 84 uint32_t *sc_mdladdr; /* MDL array */ 85 bus_dmamap_t sc_mdldmap; /* MDL DMA map */ 86 87 int sc_active; /* DMA state */ 88 int sc_datain; /* DMA Data Direction */ 89 size_t sc_dmasize; /* DMA size */ 90 uint8_t **sc_dmaaddr; /* DMA address */ 91 size_t *sc_dmalen; /* DMA length */ 92 }; 93 94 #define READ_DMAREG(sc, reg) \ 95 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 96 #define WRITE_DMAREG(sc, reg, var) \ 97 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (var)) 98 99 #define PCSCP_READ_REG(sc, reg) \ 100 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2) 101 #define PCSCP_WRITE_REG(sc, reg, val) \ 102 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2, (val)) 103 104 105 static int pcscp_match(device_t, cfdata_t, void *); 106 static void pcscp_attach(device_t, device_t, void *); 107 108 CFATTACH_DECL_NEW(pcscp, sizeof(struct pcscp_softc), 109 pcscp_match, pcscp_attach, NULL, NULL); 110 111 /* 112 * Functions and the switch for the MI code. 113 */ 114 115 static uint8_t pcscp_read_reg(struct ncr53c9x_softc *, int); 116 static void pcscp_write_reg(struct ncr53c9x_softc *, int, uint8_t); 117 static int pcscp_dma_isintr(struct ncr53c9x_softc *); 118 static void pcscp_dma_reset(struct ncr53c9x_softc *); 119 static int pcscp_dma_intr(struct ncr53c9x_softc *); 120 static int pcscp_dma_setup(struct ncr53c9x_softc *, uint8_t **, size_t *, 121 int, size_t *); 122 static void pcscp_dma_go(struct ncr53c9x_softc *); 123 static void pcscp_dma_stop(struct ncr53c9x_softc *); 124 static int pcscp_dma_isactive(struct ncr53c9x_softc *); 125 126 static struct ncr53c9x_glue pcscp_glue = { 127 pcscp_read_reg, 128 pcscp_write_reg, 129 pcscp_dma_isintr, 130 pcscp_dma_reset, 131 pcscp_dma_intr, 132 pcscp_dma_setup, 133 pcscp_dma_go, 134 pcscp_dma_stop, 135 pcscp_dma_isactive, 136 NULL, /* gl_clear_latched_intr */ 137 }; 138 139 static int 140 pcscp_match(device_t parent, cfdata_t cf, void *aux) 141 { 142 struct pci_attach_args *pa = aux; 143 144 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 145 return 0; 146 147 switch (PCI_PRODUCT(pa->pa_id)) { 148 case PCI_PRODUCT_AMD_PCSCSI_PCI: 149 return 1; 150 } 151 return 0; 152 } 153 154 /* 155 * Attach this instance, and then all the sub-devices 156 */ 157 static void 158 pcscp_attach(device_t parent, device_t self, void *aux) 159 { 160 struct pcscp_softc *esc = device_private(self); 161 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 162 struct pci_attach_args *pa = aux; 163 bus_space_tag_t iot; 164 bus_space_handle_t ioh; 165 pci_intr_handle_t ih; 166 const char *intrstr; 167 pcireg_t csr; 168 bus_dma_segment_t seg; 169 int error, rseg; 170 char devinfo[256]; 171 172 sc->sc_dev = self; 173 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 174 aprint_normal(": %s\n", devinfo); 175 aprint_normal("%s", device_xname(sc->sc_dev)); 176 177 if (pci_mapreg_map(pa, IO_MAP_REG, PCI_MAPREG_TYPE_IO, 0, 178 &iot, &ioh, NULL, NULL)) { 179 aprint_error(": unable to map registers\n"); 180 return; 181 } 182 183 sc->sc_glue = &pcscp_glue; 184 185 esc->sc_st = iot; 186 esc->sc_sh = ioh; 187 esc->sc_dmat = pa->pa_dmat; 188 189 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 190 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 191 csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE); 192 193 /* 194 * XXX More of this should be in ncr53c9x_attach(), but 195 * XXX should we really poke around the chip that much in 196 * XXX the MI code? Think about this more... 197 */ 198 199 /* 200 * Set up static configuration info. 201 */ 202 203 /* 204 * XXX should read configuration from EEPROM? 205 * 206 * MI ncr53c9x driver does not support configuration 207 * per each target device, though... 208 */ 209 sc->sc_id = 7; 210 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 211 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 212 sc->sc_cfg3 = NCRAMDCFG3_IDM | NCRAMDCFG3_FCLK; 213 sc->sc_cfg4 = NCRAMDCFG4_GE12NS | NCRAMDCFG4_RADE; 214 sc->sc_rev = NCR_VARIANT_AM53C974; 215 sc->sc_features = NCR_F_FASTSCSI; 216 sc->sc_cfg3_fscsi = NCRAMDCFG3_FSCSI; 217 sc->sc_freq = 40; /* MHz */ 218 219 /* 220 * XXX minsync and maxxfer _should_ be set up in MI code, 221 * XXX but it appears to have some dependency on what sort 222 * XXX of DMA we're hooked up to, etc. 223 */ 224 225 /* 226 * This is the value used to start sync negotiations 227 * Note that the NCR register "SYNCTP" is programmed 228 * in "clocks per byte", and has a minimum value of 4. 229 * The SCSI period used in negotiation is one-fourth 230 * of the time (in nanoseconds) needed to transfer one byte. 231 * Since the chip's clock is given in MHz, we have the following 232 * formula: 4 * period = (1000 / freq) * 4 233 */ 234 235 sc->sc_minsync = 1000 / sc->sc_freq; 236 237 /* Really no limit, but since we want to fit into the TCR... */ 238 sc->sc_maxxfer = 16 * 1024 * 1024; 239 240 /* 241 * Create the DMA maps for the data transfers. 242 */ 243 244 #define MDL_SEG_SIZE 0x1000 /* 4kbyte per segment */ 245 #define MDL_SEG_OFFSET 0x0FFF 246 #define MDL_SIZE (MAXPHYS / MDL_SEG_SIZE + 1) /* no hardware limit? */ 247 248 if (bus_dmamap_create(esc->sc_dmat, MAXPHYS, MDL_SIZE, MDL_SEG_SIZE, 249 MDL_SEG_SIZE, BUS_DMA_NOWAIT, &esc->sc_xfermap)) { 250 aprint_error(": can't create DMA maps\n"); 251 return; 252 } 253 254 /* 255 * Allocate and map memory for the MDL. 256 */ 257 258 if ((error = bus_dmamem_alloc(esc->sc_dmat, 259 sizeof(uint32_t) * MDL_SIZE, PAGE_SIZE, 0, &seg, 1, &rseg, 260 BUS_DMA_NOWAIT)) != 0) { 261 aprint_error(": unable to allocate memory for the MDL," 262 " error = %d\n", error); 263 goto fail_0; 264 } 265 if ((error = bus_dmamem_map(esc->sc_dmat, &seg, rseg, 266 sizeof(uint32_t) * MDL_SIZE , (void **)&esc->sc_mdladdr, 267 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 268 aprint_error(": unable to map the MDL memory, error = %d\n", 269 error); 270 goto fail_1; 271 } 272 if ((error = bus_dmamap_create(esc->sc_dmat, 273 sizeof(uint32_t) * MDL_SIZE, 1, sizeof(uint32_t) * MDL_SIZE, 274 0, BUS_DMA_NOWAIT, &esc->sc_mdldmap)) != 0) { 275 aprint_error(": unable to map_create for the MDL, error = %d\n", 276 error); 277 goto fail_2; 278 } 279 if ((error = bus_dmamap_load(esc->sc_dmat, esc->sc_mdldmap, 280 esc->sc_mdladdr, sizeof(uint32_t) * MDL_SIZE, 281 NULL, BUS_DMA_NOWAIT)) != 0) { 282 aprint_error(": unable to load for the MDL, error = %d\n", 283 error); 284 goto fail_3; 285 } 286 287 /* map and establish interrupt */ 288 if (pci_intr_map(pa, &ih)) { 289 aprint_error(": couldn't map interrupt\n"); 290 goto fail_4; 291 } 292 293 intrstr = pci_intr_string(pa->pa_pc, ih); 294 esc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 295 ncr53c9x_intr, esc); 296 if (esc->sc_ih == NULL) { 297 aprint_error(": couldn't establish interrupt"); 298 if (intrstr != NULL) 299 aprint_error(" at %s", intrstr); 300 aprint_error("\n"); 301 goto fail_4; 302 } 303 if (intrstr != NULL) { 304 aprint_normal(": interrupting at %s\n", intrstr); 305 aprint_normal("%s", device_xname(sc->sc_dev)); 306 } 307 308 /* Do the common parts of attachment. */ 309 sc->sc_adapter.adapt_minphys = minphys; 310 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 311 ncr53c9x_attach(sc); 312 313 /* Turn on target selection using the `DMA' method */ 314 sc->sc_features |= NCR_F_DMASELECT; 315 316 return; 317 318 fail_4: 319 bus_dmamap_unload(esc->sc_dmat, esc->sc_mdldmap); 320 fail_3: 321 bus_dmamap_destroy(esc->sc_dmat, esc->sc_mdldmap); 322 fail_2: 323 bus_dmamem_unmap(esc->sc_dmat, (void *)esc->sc_mdldmap, 324 sizeof(uint32_t) * MDL_SIZE); 325 fail_1: 326 bus_dmamem_free(esc->sc_dmat, &seg, rseg); 327 fail_0: 328 bus_dmamap_destroy(esc->sc_dmat, esc->sc_xfermap); 329 } 330 331 /* 332 * Glue functions. 333 */ 334 335 static uint8_t 336 pcscp_read_reg(struct ncr53c9x_softc *sc, int reg) 337 { 338 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 339 340 return PCSCP_READ_REG(esc, reg); 341 } 342 343 static void 344 pcscp_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t v) 345 { 346 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 347 348 PCSCP_WRITE_REG(esc, reg, v); 349 } 350 351 static int 352 pcscp_dma_isintr(struct ncr53c9x_softc *sc) 353 { 354 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 355 356 return (PCSCP_READ_REG(esc, NCR_STAT) & NCRSTAT_INT) != 0; 357 } 358 359 static void 360 pcscp_dma_reset(struct ncr53c9x_softc *sc) 361 { 362 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 363 364 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE); 365 366 esc->sc_active = 0; 367 } 368 369 static int 370 pcscp_dma_intr(struct ncr53c9x_softc *sc) 371 { 372 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 373 int trans, resid, i; 374 bus_dmamap_t dmap = esc->sc_xfermap; 375 int datain = esc->sc_datain; 376 uint32_t dmastat; 377 uint8_t *p = NULL; 378 379 dmastat = READ_DMAREG(esc, DMA_STAT); 380 381 if (dmastat & DMASTAT_ERR) { 382 /* XXX not tested... */ 383 WRITE_DMAREG(esc, DMA_CMD, 384 DMACMD_ABORT | (datain ? DMACMD_DIR : 0)); 385 386 printf("%s: error: DMA error detected; Aborting.\n", 387 device_xname(sc->sc_dev)); 388 bus_dmamap_unload(esc->sc_dmat, dmap); 389 return -1; 390 } 391 392 if (dmastat & DMASTAT_ABT) { 393 /* XXX What should be done? */ 394 printf("%s: %s: DMA aborted.\n", 395 device_xname(sc->sc_dev), __func__); 396 WRITE_DMAREG(esc, DMA_CMD, 397 DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 398 esc->sc_active = 0; 399 return 0; 400 } 401 402 #ifdef DIAGNOSTIC 403 /* This is an "assertion" :) */ 404 if (esc->sc_active == 0) 405 panic("%s: %s: DMA wasn't active", 406 device_xname(sc->sc_dev), __func__); 407 #endif 408 409 /* DMA has stopped */ 410 411 esc->sc_active = 0; 412 413 if (esc->sc_dmasize == 0) { 414 /* A "Transfer Pad" operation completed */ 415 NCR_DMA(("%s: discarded %d bytes (tcl=%d, tcm=%d)\n", 416 __func__, 417 PCSCP_READ_REG(esc, NCR_TCL) | 418 (PCSCP_READ_REG(esc, NCR_TCM) << 8), 419 PCSCP_READ_REG(esc, NCR_TCL), 420 PCSCP_READ_REG(esc, NCR_TCM))); 421 return 0; 422 } 423 424 resid = 0; 425 /* 426 * If a transfer onto the SCSI bus gets interrupted by the device 427 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 428 * as residual since the ESP counter registers get decremented as 429 * bytes are clocked into the FIFO. 430 */ 431 if (!datain && 432 (resid = (PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 433 NCR_DMA(("%s: empty esp FIFO of %d ", __func__, resid)); 434 } 435 436 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 437 /* 438 * `Terminal count' is off, so read the residue 439 * out of the ESP counter registers. 440 */ 441 if (datain) { 442 resid = PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF; 443 while (resid > 1) 444 resid = 445 PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF; 446 WRITE_DMAREG(esc, DMA_CMD, DMACMD_BLAST | DMACMD_MDL | 447 (datain ? DMACMD_DIR : 0)); 448 449 for (i = 0; i < 1000; i++) { /* XXX */ 450 if (READ_DMAREG(esc, DMA_STAT) & DMASTAT_BCMP) 451 break; 452 DELAY(1); 453 } 454 455 /* See the below comments... */ 456 if (resid) 457 p = *esc->sc_dmaaddr; 458 } 459 460 resid += PCSCP_READ_REG(esc, NCR_TCL) | 461 (PCSCP_READ_REG(esc, NCR_TCM) << 8) | 462 (PCSCP_READ_REG(esc, NCR_TCH) << 16); 463 } else { 464 while ((dmastat & DMASTAT_DONE) == 0) 465 dmastat = READ_DMAREG(esc, DMA_STAT); 466 } 467 468 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 469 470 /* sync MDL */ 471 bus_dmamap_sync(esc->sc_dmat, esc->sc_mdldmap, 472 0, sizeof(uint32_t) * dmap->dm_nsegs, BUS_DMASYNC_POSTWRITE); 473 /* sync transfer buffer */ 474 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 475 datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 476 bus_dmamap_unload(esc->sc_dmat, dmap); 477 478 trans = esc->sc_dmasize - resid; 479 480 /* 481 * From the technical manual notes: 482 * 483 * `In some odd byte conditions, one residual byte will be left 484 * in the SCSI FIFO, and the FIFO flags will never count to 0. 485 * When this happens, the residual byte should be retrieved 486 * via PIO following completion of the BLAST operation.' 487 */ 488 489 if (p) { 490 p += trans; 491 *p = PCSCP_READ_REG(esc, NCR_FIFO); 492 trans++; 493 } 494 495 if (trans < 0) { /* transferred < 0 ? */ 496 #if 0 497 /* 498 * This situation can happen in perfectly normal operation 499 * if the ESP is reselected while using DMA to select 500 * another target. As such, don't print the warning. 501 */ 502 printf("%s: xfer (%d) > req (%d)\n", 503 device_xname(sc->sc_dev), trans, esc->sc_dmasize); 504 #endif 505 trans = esc->sc_dmasize; 506 } 507 508 NCR_DMA(("%s: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 509 __func__, 510 PCSCP_READ_REG(esc, NCR_TCL), 511 PCSCP_READ_REG(esc, NCR_TCM), 512 PCSCP_READ_REG(esc, NCR_TCH), 513 trans, resid)); 514 515 *esc->sc_dmalen -= trans; 516 *esc->sc_dmaaddr += trans; 517 518 return 0; 519 } 520 521 static int 522 pcscp_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len, 523 int datain, size_t *dmasize) 524 { 525 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 526 bus_dmamap_t dmap = esc->sc_xfermap; 527 uint32_t *mdl; 528 int error, nseg, seg; 529 bus_addr_t s_offset, s_addr; 530 531 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 532 533 esc->sc_dmaaddr = addr; 534 esc->sc_dmalen = len; 535 esc->sc_dmasize = *dmasize; 536 esc->sc_datain = datain; 537 538 #ifdef DIAGNOSTIC 539 if ((*dmasize / MDL_SEG_SIZE) > MDL_SIZE) 540 panic("%s: transfer size too large", device_xname(sc->sc_dev)); 541 #endif 542 543 /* 544 * No need to set up DMA in `Transfer Pad' operation. 545 * (case of *dmasize == 0) 546 */ 547 if (*dmasize == 0) 548 return 0; 549 550 error = bus_dmamap_load(esc->sc_dmat, dmap, *esc->sc_dmaaddr, 551 *esc->sc_dmalen, NULL, 552 ((sc->sc_nexus->xs->xs_control & XS_CTL_NOSLEEP) ? 553 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | 554 ((sc->sc_nexus->xs->xs_control & XS_CTL_DATA_IN) ? 555 BUS_DMA_READ : BUS_DMA_WRITE)); 556 if (error) { 557 printf("%s: unable to load dmamap, error = %d\n", 558 device_xname(sc->sc_dev), error); 559 return error; 560 } 561 562 /* set transfer length */ 563 WRITE_DMAREG(esc, DMA_STC, *dmasize); 564 565 /* set up MDL */ 566 mdl = esc->sc_mdladdr; 567 nseg = dmap->dm_nsegs; 568 569 /* the first segment is possibly not aligned with 4k MDL boundary */ 570 s_addr = dmap->dm_segs[0].ds_addr; 571 s_offset = s_addr & MDL_SEG_OFFSET; 572 s_addr -= s_offset; 573 574 /* set the first MDL and offset */ 575 WRITE_DMAREG(esc, DMA_SPA, s_offset); 576 *mdl++ = htole32(s_addr); 577 578 /* the rest dmamap segments are aligned with 4k boundary */ 579 for (seg = 1; seg < nseg; seg++) 580 *mdl++ = htole32(dmap->dm_segs[seg].ds_addr); 581 582 return 0; 583 } 584 585 static void 586 pcscp_dma_go(struct ncr53c9x_softc *sc) 587 { 588 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 589 bus_dmamap_t dmap = esc->sc_xfermap, mdldmap = esc->sc_mdldmap; 590 int datain = esc->sc_datain; 591 592 /* No DMA transfer in Transfer Pad operation */ 593 if (esc->sc_dmasize == 0) 594 return; 595 596 /* sync transfer buffer */ 597 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 598 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 599 600 /* sync MDL */ 601 bus_dmamap_sync(esc->sc_dmat, mdldmap, 602 0, sizeof(uint32_t) * dmap->dm_nsegs, BUS_DMASYNC_PREWRITE); 603 604 /* set Starting MDL Address */ 605 WRITE_DMAREG(esc, DMA_SMDLA, mdldmap->dm_segs[0].ds_addr); 606 607 /* set DMA command register bits */ 608 /* XXX DMA Transfer Interrupt Enable bit is broken? */ 609 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | DMACMD_MDL | 610 /* DMACMD_INTE | */ 611 (datain ? DMACMD_DIR : 0)); 612 613 /* issue DMA start command */ 614 WRITE_DMAREG(esc, DMA_CMD, DMACMD_START | DMACMD_MDL | 615 /* DMACMD_INTE | */ 616 (datain ? DMACMD_DIR : 0)); 617 618 esc->sc_active = 1; 619 } 620 621 static void 622 pcscp_dma_stop(struct ncr53c9x_softc *sc) 623 { 624 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 625 626 /* DMA stop */ 627 /* XXX What should we do here ? */ 628 WRITE_DMAREG(esc, DMA_CMD, 629 DMACMD_ABORT | (esc->sc_datain ? DMACMD_DIR : 0)); 630 bus_dmamap_unload(esc->sc_dmat, esc->sc_xfermap); 631 632 esc->sc_active = 0; 633 } 634 635 static int 636 pcscp_dma_isactive(struct ncr53c9x_softc *sc) 637 { 638 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 639 640 /* XXX should check esc->sc_active? */ 641 if ((READ_DMAREG(esc, DMA_CMD) & DMACMD_CMD) != DMACMD_IDLE) 642 return 1; 643 return 0; 644 } 645