1 /* $NetBSD: pcscp.c,v 1.29 2004/04/23 21:13:07 itojun Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center; Izumi Tsutsui. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * pcscp.c: device dependent code for AMD Am53c974 (PCscsi-PCI) 42 * written by Izumi Tsutsui <tsutsui@ceres.dti.ne.jp> 43 * 44 * Technical manual available at 45 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/19113.pdf 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: pcscp.c,v 1.29 2004/04/23 21:13:07 itojun Exp $"); 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/device.h> 54 #include <sys/buf.h> 55 56 #include <machine/bus.h> 57 #include <machine/intr.h> 58 59 #include <uvm/uvm_extern.h> 60 61 #include <dev/scsipi/scsipi_all.h> 62 #include <dev/scsipi/scsi_all.h> 63 #include <dev/scsipi/scsiconf.h> 64 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcivar.h> 67 #include <dev/pci/pcidevs.h> 68 69 #include <dev/ic/ncr53c9xreg.h> 70 #include <dev/ic/ncr53c9xvar.h> 71 72 #include <dev/pci/pcscpreg.h> 73 74 #define IO_MAP_REG 0x10 75 76 struct pcscp_softc { 77 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 78 79 bus_space_tag_t sc_st; /* bus space tag */ 80 bus_space_handle_t sc_sh; /* bus space handle */ 81 void *sc_ih; /* interrupt cookie */ 82 83 bus_dma_tag_t sc_dmat; /* DMA tag */ 84 85 bus_dmamap_t sc_xfermap; /* DMA map for transfers */ 86 87 u_int32_t *sc_mdladdr; /* MDL array */ 88 bus_dmamap_t sc_mdldmap; /* MDL DMA map */ 89 90 int sc_active; /* DMA state */ 91 int sc_datain; /* DMA Data Direction */ 92 size_t sc_dmasize; /* DMA size */ 93 char **sc_dmaaddr; /* DMA address */ 94 size_t *sc_dmalen; /* DMA length */ 95 }; 96 97 #define READ_DMAREG(sc, reg) \ 98 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 99 #define WRITE_DMAREG(sc, reg, var) \ 100 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (var)) 101 102 #define PCSCP_READ_REG(sc, reg) \ 103 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2) 104 #define PCSCP_WRITE_REG(sc, reg, val) \ 105 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2, (val)) 106 107 int pcscp_match(struct device *, struct cfdata *, void *); 108 void pcscp_attach(struct device *, struct device *, void *); 109 110 CFATTACH_DECL(pcscp, sizeof(struct pcscp_softc), 111 pcscp_match, pcscp_attach, NULL, NULL); 112 113 /* 114 * Functions and the switch for the MI code. 115 */ 116 117 u_char pcscp_read_reg(struct ncr53c9x_softc *, int); 118 void pcscp_write_reg(struct ncr53c9x_softc *, int, u_char); 119 int pcscp_dma_isintr(struct ncr53c9x_softc *); 120 void pcscp_dma_reset(struct ncr53c9x_softc *); 121 int pcscp_dma_intr(struct ncr53c9x_softc *); 122 int pcscp_dma_setup(struct ncr53c9x_softc *, caddr_t *, size_t *, int, 123 size_t *); 124 void pcscp_dma_go(struct ncr53c9x_softc *); 125 void pcscp_dma_stop(struct ncr53c9x_softc *); 126 int pcscp_dma_isactive(struct ncr53c9x_softc *); 127 128 struct ncr53c9x_glue pcscp_glue = { 129 pcscp_read_reg, 130 pcscp_write_reg, 131 pcscp_dma_isintr, 132 pcscp_dma_reset, 133 pcscp_dma_intr, 134 pcscp_dma_setup, 135 pcscp_dma_go, 136 pcscp_dma_stop, 137 pcscp_dma_isactive, 138 NULL, /* gl_clear_latched_intr */ 139 }; 140 141 int 142 pcscp_match(parent, match, aux) 143 struct device *parent; 144 struct cfdata *match; 145 void *aux; 146 { 147 struct pci_attach_args *pa = aux; 148 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 149 return 0; 150 151 switch (PCI_PRODUCT(pa->pa_id)) { 152 case PCI_PRODUCT_AMD_PCSCSI_PCI: 153 return 1; 154 } 155 return 0; 156 } 157 158 /* 159 * Attach this instance, and then all the sub-devices 160 */ 161 void 162 pcscp_attach(parent, self, aux) 163 struct device *parent, *self; 164 void *aux; 165 { 166 struct pci_attach_args *pa = aux; 167 struct pcscp_softc *esc = (void *)self; 168 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 169 bus_space_tag_t iot; 170 bus_space_handle_t ioh; 171 pci_intr_handle_t ih; 172 const char *intrstr; 173 pcireg_t csr; 174 bus_dma_segment_t seg; 175 int error, rseg; 176 char devinfo[256]; 177 178 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 179 printf(": %s\n", devinfo); 180 printf("%s", sc->sc_dev.dv_xname); 181 182 if (pci_mapreg_map(pa, IO_MAP_REG, PCI_MAPREG_TYPE_IO, 0, 183 &iot, &ioh, NULL, NULL)) { 184 printf(": unable to map registers\n"); 185 return; 186 } 187 188 sc->sc_glue = &pcscp_glue; 189 190 esc->sc_st = iot; 191 esc->sc_sh = ioh; 192 esc->sc_dmat = pa->pa_dmat; 193 194 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 195 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 196 csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE); 197 198 /* 199 * XXX More of this should be in ncr53c9x_attach(), but 200 * XXX should we really poke around the chip that much in 201 * XXX the MI code? Think about this more... 202 */ 203 204 /* 205 * Set up static configuration info. 206 */ 207 208 /* 209 * XXX should read configuration from EEPROM? 210 * 211 * MI ncr53c9x driver does not support configuration 212 * per each target device, though... 213 */ 214 sc->sc_id = 7; 215 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 216 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 217 sc->sc_cfg3 = NCRAMDCFG3_IDM | NCRAMDCFG3_FCLK; 218 sc->sc_cfg4 = NCRAMDCFG4_GE12NS | NCRAMDCFG4_RADE; 219 sc->sc_rev = NCR_VARIANT_AM53C974; 220 sc->sc_features = NCR_F_FASTSCSI; 221 sc->sc_cfg3_fscsi = NCRAMDCFG3_FSCSI; 222 sc->sc_freq = 40; /* MHz */ 223 224 /* 225 * XXX minsync and maxxfer _should_ be set up in MI code, 226 * XXX but it appears to have some dependency on what sort 227 * XXX of DMA we're hooked up to, etc. 228 */ 229 230 /* 231 * This is the value used to start sync negotiations 232 * Note that the NCR register "SYNCTP" is programmed 233 * in "clocks per byte", and has a minimum value of 4. 234 * The SCSI period used in negotiation is one-fourth 235 * of the time (in nanoseconds) needed to transfer one byte. 236 * Since the chip's clock is given in MHz, we have the following 237 * formula: 4 * period = (1000 / freq) * 4 238 */ 239 240 sc->sc_minsync = 1000 / sc->sc_freq; 241 242 /* Really no limit, but since we want to fit into the TCR... */ 243 sc->sc_maxxfer = 16 * 1024 * 1024; 244 245 /* 246 * Create the DMA maps for the data transfers. 247 */ 248 249 #define MDL_SEG_SIZE 0x1000 /* 4kbyte per segment */ 250 #define MDL_SEG_OFFSET 0x0FFF 251 #define MDL_SIZE (MAXPHYS / MDL_SEG_SIZE + 1) /* no hardware limit? */ 252 253 if (bus_dmamap_create(esc->sc_dmat, MAXPHYS, MDL_SIZE, MDL_SEG_SIZE, 254 MDL_SEG_SIZE, BUS_DMA_NOWAIT, &esc->sc_xfermap)) { 255 printf(": can't create DMA maps\n"); 256 return; 257 } 258 259 /* 260 * Allocate and map memory for the MDL. 261 */ 262 263 if ((error = bus_dmamem_alloc(esc->sc_dmat, 264 sizeof(u_int32_t) * MDL_SIZE, PAGE_SIZE, 0, &seg, 1, &rseg, 265 BUS_DMA_NOWAIT)) != 0) { 266 printf(": unable to allocate memory for the MDL, error = %d\n", 267 error); 268 return; 269 } 270 if ((error = bus_dmamem_map(esc->sc_dmat, &seg, rseg, 271 sizeof(u_int32_t) * MDL_SIZE , (caddr_t *)&esc->sc_mdladdr, 272 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 273 printf(": unable to map the MDL memory, error = %d\n", error); 274 return; 275 } 276 if ((error = bus_dmamap_create(esc->sc_dmat, 277 sizeof(u_int32_t) * MDL_SIZE, 1, sizeof(u_int32_t) * MDL_SIZE, 278 0, BUS_DMA_NOWAIT, &esc->sc_mdldmap)) != 0) { 279 printf(": unable to map_create for the MDL, error = %d\n", 280 error); 281 return; 282 } 283 if ((error = bus_dmamap_load(esc->sc_dmat, esc->sc_mdldmap, 284 esc->sc_mdladdr, sizeof(u_int32_t) * MDL_SIZE, 285 NULL, BUS_DMA_NOWAIT)) != 0) { 286 printf(": unable to load for the MDL, error = %d\n", error); 287 return; 288 } 289 290 /* map and establish interrupt */ 291 if (pci_intr_map(pa, &ih)) { 292 printf(": couldn't map interrupt\n"); 293 return; 294 } 295 296 intrstr = pci_intr_string(pa->pa_pc, ih); 297 esc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 298 ncr53c9x_intr, esc); 299 if (esc->sc_ih == NULL) { 300 printf(": couldn't establish interrupt"); 301 if (intrstr != NULL) 302 printf(" at %s", intrstr); 303 printf("\n"); 304 return; 305 } 306 if (intrstr != NULL) 307 printf(": interrupting at %s\n", intrstr); 308 309 /* Do the common parts of attachment. */ 310 printf("%s", sc->sc_dev.dv_xname); 311 sc->sc_adapter.adapt_minphys = minphys; 312 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 313 ncr53c9x_attach(sc); 314 315 /* Turn on target selection using the `DMA' method */ 316 sc->sc_features |= NCR_F_DMASELECT; 317 } 318 319 /* 320 * Glue functions. 321 */ 322 323 u_char 324 pcscp_read_reg(sc, reg) 325 struct ncr53c9x_softc *sc; 326 int reg; 327 { 328 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 329 330 return PCSCP_READ_REG(esc, reg); 331 } 332 333 void 334 pcscp_write_reg(sc, reg, v) 335 struct ncr53c9x_softc *sc; 336 int reg; 337 u_char v; 338 { 339 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 340 341 PCSCP_WRITE_REG(esc, reg, v); 342 } 343 344 int 345 pcscp_dma_isintr(sc) 346 struct ncr53c9x_softc *sc; 347 { 348 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 349 350 return (PCSCP_READ_REG(esc, NCR_STAT) & NCRSTAT_INT) != 0; 351 } 352 353 void 354 pcscp_dma_reset(sc) 355 struct ncr53c9x_softc *sc; 356 { 357 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 358 359 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE); 360 361 esc->sc_active = 0; 362 } 363 364 int 365 pcscp_dma_intr(sc) 366 struct ncr53c9x_softc *sc; 367 { 368 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 369 int trans, resid, i; 370 bus_dmamap_t dmap = esc->sc_xfermap; 371 int datain = esc->sc_datain; 372 u_int32_t dmastat; 373 char *p = NULL; 374 375 dmastat = READ_DMAREG(esc, DMA_STAT); 376 377 if (dmastat & DMASTAT_ERR) { 378 /* XXX not tested... */ 379 WRITE_DMAREG(esc, DMA_CMD, 380 DMACMD_ABORT | (datain ? DMACMD_DIR : 0)); 381 382 printf("%s: error: DMA error detected; Aborting.\n", 383 sc->sc_dev.dv_xname); 384 bus_dmamap_unload(esc->sc_dmat, dmap); 385 return -1; 386 } 387 388 if (dmastat & DMASTAT_ABT) { 389 /* XXX What should be done? */ 390 printf("%s: dma_intr: DMA aborted.\n", sc->sc_dev.dv_xname); 391 WRITE_DMAREG(esc, DMA_CMD, 392 DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 393 esc->sc_active = 0; 394 return 0; 395 } 396 397 #ifdef DIAGNOSTIC 398 /* This is an "assertion" :) */ 399 if (esc->sc_active == 0) 400 panic("pcscp dmaintr: DMA wasn't active"); 401 #endif 402 403 /* DMA has stopped */ 404 405 esc->sc_active = 0; 406 407 if (esc->sc_dmasize == 0) { 408 /* A "Transfer Pad" operation completed */ 409 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 410 PCSCP_READ_REG(esc, NCR_TCL) | 411 (PCSCP_READ_REG(esc, NCR_TCM) << 8), 412 PCSCP_READ_REG(esc, NCR_TCL), 413 PCSCP_READ_REG(esc, NCR_TCM))); 414 return 0; 415 } 416 417 resid = 0; 418 /* 419 * If a transfer onto the SCSI bus gets interrupted by the device 420 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 421 * as residual since the ESP counter registers get decremented as 422 * bytes are clocked into the FIFO. 423 */ 424 if (!datain && 425 (resid = (PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 426 NCR_DMA(("pcscp_dma_intr: empty esp FIFO of %d ", resid)); 427 } 428 429 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 430 /* 431 * `Terminal count' is off, so read the residue 432 * out of the ESP counter registers. 433 */ 434 if (datain) { 435 resid = PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF; 436 while (resid > 1) 437 resid = 438 PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF; 439 WRITE_DMAREG(esc, DMA_CMD, DMACMD_BLAST | DMACMD_MDL | 440 (datain ? DMACMD_DIR : 0)); 441 442 for (i = 0; i < 0x8000; i++) /* XXX 0x8000 ? */ 443 if (READ_DMAREG(esc, DMA_STAT) & DMASTAT_BCMP) 444 break; 445 446 /* See the below comments... */ 447 if (resid) 448 p = *esc->sc_dmaaddr; 449 } 450 451 resid += PCSCP_READ_REG(esc, NCR_TCL) | 452 (PCSCP_READ_REG(esc, NCR_TCM) << 8) | 453 (PCSCP_READ_REG(esc, NCR_TCH) << 16); 454 } else { 455 while ((dmastat & DMASTAT_DONE) == 0) 456 dmastat = READ_DMAREG(esc, DMA_STAT); 457 } 458 459 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 460 461 /* sync MDL */ 462 bus_dmamap_sync(esc->sc_dmat, esc->sc_mdldmap, 463 0, sizeof(u_int32_t) * dmap->dm_nsegs, BUS_DMASYNC_POSTWRITE); 464 /* sync transfer buffer */ 465 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 466 datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 467 bus_dmamap_unload(esc->sc_dmat, dmap); 468 469 trans = esc->sc_dmasize - resid; 470 471 /* 472 * From the technical manual notes: 473 * 474 * `In some odd byte conditions, one residual byte will be left 475 * in the SCSI FIFO, and the FIFO flags will never count to 0. 476 * When this happens, the residual byte should be retrieved 477 * via PIO following completion of the BLAST operation.' 478 */ 479 480 if (p) { 481 p += trans; 482 *p = PCSCP_READ_REG(esc, NCR_FIFO); 483 trans++; 484 } 485 486 if (trans < 0) { /* transferred < 0 ? */ 487 #if 0 488 /* 489 * This situation can happen in perfectly normal operation 490 * if the ESP is reselected while using DMA to select 491 * another target. As such, don't print the warning. 492 */ 493 printf("%s: xfer (%d) > req (%d)\n", 494 sc->sc_dev.dv_xname, trans, esc->sc_dmasize); 495 #endif 496 trans = esc->sc_dmasize; 497 } 498 499 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 500 PCSCP_READ_REG(esc, NCR_TCL), 501 PCSCP_READ_REG(esc, NCR_TCM), 502 PCSCP_READ_REG(esc, NCR_TCH), 503 trans, resid)); 504 505 *esc->sc_dmalen -= trans; 506 *esc->sc_dmaaddr += trans; 507 508 return 0; 509 } 510 511 int 512 pcscp_dma_setup(sc, addr, len, datain, dmasize) 513 struct ncr53c9x_softc *sc; 514 caddr_t *addr; 515 size_t *len; 516 int datain; 517 size_t *dmasize; 518 { 519 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 520 bus_dmamap_t dmap = esc->sc_xfermap; 521 u_int32_t *mdl; 522 int error, nseg, seg; 523 bus_addr_t s_offset, s_addr; 524 525 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 526 527 esc->sc_dmaaddr = addr; 528 esc->sc_dmalen = len; 529 esc->sc_dmasize = *dmasize; 530 esc->sc_datain = datain; 531 532 #ifdef DIAGNOSTIC 533 if ((*dmasize / MDL_SEG_SIZE) > MDL_SIZE) 534 panic("pcscp: transfer size too large"); 535 #endif 536 537 /* 538 * No need to set up DMA in `Transfer Pad' operation. 539 * (case of *dmasize == 0) 540 */ 541 if (*dmasize == 0) 542 return 0; 543 544 error = bus_dmamap_load(esc->sc_dmat, dmap, *esc->sc_dmaaddr, 545 *esc->sc_dmalen, NULL, 546 ((sc->sc_nexus->xs->xs_control & XS_CTL_NOSLEEP) ? 547 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | 548 ((sc->sc_nexus->xs->xs_control & XS_CTL_DATA_IN) ? 549 BUS_DMA_READ : BUS_DMA_WRITE)); 550 if (error) { 551 printf("%s: unable to load dmamap, error = %d\n", 552 sc->sc_dev.dv_xname, error); 553 return error; 554 } 555 556 /* set transfer length */ 557 WRITE_DMAREG(esc, DMA_STC, *dmasize); 558 559 /* set up MDL */ 560 mdl = esc->sc_mdladdr; 561 nseg = dmap->dm_nsegs; 562 563 /* the first segment is possibly not aligned with 4k MDL boundary */ 564 s_addr = dmap->dm_segs[0].ds_addr; 565 s_offset = s_addr & MDL_SEG_OFFSET; 566 s_addr -= s_offset; 567 568 /* set the first MDL and offset */ 569 WRITE_DMAREG(esc, DMA_SPA, s_offset); 570 *mdl++ = htole32(s_addr); 571 572 /* the rest dmamap segments are aligned with 4k boundary */ 573 for (seg = 1; seg < nseg; seg++) 574 *mdl++ = htole32(dmap->dm_segs[seg].ds_addr); 575 576 return 0; 577 } 578 579 void 580 pcscp_dma_go(sc) 581 struct ncr53c9x_softc *sc; 582 { 583 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 584 bus_dmamap_t dmap = esc->sc_xfermap, mdldmap = esc->sc_mdldmap; 585 int datain = esc->sc_datain; 586 587 /* No DMA transfer in Transfer Pad operation */ 588 if (esc->sc_dmasize == 0) 589 return; 590 591 /* sync transfer buffer */ 592 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 593 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 594 595 /* sync MDL */ 596 bus_dmamap_sync(esc->sc_dmat, mdldmap, 597 0, sizeof(u_int32_t) * dmap->dm_nsegs, BUS_DMASYNC_PREWRITE); 598 599 /* set Starting MDL Address */ 600 WRITE_DMAREG(esc, DMA_SMDLA, mdldmap->dm_segs[0].ds_addr); 601 602 /* set DMA command register bits */ 603 /* XXX DMA Transfer Interrupt Enable bit is broken? */ 604 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | DMACMD_MDL | 605 /* DMACMD_INTE | */ 606 (datain ? DMACMD_DIR : 0)); 607 608 /* issue DMA start command */ 609 WRITE_DMAREG(esc, DMA_CMD, DMACMD_START | DMACMD_MDL | 610 /* DMACMD_INTE | */ 611 (datain ? DMACMD_DIR : 0)); 612 613 esc->sc_active = 1; 614 } 615 616 void 617 pcscp_dma_stop(sc) 618 struct ncr53c9x_softc *sc; 619 { 620 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 621 622 /* DMA stop */ 623 /* XXX What should we do here ? */ 624 WRITE_DMAREG(esc, DMA_CMD, 625 DMACMD_ABORT | (esc->sc_datain ? DMACMD_DIR : 0)); 626 627 esc->sc_active = 0; 628 } 629 630 int 631 pcscp_dma_isactive(sc) 632 struct ncr53c9x_softc *sc; 633 { 634 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 635 636 /* XXX should check esc->sc_active? */ 637 if ((READ_DMAREG(esc, DMA_CMD) & DMACMD_CMD) != DMACMD_IDLE) 638 return 1; 639 return 0; 640 } 641