1 /* $NetBSD: pcscp.c,v 1.20 2002/10/02 16:51:53 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center; Izumi Tsutsui. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * pcscp.c: device dependent code for AMD Am53c974 (PCscsi-PCI) 42 * written by Izumi Tsutsui <tsutsui@ceres.dti.ne.jp> 43 * 44 * Technical manual available at 45 * http://www.amd.com/products/npd/techdocs/techdocs.html 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: pcscp.c,v 1.20 2002/10/02 16:51:53 thorpej Exp $"); 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/device.h> 54 #include <sys/buf.h> 55 56 #include <machine/bus.h> 57 #include <machine/intr.h> 58 #include <machine/endian.h> 59 60 #include <uvm/uvm_extern.h> 61 62 #include <dev/scsipi/scsipi_all.h> 63 #include <dev/scsipi/scsi_all.h> 64 #include <dev/scsipi/scsiconf.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/pcidevs.h> 69 70 #include <dev/ic/ncr53c9xreg.h> 71 #include <dev/ic/ncr53c9xvar.h> 72 73 #include <dev/pci/pcscpreg.h> 74 75 #define IO_MAP_REG 0x10 76 #define MEM_MAP_REG 0x14 77 78 struct pcscp_softc { 79 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 80 81 bus_space_tag_t sc_st; /* bus space tag */ 82 bus_space_handle_t sc_sh; /* bus space handle */ 83 void *sc_ih; /* interrupt cookie */ 84 85 bus_dma_tag_t sc_dmat; /* DMA tag */ 86 87 bus_dmamap_t sc_xfermap; /* DMA map for transfers */ 88 89 u_int32_t *sc_mdladdr; /* MDL array */ 90 bus_dmamap_t sc_mdldmap; /* MDL DMA map */ 91 92 int sc_active; /* DMA state */ 93 int sc_datain; /* DMA Data Direction */ 94 size_t sc_dmasize; /* DMA size */ 95 char **sc_dmaaddr; /* DMA address */ 96 size_t *sc_dmalen; /* DMA length */ 97 }; 98 99 #define READ_DMAREG(sc, reg) \ 100 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 101 #define WRITE_DMAREG(sc, reg, var) \ 102 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (var)) 103 104 /* don't have to use MI defines in MD code... */ 105 #undef NCR_READ_REG 106 #define NCR_READ_REG(sc, reg) pcscp_read_reg((sc), (reg)) 107 #undef NCR_WRITE_REG 108 #define NCR_WRITE_REG(sc, reg, val) pcscp_write_reg((sc), (reg), (val)) 109 110 int pcscp_match __P((struct device *, struct cfdata *, void *)); 111 void pcscp_attach __P((struct device *, struct device *, void *)); 112 113 CFATTACH_DECL(pcscp, sizeof(struct pcscp_softc), 114 pcscp_match, pcscp_attach, NULL, NULL); 115 116 /* 117 * Functions and the switch for the MI code. 118 */ 119 120 u_char pcscp_read_reg __P((struct ncr53c9x_softc *, int)); 121 void pcscp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 122 int pcscp_dma_isintr __P((struct ncr53c9x_softc *)); 123 void pcscp_dma_reset __P((struct ncr53c9x_softc *)); 124 int pcscp_dma_intr __P((struct ncr53c9x_softc *)); 125 int pcscp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 126 size_t *, int, size_t *)); 127 void pcscp_dma_go __P((struct ncr53c9x_softc *)); 128 void pcscp_dma_stop __P((struct ncr53c9x_softc *)); 129 int pcscp_dma_isactive __P((struct ncr53c9x_softc *)); 130 131 struct ncr53c9x_glue pcscp_glue = { 132 pcscp_read_reg, 133 pcscp_write_reg, 134 pcscp_dma_isintr, 135 pcscp_dma_reset, 136 pcscp_dma_intr, 137 pcscp_dma_setup, 138 pcscp_dma_go, 139 pcscp_dma_stop, 140 pcscp_dma_isactive, 141 NULL, /* gl_clear_latched_intr */ 142 }; 143 144 int 145 pcscp_match(parent, match, aux) 146 struct device *parent; 147 struct cfdata *match; 148 void *aux; 149 { 150 struct pci_attach_args *pa = aux; 151 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 152 return 0; 153 154 switch (PCI_PRODUCT(pa->pa_id)) { 155 case PCI_PRODUCT_AMD_PCSCSI_PCI: 156 #if 0 157 case PCI_PRODUCT_AMD_PCNETS_PCI: 158 #endif 159 return 1; 160 } 161 return 0; 162 } 163 164 /* 165 * Attach this instance, and then all the sub-devices 166 */ 167 void 168 pcscp_attach(parent, self, aux) 169 struct device *parent, *self; 170 void *aux; 171 { 172 struct pci_attach_args *pa = aux; 173 struct pcscp_softc *esc = (void *)self; 174 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 175 bus_space_tag_t st, iot, memt; 176 bus_space_handle_t sh, ioh, memh; 177 int ioh_valid, memh_valid; 178 pci_intr_handle_t ih; 179 const char *intrstr; 180 pcireg_t csr; 181 bus_dma_segment_t seg; 182 int error, rseg; 183 184 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG, 185 PCI_MAPREG_TYPE_IO, 0, 186 &iot, &ioh, NULL, NULL) == 0); 187 #if 0 /* XXX cannot use memory map? */ 188 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, 189 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 190 &memt, &memh, NULL, NULL) == 0); 191 #else 192 memh_valid = 0; 193 #endif 194 195 if (memh_valid) { 196 st = memt; 197 sh = memh; 198 } else if (ioh_valid) { 199 st = iot; 200 sh = ioh; 201 } else { 202 printf(": unable to map registers\n"); 203 return; 204 } 205 printf("\n"); 206 207 sc->sc_glue = &pcscp_glue; 208 209 esc->sc_st = st; 210 esc->sc_sh = sh; 211 esc->sc_dmat = pa->pa_dmat; 212 213 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 214 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 215 csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE); 216 217 /* 218 * XXX More of this should be in ncr53c9x_attach(), but 219 * XXX should we really poke around the chip that much in 220 * XXX the MI code? Think about this more... 221 */ 222 223 /* 224 * Set up static configuration info. 225 */ 226 227 /* 228 * XXX should read configuration from EEPROM? 229 * 230 * MI ncr53c9x driver does not support configuration 231 * per each target device, though... 232 */ 233 sc->sc_id = 7; 234 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 235 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 236 sc->sc_cfg3 = NCRAMDCFG3_IDM | NCRAMDCFG3_FCLK; 237 sc->sc_cfg4 = NCRAMDCFG4_GE12NS | NCRAMDCFG4_RADE; 238 sc->sc_rev = NCR_VARIANT_AM53C974; 239 sc->sc_features = NCR_F_FASTSCSI; 240 sc->sc_cfg3_fscsi = NCRAMDCFG3_FSCSI; 241 sc->sc_freq = 40; /* MHz */ 242 243 /* 244 * XXX minsync and maxxfer _should_ be set up in MI code, 245 * XXX but it appears to have some dependency on what sort 246 * XXX of DMA we're hooked up to, etc. 247 */ 248 249 /* 250 * This is the value used to start sync negotiations 251 * Note that the NCR register "SYNCTP" is programmed 252 * in "clocks per byte", and has a minimum value of 4. 253 * The SCSI period used in negotiation is one-fourth 254 * of the time (in nanoseconds) needed to transfer one byte. 255 * Since the chip's clock is given in MHz, we have the following 256 * formula: 4 * period = (1000 / freq) * 4 257 */ 258 259 sc->sc_minsync = 1000 / sc->sc_freq; 260 261 /* Really no limit, but since we want to fit into the TCR... */ 262 sc->sc_maxxfer = 16 * 1024 * 1024; 263 264 /* map and establish interrupt */ 265 if (pci_intr_map(pa, &ih)) { 266 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 267 return; 268 } 269 270 intrstr = pci_intr_string(pa->pa_pc, ih); 271 esc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 272 ncr53c9x_intr, esc); 273 if (esc->sc_ih == NULL) { 274 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 275 if (intrstr != NULL) 276 printf(" at %s", intrstr); 277 printf("\n"); 278 return; 279 } 280 if (intrstr != NULL) 281 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, 282 intrstr); 283 284 /* 285 * Create the DMA maps for the data transfers. 286 */ 287 288 #define MDL_SEG_SIZE 0x1000 /* 4kbyte per segment */ 289 #define MDL_SEG_OFFSET 0x0FFF 290 #define MDL_SIZE (MAXPHYS / MDL_SEG_SIZE + 1) /* no hardware limit? */ 291 292 if (bus_dmamap_create(esc->sc_dmat, MAXPHYS, MDL_SIZE, MAXPHYS, 0, 293 BUS_DMA_NOWAIT, &esc->sc_xfermap)) { 294 printf("%s: can't create dma maps\n", sc->sc_dev.dv_xname); 295 return; 296 } 297 298 /* 299 * Allocate and map memory for the MDL. 300 */ 301 302 if ((error = bus_dmamem_alloc(esc->sc_dmat, 303 sizeof(u_int32_t) * MDL_SIZE, PAGE_SIZE, 0, &seg, 1, &rseg, 304 BUS_DMA_NOWAIT)) != 0) { 305 printf("%s: unable to allocate memory for the MDL, " 306 "error = %d\n", sc->sc_dev.dv_xname, error); 307 return; 308 } 309 if ((error = bus_dmamem_map(esc->sc_dmat, &seg, rseg, 310 sizeof(u_int32_t) * MDL_SIZE , (caddr_t *)&esc->sc_mdladdr, 311 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 312 printf("%s: unable to map the MDL memory, error = %d\n", 313 sc->sc_dev.dv_xname, error); 314 return; 315 } 316 if ((error = bus_dmamap_create(esc->sc_dmat, 317 sizeof(u_int32_t) * MDL_SIZE, 1, sizeof(u_int32_t) * MDL_SIZE, 318 0, BUS_DMA_NOWAIT, &esc->sc_mdldmap)) != 0) { 319 printf("%s: unable to map_create for the MDL, error = %d\n", 320 sc->sc_dev.dv_xname, error); 321 return; 322 } 323 if ((error = bus_dmamap_load(esc->sc_dmat, esc->sc_mdldmap, 324 esc->sc_mdladdr, sizeof(u_int32_t) * MDL_SIZE, 325 NULL, BUS_DMA_NOWAIT)) != 0) { 326 printf("%s: unable to load for the MDL, error = %d\n", 327 sc->sc_dev.dv_xname, error); 328 return; 329 } 330 331 /* Do the common parts of attachment. */ 332 printf("%s", sc->sc_dev.dv_xname); 333 334 sc->sc_adapter.adapt_minphys = minphys; 335 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 336 ncr53c9x_attach(sc); 337 338 /* Turn on target selection using the `dma' method */ 339 sc->sc_features |= NCR_F_DMASELECT; 340 } 341 342 /* 343 * Glue functions. 344 */ 345 346 u_char 347 pcscp_read_reg(sc, reg) 348 struct ncr53c9x_softc *sc; 349 int reg; 350 { 351 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 352 353 return bus_space_read_1(esc->sc_st, esc->sc_sh, reg << 2); 354 } 355 356 void 357 pcscp_write_reg(sc, reg, v) 358 struct ncr53c9x_softc *sc; 359 int reg; 360 u_char v; 361 { 362 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 363 364 bus_space_write_1(esc->sc_st, esc->sc_sh, reg << 2, v); 365 } 366 367 int 368 pcscp_dma_isintr(sc) 369 struct ncr53c9x_softc *sc; 370 { 371 372 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 373 } 374 375 void 376 pcscp_dma_reset(sc) 377 struct ncr53c9x_softc *sc; 378 { 379 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 380 381 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE); 382 383 esc->sc_active = 0; 384 } 385 386 int 387 pcscp_dma_intr(sc) 388 struct ncr53c9x_softc *sc; 389 { 390 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 391 int trans, resid, i; 392 bus_dmamap_t dmap = esc->sc_xfermap; 393 int datain = esc->sc_datain; 394 u_int32_t dmastat; 395 char *p = NULL; 396 397 dmastat = READ_DMAREG(esc, DMA_STAT); 398 399 if (dmastat & DMASTAT_ERR) { 400 /* XXX not tested... */ 401 WRITE_DMAREG(esc, DMA_CMD, 402 DMACMD_ABORT | (datain ? DMACMD_DIR : 0)); 403 404 printf("%s: error: DMA error detected; Aborting.\n", 405 sc->sc_dev.dv_xname); 406 bus_dmamap_unload(esc->sc_dmat, dmap); 407 return -1; 408 } 409 410 if (dmastat & DMASTAT_ABT) { 411 /* XXX What should be done? */ 412 printf("%s: dma_intr: DMA aborted.\n", sc->sc_dev.dv_xname); 413 WRITE_DMAREG(esc, DMA_CMD, 414 DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 415 esc->sc_active = 0; 416 return 0; 417 } 418 419 /* This is an "assertion" :) */ 420 if (esc->sc_active == 0) 421 panic("pcscp dmaintr: DMA wasn't active"); 422 423 /* DMA has stopped */ 424 425 esc->sc_active = 0; 426 427 if (esc->sc_dmasize == 0) { 428 /* A "Transfer Pad" operation completed */ 429 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 430 NCR_READ_REG(sc, NCR_TCL) | 431 (NCR_READ_REG(sc, NCR_TCM) << 8), 432 NCR_READ_REG(sc, NCR_TCL), 433 NCR_READ_REG(sc, NCR_TCM))); 434 return 0; 435 } 436 437 resid = 0; 438 /* 439 * If a transfer onto the SCSI bus gets interrupted by the device 440 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 441 * as residual since the ESP counter registers get decremented as 442 * bytes are clocked into the FIFO. 443 */ 444 if (!datain && 445 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 446 NCR_DMA(("pcscp_dma_intr: empty esp FIFO of %d ", resid)); 447 } 448 449 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 450 /* 451 * `Terminal count' is off, so read the residue 452 * out of the ESP counter registers. 453 */ 454 if (datain) { 455 resid = NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF; 456 while (resid > 1) 457 resid = 458 NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF; 459 WRITE_DMAREG(esc, DMA_CMD, DMACMD_BLAST | DMACMD_MDL | 460 (datain ? DMACMD_DIR : 0)); 461 462 for (i = 0; i < 0x8000; i++) /* XXX 0x8000 ? */ 463 if (READ_DMAREG(esc, DMA_STAT) & DMASTAT_BCMP) 464 break; 465 466 /* See the below comments... */ 467 if (resid) 468 p = *esc->sc_dmaaddr; 469 } 470 471 resid += (NCR_READ_REG(sc, NCR_TCL) | 472 (NCR_READ_REG(sc, NCR_TCM) << 8) | 473 ((sc->sc_cfg2 & NCRCFG2_FE) 474 ? (NCR_READ_REG(sc, NCR_TCH) << 16) : 0)); 475 476 if (resid == 0 && esc->sc_dmasize == 65536 && 477 (sc->sc_cfg2 & NCRCFG2_FE) == 0) 478 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 479 resid = 65536; 480 } else { 481 while((dmastat & DMASTAT_DONE) == 0) 482 dmastat = READ_DMAREG(esc, DMA_STAT); 483 } 484 485 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 486 487 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 488 datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 489 bus_dmamap_unload(esc->sc_dmat, dmap); 490 491 trans = esc->sc_dmasize - resid; 492 493 /* 494 * From the technical manual notes: 495 * 496 * `In some odd byte conditions, one residual byte will be left 497 * in the SCSI FIFO, and the FIFO flags will never count to 0. 498 * When this happens, the residual byte should be retrieved 499 * via PIO following completion of the BLAST operation.' 500 */ 501 502 if (p) { 503 p += trans; 504 *p = NCR_READ_REG(sc, NCR_FIFO); 505 trans++; 506 } 507 508 if (trans < 0) { /* transferred < 0 ? */ 509 #if 0 510 /* 511 * This situation can happen in perfectly normal operation 512 * if the ESP is reselected while using DMA to select 513 * another target. As such, don't print the warning. 514 */ 515 printf("%s: xfer (%d) > req (%d)\n", 516 sc->sc_dev.dv_xname, trans, esc->sc_dmasize); 517 #endif 518 trans = esc->sc_dmasize; 519 } 520 521 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 522 NCR_READ_REG(sc, NCR_TCL), 523 NCR_READ_REG(sc, NCR_TCM), 524 (sc->sc_cfg2 & NCRCFG2_FE) ? NCR_READ_REG(sc, NCR_TCH) : 0, 525 trans, resid)); 526 527 *esc->sc_dmalen -= trans; 528 *esc->sc_dmaaddr += trans; 529 530 return 0; 531 } 532 533 int 534 pcscp_dma_setup(sc, addr, len, datain, dmasize) 535 struct ncr53c9x_softc *sc; 536 caddr_t *addr; 537 size_t *len; 538 int datain; 539 size_t *dmasize; 540 { 541 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 542 bus_dmamap_t dmap = esc->sc_xfermap; 543 u_int32_t *mdl; 544 int error, nseg, seg; 545 bus_addr_t s_offset, s_addr; 546 long rest, count; 547 548 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 549 550 esc->sc_dmaaddr = addr; 551 esc->sc_dmalen = len; 552 esc->sc_dmasize = *dmasize; 553 esc->sc_datain = datain; 554 555 #ifdef DIAGNOSTIC 556 if ((*dmasize / MDL_SEG_SIZE) > MDL_SIZE) 557 panic("pcscp: transfer size too large"); 558 #endif 559 560 /* 561 * No need to set up DMA in `Transfer Pad' operation. 562 * (case of *dmasize == 0) 563 */ 564 if (*dmasize == 0) 565 return 0; 566 567 error = bus_dmamap_load(esc->sc_dmat, dmap, *esc->sc_dmaaddr, 568 *esc->sc_dmalen, NULL, 569 ((sc->sc_nexus->xs->xs_control & XS_CTL_NOSLEEP) ? 570 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | 571 ((sc->sc_nexus->xs->xs_control & XS_CTL_DATA_IN) ? 572 BUS_DMA_READ : BUS_DMA_WRITE)); 573 if (error) { 574 printf("%s: unable to load dmamap, error = %d\n", 575 sc->sc_dev.dv_xname, error); 576 return error; 577 } 578 579 /* set transfer length */ 580 WRITE_DMAREG(esc, DMA_STC, *dmasize); 581 582 /* set up MDL */ 583 mdl = esc->sc_mdladdr; 584 nseg = dmap->dm_nsegs; 585 586 /* the first segment is possibly not aligned with 4k MDL boundary */ 587 count = dmap->dm_segs[0].ds_len; 588 s_addr = dmap->dm_segs[0].ds_addr; 589 s_offset = s_addr & MDL_SEG_OFFSET; 590 s_addr -= s_offset; 591 rest = MDL_SEG_SIZE - s_offset; 592 593 /* set the first MDL and offset */ 594 WRITE_DMAREG(esc, DMA_SPA, s_offset); 595 *mdl++ = htole32(s_addr); 596 count -= rest; 597 598 /* rests of the first dmamap segment */ 599 while (count > 0) { 600 s_addr += MDL_SEG_SIZE; 601 *mdl++ = htole32(s_addr); 602 count -= MDL_SEG_SIZE; 603 } 604 605 /* the rest dmamap segments are aligned with 4k boundary */ 606 for (seg = 1; seg < nseg; seg++) { 607 count = dmap->dm_segs[seg].ds_len; 608 s_addr = dmap->dm_segs[seg].ds_addr; 609 610 /* first 4kbyte of each dmamap segment */ 611 *mdl++ = htole32(s_addr); 612 count -= MDL_SEG_SIZE; 613 614 /* trailing contiguous 4k frames of each dmamap segments */ 615 while (count > 0) { 616 s_addr += MDL_SEG_SIZE; 617 *mdl++ = htole32(s_addr); 618 count -= MDL_SEG_SIZE; 619 } 620 } 621 622 return 0; 623 } 624 625 void 626 pcscp_dma_go(sc) 627 struct ncr53c9x_softc *sc; 628 { 629 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 630 bus_dmamap_t dmap = esc->sc_xfermap, mdldmap = esc->sc_mdldmap; 631 int datain = esc->sc_datain; 632 633 /* No DMA transfer in Transfer Pad operation */ 634 if (esc->sc_dmasize == 0) 635 return; 636 637 /* sync transfer buffer */ 638 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 639 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 640 641 /* sync MDL */ 642 bus_dmamap_sync(esc->sc_dmat, mdldmap, 0, mdldmap->dm_mapsize, 643 BUS_DMASYNC_PREWRITE); 644 645 /* set Starting MDL Address */ 646 WRITE_DMAREG(esc, DMA_SMDLA, mdldmap->dm_segs[0].ds_addr); 647 648 /* set DMA command register bits */ 649 /* XXX DMA Transfer Interrupt Enable bit is broken? */ 650 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | DMACMD_MDL | 651 /* DMACMD_INTE | */ 652 (datain ? DMACMD_DIR : 0)); 653 654 /* issue DMA start command */ 655 WRITE_DMAREG(esc, DMA_CMD, DMACMD_START | DMACMD_MDL | 656 /* DMACMD_INTE | */ 657 (datain ? DMACMD_DIR : 0)); 658 659 esc->sc_active = 1; 660 } 661 662 void 663 pcscp_dma_stop(sc) 664 struct ncr53c9x_softc *sc; 665 { 666 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 667 668 /* dma stop */ 669 /* XXX What should we do here ? */ 670 WRITE_DMAREG(esc, DMA_CMD, 671 DMACMD_ABORT | (esc->sc_datain ? DMACMD_DIR : 0)); 672 673 esc->sc_active = 0; 674 } 675 676 int 677 pcscp_dma_isactive(sc) 678 struct ncr53c9x_softc *sc; 679 { 680 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 681 682 /* XXX should check esc->sc_active? */ 683 if ((READ_DMAREG(esc, DMA_CMD) & DMACMD_CMD) != DMACMD_IDLE) 684 return 1; 685 return 0; 686 } 687