1 /* $NetBSD: pcscp.c,v 1.30 2004/09/25 11:58:19 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center; Izumi Tsutsui. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * pcscp.c: device dependent code for AMD Am53c974 (PCscsi-PCI) 42 * written by Izumi Tsutsui <tsutsui@ceres.dti.ne.jp> 43 * 44 * Technical manual available at 45 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/19113.pdf 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: pcscp.c,v 1.30 2004/09/25 11:58:19 tsutsui Exp $"); 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/device.h> 54 #include <sys/buf.h> 55 56 #include <machine/bus.h> 57 #include <machine/intr.h> 58 59 #include <uvm/uvm_extern.h> 60 61 #include <dev/scsipi/scsipi_all.h> 62 #include <dev/scsipi/scsi_all.h> 63 #include <dev/scsipi/scsiconf.h> 64 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcivar.h> 67 #include <dev/pci/pcidevs.h> 68 69 #include <dev/ic/ncr53c9xreg.h> 70 #include <dev/ic/ncr53c9xvar.h> 71 72 #include <dev/pci/pcscpreg.h> 73 74 #define IO_MAP_REG 0x10 75 76 struct pcscp_softc { 77 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 78 79 bus_space_tag_t sc_st; /* bus space tag */ 80 bus_space_handle_t sc_sh; /* bus space handle */ 81 void *sc_ih; /* interrupt cookie */ 82 83 bus_dma_tag_t sc_dmat; /* DMA tag */ 84 85 bus_dmamap_t sc_xfermap; /* DMA map for transfers */ 86 87 u_int32_t *sc_mdladdr; /* MDL array */ 88 bus_dmamap_t sc_mdldmap; /* MDL DMA map */ 89 90 int sc_active; /* DMA state */ 91 int sc_datain; /* DMA Data Direction */ 92 size_t sc_dmasize; /* DMA size */ 93 char **sc_dmaaddr; /* DMA address */ 94 size_t *sc_dmalen; /* DMA length */ 95 }; 96 97 #define READ_DMAREG(sc, reg) \ 98 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 99 #define WRITE_DMAREG(sc, reg, var) \ 100 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (var)) 101 102 #define PCSCP_READ_REG(sc, reg) \ 103 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2) 104 #define PCSCP_WRITE_REG(sc, reg, val) \ 105 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2, (val)) 106 107 int pcscp_match(struct device *, struct cfdata *, void *); 108 void pcscp_attach(struct device *, struct device *, void *); 109 110 CFATTACH_DECL(pcscp, sizeof(struct pcscp_softc), 111 pcscp_match, pcscp_attach, NULL, NULL); 112 113 /* 114 * Functions and the switch for the MI code. 115 */ 116 117 u_char pcscp_read_reg(struct ncr53c9x_softc *, int); 118 void pcscp_write_reg(struct ncr53c9x_softc *, int, u_char); 119 int pcscp_dma_isintr(struct ncr53c9x_softc *); 120 void pcscp_dma_reset(struct ncr53c9x_softc *); 121 int pcscp_dma_intr(struct ncr53c9x_softc *); 122 int pcscp_dma_setup(struct ncr53c9x_softc *, caddr_t *, size_t *, int, 123 size_t *); 124 void pcscp_dma_go(struct ncr53c9x_softc *); 125 void pcscp_dma_stop(struct ncr53c9x_softc *); 126 int pcscp_dma_isactive(struct ncr53c9x_softc *); 127 128 struct ncr53c9x_glue pcscp_glue = { 129 pcscp_read_reg, 130 pcscp_write_reg, 131 pcscp_dma_isintr, 132 pcscp_dma_reset, 133 pcscp_dma_intr, 134 pcscp_dma_setup, 135 pcscp_dma_go, 136 pcscp_dma_stop, 137 pcscp_dma_isactive, 138 NULL, /* gl_clear_latched_intr */ 139 }; 140 141 int 142 pcscp_match(struct device *parent, struct cfdata *match, void *aux) 143 { 144 struct pci_attach_args *pa = aux; 145 146 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 147 return 0; 148 149 switch (PCI_PRODUCT(pa->pa_id)) { 150 case PCI_PRODUCT_AMD_PCSCSI_PCI: 151 return 1; 152 } 153 return 0; 154 } 155 156 /* 157 * Attach this instance, and then all the sub-devices 158 */ 159 void 160 pcscp_attach(struct device *parent, struct device *self, void *aux) 161 { 162 struct pci_attach_args *pa = aux; 163 struct pcscp_softc *esc = (void *)self; 164 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 165 bus_space_tag_t iot; 166 bus_space_handle_t ioh; 167 pci_intr_handle_t ih; 168 const char *intrstr; 169 pcireg_t csr; 170 bus_dma_segment_t seg; 171 int error, rseg; 172 char devinfo[256]; 173 174 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 175 printf(": %s\n", devinfo); 176 printf("%s", sc->sc_dev.dv_xname); 177 178 if (pci_mapreg_map(pa, IO_MAP_REG, PCI_MAPREG_TYPE_IO, 0, 179 &iot, &ioh, NULL, NULL)) { 180 printf(": unable to map registers\n"); 181 return; 182 } 183 184 sc->sc_glue = &pcscp_glue; 185 186 esc->sc_st = iot; 187 esc->sc_sh = ioh; 188 esc->sc_dmat = pa->pa_dmat; 189 190 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 191 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 192 csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE); 193 194 /* 195 * XXX More of this should be in ncr53c9x_attach(), but 196 * XXX should we really poke around the chip that much in 197 * XXX the MI code? Think about this more... 198 */ 199 200 /* 201 * Set up static configuration info. 202 */ 203 204 /* 205 * XXX should read configuration from EEPROM? 206 * 207 * MI ncr53c9x driver does not support configuration 208 * per each target device, though... 209 */ 210 sc->sc_id = 7; 211 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 212 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 213 sc->sc_cfg3 = NCRAMDCFG3_IDM | NCRAMDCFG3_FCLK; 214 sc->sc_cfg4 = NCRAMDCFG4_GE12NS | NCRAMDCFG4_RADE; 215 sc->sc_rev = NCR_VARIANT_AM53C974; 216 sc->sc_features = NCR_F_FASTSCSI; 217 sc->sc_cfg3_fscsi = NCRAMDCFG3_FSCSI; 218 sc->sc_freq = 40; /* MHz */ 219 220 /* 221 * XXX minsync and maxxfer _should_ be set up in MI code, 222 * XXX but it appears to have some dependency on what sort 223 * XXX of DMA we're hooked up to, etc. 224 */ 225 226 /* 227 * This is the value used to start sync negotiations 228 * Note that the NCR register "SYNCTP" is programmed 229 * in "clocks per byte", and has a minimum value of 4. 230 * The SCSI period used in negotiation is one-fourth 231 * of the time (in nanoseconds) needed to transfer one byte. 232 * Since the chip's clock is given in MHz, we have the following 233 * formula: 4 * period = (1000 / freq) * 4 234 */ 235 236 sc->sc_minsync = 1000 / sc->sc_freq; 237 238 /* Really no limit, but since we want to fit into the TCR... */ 239 sc->sc_maxxfer = 16 * 1024 * 1024; 240 241 /* 242 * Create the DMA maps for the data transfers. 243 */ 244 245 #define MDL_SEG_SIZE 0x1000 /* 4kbyte per segment */ 246 #define MDL_SEG_OFFSET 0x0FFF 247 #define MDL_SIZE (MAXPHYS / MDL_SEG_SIZE + 1) /* no hardware limit? */ 248 249 if (bus_dmamap_create(esc->sc_dmat, MAXPHYS, MDL_SIZE, MDL_SEG_SIZE, 250 MDL_SEG_SIZE, BUS_DMA_NOWAIT, &esc->sc_xfermap)) { 251 printf(": can't create DMA maps\n"); 252 return; 253 } 254 255 /* 256 * Allocate and map memory for the MDL. 257 */ 258 259 if ((error = bus_dmamem_alloc(esc->sc_dmat, 260 sizeof(u_int32_t) * MDL_SIZE, PAGE_SIZE, 0, &seg, 1, &rseg, 261 BUS_DMA_NOWAIT)) != 0) { 262 printf(": unable to allocate memory for the MDL, error = %d\n", 263 error); 264 return; 265 } 266 if ((error = bus_dmamem_map(esc->sc_dmat, &seg, rseg, 267 sizeof(u_int32_t) * MDL_SIZE , (caddr_t *)&esc->sc_mdladdr, 268 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 269 printf(": unable to map the MDL memory, error = %d\n", error); 270 return; 271 } 272 if ((error = bus_dmamap_create(esc->sc_dmat, 273 sizeof(u_int32_t) * MDL_SIZE, 1, sizeof(u_int32_t) * MDL_SIZE, 274 0, BUS_DMA_NOWAIT, &esc->sc_mdldmap)) != 0) { 275 printf(": unable to map_create for the MDL, error = %d\n", 276 error); 277 return; 278 } 279 if ((error = bus_dmamap_load(esc->sc_dmat, esc->sc_mdldmap, 280 esc->sc_mdladdr, sizeof(u_int32_t) * MDL_SIZE, 281 NULL, BUS_DMA_NOWAIT)) != 0) { 282 printf(": unable to load for the MDL, error = %d\n", error); 283 return; 284 } 285 286 /* map and establish interrupt */ 287 if (pci_intr_map(pa, &ih)) { 288 printf(": couldn't map interrupt\n"); 289 return; 290 } 291 292 intrstr = pci_intr_string(pa->pa_pc, ih); 293 esc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 294 ncr53c9x_intr, esc); 295 if (esc->sc_ih == NULL) { 296 printf(": couldn't establish interrupt"); 297 if (intrstr != NULL) 298 printf(" at %s", intrstr); 299 printf("\n"); 300 return; 301 } 302 if (intrstr != NULL) 303 printf(": interrupting at %s\n", intrstr); 304 305 /* Do the common parts of attachment. */ 306 printf("%s", sc->sc_dev.dv_xname); 307 sc->sc_adapter.adapt_minphys = minphys; 308 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 309 ncr53c9x_attach(sc); 310 311 /* Turn on target selection using the `DMA' method */ 312 sc->sc_features |= NCR_F_DMASELECT; 313 } 314 315 /* 316 * Glue functions. 317 */ 318 319 u_char 320 pcscp_read_reg(struct ncr53c9x_softc *sc, int reg) 321 { 322 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 323 324 return PCSCP_READ_REG(esc, reg); 325 } 326 327 void 328 pcscp_write_reg(struct ncr53c9x_softc *sc, int reg, u_char v) 329 { 330 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 331 332 PCSCP_WRITE_REG(esc, reg, v); 333 } 334 335 int 336 pcscp_dma_isintr(struct ncr53c9x_softc *sc) 337 { 338 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 339 340 return (PCSCP_READ_REG(esc, NCR_STAT) & NCRSTAT_INT) != 0; 341 } 342 343 void 344 pcscp_dma_reset(struct ncr53c9x_softc *sc) 345 { 346 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 347 348 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE); 349 350 esc->sc_active = 0; 351 } 352 353 int 354 pcscp_dma_intr(struct ncr53c9x_softc *sc) 355 { 356 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 357 int trans, resid, i; 358 bus_dmamap_t dmap = esc->sc_xfermap; 359 int datain = esc->sc_datain; 360 u_int32_t dmastat; 361 char *p = NULL; 362 363 dmastat = READ_DMAREG(esc, DMA_STAT); 364 365 if (dmastat & DMASTAT_ERR) { 366 /* XXX not tested... */ 367 WRITE_DMAREG(esc, DMA_CMD, 368 DMACMD_ABORT | (datain ? DMACMD_DIR : 0)); 369 370 printf("%s: error: DMA error detected; Aborting.\n", 371 sc->sc_dev.dv_xname); 372 bus_dmamap_unload(esc->sc_dmat, dmap); 373 return -1; 374 } 375 376 if (dmastat & DMASTAT_ABT) { 377 /* XXX What should be done? */ 378 printf("%s: dma_intr: DMA aborted.\n", sc->sc_dev.dv_xname); 379 WRITE_DMAREG(esc, DMA_CMD, 380 DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 381 esc->sc_active = 0; 382 return 0; 383 } 384 385 #ifdef DIAGNOSTIC 386 /* This is an "assertion" :) */ 387 if (esc->sc_active == 0) 388 panic("pcscp dmaintr: DMA wasn't active"); 389 #endif 390 391 /* DMA has stopped */ 392 393 esc->sc_active = 0; 394 395 if (esc->sc_dmasize == 0) { 396 /* A "Transfer Pad" operation completed */ 397 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 398 PCSCP_READ_REG(esc, NCR_TCL) | 399 (PCSCP_READ_REG(esc, NCR_TCM) << 8), 400 PCSCP_READ_REG(esc, NCR_TCL), 401 PCSCP_READ_REG(esc, NCR_TCM))); 402 return 0; 403 } 404 405 resid = 0; 406 /* 407 * If a transfer onto the SCSI bus gets interrupted by the device 408 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 409 * as residual since the ESP counter registers get decremented as 410 * bytes are clocked into the FIFO. 411 */ 412 if (!datain && 413 (resid = (PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 414 NCR_DMA(("pcscp_dma_intr: empty esp FIFO of %d ", resid)); 415 } 416 417 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 418 /* 419 * `Terminal count' is off, so read the residue 420 * out of the ESP counter registers. 421 */ 422 if (datain) { 423 resid = PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF; 424 while (resid > 1) 425 resid = 426 PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF; 427 WRITE_DMAREG(esc, DMA_CMD, DMACMD_BLAST | DMACMD_MDL | 428 (datain ? DMACMD_DIR : 0)); 429 430 for (i = 0; i < 0x8000; i++) /* XXX 0x8000 ? */ 431 if (READ_DMAREG(esc, DMA_STAT) & DMASTAT_BCMP) 432 break; 433 434 /* See the below comments... */ 435 if (resid) 436 p = *esc->sc_dmaaddr; 437 } 438 439 resid += PCSCP_READ_REG(esc, NCR_TCL) | 440 (PCSCP_READ_REG(esc, NCR_TCM) << 8) | 441 (PCSCP_READ_REG(esc, NCR_TCH) << 16); 442 } else { 443 while ((dmastat & DMASTAT_DONE) == 0) 444 dmastat = READ_DMAREG(esc, DMA_STAT); 445 } 446 447 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 448 449 /* sync MDL */ 450 bus_dmamap_sync(esc->sc_dmat, esc->sc_mdldmap, 451 0, sizeof(u_int32_t) * dmap->dm_nsegs, BUS_DMASYNC_POSTWRITE); 452 /* sync transfer buffer */ 453 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 454 datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 455 bus_dmamap_unload(esc->sc_dmat, dmap); 456 457 trans = esc->sc_dmasize - resid; 458 459 /* 460 * From the technical manual notes: 461 * 462 * `In some odd byte conditions, one residual byte will be left 463 * in the SCSI FIFO, and the FIFO flags will never count to 0. 464 * When this happens, the residual byte should be retrieved 465 * via PIO following completion of the BLAST operation.' 466 */ 467 468 if (p) { 469 p += trans; 470 *p = PCSCP_READ_REG(esc, NCR_FIFO); 471 trans++; 472 } 473 474 if (trans < 0) { /* transferred < 0 ? */ 475 #if 0 476 /* 477 * This situation can happen in perfectly normal operation 478 * if the ESP is reselected while using DMA to select 479 * another target. As such, don't print the warning. 480 */ 481 printf("%s: xfer (%d) > req (%d)\n", 482 sc->sc_dev.dv_xname, trans, esc->sc_dmasize); 483 #endif 484 trans = esc->sc_dmasize; 485 } 486 487 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 488 PCSCP_READ_REG(esc, NCR_TCL), 489 PCSCP_READ_REG(esc, NCR_TCM), 490 PCSCP_READ_REG(esc, NCR_TCH), 491 trans, resid)); 492 493 *esc->sc_dmalen -= trans; 494 *esc->sc_dmaaddr += trans; 495 496 return 0; 497 } 498 499 int 500 pcscp_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 501 int datain, size_t *dmasize) 502 { 503 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 504 bus_dmamap_t dmap = esc->sc_xfermap; 505 u_int32_t *mdl; 506 int error, nseg, seg; 507 bus_addr_t s_offset, s_addr; 508 509 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0)); 510 511 esc->sc_dmaaddr = addr; 512 esc->sc_dmalen = len; 513 esc->sc_dmasize = *dmasize; 514 esc->sc_datain = datain; 515 516 #ifdef DIAGNOSTIC 517 if ((*dmasize / MDL_SEG_SIZE) > MDL_SIZE) 518 panic("pcscp: transfer size too large"); 519 #endif 520 521 /* 522 * No need to set up DMA in `Transfer Pad' operation. 523 * (case of *dmasize == 0) 524 */ 525 if (*dmasize == 0) 526 return 0; 527 528 error = bus_dmamap_load(esc->sc_dmat, dmap, *esc->sc_dmaaddr, 529 *esc->sc_dmalen, NULL, 530 ((sc->sc_nexus->xs->xs_control & XS_CTL_NOSLEEP) ? 531 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | 532 ((sc->sc_nexus->xs->xs_control & XS_CTL_DATA_IN) ? 533 BUS_DMA_READ : BUS_DMA_WRITE)); 534 if (error) { 535 printf("%s: unable to load dmamap, error = %d\n", 536 sc->sc_dev.dv_xname, error); 537 return error; 538 } 539 540 /* set transfer length */ 541 WRITE_DMAREG(esc, DMA_STC, *dmasize); 542 543 /* set up MDL */ 544 mdl = esc->sc_mdladdr; 545 nseg = dmap->dm_nsegs; 546 547 /* the first segment is possibly not aligned with 4k MDL boundary */ 548 s_addr = dmap->dm_segs[0].ds_addr; 549 s_offset = s_addr & MDL_SEG_OFFSET; 550 s_addr -= s_offset; 551 552 /* set the first MDL and offset */ 553 WRITE_DMAREG(esc, DMA_SPA, s_offset); 554 *mdl++ = htole32(s_addr); 555 556 /* the rest dmamap segments are aligned with 4k boundary */ 557 for (seg = 1; seg < nseg; seg++) 558 *mdl++ = htole32(dmap->dm_segs[seg].ds_addr); 559 560 return 0; 561 } 562 563 void 564 pcscp_dma_go(struct ncr53c9x_softc *sc) 565 { 566 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 567 bus_dmamap_t dmap = esc->sc_xfermap, mdldmap = esc->sc_mdldmap; 568 int datain = esc->sc_datain; 569 570 /* No DMA transfer in Transfer Pad operation */ 571 if (esc->sc_dmasize == 0) 572 return; 573 574 /* sync transfer buffer */ 575 bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize, 576 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 577 578 /* sync MDL */ 579 bus_dmamap_sync(esc->sc_dmat, mdldmap, 580 0, sizeof(u_int32_t) * dmap->dm_nsegs, BUS_DMASYNC_PREWRITE); 581 582 /* set Starting MDL Address */ 583 WRITE_DMAREG(esc, DMA_SMDLA, mdldmap->dm_segs[0].ds_addr); 584 585 /* set DMA command register bits */ 586 /* XXX DMA Transfer Interrupt Enable bit is broken? */ 587 WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | DMACMD_MDL | 588 /* DMACMD_INTE | */ 589 (datain ? DMACMD_DIR : 0)); 590 591 /* issue DMA start command */ 592 WRITE_DMAREG(esc, DMA_CMD, DMACMD_START | DMACMD_MDL | 593 /* DMACMD_INTE | */ 594 (datain ? DMACMD_DIR : 0)); 595 596 esc->sc_active = 1; 597 } 598 599 void 600 pcscp_dma_stop(struct ncr53c9x_softc *sc) 601 { 602 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 603 604 /* DMA stop */ 605 /* XXX What should we do here ? */ 606 WRITE_DMAREG(esc, DMA_CMD, 607 DMACMD_ABORT | (esc->sc_datain ? DMACMD_DIR : 0)); 608 609 esc->sc_active = 0; 610 } 611 612 int 613 pcscp_dma_isactive(struct ncr53c9x_softc *sc) 614 { 615 struct pcscp_softc *esc = (struct pcscp_softc *)sc; 616 617 /* XXX should check esc->sc_active? */ 618 if ((READ_DMAREG(esc, DMA_CMD) & DMACMD_CMD) != DMACMD_IDLE) 619 return 1; 620 return 0; 621 } 622