1 /* $NetBSD: pcireg.h,v 1.51 2006/06/17 23:34:27 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1999, 2000 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _DEV_PCI_PCIREG_H_ 35 #define _DEV_PCI_PCIREG_H_ 36 37 /* 38 * Standardized PCI configuration information 39 * 40 * XXX This is not complete. 41 */ 42 43 /* 44 * Device identification register; contains a vendor ID and a device ID. 45 */ 46 #define PCI_ID_REG 0x00 47 48 typedef u_int16_t pci_vendor_id_t; 49 typedef u_int16_t pci_product_id_t; 50 51 #define PCI_VENDOR_SHIFT 0 52 #define PCI_VENDOR_MASK 0xffff 53 #define PCI_VENDOR(id) \ 54 (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK) 55 56 #define PCI_PRODUCT_SHIFT 16 57 #define PCI_PRODUCT_MASK 0xffff 58 #define PCI_PRODUCT(id) \ 59 (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) 60 61 #define PCI_ID_CODE(vid,pid) \ 62 ((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) | \ 63 (((pid) & PCI_PRODUCT_MASK) << PCI_PRODUCT_SHIFT)) \ 64 65 /* 66 * Command and status register. 67 */ 68 #define PCI_COMMAND_STATUS_REG 0x04 69 #define PCI_COMMAND_SHIFT 0 70 #define PCI_COMMAND_MASK 0xffff 71 #define PCI_STATUS_SHIFT 16 72 #define PCI_STATUS_MASK 0xffff 73 74 #define PCI_COMMAND_STATUS_CODE(cmd,stat) \ 75 ((((cmd) & PCI_COMMAND_MASK) >> PCI_COMMAND_SHIFT) | \ 76 (((stat) & PCI_STATUS_MASK) >> PCI_STATUS_SHIFT)) \ 77 78 #define PCI_COMMAND_IO_ENABLE 0x00000001 79 #define PCI_COMMAND_MEM_ENABLE 0x00000002 80 #define PCI_COMMAND_MASTER_ENABLE 0x00000004 81 #define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 82 #define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 83 #define PCI_COMMAND_PALETTE_ENABLE 0x00000020 84 #define PCI_COMMAND_PARITY_ENABLE 0x00000040 85 #define PCI_COMMAND_STEPPING_ENABLE 0x00000080 86 #define PCI_COMMAND_SERR_ENABLE 0x00000100 87 #define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 88 89 #define PCI_STATUS_CAPLIST_SUPPORT 0x00100000 90 #define PCI_STATUS_66MHZ_SUPPORT 0x00200000 91 #define PCI_STATUS_UDF_SUPPORT 0x00400000 92 #define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000 93 #define PCI_STATUS_PARITY_ERROR 0x01000000 94 #define PCI_STATUS_DEVSEL_FAST 0x00000000 95 #define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 96 #define PCI_STATUS_DEVSEL_SLOW 0x04000000 97 #define PCI_STATUS_DEVSEL_MASK 0x06000000 98 #define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 99 #define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 100 #define PCI_STATUS_MASTER_ABORT 0x20000000 101 #define PCI_STATUS_SPECIAL_ERROR 0x40000000 102 #define PCI_STATUS_PARITY_DETECT 0x80000000 103 104 /* 105 * PCI Class and Revision Register; defines type and revision of device. 106 */ 107 #define PCI_CLASS_REG 0x08 108 109 typedef u_int8_t pci_class_t; 110 typedef u_int8_t pci_subclass_t; 111 typedef u_int8_t pci_interface_t; 112 typedef u_int8_t pci_revision_t; 113 114 #define PCI_CLASS_SHIFT 24 115 #define PCI_CLASS_MASK 0xff 116 #define PCI_CLASS(cr) \ 117 (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) 118 119 #define PCI_SUBCLASS_SHIFT 16 120 #define PCI_SUBCLASS_MASK 0xff 121 #define PCI_SUBCLASS(cr) \ 122 (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) 123 124 #define PCI_INTERFACE_SHIFT 8 125 #define PCI_INTERFACE_MASK 0xff 126 #define PCI_INTERFACE(cr) \ 127 (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) 128 129 #define PCI_REVISION_SHIFT 0 130 #define PCI_REVISION_MASK 0xff 131 #define PCI_REVISION(cr) \ 132 (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) 133 134 #define PCI_CLASS_CODE(mainclass, subclass, interface) \ 135 ((((mainclass) & PCI_CLASS_MASK) << PCI_CLASS_SHIFT) | \ 136 (((subclass) & PCI_SUBCLASS_MASK) << PCI_SUBCLASS_SHIFT) | \ 137 (((interface) & PCI_INTERFACE_MASK) << PCI_INTERFACE_SHIFT)) 138 139 /* base classes */ 140 #define PCI_CLASS_PREHISTORIC 0x00 141 #define PCI_CLASS_MASS_STORAGE 0x01 142 #define PCI_CLASS_NETWORK 0x02 143 #define PCI_CLASS_DISPLAY 0x03 144 #define PCI_CLASS_MULTIMEDIA 0x04 145 #define PCI_CLASS_MEMORY 0x05 146 #define PCI_CLASS_BRIDGE 0x06 147 #define PCI_CLASS_COMMUNICATIONS 0x07 148 #define PCI_CLASS_SYSTEM 0x08 149 #define PCI_CLASS_INPUT 0x09 150 #define PCI_CLASS_DOCK 0x0a 151 #define PCI_CLASS_PROCESSOR 0x0b 152 #define PCI_CLASS_SERIALBUS 0x0c 153 #define PCI_CLASS_WIRELESS 0x0d 154 #define PCI_CLASS_I2O 0x0e 155 #define PCI_CLASS_SATCOM 0x0f 156 #define PCI_CLASS_CRYPTO 0x10 157 #define PCI_CLASS_DASP 0x11 158 #define PCI_CLASS_UNDEFINED 0xff 159 160 /* 0x00 prehistoric subclasses */ 161 #define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 162 #define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 163 164 /* 0x01 mass storage subclasses */ 165 #define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 166 #define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 167 #define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 168 #define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 169 #define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04 170 #define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05 171 #define PCI_SUBCLASS_MASS_STORAGE_SATA 0x06 172 #define PCI_SUBCLASS_MASS_STORAGE_SAS 0x07 173 #define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 174 175 /* 0x02 network subclasses */ 176 #define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 177 #define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 178 #define PCI_SUBCLASS_NETWORK_FDDI 0x02 179 #define PCI_SUBCLASS_NETWORK_ATM 0x03 180 #define PCI_SUBCLASS_NETWORK_ISDN 0x04 181 #define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05 182 #define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06 183 #define PCI_SUBCLASS_NETWORK_MISC 0x80 184 185 /* 0x03 display subclasses */ 186 #define PCI_SUBCLASS_DISPLAY_VGA 0x00 187 #define PCI_SUBCLASS_DISPLAY_XGA 0x01 188 #define PCI_SUBCLASS_DISPLAY_3D 0x02 189 #define PCI_SUBCLASS_DISPLAY_MISC 0x80 190 191 /* 0x04 multimedia subclasses */ 192 #define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 193 #define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 194 #define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02 195 #define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 196 197 /* 0x05 memory subclasses */ 198 #define PCI_SUBCLASS_MEMORY_RAM 0x00 199 #define PCI_SUBCLASS_MEMORY_FLASH 0x01 200 #define PCI_SUBCLASS_MEMORY_MISC 0x80 201 202 /* 0x06 bridge subclasses */ 203 #define PCI_SUBCLASS_BRIDGE_HOST 0x00 204 #define PCI_SUBCLASS_BRIDGE_ISA 0x01 205 #define PCI_SUBCLASS_BRIDGE_EISA 0x02 206 #define PCI_SUBCLASS_BRIDGE_MC 0x03 /* XXX _MCA? */ 207 #define PCI_SUBCLASS_BRIDGE_PCI 0x04 208 #define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 209 #define PCI_SUBCLASS_BRIDGE_NUBUS 0x06 210 #define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 211 #define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08 212 #define PCI_SUBCLASS_BRIDGE_STPCI 0x09 213 #define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a 214 #define PCI_SUBCLASS_BRIDGE_MISC 0x80 215 216 /* 0x07 communications subclasses */ 217 #define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 218 #define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 219 #define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02 220 #define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03 221 #define PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04 222 #define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05 223 #define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 224 225 /* 0x08 system subclasses */ 226 #define PCI_SUBCLASS_SYSTEM_PIC 0x00 227 #define PCI_SUBCLASS_SYSTEM_DMA 0x01 228 #define PCI_SUBCLASS_SYSTEM_TIMER 0x02 229 #define PCI_SUBCLASS_SYSTEM_RTC 0x03 230 #define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04 231 #define PCI_SUBCLASS_SYSTEM_SDHC 0x05 232 #define PCI_SUBCLASS_SYSTEM_MISC 0x80 233 234 /* 0x09 input subclasses */ 235 #define PCI_SUBCLASS_INPUT_KEYBOARD 0x00 236 #define PCI_SUBCLASS_INPUT_DIGITIZER 0x01 237 #define PCI_SUBCLASS_INPUT_MOUSE 0x02 238 #define PCI_SUBCLASS_INPUT_SCANNER 0x03 239 #define PCI_SUBCLASS_INPUT_GAMEPORT 0x04 240 #define PCI_SUBCLASS_INPUT_MISC 0x80 241 242 /* 0x0a dock subclasses */ 243 #define PCI_SUBCLASS_DOCK_GENERIC 0x00 244 #define PCI_SUBCLASS_DOCK_MISC 0x80 245 246 /* 0x0b processor subclasses */ 247 #define PCI_SUBCLASS_PROCESSOR_386 0x00 248 #define PCI_SUBCLASS_PROCESSOR_486 0x01 249 #define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02 250 #define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10 251 #define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20 252 #define PCI_SUBCLASS_PROCESSOR_MIPS 0x30 253 #define PCI_SUBCLASS_PROCESSOR_COPROC 0x40 254 255 /* 0x0c serial bus subclasses */ 256 #define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00 257 #define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01 258 #define PCI_SUBCLASS_SERIALBUS_SSA 0x02 259 #define PCI_SUBCLASS_SERIALBUS_USB 0x03 260 #define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 /* XXX _FIBRECHANNEL */ 261 #define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05 262 #define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06 263 #define PCI_SUBCLASS_SERIALBUS_IPMI 0x07 264 #define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08 265 #define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09 266 267 /* 0x0d wireless subclasses */ 268 #define PCI_SUBCLASS_WIRELESS_IRDA 0x00 269 #define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01 270 #define PCI_SUBCLASS_WIRELESS_RF 0x10 271 #define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11 272 #define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12 273 #define PCI_SUBCLASS_WIRELESS_802_11A 0x20 274 #define PCI_SUBCLASS_WIRELESS_802_11B 0x21 275 #define PCI_SUBCLASS_WIRELESS_MISC 0x80 276 277 /* 0x0e I2O (Intelligent I/O) subclasses */ 278 #define PCI_SUBCLASS_I2O_STANDARD 0x00 279 280 /* 0x0f satellite communication subclasses */ 281 /* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */ 282 #define PCI_SUBCLASS_SATCOM_TV 0x01 283 #define PCI_SUBCLASS_SATCOM_AUDIO 0x02 284 #define PCI_SUBCLASS_SATCOM_VOICE 0x03 285 #define PCI_SUBCLASS_SATCOM_DATA 0x04 286 287 /* 0x10 encryption/decryption subclasses */ 288 #define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00 289 #define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10 290 #define PCI_SUBCLASS_CRYPTO_MISC 0x80 291 292 /* 0x11 data acquisition and signal processing subclasses */ 293 #define PCI_SUBCLASS_DASP_DPIO 0x00 294 #define PCI_SUBCLASS_DASP_TIMEFREQ 0x01 295 #define PCI_SUBCLASS_DASP_SYNC 0x10 296 #define PCI_SUBCLASS_DASP_MGMT 0x20 297 #define PCI_SUBCLASS_DASP_MISC 0x80 298 299 /* 300 * PCI BIST/Header Type/Latency Timer/Cache Line Size Register. 301 */ 302 #define PCI_BHLC_REG 0x0c 303 304 #define PCI_BIST_SHIFT 24 305 #define PCI_BIST_MASK 0xff 306 #define PCI_BIST(bhlcr) \ 307 (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK) 308 309 #define PCI_HDRTYPE_SHIFT 16 310 #define PCI_HDRTYPE_MASK 0xff 311 #define PCI_HDRTYPE(bhlcr) \ 312 (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK) 313 314 #define PCI_HDRTYPE_TYPE(bhlcr) \ 315 (PCI_HDRTYPE(bhlcr) & 0x7f) 316 #define PCI_HDRTYPE_MULTIFN(bhlcr) \ 317 ((PCI_HDRTYPE(bhlcr) & 0x80) != 0) 318 319 #define PCI_LATTIMER_SHIFT 8 320 #define PCI_LATTIMER_MASK 0xff 321 #define PCI_LATTIMER(bhlcr) \ 322 (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK) 323 324 #define PCI_CACHELINE_SHIFT 0 325 #define PCI_CACHELINE_MASK 0xff 326 #define PCI_CACHELINE(bhlcr) \ 327 (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK) 328 329 #define PCI_BHLC_CODE(bist,type,multi,latency,cacheline) \ 330 ((((bist) & PCI_BIST_MASK) << PCI_BIST_SHIFT) | \ 331 (((type) & PCI_HDRTYPE_MASK) << PCI_HDRTYPE_SHIFT) | \ 332 (((multi)?0x80:0) << PCI_HDRTYPE_SHIFT) | \ 333 (((latency) & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT) | \ 334 (((cacheline) & PCI_CACHELINE_MASK) << PCI_CACHELINE_SHIFT)) 335 336 /* 337 * PCI header type 338 */ 339 #define PCI_HDRTYPE_DEVICE 0 340 #define PCI_HDRTYPE_PPB 1 341 #define PCI_HDRTYPE_PCB 2 342 343 /* 344 * Mapping registers 345 */ 346 #define PCI_MAPREG_START 0x10 347 #define PCI_MAPREG_END 0x28 348 #define PCI_MAPREG_ROM 0x30 349 #define PCI_MAPREG_PPB_END 0x18 350 #define PCI_MAPREG_PCB_END 0x14 351 352 #define PCI_MAPREG_TYPE(mr) \ 353 ((mr) & PCI_MAPREG_TYPE_MASK) 354 #define PCI_MAPREG_TYPE_MASK 0x00000001 355 356 #define PCI_MAPREG_TYPE_MEM 0x00000000 357 #define PCI_MAPREG_TYPE_ROM 0x00000000 358 #define PCI_MAPREG_TYPE_IO 0x00000001 359 #define PCI_MAPREG_ROM_ENABLE 0x00000001 360 361 #define PCI_MAPREG_MEM_TYPE(mr) \ 362 ((mr) & PCI_MAPREG_MEM_TYPE_MASK) 363 #define PCI_MAPREG_MEM_TYPE_MASK 0x00000006 364 365 #define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000 366 #define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002 367 #define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 368 369 #define PCI_MAPREG_MEM_PREFETCHABLE(mr) \ 370 (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0) 371 #define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008 372 373 #define PCI_MAPREG_MEM_ADDR(mr) \ 374 ((mr) & PCI_MAPREG_MEM_ADDR_MASK) 375 #define PCI_MAPREG_MEM_SIZE(mr) \ 376 (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr)) 377 #define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 378 379 #define PCI_MAPREG_MEM64_ADDR(mr) \ 380 ((mr) & PCI_MAPREG_MEM64_ADDR_MASK) 381 #define PCI_MAPREG_MEM64_SIZE(mr) \ 382 (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr)) 383 #define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL 384 385 #define PCI_MAPREG_IO_ADDR(mr) \ 386 ((mr) & PCI_MAPREG_IO_ADDR_MASK) 387 #define PCI_MAPREG_IO_SIZE(mr) \ 388 (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) 389 #define PCI_MAPREG_IO_ADDR_MASK 0xfffffffc 390 391 #define PCI_MAPREG_SIZE_TO_MASK(size) \ 392 (-(size)) 393 394 #define PCI_MAPREG_NUM(offset) \ 395 (((unsigned)(offset)-PCI_MAPREG_START)/4) 396 397 398 /* 399 * Cardbus CIS pointer (PCI rev. 2.1) 400 */ 401 #define PCI_CARDBUS_CIS_REG 0x28 402 403 /* 404 * Subsystem identification register; contains a vendor ID and a device ID. 405 * Types/macros for PCI_ID_REG apply. 406 * (PCI rev. 2.1) 407 */ 408 #define PCI_SUBSYS_ID_REG 0x2c 409 410 /* 411 * Capabilities link list (PCI rev. 2.2) 412 */ 413 #define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */ 414 #define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */ 415 #define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff) 416 #define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff) 417 #define PCI_CAPLIST_CAP(cr) ((cr) & 0xff) 418 419 #define PCI_CAP_RESERVED0 0x00 420 #define PCI_CAP_PWRMGMT 0x01 421 #define PCI_CAP_AGP 0x02 422 #define PCI_CAP_AGP_MAJOR(cr) (((cr) >> 20) & 0xf) 423 #define PCI_CAP_AGP_MINOR(cr) (((cr) >> 16) & 0xf) 424 #define PCI_CAP_VPD 0x03 425 #define PCI_CAP_SLOTID 0x04 426 #define PCI_CAP_MSI 0x05 427 #define PCI_CAP_CPCI_HOTSWAP 0x06 428 #define PCI_CAP_PCIX 0x07 429 #define PCI_CAP_LDT 0x08 430 #define PCI_CAP_VENDSPEC 0x09 431 #define PCI_CAP_DEBUGPORT 0x0a 432 #define PCI_CAP_CPCI_RSRCCTL 0x0b 433 #define PCI_CAP_HOTPLUG 0x0c 434 #define PCI_CAP_AGP8 0x0e 435 #define PCI_CAP_SECURE 0x0f 436 #define PCI_CAP_PCIEXPRESS 0x10 437 #define PCI_CAP_MSIX 0x11 438 439 /* 440 * Vital Product Data; access via capability pointer (PCI rev 2.2). 441 */ 442 #define PCI_VPD_ADDRESS_MASK 0x7fff 443 #define PCI_VPD_ADDRESS_SHIFT 16 444 #define PCI_VPD_ADDRESS(ofs) \ 445 (((ofs) & PCI_VPD_ADDRESS_MASK) << PCI_VPD_ADDRESS_SHIFT) 446 #define PCI_VPD_DATAREG(ofs) ((ofs) + 4) 447 #define PCI_VPD_OPFLAG 0x80000000 448 449 /* 450 * Power Management Capability; access via capability pointer. 451 */ 452 453 /* Power Management Capability Register */ 454 #define PCI_PMCR_SHIFT 16 455 #define PCI_PMCR 0x02 456 #define PCI_PMCR_D1SUPP 0x0200 457 #define PCI_PMCR_D2SUPP 0x0400 458 /* Power Management Control Status Register */ 459 #define PCI_PMCSR 0x04 460 #define PCI_PMCSR_STATE_MASK 0x03 461 #define PCI_PMCSR_STATE_D0 0x00 462 #define PCI_PMCSR_STATE_D1 0x01 463 #define PCI_PMCSR_STATE_D2 0x02 464 #define PCI_PMCSR_STATE_D3 0x03 465 466 /* 467 * PCI-X capability. 468 */ 469 470 /* 471 * Command. 16 bits at offset 2 (e.g. upper 16 bits of the first 32-bit 472 * word at the capability; the lower 16 bits are the capability ID and 473 * next capability pointer). 474 * 475 * Since we always read PCI config space in 32-bit words, we define these 476 * as 32-bit values, offset and shifted appropriately. Make sure you perform 477 * the appropriate R/M/W cycles! 478 */ 479 #define PCI_PCIX_CMD 0x00 480 #define PCI_PCIX_CMD_PERR_RECOVER 0x00010000 481 #define PCI_PCIX_CMD_RELAXED_ORDER 0x00020000 482 #define PCI_PCIX_CMD_BYTECNT_MASK 0x000c0000 483 #define PCI_PCIX_CMD_BYTECNT_SHIFT 18 484 #define PCI_PCIX_CMD_BCNT_512 0x00000000 485 #define PCI_PCIX_CMD_BCNT_1024 0x00040000 486 #define PCI_PCIX_CMD_BCNT_2048 0x00080000 487 #define PCI_PCIX_CMD_BCNT_4096 0x000c0000 488 #define PCI_PCIX_CMD_SPLTRANS_MASK 0x00700000 489 #define PCI_PCIX_CMD_SPLTRANS_1 0x00000000 490 #define PCI_PCIX_CMD_SPLTRANS_2 0x00100000 491 #define PCI_PCIX_CMD_SPLTRANS_3 0x00200000 492 #define PCI_PCIX_CMD_SPLTRANS_4 0x00300000 493 #define PCI_PCIX_CMD_SPLTRANS_8 0x00400000 494 #define PCI_PCIX_CMD_SPLTRANS_12 0x00500000 495 #define PCI_PCIX_CMD_SPLTRANS_16 0x00600000 496 #define PCI_PCIX_CMD_SPLTRANS_32 0x00700000 497 498 /* 499 * Status. 32 bits at offset 4. 500 */ 501 #define PCI_PCIX_STATUS 0x04 502 #define PCI_PCIX_STATUS_FN_MASK 0x00000007 503 #define PCI_PCIX_STATUS_DEV_MASK 0x000000f8 504 #define PCI_PCIX_STATUS_BUS_MASK 0x0000ff00 505 #define PCI_PCIX_STATUS_64BIT 0x00010000 506 #define PCI_PCIX_STATUS_133 0x00020000 507 #define PCI_PCIX_STATUS_SPLDISC 0x00040000 508 #define PCI_PCIX_STATUS_SPLUNEX 0x00080000 509 #define PCI_PCIX_STATUS_DEVCPLX 0x00100000 510 #define PCI_PCIX_STATUS_MAXB_MASK 0x00600000 511 #define PCI_PCIX_STATUS_MAXB_SHIFT 21 512 #define PCI_PCIX_STATUS_MAXB_512 0x00000000 513 #define PCI_PCIX_STATUS_MAXB_1024 0x00200000 514 #define PCI_PCIX_STATUS_MAXB_2048 0x00400000 515 #define PCI_PCIX_STATUS_MAXB_4096 0x00600000 516 #define PCI_PCIX_STATUS_MAXST_MASK 0x03800000 517 #define PCI_PCIX_STATUS_MAXST_1 0x00000000 518 #define PCI_PCIX_STATUS_MAXST_2 0x00800000 519 #define PCI_PCIX_STATUS_MAXST_3 0x01000000 520 #define PCI_PCIX_STATUS_MAXST_4 0x01800000 521 #define PCI_PCIX_STATUS_MAXST_8 0x02000000 522 #define PCI_PCIX_STATUS_MAXST_12 0x02800000 523 #define PCI_PCIX_STATUS_MAXST_16 0x03000000 524 #define PCI_PCIX_STATUS_MAXST_32 0x03800000 525 #define PCI_PCIX_STATUS_MAXRS_MASK 0x1c000000 526 #define PCI_PCIX_STATUS_MAXRS_1K 0x00000000 527 #define PCI_PCIX_STATUS_MAXRS_2K 0x04000000 528 #define PCI_PCIX_STATUS_MAXRS_4K 0x08000000 529 #define PCI_PCIX_STATUS_MAXRS_8K 0x0c000000 530 #define PCI_PCIX_STATUS_MAXRS_16K 0x10000000 531 #define PCI_PCIX_STATUS_MAXRS_32K 0x14000000 532 #define PCI_PCIX_STATUS_MAXRS_64K 0x18000000 533 #define PCI_PCIX_STATUS_MAXRS_128K 0x1c000000 534 #define PCI_PCIX_STATUS_SCERR 0x20000000 535 536 537 /* 538 * Interrupt Configuration Register; contains interrupt pin and line. 539 */ 540 #define PCI_INTERRUPT_REG 0x3c 541 542 typedef u_int8_t pci_intr_latency_t; 543 typedef u_int8_t pci_intr_grant_t; 544 typedef u_int8_t pci_intr_pin_t; 545 typedef u_int8_t pci_intr_line_t; 546 547 #define PCI_MAX_LAT_SHIFT 24 548 #define PCI_MAX_LAT_MASK 0xff 549 #define PCI_MAX_LAT(icr) \ 550 (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK) 551 552 #define PCI_MIN_GNT_SHIFT 16 553 #define PCI_MIN_GNT_MASK 0xff 554 #define PCI_MIN_GNT(icr) \ 555 (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK) 556 557 #define PCI_INTERRUPT_GRANT_SHIFT 24 558 #define PCI_INTERRUPT_GRANT_MASK 0xff 559 #define PCI_INTERRUPT_GRANT(icr) \ 560 (((icr) >> PCI_INTERRUPT_GRANT_SHIFT) & PCI_INTERRUPT_GRANT_MASK) 561 562 #define PCI_INTERRUPT_LATENCY_SHIFT 16 563 #define PCI_INTERRUPT_LATENCY_MASK 0xff 564 #define PCI_INTERRUPT_LATENCY(icr) \ 565 (((icr) >> PCI_INTERRUPT_LATENCY_SHIFT) & PCI_INTERRUPT_LATENCY_MASK) 566 567 #define PCI_INTERRUPT_PIN_SHIFT 8 568 #define PCI_INTERRUPT_PIN_MASK 0xff 569 #define PCI_INTERRUPT_PIN(icr) \ 570 (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK) 571 572 #define PCI_INTERRUPT_LINE_SHIFT 0 573 #define PCI_INTERRUPT_LINE_MASK 0xff 574 #define PCI_INTERRUPT_LINE(icr) \ 575 (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK) 576 577 #define PCI_INTERRUPT_CODE(lat,gnt,pin,line) \ 578 ((((lat)&PCI_INTERRUPT_LATENCY_MASK)<<PCI_INTERRUPT_LATENCY_SHIFT)| \ 579 (((gnt)&PCI_INTERRUPT_GRANT_MASK) <<PCI_INTERRUPT_GRANT_SHIFT) | \ 580 (((pin)&PCI_INTERRUPT_PIN_MASK) <<PCI_INTERRUPT_PIN_SHIFT) | \ 581 (((line)&PCI_INTERRUPT_LINE_MASK) <<PCI_INTERRUPT_LINE_SHIFT)) 582 583 #define PCI_INTERRUPT_PIN_NONE 0x00 584 #define PCI_INTERRUPT_PIN_A 0x01 585 #define PCI_INTERRUPT_PIN_B 0x02 586 #define PCI_INTERRUPT_PIN_C 0x03 587 #define PCI_INTERRUPT_PIN_D 0x04 588 #define PCI_INTERRUPT_PIN_MAX 0x04 589 590 /* Header Type 1 (Bridge) configuration registers */ 591 #define PCI_BRIDGE_BUS_REG 0x18 592 #define PCI_BRIDGE_BUS_PRIMARY_SHIFT 0 593 #define PCI_BRIDGE_BUS_SECONDARY_SHIFT 8 594 #define PCI_BRIDGE_BUS_SUBORDINATE_SHIFT 16 595 596 #define PCI_BRIDGE_STATIO_REG 0x1C 597 #define PCI_BRIDGE_STATIO_IOBASE_SHIFT 0 598 #define PCI_BRIDGE_STATIO_IOLIMIT_SHIFT 8 599 #define PCI_BRIDGE_STATIO_STATUS_SHIFT 16 600 #define PCI_BRIDGE_STATIO_IOBASE_MASK 0xf0 601 #define PCI_BRIDGE_STATIO_IOLIMIT_MASK 0xf0 602 #define PCI_BRIDGE_STATIO_STATUS_MASK 0xffff 603 #define PCI_BRIDGE_IO_32BITS(reg) (((reg) & 0xf) == 1) 604 605 #define PCI_BRIDGE_MEMORY_REG 0x20 606 #define PCI_BRIDGE_MEMORY_BASE_SHIFT 4 607 #define PCI_BRIDGE_MEMORY_LIMIT_SHIFT 20 608 #define PCI_BRIDGE_MEMORY_BASE_MASK 0x0fff 609 #define PCI_BRIDGE_MEMORY_LIMIT_MASK 0x0fff 610 611 #define PCI_BRIDGE_PREFETCHMEM_REG 0x24 612 #define PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT 4 613 #define PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT 20 614 #define PCI_BRIDGE_PREFETCHMEM_BASE_MASK 0x0fff 615 #define PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK 0x0fff 616 #define PCI_BRIDGE_PREFETCHMEM_64BITS(reg) ((reg) & 0xf) 617 618 #define PCI_BRIDGE_PREFETCHBASE32_REG 0x28 619 #define PCI_BRIDGE_PREFETCHLIMIT32_REG 0x2C 620 621 #define PCI_BRIDGE_IOHIGH_REG 0x30 622 #define PCI_BRIDGE_IOHIGH_BASE_SHIFT 0 623 #define PCI_BRIDGE_IOHIGH_LIMIT_SHIFT 16 624 #define PCI_BRIDGE_IOHIGH_BASE_MASK 0xffff 625 #define PCI_BRIDGE_IOHIGH_LIMIT_MASK 0xffff 626 627 #define PCI_BRIDGE_CONTROL_REG 0x3C 628 #define PCI_BRIDGE_CONTROL_SHIFT 16 629 #define PCI_BRIDGE_CONTROL_MASK 0xffff 630 #define PCI_BRIDGE_CONTROL_PERE (1 << 0) 631 #define PCI_BRIDGE_CONTROL_SERR (1 << 1) 632 #define PCI_BRIDGE_CONTROL_ISA (1 << 2) 633 #define PCI_BRIDGE_CONTROL_VGA (1 << 3) 634 /* Reserved (1 << 4) */ 635 #define PCI_BRIDGE_CONTROL_MABRT (1 << 5) 636 #define PCI_BRIDGE_CONTROL_SECBR (1 << 6) 637 #define PCI_BRIDGE_CONTROL_SECFASTB2B (1 << 7) 638 #define PCI_BRIDGE_CONTROL_PRI_DISC_TIMER (1 << 8) 639 #define PCI_BRIDGE_CONTROL_SEC_DISC_TIMER (1 << 9) 640 #define PCI_BRIDGE_CONTROL_DISC_TIMER_STAT (1 << 10) 641 #define PCI_BRIDGE_CONTROL_DISC_TIMER_SERR (1 << 11) 642 /* Reserved (1 << 12) - (1 << 15) */ 643 644 /* 645 * Vital Product Data resource tags. 646 */ 647 struct pci_vpd_smallres { 648 uint8_t vpdres_byte0; /* length of data + tag */ 649 /* Actual data. */ 650 } __attribute__((__packed__)); 651 652 struct pci_vpd_largeres { 653 uint8_t vpdres_byte0; 654 uint8_t vpdres_len_lsb; /* length of data only */ 655 uint8_t vpdres_len_msb; 656 /* Actual data. */ 657 } __attribute__((__packed__)); 658 659 #define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) 660 661 #define PCI_VPDRES_SMALL_LENGTH(x) ((x) & 0x7) 662 #define PCI_VPDRES_SMALL_NAME(x) (((x) >> 3) & 0xf) 663 664 #define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) 665 666 #define PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID 0x3 /* small */ 667 #define PCI_VPDRES_TYPE_VENDOR_DEFINED 0xe /* small */ 668 #define PCI_VPDRES_TYPE_END_TAG 0xf /* small */ 669 670 #define PCI_VPDRES_TYPE_IDENTIFIER_STRING 0x02 /* large */ 671 #define PCI_VPDRES_TYPE_VPD 0x10 /* large */ 672 673 struct pci_vpd { 674 uint8_t vpd_key0; 675 uint8_t vpd_key1; 676 uint8_t vpd_len; /* length of data only */ 677 /* Actual data. */ 678 } __attribute__((__packed__)); 679 680 /* 681 * Recommended VPD fields: 682 * 683 * PN Part number of assembly 684 * FN FRU part number 685 * EC EC level of assembly 686 * MN Manufacture ID 687 * SN Serial Number 688 * 689 * Conditionally recommended VPD fields: 690 * 691 * LI Load ID 692 * RL ROM Level 693 * RM Alterable ROM Level 694 * NA Network Address 695 * DD Device Driver Level 696 * DG Diagnostic Level 697 * LL Loadable Microcode Level 698 * VI Vendor ID/Device ID 699 * FU Function Number 700 * SI Subsystem Vendor ID/Subsystem ID 701 * 702 * Additional VPD fields: 703 * 704 * Z0-ZZ User/Product Specific 705 */ 706 707 /* 708 * PCI Expansion Rom 709 */ 710 711 struct pci_rom_header { 712 uint16_t romh_magic; /* 0xAA55 little endian */ 713 uint8_t romh_reserved[22]; 714 uint16_t romh_data_ptr; /* pointer to pci_rom struct */ 715 } __attribute__((__packed__)); 716 717 #define PCI_ROM_HEADER_MAGIC 0xAA55 /* little endian */ 718 719 struct pci_rom { 720 uint32_t rom_signature; 721 pci_vendor_id_t rom_vendor; 722 pci_product_id_t rom_product; 723 uint16_t rom_vpd_ptr; /* reserved in PCI 2.2 */ 724 uint16_t rom_data_len; 725 uint8_t rom_data_rev; 726 pci_interface_t rom_interface; /* the class reg is 24-bits */ 727 pci_subclass_t rom_subclass; /* in little endian */ 728 pci_class_t rom_class; 729 uint16_t rom_len; /* code length / 512 byte */ 730 uint16_t rom_rev; /* code revision level */ 731 uint8_t rom_code_type; /* type of code */ 732 uint8_t rom_indicator; 733 uint16_t rom_reserved; 734 /* Actual data. */ 735 } __attribute__((__packed__)); 736 737 #define PCI_ROM_SIGNATURE 0x52494350 /* "PCIR", endian reversed */ 738 #define PCI_ROM_CODE_TYPE_X86 0 /* Intel x86 BIOS */ 739 #define PCI_ROM_CODE_TYPE_OFW 1 /* Open Firmware */ 740 #define PCI_ROM_CODE_TYPE_HPPA 2 /* HP PA/RISC */ 741 742 #define PCI_ROM_INDICATOR_LAST 0x80 743 744 /* 745 * Threshold below which 32bit PCI DMA needs bouncing. 746 */ 747 #define PCI32_DMA_BOUNCE_THRESHOLD 0x100000000ULL 748 749 #endif /* _DEV_PCI_PCIREG_H_ */ 750