1 /* $NetBSD: pcireg.h,v 1.101 2015/02/23 04:16:17 knakahara Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1999, 2000 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _DEV_PCI_PCIREG_H_ 35 #define _DEV_PCI_PCIREG_H_ 36 37 /* 38 * Standardized PCI configuration information 39 * 40 * XXX This is not complete. 41 */ 42 43 /* 44 * Size of each function's configuration space. 45 */ 46 47 #define PCI_CONF_SIZE 0x100 48 #define PCI_EXTCONF_SIZE 0x1000 49 50 /* 51 * Device identification register; contains a vendor ID and a device ID. 52 */ 53 #define PCI_ID_REG 0x00 54 55 typedef u_int16_t pci_vendor_id_t; 56 typedef u_int16_t pci_product_id_t; 57 58 #define PCI_VENDOR_SHIFT 0 59 #define PCI_VENDOR_MASK 0xffff 60 #define PCI_VENDOR(id) \ 61 (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK) 62 63 #define PCI_PRODUCT_SHIFT 16 64 #define PCI_PRODUCT_MASK 0xffff 65 #define PCI_PRODUCT(id) \ 66 (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) 67 68 #define PCI_ID_CODE(vid,pid) \ 69 ((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) | \ 70 (((pid) & PCI_PRODUCT_MASK) << PCI_PRODUCT_SHIFT)) \ 71 72 /* 73 * Command and status register. 74 */ 75 #define PCI_COMMAND_STATUS_REG 0x04 76 #define PCI_COMMAND_SHIFT 0 77 #define PCI_COMMAND_MASK 0xffff 78 #define PCI_STATUS_SHIFT 16 79 #define PCI_STATUS_MASK 0xffff 80 81 #define PCI_COMMAND_STATUS_CODE(cmd,stat) \ 82 ((((cmd) & PCI_COMMAND_MASK) << PCI_COMMAND_SHIFT) | \ 83 (((stat) & PCI_STATUS_MASK) << PCI_STATUS_SHIFT)) \ 84 85 #define PCI_COMMAND_IO_ENABLE 0x00000001 86 #define PCI_COMMAND_MEM_ENABLE 0x00000002 87 #define PCI_COMMAND_MASTER_ENABLE 0x00000004 88 #define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 89 #define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 90 #define PCI_COMMAND_PALETTE_ENABLE 0x00000020 91 #define PCI_COMMAND_PARITY_ENABLE 0x00000040 92 #define PCI_COMMAND_STEPPING_ENABLE 0x00000080 93 #define PCI_COMMAND_SERR_ENABLE 0x00000100 94 #define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 95 #define PCI_COMMAND_INTERRUPT_DISABLE 0x00000400 96 97 #define PCI_STATUS_INT_STATUS 0x00080000 98 #define PCI_STATUS_CAPLIST_SUPPORT 0x00100000 99 #define PCI_STATUS_66MHZ_SUPPORT 0x00200000 100 #define PCI_STATUS_UDF_SUPPORT 0x00400000 101 #define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000 102 #define PCI_STATUS_PARITY_ERROR 0x01000000 103 #define PCI_STATUS_DEVSEL_FAST 0x00000000 104 #define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 105 #define PCI_STATUS_DEVSEL_SLOW 0x04000000 106 #define PCI_STATUS_DEVSEL_MASK 0x06000000 107 #define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 108 #define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 109 #define PCI_STATUS_MASTER_ABORT 0x20000000 110 #define PCI_STATUS_SPECIAL_ERROR 0x40000000 111 #define PCI_STATUS_PARITY_DETECT 0x80000000 112 113 /* 114 * PCI Class and Revision Register; defines type and revision of device. 115 */ 116 #define PCI_CLASS_REG 0x08 117 118 typedef u_int8_t pci_class_t; 119 typedef u_int8_t pci_subclass_t; 120 typedef u_int8_t pci_interface_t; 121 typedef u_int8_t pci_revision_t; 122 123 #define PCI_CLASS_SHIFT 24 124 #define PCI_CLASS_MASK 0xff 125 #define PCI_CLASS(cr) \ 126 (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) 127 128 #define PCI_SUBCLASS_SHIFT 16 129 #define PCI_SUBCLASS_MASK 0xff 130 #define PCI_SUBCLASS(cr) \ 131 (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) 132 133 #define PCI_INTERFACE_SHIFT 8 134 #define PCI_INTERFACE_MASK 0xff 135 #define PCI_INTERFACE(cr) \ 136 (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) 137 138 #define PCI_REVISION_SHIFT 0 139 #define PCI_REVISION_MASK 0xff 140 #define PCI_REVISION(cr) \ 141 (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) 142 143 #define PCI_CLASS_CODE(mainclass, subclass, interface) \ 144 ((((mainclass) & PCI_CLASS_MASK) << PCI_CLASS_SHIFT) | \ 145 (((subclass) & PCI_SUBCLASS_MASK) << PCI_SUBCLASS_SHIFT) | \ 146 (((interface) & PCI_INTERFACE_MASK) << PCI_INTERFACE_SHIFT)) 147 148 /* base classes */ 149 #define PCI_CLASS_PREHISTORIC 0x00 150 #define PCI_CLASS_MASS_STORAGE 0x01 151 #define PCI_CLASS_NETWORK 0x02 152 #define PCI_CLASS_DISPLAY 0x03 153 #define PCI_CLASS_MULTIMEDIA 0x04 154 #define PCI_CLASS_MEMORY 0x05 155 #define PCI_CLASS_BRIDGE 0x06 156 #define PCI_CLASS_COMMUNICATIONS 0x07 157 #define PCI_CLASS_SYSTEM 0x08 158 #define PCI_CLASS_INPUT 0x09 159 #define PCI_CLASS_DOCK 0x0a 160 #define PCI_CLASS_PROCESSOR 0x0b 161 #define PCI_CLASS_SERIALBUS 0x0c 162 #define PCI_CLASS_WIRELESS 0x0d 163 #define PCI_CLASS_I2O 0x0e 164 #define PCI_CLASS_SATCOM 0x0f 165 #define PCI_CLASS_CRYPTO 0x10 166 #define PCI_CLASS_DASP 0x11 167 #define PCI_CLASS_UNDEFINED 0xff 168 169 /* 0x00 prehistoric subclasses */ 170 #define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 171 #define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 172 173 /* 0x01 mass storage subclasses */ 174 #define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 175 #define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 176 #define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 177 #define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 178 #define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04 179 #define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05 180 #define PCI_INTERFACE_ATA_SINGLEDMA 0x20 181 #define PCI_INTERFACE_ATA_CHAINEDDMA 0x30 182 #define PCI_SUBCLASS_MASS_STORAGE_SATA 0x06 183 #define PCI_INTERFACE_SATA_VND 0x00 184 #define PCI_INTERFACE_SATA_AHCI10 0x01 185 #define PCI_INTERFACE_SATA_SSBI 0x02 186 #define PCI_SUBCLASS_MASS_STORAGE_SAS 0x07 187 #define PCI_SUBCLASS_MASS_STORAGE_NVM 0x08 188 #define PCI_INTERFACE_NVM_VND 0x00 189 #define PCI_INTERFACE_NVM_NVMHCI10 0x01 190 #define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 191 192 /* 0x02 network subclasses */ 193 #define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 194 #define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 195 #define PCI_SUBCLASS_NETWORK_FDDI 0x02 196 #define PCI_SUBCLASS_NETWORK_ATM 0x03 197 #define PCI_SUBCLASS_NETWORK_ISDN 0x04 198 #define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05 199 #define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06 200 #define PCI_SUBCLASS_NETWORK_INFINIBAND 0x07 201 #define PCI_SUBCLASS_NETWORK_MISC 0x80 202 203 /* 0x03 display subclasses */ 204 #define PCI_SUBCLASS_DISPLAY_VGA 0x00 205 #define PCI_INTERFACE_VGA_VGA 0x00 206 #define PCI_INTERFACE_VGA_8514 0x01 207 #define PCI_SUBCLASS_DISPLAY_XGA 0x01 208 #define PCI_SUBCLASS_DISPLAY_3D 0x02 209 #define PCI_SUBCLASS_DISPLAY_MISC 0x80 210 211 /* 0x04 multimedia subclasses */ 212 #define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 213 #define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 214 #define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02 215 #define PCI_SUBCLASS_MULTIMEDIA_HDAUDIO 0x03 216 #define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 217 218 /* 0x05 memory subclasses */ 219 #define PCI_SUBCLASS_MEMORY_RAM 0x00 220 #define PCI_SUBCLASS_MEMORY_FLASH 0x01 221 #define PCI_SUBCLASS_MEMORY_MISC 0x80 222 223 /* 0x06 bridge subclasses */ 224 #define PCI_SUBCLASS_BRIDGE_HOST 0x00 225 #define PCI_SUBCLASS_BRIDGE_ISA 0x01 226 #define PCI_SUBCLASS_BRIDGE_EISA 0x02 227 #define PCI_SUBCLASS_BRIDGE_MC 0x03 /* XXX _MCA */ 228 #define PCI_SUBCLASS_BRIDGE_PCI 0x04 229 #define PCI_INTERFACE_BRIDGE_PCI_PCI 0x00 230 #define PCI_INTERFACE_BRIDGE_PCI_SUBDEC 0x01 231 #define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 232 #define PCI_SUBCLASS_BRIDGE_NUBUS 0x06 233 #define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 234 #define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08 235 /* bit0 == 0 ? "transparent mode" : "endpoint mode" */ 236 #define PCI_SUBCLASS_BRIDGE_STPCI 0x09 237 #define PCI_INTERFACE_STPCI_PRIMARY 0x40 238 #define PCI_INTERFACE_STPCI_SECONDARY 0x80 239 #define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a 240 #define PCI_SUBCLASS_BRIDGE_ADVSW 0x0b 241 #define PCI_INTERFACE_ADVSW_CUSTOM 0x00 242 #define PCI_INTERFACE_ADVSW_ASISIG 0x01 243 #define PCI_SUBCLASS_BRIDGE_MISC 0x80 244 245 /* 0x07 communications subclasses */ 246 #define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 247 #define PCI_INTERFACE_SERIAL_XT 0x00 248 #define PCI_INTERFACE_SERIAL_16450 0x01 249 #define PCI_INTERFACE_SERIAL_16550 0x02 250 #define PCI_INTERFACE_SERIAL_16650 0x03 251 #define PCI_INTERFACE_SERIAL_16750 0x04 252 #define PCI_INTERFACE_SERIAL_16850 0x05 253 #define PCI_INTERFACE_SERIAL_16950 0x06 254 #define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 255 #define PCI_INTERFACE_PARALLEL 0x00 256 #define PCI_INTERFACE_PARALLEL_BIDIRECTIONAL 0x01 257 #define PCI_INTERFACE_PARALLEL_ECP1X 0x02 258 #define PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL 0x03 259 #define PCI_INTERFACE_PARALLEL_IEEE1284_TGT 0xfe 260 #define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02 261 #define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03 262 #define PCI_INTERFACE_MODEM 0x00 263 #define PCI_INTERFACE_MODEM_HAYES16450 0x01 264 #define PCI_INTERFACE_MODEM_HAYES16550 0x02 265 #define PCI_INTERFACE_MODEM_HAYES16650 0x03 266 #define PCI_INTERFACE_MODEM_HAYES16750 0x04 267 #define PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04 268 #define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05 269 #define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 270 271 /* 0x08 system subclasses */ 272 #define PCI_SUBCLASS_SYSTEM_PIC 0x00 273 #define PCI_INTERFACE_PIC_8259 0x00 274 #define PCI_INTERFACE_PIC_ISA 0x01 275 #define PCI_INTERFACE_PIC_EISA 0x02 276 #define PCI_INTERFACE_PIC_IOAPIC 0x10 277 #define PCI_INTERFACE_PIC_IOXAPIC 0x20 278 #define PCI_SUBCLASS_SYSTEM_DMA 0x01 279 #define PCI_INTERFACE_DMA_8237 0x00 280 #define PCI_INTERFACE_DMA_ISA 0x01 281 #define PCI_INTERFACE_DMA_EISA 0x02 282 #define PCI_SUBCLASS_SYSTEM_TIMER 0x02 283 #define PCI_INTERFACE_TIMER_8254 0x00 284 #define PCI_INTERFACE_TIMER_ISA 0x01 285 #define PCI_INTERFACE_TIMER_EISA 0x02 286 #define PCI_INTERFACE_TIMER_HPET 0x03 287 #define PCI_SUBCLASS_SYSTEM_RTC 0x03 288 #define PCI_INTERFACE_RTC_GENERIC 0x00 289 #define PCI_INTERFACE_RTC_ISA 0x01 290 #define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04 291 #define PCI_SUBCLASS_SYSTEM_SDHC 0x05 292 #define PCI_SUBCLASS_SYSTEM_IOMMU 0x06 /* or RCEC in old spec */ 293 #define PCI_SUBCLASS_SYSTEM_RCEC 0x07 294 #define PCI_SUBCLASS_SYSTEM_MISC 0x80 295 296 /* 0x09 input subclasses */ 297 #define PCI_SUBCLASS_INPUT_KEYBOARD 0x00 298 #define PCI_SUBCLASS_INPUT_DIGITIZER 0x01 299 #define PCI_SUBCLASS_INPUT_MOUSE 0x02 300 #define PCI_SUBCLASS_INPUT_SCANNER 0x03 301 #define PCI_SUBCLASS_INPUT_GAMEPORT 0x04 302 #define PCI_INTERFACE_GAMEPORT_GENERIC 0x00 303 #define PCI_INTERFACE_GAMEPORT_LEGACY 0x10 304 #define PCI_SUBCLASS_INPUT_MISC 0x80 305 306 /* 0x0a dock subclasses */ 307 #define PCI_SUBCLASS_DOCK_GENERIC 0x00 308 #define PCI_SUBCLASS_DOCK_MISC 0x80 309 310 /* 0x0b processor subclasses */ 311 #define PCI_SUBCLASS_PROCESSOR_386 0x00 312 #define PCI_SUBCLASS_PROCESSOR_486 0x01 313 #define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02 314 #define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10 315 #define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20 316 #define PCI_SUBCLASS_PROCESSOR_MIPS 0x30 317 #define PCI_SUBCLASS_PROCESSOR_COPROC 0x40 318 #define PCI_SUBCLASS_PROCESSOR_MISC 0x80 319 320 /* 0x0c serial bus subclasses */ 321 #define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00 322 #define PCI_INTERFACE_IEEE1394_FIREWIRE 0x00 323 #define PCI_INTERFACE_IEEE1394_OPENHCI 0x10 324 #define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01 325 #define PCI_SUBCLASS_SERIALBUS_SSA 0x02 326 #define PCI_SUBCLASS_SERIALBUS_USB 0x03 327 #define PCI_INTERFACE_USB_UHCI 0x00 328 #define PCI_INTERFACE_USB_OHCI 0x10 329 #define PCI_INTERFACE_USB_EHCI 0x20 330 #define PCI_INTERFACE_USB_XHCI 0x30 331 #define PCI_INTERFACE_USB_OTHERHC 0x80 332 #define PCI_INTERFACE_USB_DEVICE 0xfe 333 #define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 /* XXX _FIBRECHANNEL */ 334 #define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05 335 #define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06 /* Deprecated */ 336 #define PCI_SUBCLASS_SERIALBUS_IPMI 0x07 337 #define PCI_INTERFACE_IPMI_SMIC 0x00 338 #define PCI_INTERFACE_IPMI_KBD 0x01 339 #define PCI_INTERFACE_IPMI_BLOCKXFER 0x02 340 #define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08 341 #define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09 342 #define PCI_SUBCLASS_SERIALBUS_MISC 0x80 343 344 /* 0x0d wireless subclasses */ 345 #define PCI_SUBCLASS_WIRELESS_IRDA 0x00 346 #define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01 347 #define PCI_INTERFACE_CONSUMERIR 0x00 348 #define PCI_INTERFACE_UWB 0x10 349 #define PCI_SUBCLASS_WIRELESS_RF 0x10 350 #define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11 351 #define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12 352 #define PCI_SUBCLASS_WIRELESS_802_11A 0x20 353 #define PCI_SUBCLASS_WIRELESS_802_11B 0x21 354 #define PCI_SUBCLASS_WIRELESS_MISC 0x80 355 356 /* 0x0e I2O (Intelligent I/O) subclasses */ 357 #define PCI_SUBCLASS_I2O_STANDARD 0x00 358 #define PCI_INTERFACE_I2O_FIFOAT40 0x00 359 /* others for I2O spec */ 360 #define PCI_SUBCLASS_I2O_MISC 0x80 361 362 /* 0x0f satellite communication subclasses */ 363 /* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */ 364 #define PCI_SUBCLASS_SATCOM_TV 0x01 365 #define PCI_SUBCLASS_SATCOM_AUDIO 0x02 366 #define PCI_SUBCLASS_SATCOM_VOICE 0x03 367 #define PCI_SUBCLASS_SATCOM_DATA 0x04 368 #define PCI_SUBCLASS_SATCOM_MISC 0x80 369 370 /* 0x10 encryption/decryption subclasses */ 371 #define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00 372 #define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10 373 #define PCI_SUBCLASS_CRYPTO_MISC 0x80 374 375 /* 0x11 data acquisition and signal processing subclasses */ 376 #define PCI_SUBCLASS_DASP_DPIO 0x00 377 #define PCI_SUBCLASS_DASP_TIMEFREQ 0x01 /* performance counters */ 378 #define PCI_SUBCLASS_DASP_SYNC 0x10 379 #define PCI_SUBCLASS_DASP_MGMT 0x20 380 #define PCI_SUBCLASS_DASP_MISC 0x80 381 382 /* 383 * PCI BIST/Header Type/Latency Timer/Cache Line Size Register. 384 */ 385 #define PCI_BHLC_REG 0x0c 386 387 #define PCI_BIST_SHIFT 24 388 #define PCI_BIST_MASK 0xff 389 #define PCI_BIST(bhlcr) \ 390 (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK) 391 392 #define PCI_HDRTYPE_SHIFT 16 393 #define PCI_HDRTYPE_MASK 0xff 394 #define PCI_HDRTYPE(bhlcr) \ 395 (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK) 396 397 #define PCI_HDRTYPE_TYPE(bhlcr) \ 398 (PCI_HDRTYPE(bhlcr) & 0x7f) 399 #define PCI_HDRTYPE_MULTIFN(bhlcr) \ 400 ((PCI_HDRTYPE(bhlcr) & 0x80) != 0) 401 402 #define PCI_LATTIMER_SHIFT 8 403 #define PCI_LATTIMER_MASK 0xff 404 #define PCI_LATTIMER(bhlcr) \ 405 (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK) 406 407 #define PCI_CACHELINE_SHIFT 0 408 #define PCI_CACHELINE_MASK 0xff 409 #define PCI_CACHELINE(bhlcr) \ 410 (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK) 411 412 #define PCI_BHLC_CODE(bist,type,multi,latency,cacheline) \ 413 ((((bist) & PCI_BIST_MASK) << PCI_BIST_SHIFT) | \ 414 (((type) & PCI_HDRTYPE_MASK) << PCI_HDRTYPE_SHIFT) | \ 415 (((multi)?0x80:0) << PCI_HDRTYPE_SHIFT) | \ 416 (((latency) & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT) | \ 417 (((cacheline) & PCI_CACHELINE_MASK) << PCI_CACHELINE_SHIFT)) 418 419 /* 420 * PCI header type 421 */ 422 #define PCI_HDRTYPE_DEVICE 0 /* PCI/PCIX/Cardbus */ 423 #define PCI_HDRTYPE_PPB 1 /* PCI/PCIX/Cardbus */ 424 #define PCI_HDRTYPE_PCB 2 /* PCI/PCIX/Cardbus */ 425 #define PCI_HDRTYPE_EP 0 /* PCI Express */ 426 #define PCI_HDRTYPE_RC 1 /* PCI Express */ 427 428 429 /* 430 * Mapping registers 431 */ 432 #define PCI_MAPREG_START 0x10 433 #define PCI_MAPREG_END 0x28 434 #define PCI_MAPREG_ROM 0x30 435 #define PCI_MAPREG_PPB_END 0x18 436 #define PCI_MAPREG_PCB_END 0x14 437 438 #define PCI_BAR0 0x10 439 #define PCI_BAR1 0x14 440 #define PCI_BAR2 0x18 441 #define PCI_BAR3 0x1C 442 #define PCI_BAR4 0x20 443 #define PCI_BAR5 0x24 444 445 #define PCI_BAR(__n) (PCI_MAPREG_START + 4 * (__n)) 446 447 #define PCI_MAPREG_TYPE(mr) \ 448 ((mr) & PCI_MAPREG_TYPE_MASK) 449 #define PCI_MAPREG_TYPE_MASK 0x00000001 450 451 #define PCI_MAPREG_TYPE_MEM 0x00000000 452 #define PCI_MAPREG_TYPE_ROM 0x00000000 453 #define PCI_MAPREG_TYPE_IO 0x00000001 454 #define PCI_MAPREG_ROM_ENABLE 0x00000001 455 456 #define PCI_MAPREG_MEM_TYPE(mr) \ 457 ((mr) & PCI_MAPREG_MEM_TYPE_MASK) 458 #define PCI_MAPREG_MEM_TYPE_MASK 0x00000006 459 460 #define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000 461 #define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002 462 #define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 463 464 #define PCI_MAPREG_MEM_PREFETCHABLE(mr) \ 465 (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0) 466 #define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008 467 468 #define PCI_MAPREG_MEM_ADDR(mr) \ 469 ((mr) & PCI_MAPREG_MEM_ADDR_MASK) 470 #define PCI_MAPREG_MEM_SIZE(mr) \ 471 (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr)) 472 #define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 473 474 #define PCI_MAPREG_MEM64_ADDR(mr) \ 475 ((mr) & PCI_MAPREG_MEM64_ADDR_MASK) 476 #define PCI_MAPREG_MEM64_SIZE(mr) \ 477 (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr)) 478 #define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL 479 480 #define PCI_MAPREG_IO_ADDR(mr) \ 481 ((mr) & PCI_MAPREG_IO_ADDR_MASK) 482 #define PCI_MAPREG_IO_SIZE(mr) \ 483 (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) 484 #define PCI_MAPREG_IO_ADDR_MASK 0xfffffffc 485 486 #define PCI_MAPREG_SIZE_TO_MASK(size) \ 487 (-(size)) 488 489 #define PCI_MAPREG_NUM(offset) \ 490 (((unsigned)(offset)-PCI_MAPREG_START)/4) 491 492 493 /* 494 * Cardbus CIS pointer (PCI rev. 2.1) 495 */ 496 #define PCI_CARDBUS_CIS_REG 0x28 497 498 /* 499 * Subsystem identification register; contains a vendor ID and a device ID. 500 * Types/macros for PCI_ID_REG apply. 501 * (PCI rev. 2.1) 502 */ 503 #define PCI_SUBSYS_ID_REG 0x2c 504 505 #define PCI_SUBSYS_VENDOR_MASK __BITS(15, 0) 506 #define PCI_SUBSYS_ID_MASK __BITS(31, 16) 507 508 #define PCI_SUBSYS_VENDOR(__subsys_id) \ 509 __SHIFTOUT(__subsys_id, PCI_SUBSYS_VENDOR_MASK) 510 511 #define PCI_SUBSYS_ID(__subsys_id) \ 512 __SHIFTOUT(__subsys_id, PCI_SUBSYS_ID_MASK) 513 514 /* 515 * Capabilities link list (PCI rev. 2.2) 516 */ 517 #define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */ 518 #define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */ 519 #define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff) 520 #define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff) 521 #define PCI_CAPLIST_CAP(cr) ((cr) & 0xff) 522 523 #define PCI_CAP_RESERVED0 0x00 524 #define PCI_CAP_PWRMGMT 0x01 525 #define PCI_CAP_AGP 0x02 526 #define PCI_CAP_AGP_MAJOR(cr) (((cr) >> 20) & 0xf) 527 #define PCI_CAP_AGP_MINOR(cr) (((cr) >> 16) & 0xf) 528 #define PCI_CAP_VPD 0x03 529 #define PCI_CAP_SLOTID 0x04 530 #define PCI_CAP_MSI 0x05 531 #define PCI_CAP_CPCI_HOTSWAP 0x06 532 #define PCI_CAP_PCIX 0x07 533 #define PCI_CAP_LDT 0x08 /* HyperTransport */ 534 #define PCI_CAP_VENDSPEC 0x09 535 #define PCI_CAP_DEBUGPORT 0x0a 536 #define PCI_CAP_CPCI_RSRCCTL 0x0b 537 #define PCI_CAP_HOTPLUG 0x0c 538 #define PCI_CAP_SUBVENDOR 0x0d 539 #define PCI_CAP_AGP8 0x0e 540 #define PCI_CAP_SECURE 0x0f 541 #define PCI_CAP_PCIEXPRESS 0x10 542 #define PCI_CAP_MSIX 0x11 543 #define PCI_CAP_SATA 0x12 544 #define PCI_CAP_PCIAF 0x13 545 546 /* 547 * Capability ID: 0x01 548 * Power Management Capability; access via capability pointer. 549 */ 550 551 /* Power Management Capability Register */ 552 #define PCI_PMCR_SHIFT 16 553 #define PCI_PMCR 0x02 554 #define PCI_PMCR_VERSION_MASK 0x0007 555 #define PCI_PMCR_VERSION_10 0x0001 556 #define PCI_PMCR_VERSION_11 0x0002 557 #define PCI_PMCR_VERSION_12 0x0003 558 #define PCI_PMCR_PME_CLOCK 0x0008 559 #define PCI_PMCR_DSI 0x0020 560 #define PCI_PMCR_AUXCUR_MASK 0x01c0 561 #define PCI_PMCR_AUXCUR_0 0x0000 562 #define PCI_PMCR_AUXCUR_55 0x0040 563 #define PCI_PMCR_AUXCUR_100 0x0080 564 #define PCI_PMCR_AUXCUR_160 0x00c0 565 #define PCI_PMCR_AUXCUR_220 0x0100 566 #define PCI_PMCR_AUXCUR_270 0x0140 567 #define PCI_PMCR_AUXCUR_320 0x0180 568 #define PCI_PMCR_AUXCUR_375 0x01c0 569 #define PCI_PMCR_D1SUPP 0x0200 570 #define PCI_PMCR_D2SUPP 0x0400 571 #define PCI_PMCR_PME_D0 0x0800 572 #define PCI_PMCR_PME_D1 0x1000 573 #define PCI_PMCR_PME_D2 0x2000 574 #define PCI_PMCR_PME_D3HOT 0x4000 575 #define PCI_PMCR_PME_D3COLD 0x8000 576 /* 577 * Power Management Control Status Register, Bridge Support Extensions Register 578 * and Data Register. 579 */ 580 #define PCI_PMCSR 0x04 581 #define PCI_PMCSR_STATE_MASK 0x00000003 582 #define PCI_PMCSR_STATE_D0 0x00000000 583 #define PCI_PMCSR_STATE_D1 0x00000001 584 #define PCI_PMCSR_STATE_D2 0x00000002 585 #define PCI_PMCSR_STATE_D3 0x00000003 586 #define PCI_PMCSR_NO_SOFTRST 0x00000008 587 #define PCI_PMCSR_PME_EN 0x00000100 588 #define PCI_PMCSR_DATASEL_MASK 0x00001e00 589 #define PCI_PMCSR_DATASCL_MASK 0x00006000 590 #define PCI_PMCSR_PME_STS 0x00008000 591 #define PCI_PMCSR_B2B3_SUPPORT 0x00400000 592 #define PCI_PMCSR_BPCC_EN 0x00800000 593 594 595 /* 596 * Capability ID: 0x02 597 * AGP 598 */ 599 600 /* 601 * Capability ID: 0x03 602 * Vital Product Data; access via capability pointer (PCI rev 2.2). 603 */ 604 #define PCI_VPD_ADDRESS_MASK 0x7fff 605 #define PCI_VPD_ADDRESS_SHIFT 16 606 #define PCI_VPD_ADDRESS(ofs) \ 607 (((ofs) & PCI_VPD_ADDRESS_MASK) << PCI_VPD_ADDRESS_SHIFT) 608 #define PCI_VPD_DATAREG(ofs) ((ofs) + 4) 609 #define PCI_VPD_OPFLAG 0x80000000 610 611 /* 612 * Capability ID: 0x04 613 * Slot ID 614 */ 615 616 /* 617 * Capability ID: 0x05 618 * MSI 619 */ 620 621 #define PCI_MSI_CTL 0x0 /* Message Control Register offset */ 622 #define PCI_MSI_MADDR 0x4 /* Message Address Register (least 623 * significant bits) offset 624 */ 625 #define PCI_MSI_MADDR64_LO 0x4 /* 64-bit Message Address Register 626 * (least significant bits) offset 627 */ 628 #define PCI_MSI_MADDR64_HI 0x8 /* 64-bit Message Address Register 629 * (most significant bits) offset 630 */ 631 #define PCI_MSI_MDATA 0x8 /* Message Data Register offset */ 632 #define PCI_MSI_MDATA64 0xC /* 64-bit Message Data Register 633 * offset 634 */ 635 #define PCI_MSI_MASK 0x10 /* Vector Mask register */ 636 #define PCI_MSI_PENDING 0x14 /* Vector Pending register */ 637 638 #define PCI_MSI_CTL_MASK __BITS(31, 16) 639 #define PCI_MSI_CTL_PERVEC_MASK __SHIFTIN(__BIT(8), PCI_MSI_CTL_MASK) 640 #define PCI_MSI_CTL_64BIT_ADDR __SHIFTIN(__BIT(7), PCI_MSI_CTL_MASK) 641 #define PCI_MSI_CTL_MME_MASK __SHIFTIN(__BITS(6, 4), PCI_MSI_CTL_MASK) 642 #define PCI_MSI_CTL_MME(reg) __SHIFTOUT(reg, PCI_MSI_CTL_MME_MASK) 643 #define PCI_MSI_CTL_MMC_MASK __SHIFTIN(__BITS(3, 1), PCI_MSI_CTL_MASK) 644 #define PCI_MSI_CTL_MMC(reg) __SHIFTOUT(reg, PCI_MSI_CTL_MMC_MASK) 645 #define PCI_MSI_CTL_MSI_ENABLE __SHIFTIN(__BIT(0), PCI_MSI_CTL_MASK) 646 647 /* 648 * MSI Message Address is at offset 4. 649 * MSI Message Upper Address (if 64bit) is at offset 8. 650 * MSI Message data is at offset 8 or 12 and is 16 bits. 651 * [16 bit reserved field] 652 * MSI Mask Bits (32 bit field) 653 * MSI Pending Bits (32 bit field) 654 */ 655 656 /* 657 * Capability ID: 0x07 658 * PCI-X capability. 659 * 660 * PCI-X capability register has two different layouts. One is for bridge 661 * function. Another is for non-bridge functions. 662 */ 663 664 665 /* For non-bridge functions */ 666 667 /* 668 * Command. 16 bits at offset 2 (e.g. upper 16 bits of the first 32-bit 669 * word at the capability; the lower 16 bits are the capability ID and 670 * next capability pointer). 671 * 672 * Since we always read PCI config space in 32-bit words, we define these 673 * as 32-bit values, offset and shifted appropriately. Make sure you perform 674 * the appropriate R/M/W cycles! 675 */ 676 #define PCIX_CMD 0x00 677 #define PCIX_CMD_PERR_RECOVER 0x00010000 678 #define PCIX_CMD_RELAXED_ORDER 0x00020000 679 #define PCIX_CMD_BYTECNT_MASK 0x000c0000 680 #define PCIX_CMD_BYTECNT_SHIFT 18 681 #define PCIX_CMD_BYTECNT(reg) \ 682 (512 << (((reg) & PCIX_CMD_BYTECNT_MASK) >> PCIX_CMD_BYTECNT_SHIFT)) 683 #define PCIX_CMD_BCNT_512 0x00000000 684 #define PCIX_CMD_BCNT_1024 0x00040000 685 #define PCIX_CMD_BCNT_2048 0x00080000 686 #define PCIX_CMD_BCNT_4096 0x000c0000 687 #define PCIX_CMD_SPLTRANS_MASK 0x00700000 688 #define PCIX_CMD_SPLTRANS_SHIFT 20 689 #define PCIX_CMD_SPLTRANS_1 0x00000000 690 #define PCIX_CMD_SPLTRANS_2 0x00100000 691 #define PCIX_CMD_SPLTRANS_3 0x00200000 692 #define PCIX_CMD_SPLTRANS_4 0x00300000 693 #define PCIX_CMD_SPLTRANS_8 0x00400000 694 #define PCIX_CMD_SPLTRANS_12 0x00500000 695 #define PCIX_CMD_SPLTRANS_16 0x00600000 696 #define PCIX_CMD_SPLTRANS_32 0x00700000 697 698 /* 699 * Status. 32 bits at offset 4. 700 */ 701 #define PCIX_STATUS 0x04 702 #define PCIX_STATUS_FN_MASK 0x00000007 703 #define PCIX_STATUS_DEV_MASK 0x000000f8 704 #define PCIX_STATUS_DEV_SHIFT 3 705 #define PCIX_STATUS_BUS_MASK 0x0000ff00 706 #define PCIX_STATUS_BUS_SHIFT 8 707 #define PCIX_STATUS_FN(val) ((val) & PCIX_STATUS_FN_MASK) 708 #define PCIX_STATUS_DEV(val) \ 709 (((val) & PCIX_STATUS_DEV_MASK) >> PCIX_STATUS_DEV_SHIFT) 710 #define PCIX_STATUS_BUS(val) \ 711 (((val) & PCIX_STATUS_BUS_MASK) >> PCIX_STATUS_BUS_SHIFT) 712 #define PCIX_STATUS_64BIT 0x00010000 /* 64bit device */ 713 #define PCIX_STATUS_133 0x00020000 /* 133MHz capable */ 714 #define PCIX_STATUS_SPLDISC 0x00040000 /* Split completion discarded*/ 715 #define PCIX_STATUS_SPLUNEX 0x00080000 /* Unexpected split complet. */ 716 #define PCIX_STATUS_DEVCPLX 0x00100000 /* Device Complexity */ 717 #define PCIX_STATUS_MAXB_MASK 0x00600000 /* MAX memory read Byte count*/ 718 #define PCIX_STATUS_MAXB_SHIFT 21 719 #define PCIX_STATUS_MAXB_512 0x00000000 720 #define PCIX_STATUS_MAXB_1024 0x00200000 721 #define PCIX_STATUS_MAXB_2048 0x00400000 722 #define PCIX_STATUS_MAXB_4096 0x00600000 723 #define PCIX_STATUS_MAXST_MASK 0x03800000 /* MAX outstand. Split Trans.*/ 724 #define PCIX_STATUS_MAXST_SHIFT 23 725 #define PCIX_STATUS_MAXST_1 0x00000000 726 #define PCIX_STATUS_MAXST_2 0x00800000 727 #define PCIX_STATUS_MAXST_3 0x01000000 728 #define PCIX_STATUS_MAXST_4 0x01800000 729 #define PCIX_STATUS_MAXST_8 0x02000000 730 #define PCIX_STATUS_MAXST_12 0x02800000 731 #define PCIX_STATUS_MAXST_16 0x03000000 732 #define PCIX_STATUS_MAXST_32 0x03800000 733 #define PCIX_STATUS_MAXRS_MASK 0x1c000000 /* MAX cumulative Read Size */ 734 #define PCIX_STATUS_MAXRS_SHIFT 26 735 #define PCIX_STATUS_MAXRS_1K 0x00000000 736 #define PCIX_STATUS_MAXRS_2K 0x04000000 737 #define PCIX_STATUS_MAXRS_4K 0x08000000 738 #define PCIX_STATUS_MAXRS_8K 0x0c000000 739 #define PCIX_STATUS_MAXRS_16K 0x10000000 740 #define PCIX_STATUS_MAXRS_32K 0x14000000 741 #define PCIX_STATUS_MAXRS_64K 0x18000000 742 #define PCIX_STATUS_MAXRS_128K 0x1c000000 743 #define PCIX_STATUS_SCERR 0x20000000 /* rcv. Split Completion ERR.*/ 744 #define PCIX_STATUS_266 0x40000000 /* 266MHz capable */ 745 #define PCIX_STATUS_533 0x80000000 /* 533MHz capable */ 746 747 /* For bridge function */ 748 749 #define PCIX_BRIDGE_2ND_STATUS 0x00 750 #define PCIX_BRIDGE_ST_64BIT 0x00010000 /* Same as PCIX_STATUS (nonb)*/ 751 #define PCIX_BRIDGE_ST_133 0x00020000 /* Same as PCIX_STATUS (nonb)*/ 752 #define PCIX_BRIDGE_ST_SPLDISC 0x00040000 /* Same as PCIX_STATUS (nonb)*/ 753 #define PCIX_BRIDGE_ST_SPLUNEX 0x00080000 /* Same as PCIX_STATUS (nonb)*/ 754 #define PCIX_BRIDGE_ST_SPLOVRN 0x00100000 /* Split completion overrun */ 755 #define PCIX_BRIDGE_ST_SPLRQDL 0x00200000 /* Split request delayed */ 756 #define PCIX_BRIDGE_2NDST_CLKF 0x03c00000 /* Secondary clock frequency */ 757 #define PCIX_BRIDGE_2NDST_CLKF_SHIFT 22 758 #define PCIX_BRIDGE_2NDST_VER_MASK 0x30000000 /* Version */ 759 #define PCIX_BRIDGE_2NDST_VER_SHIFT 28 760 #define PCIX_BRIDGE_ST_266 0x40000000 /* Same as PCIX_STATUS (nonb)*/ 761 #define PCIX_BRIDGE_ST_533 0x80000000 /* Same as PCIX_STATUS (nonb)*/ 762 763 #define PCIX_BRIDGE_PRI_STATUS 0x04 764 /* Bit 0 to 15 are the same as PCIX_STATUS */ 765 /* Bit 16 to 21 are the same as PCIX_BRIDGE_2ND_STATUS */ 766 /* Bit 30 and 31 are the same as PCIX_BRIDGE_2ND_STATUS */ 767 768 #define PCIX_BRIDGE_UP_STCR 0x08 /* Upstream Split Transaction Control */ 769 #define PCIX_BRIDGE_DOWN_STCR 0x0c /* Downstream Split Transaction Control */ 770 /* The layouts of above two registers are the same */ 771 #define PCIX_BRIDGE_STCAP 0x0000ffff /* Sp. Tr. Capacity */ 772 #define PCIX_BRIDGE_STCLIM 0xffff0000 /* Sp. Tr. Commitment Limit */ 773 #define PCIX_BRIDGE_STCLIM_SHIFT 16 774 775 /* 776 * Capability ID: 0x08 777 * HyperTransport 778 */ 779 780 #define PCI_HT_CMD 0x00 /* Capability List & Command Register */ 781 #define PCI_HT_CMD_MASK __BITS(31, 16) 782 #define PCI_HT_MSI_ENABLED __BIT(16) 783 #define PCI_HT_MSI_FIXED __BIT(17) 784 #define PCI_HT_CAP(cr) ((((cr) >> 27) < 0x08) ? \ 785 (((cr) >> 27) & 0x1c) : (((cr) >> 27) & 0x1f)) 786 #define PCI_HT_CAPMASK __BITS(31, 27) 787 #define PCI_HT_CAP_SLAVE __SHIFTIN(0b00000, PCI_HT_CAPMASK) /* 000xx */ 788 #define PCI_HT_CAP_HOST __SHIFTIN(0b00100, PCI_HT_CAPMASK) /* 001xx */ 789 #define PCI_HT_CAP_SWITCH __SHIFTIN(0b01000, PCI_HT_CAPMASK) 790 #define PCI_HT_CAP_INTERRUPT __SHIFTIN(0b10000, PCI_HT_CAPMASK) 791 #define PCI_HT_CAP_REVID __SHIFTIN(0b10001, PCI_HT_CAPMASK) 792 #define PCI_HT_CAP_UNITID_CLUMP __SHIFTIN(0b10010, PCI_HT_CAPMASK) 793 #define PCI_HT_CAP_EXTCNFSPACE __SHIFTIN(0b10011, PCI_HT_CAPMASK) 794 #define PCI_HT_CAP_ADDRMAP __SHIFTIN(0b10100, PCI_HT_CAPMASK) 795 #define PCI_HT_CAP_MSIMAP __SHIFTIN(0b10101, PCI_HT_CAPMASK) 796 #define PCI_HT_CAP_DIRECTROUTE __SHIFTIN(0b10110, PCI_HT_CAPMASK) 797 #define PCI_HT_CAP_VCSET __SHIFTIN(0b10111, PCI_HT_CAPMASK) 798 #define PCI_HT_CAP_RETRYMODE __SHIFTIN(0b11000, PCI_HT_CAPMASK) 799 #define PCI_HT_CAP_X86ENCODE __SHIFTIN(0b11001, PCI_HT_CAPMASK) 800 #define PCI_HT_CAP_GEN3 __SHIFTIN(0b11010, PCI_HT_CAPMASK) 801 #define PCI_HT_CAP_FLE __SHIFTIN(0b11011, PCI_HT_CAPMASK) 802 #define PCI_HT_CAP_PM __SHIFTIN(0b11100, PCI_HT_CAPMASK) 803 #define PCI_HT_CAP_HIGHNODECNT __SHIFTIN(0b11101, PCI_HT_CAPMASK) 804 805 #define PCI_HT_MSI_ADDR_LO 0x04 806 #define PCI_HT_MSI_ADDR_HI 0x08 807 #define PCI_HT_MSI_FIXED_ADDR 0xfee00000UL 808 809 /* 810 * Capability ID: 0x09 811 * Vendor Specific 812 */ 813 #define PCI_VENDORSPECIFIC_SHIFT 16 814 #define PCI_VENDORSPECIFIC 0x02 815 816 /* 817 * Capability ID: 0x0a 818 * Debug Port 819 */ 820 #define PCI_DEBUG_BASER 0x00 /* Debug Base Register */ 821 #define PCI_DEBUG_BASER_SHIFT 16 822 #define PCI_DEBUG_PORTOFF_SHIFT 16 823 #define PCI_DEBUG_PORTOFF_MASK 0x1fff0000 /* Debug port offset */ 824 #define PCI_DEBUG_BARNUM_SHIFT 29 825 #define PCI_DEBUG_BARNUM_MASK 0xe0000000 /* BAR number */ 826 827 /* 828 * Capability ID: 0x0b 829 * Compact PCI 830 */ 831 832 /* 833 * Capability ID: 0x0c 834 * Hotplug 835 */ 836 837 /* 838 * Capability ID: 0x0d 839 * Subsystem 840 */ 841 #define PCI_CAP_SUBSYS_ID 0x04 842 /* bit field layout is the same as PCI_SUBSYS_ID_REG's one */ 843 844 /* 845 * Capability ID: 0x0e 846 * AGP8 847 */ 848 849 /* 850 * Capability ID: 0x0f 851 * Secure 852 */ 853 854 /* 855 * Capability ID: 0x10 856 * PCI Express; access via capability pointer. 857 */ 858 #define PCIE_XCAP 0x00 /* Capability List & Capabilities Register */ 859 #define PCIE_XCAP_MASK __BITS(31, 16) 860 /* Capability Version */ 861 #define PCIE_XCAP_VER_MASK __SHIFTIN(__BITS(3, 0), PCIE_XCAP_MASK) 862 #define PCIE_XCAP_VER_1 __SHIFTIN(1, PCIE_XCAP_VER_MASK) 863 #define PCIE_XCAP_VER_2 __SHIFTIN(2, PCIE_XCAP_VER_MASK) 864 #define PCIE_XCAP_TYPE_MASK __SHIFTIN(__BITS(7, 4), PCIE_XCAP_MASK) 865 #define PCIE_XCAP_TYPE_PCIE_DEV __SHIFTIN(0x0, PCIE_XCAP_TYPE_MASK) 866 #define PCIE_XCAP_TYPE_PCI_DEV __SHIFTIN(0x1, PCIE_XCAP_TYPE_MASK) 867 #define PCIE_XCAP_TYPE_ROOT __SHIFTIN(0x4, PCIE_XCAP_TYPE_MASK) 868 #define PCIE_XCAP_TYPE_UP __SHIFTIN(0x5, PCIE_XCAP_TYPE_MASK) 869 #define PCIE_XCAP_TYPE_DOWN __SHIFTIN(0x6, PCIE_XCAP_TYPE_MASK) 870 #define PCIE_XCAP_TYPE_PCIE2PCI __SHIFTIN(0x7, PCIE_XCAP_TYPE_MASK) 871 #define PCIE_XCAP_TYPE_PCI2PCIE __SHIFTIN(0x8, PCIE_XCAP_TYPE_MASK) 872 #define PCIE_XCAP_TYPE_ROOT_INTEP __SHIFTIN(0x9, PCIE_XCAP_TYPE_MASK) 873 #define PCIE_XCAP_TYPE_ROOT_EVNTC __SHIFTIN(0xa, PCIE_XCAP_TYPE_MASK) 874 #define PCIE_XCAP_SI __SHIFTIN(__BIT(8), PCIE_XCAP_MASK) /* Slot Implemented */ 875 #define PCIE_XCAP_IRQ __SHIFTIN(__BITS(13, 9), PCIE_XCAP_MASK) 876 #define PCIE_DCAP 0x04 /* Device Capabilities Register */ 877 #define PCIE_DCAP_MAX_PAYLOAD __BITS(2, 0) /* Max Payload Size Supported */ 878 #define PCIE_DCAP_PHANTOM_FUNCS __BITS(4, 3) /* Phantom Functions Supported*/ 879 #define PCIE_DCAP_EXT_TAG_FIELD __BIT(5) /* Extended Tag Field Support */ 880 #define PCIE_DCAP_L0S_LATENCY __BITS(8, 6) /* Endpoint L0 Accptbl Latency*/ 881 #define PCIE_DCAP_L1_LATENCY __BITS(11, 9) /* Endpoint L1 Accptbl Latency*/ 882 #define PCIE_DCAP_ATTN_BUTTON __BIT(12) /* Attention Indicator Button */ 883 #define PCIE_DCAP_ATTN_IND __BIT(13) /* Attention Indicator Present*/ 884 #define PCIE_DCAP_PWR_IND __BIT(14) /* Power Indicator Present */ 885 #define PCIE_DCAP_ROLE_ERR_RPT __BIT(15) /* Role-Based Error Reporting */ 886 #define PCIE_DCAP_SLOT_PWR_LIM_VAL __BITS(25, 18) /* Cap. Slot PWR Limit Val */ 887 #define PCIE_DCAP_SLOT_PWR_LIM_SCALE __BITS(27, 26) /* Cap. SlotPWRLimit Scl */ 888 #define PCIE_DCAP_FLR __BIT(28) /* Function-Level Reset Cap. */ 889 #define PCIE_DCSR 0x08 /* Device Control & Status Register */ 890 #define PCIE_DCSR_ENA_COR_ERR __BIT(0) /* Correctable Error Report En*/ 891 #define PCIE_DCSR_ENA_NFER __BIT(1) /* Non-Fatal Error Report En. */ 892 #define PCIE_DCSR_ENA_FER __BIT(2) /* Fatal Error Reporting Enabl*/ 893 #define PCIE_DCSR_ENA_URR __BIT(3) /* Unsupported Request Rpt En */ 894 #define PCIE_DCSR_ENA_RELAX_ORD __BIT(4) /* Enable Relaxed Ordering */ 895 #define PCIE_DCSR_MAX_PAYLOAD __BITS(7, 5) /* Max Payload Size */ 896 #define PCIE_DCSR_EXT_TAG_FIELD __BIT(8) /* Extended Tag Field Enable */ 897 #define PCIE_DCSR_PHANTOM_FUNCS __BIT(9) /* Phantom Functions Enable */ 898 #define PCIE_DCSR_AUX_POWER_PM __BIT(10) /* Aux Power PM Enable */ 899 #define PCIE_DCSR_ENA_NO_SNOOP __BIT(11) /* Enable No Snoop */ 900 #define PCIE_DCSR_MAX_READ_REQ __BITS(14, 12) /* Max Read Request Size */ 901 #define PCIE_DCSR_BRDG_CFG_RETRY __BIT(15) /* Bridge Config Retry Enable */ 902 #define PCIE_DCSR_INITIATE_FLR __BIT(15) /* Initiate Function-Level Rst*/ 903 #define PCIE_DCSR_CED __BIT(0 + 16) /* Correctable Error Detected */ 904 #define PCIE_DCSR_NFED __BIT(1 + 16) /* Non-Fatal Error Detected */ 905 #define PCIE_DCSR_FED __BIT(2 + 16) /* Fatal Error Detected */ 906 #define PCIE_DCSR_URD __BIT(3 + 16) /* Unsupported Req. Detected */ 907 #define PCIE_DCSR_AUX_PWR __BIT(4 + 16) /* Aux Power Detected */ 908 #define PCIE_DCSR_TRANSACTION_PND __BIT(5 + 16) /* Transaction Pending */ 909 #define PCIE_LCAP 0x0c /* Link Capabilities Register */ 910 #define PCIE_LCAP_MAX_SPEED __BITS(3, 0) /* Max Link Speed */ 911 #define PCIE_LCAP_MAX_WIDTH __BITS(9, 4) /* Maximum Link Width */ 912 #define PCIE_LCAP_ASPM __BITS(11, 10) /* Active State Link PM Supp. */ 913 #define PCIE_LCAP_L0S_EXIT __BITS(14, 12) /* L0s Exit Latency */ 914 #define PCIE_LCAP_L1_EXIT __BITS(17, 15) /* L1 Exit Latency */ 915 #define PCIE_LCAP_CLOCK_PM __BIT(18) /* Clock Power Management */ 916 #define PCIE_LCAP_SURPRISE_DOWN __BIT(19) /* Surprise Down Err Rpt Cap. */ 917 #define PCIE_LCAP_DL_ACTIVE __BIT(20) /* Data Link Layer Link Active*/ 918 #define PCIE_LCAP_LINK_BW_NOTIFY __BIT(21) /* Link BW Notification Capabl*/ 919 #define PCIE_LCAP_ASPM_COMPLIANCE __BIT(22) /* ASPM Optionally Compliance */ 920 #define PCIE_LCAP_PORT __BITS(31, 24) /* Port Number */ 921 #define PCIE_LCSR 0x10 /* Link Control & Status Register */ 922 #define PCIE_LCSR_ASPM_L0S __BIT(0) /* Active State PM Control L0s*/ 923 #define PCIE_LCSR_ASPM_L1 __BIT(1) /* Active State PM Control L1 */ 924 #define PCIE_LCSR_RCB __BIT(3) /* Read Completion Boundry Ctl*/ 925 #define PCIE_LCSR_LINK_DIS __BIT(4) /* Link Disable */ 926 #define PCIE_LCSR_RETRAIN __BIT(5) /* Retrain Link */ 927 #define PCIE_LCSR_COMCLKCFG __BIT(6) /* Common Clock Configuration */ 928 #define PCIE_LCSR_EXTNDSYNC __BIT(7) /* Extended Synch */ 929 #define PCIE_LCSR_ENCLKPM __BIT(8) /* Enable Clock Power Managmt */ 930 #define PCIE_LCSR_HAWD __BIT(9) /* HW Autonomous Width Disable*/ 931 #define PCIE_LCSR_LBMIE __BIT(10) /* Link BW Management Intr En */ 932 #define PCIE_LCSR_LABIE __BIT(11) /* Link Autonomous BW Intr En */ 933 #define PCIE_LCSR_LINKSPEED __BITS(19, 16) /* Link Speed */ 934 #define PCIE_LCSR_NLW __BITS(25, 20) /* Negotiated Link Width */ 935 #define PCIE_LCSR_LINKTRAIN_ERR __BIT(10 + 16) /* Link Training Error */ 936 #define PCIE_LCSR_LINKTRAIN __BIT(11 + 16) /* Link Training */ 937 #define PCIE_LCSR_SLOTCLKCFG __BIT(12 + 16) /* Slot Clock Configuration */ 938 #define PCIE_LCSR_DLACTIVE __BIT(13 + 16) /* Data Link Layer Link Active*/ 939 #define PCIE_LCSR_LINK_BW_MGMT __BIT(14 + 16) /* Link BW Management Status */ 940 #define PCIE_LCSR_LINK_AUTO_BW __BIT(15 + 16) /* Link Autonomous BW Status */ 941 #define PCIE_SLCAP 0x14 /* Slot Capabilities Register */ 942 #define PCIE_SLCAP_ABP __BIT(0) /* Attention Button Present */ 943 #define PCIE_SLCAP_PCP __BIT(1) /* Power Controller Present */ 944 #define PCIE_SLCAP_MSP __BIT(2) /* MRL Sensor Present */ 945 #define PCIE_SLCAP_AIP __BIT(3) /* Attention Indicator Present*/ 946 #define PCIE_SLCAP_PIP __BIT(4) /* Power Indicator Present */ 947 #define PCIE_SLCAP_HPS __BIT(5) /* Hot-Plug Surprise */ 948 #define PCIE_SLCAP_HPC __BIT(6) /* Hot-Plug Capable */ 949 #define PCIE_SLCAP_SPLV __BITS(14, 7) /* Slot Power Limit Value */ 950 #define PCIE_SLCAP_SPLS __BITS(16, 15) /* Slot Power Limit Scale */ 951 #define PCIE_SLCAP_EIP __BIT(17) /* Electromechanical Interlock*/ 952 #define PCIE_SLCAP_NCCS __BIT(18) /* No Command Completed Supp. */ 953 #define PCIE_SLCAP_PSN __BITS(31, 19) /* Physical Slot Number */ 954 #define PCIE_SLCSR 0x18 /* Slot Control & Status Register */ 955 #define PCIE_SLCSR_ABE __BIT(0) /* Attention Button Pressed En*/ 956 #define PCIE_SLCSR_PFE __BIT(1) /* Power Button Pressed Enable*/ 957 #define PCIE_SLCSR_MSE __BIT(2) /* MRL Sensor Changed Enable */ 958 #define PCIE_SLCSR_PDE __BIT(3) /* Presence Detect Changed Ena*/ 959 #define PCIE_SLCSR_CCE __BIT(4) /* Command Completed Intr. En */ 960 #define PCIE_SLCSR_HPE __BIT(5) /* Hot Plug Interrupt Enable */ 961 #define PCIE_SLCSR_AIC __BITS(7, 6) /* Attention Indicator Control*/ 962 #define PCIE_SLCSR_PIC __BITS(9, 8) /* Power Indicator Control */ 963 #define PCIE_SLCSR_PCC __BIT(10) /* Power Controller Control */ 964 #define PCIE_SLCSR_EIC __BIT(11) /* Electromechanical Interlock*/ 965 #define PCIE_SLCSR_DLLSCE __BIT(12) /* DataLinkLayer State Changed*/ 966 #define PCIE_SLCSR_ABP __BIT(0 + 16) /* Attention Button Pressed */ 967 #define PCIE_SLCSR_PFD __BIT(1 + 16) /* Power Fault Detected */ 968 #define PCIE_SLCSR_MSC __BIT(2 + 16) /* MRL Sensor Changed */ 969 #define PCIE_SLCSR_PDC __BIT(3 + 16) /* Presence Detect Changed */ 970 #define PCIE_SLCSR_CC __BIT(4 + 16) /* Command Completed */ 971 #define PCIE_SLCSR_MS __BIT(5 + 16) /* MRL Sensor State */ 972 #define PCIE_SLCSR_PDS __BIT(6 + 16) /* Presence Detect State */ 973 #define PCIE_SLCSR_EIS __BIT(7 + 16) /* Electromechanical Interlock*/ 974 #define PCIE_SLCSR_LACS __BIT(8 + 16) /* Data Link Layer State Chg. */ 975 #define PCIE_RCR 0x1c /* Root Control & Capabilities Reg. */ 976 #define PCIE_RCR_SERR_CER __BIT(0) /* SERR on Correctable Err. En*/ 977 #define PCIE_RCR_SERR_NFER __BIT(1) /* SERR on Non-Fatal Error En */ 978 #define PCIE_RCR_SERR_FER __BIT(2) /* SERR on Fatal Error Enable */ 979 #define PCIE_RCR_PME_IE __BIT(3) /* PME Interrupt Enable */ 980 #define PCIE_RCR_CRS_SVE __BIT(4) /* CRS Software Visibility En */ 981 #define PCIE_RCR_CRS_SV __BIT(16) /* CRS Software Visibility */ 982 #define PCIE_RSR 0x20 /* Root Status Register */ 983 #define PCIE_RSR_PME_REQESTER __BITS(15, 0) /* PME Requester ID */ 984 #define PCIE_RSR_PME_STAT __BIT(16) /* PME Status */ 985 #define PCIE_RSR_PME_PEND __BIT(17) /* PME Pending */ 986 #define PCIE_DCAP2 0x24 /* Device Capabilities 2 Register */ 987 #define PCIE_DCAP2_COMPT_RANGE __BITS(3,0) /* Compl. Timeout Ranges Supp */ 988 #define PCIE_DCAP2_COMPT_DIS __BIT(4) /* Compl. Timeout Disable Supp*/ 989 #define PCIE_DCAP2_ARI_FWD __BIT(5) /* ARI Forward Supported */ 990 #define PCIE_DCAP2_ATOM_ROUT __BIT(6) /* AtomicOp Routing Supported */ 991 #define PCIE_DCAP2_32ATOM __BIT(7) /* 32bit AtomicOp Compl. Supp */ 992 #define PCIE_DCAP2_64ATOM __BIT(8) /* 64bit AtomicOp Compl. Supp */ 993 #define PCIE_DCAP2_128CAS __BIT(9) /* 128bit Cas Completer Supp. */ 994 #define PCIE_DCAP2_NO_ROPR_PASS __BIT(10) /* No RO-enabled PR-PR Passng */ 995 #define PCIE_DCAP2_LTR_MEC __BIT(11) /* LTR Mechanism Supported */ 996 #define PCIE_DCAP2_TPH_COMP __BITS(13, 12) /* TPH Completer Supported */ 997 #define PCIE_DCAP2_OBFF __BITS(19, 18) /* OBPF */ 998 #define PCIE_DCAP2_EXTFMT_FLD __BIT(20) /* Extended Fmt Field Support */ 999 #define PCIE_DCAP2_EETLP_PREF __BIT(21) /* End-End TLP Prefix Support */ 1000 #define PCIE_DCAP2_MAX_EETLP __BITS(23, 22) /* Max End-End TLP Prefix Sup */ 1001 #define PCIE_DCSR2 0x28 /* Device Control & Status 2 Register */ 1002 #define PCIE_DCSR2_COMPT_VAL __BITS(3, 0) /* Completion Timeout Value */ 1003 #define PCIE_DCSR2_COMPT_DIS __BIT(4) /* Completion Timeout Disable */ 1004 #define PCIE_DCSR2_ARI_FWD __BIT(5) /* ARI Forwarding Enable */ 1005 #define PCIE_DCSR2_ATOM_REQ __BIT(6) /* AtomicOp Requester Enable */ 1006 #define PCIE_DCSR2_ATOM_EBLK __BIT(7) /* AtomicOp Egress Blocking */ 1007 #define PCIE_DCSR2_IDO_REQ __BIT(8) /* IDO Request Enable */ 1008 #define PCIE_DCSR2_IDO_COMP __BIT(9) /* IDO Completion Enable */ 1009 #define PCIE_DCSR2_LTR_MEC __BIT(10) /* LTR Mechanism Enable */ 1010 #define PCIE_DCSR2_OBFF_EN __BITS(14, 13) /* OBPF Enable */ 1011 #define PCIE_DCSR2_EETLP __BIT(15) /* End-End TLP Prefix Blcking */ 1012 #define PCIE_LCAP2 0x2c /* Link Capabilities 2 Register */ 1013 #define PCIE_LCAP2_SUP_LNKSV __BITS(7, 1) /* Supported Link Speeds Vect */ 1014 #define PCIE_LCAP2_CROSSLNK __BIT(8) /* Crosslink Supported */ 1015 #define PCIE_LCSR2 0x30 /* Link Control & Status 2 Register */ 1016 #define PCIE_LCSR2_TGT_LSPEED __BITS(3, 0) /* Target Link Speed */ 1017 #define PCIE_LCSR2_ENT_COMPL __BIT(4) /* Enter Compliance */ 1018 #define PCIE_LCSR2_HW_AS_DIS __BIT(5) /* HW Autonomous Speed Disabl */ 1019 #define PCIE_LCSR2_SEL_DEEMP __BIT(6) /* Selectable De-emphasis */ 1020 #define PCIE_LCSR2_TX_MARGIN __BITS(9, 7) /* Transmit Margin */ 1021 #define PCIE_LCSR2_EN_MCOMP __BIT(10) /* Enter Modified Compliance */ 1022 #define PCIE_LCSR2_COMP_SOS __BIT(11) /* Compliance SOS */ 1023 #define PCIE_LCSR2_COMP_DEEMP __BITS(15, 12) /* Compliance Present/De-emph */ 1024 #define PCIE_LCSR2_DEEMP_LVL __BIT(0 + 16) /* Current De-emphasis Level */ 1025 #define PCIE_LCSR2_EQ_COMPL __BIT(1 + 16) /* Equalization Complete */ 1026 #define PCIE_LCSR2_EQP1_SUC __BIT(2 + 16) /* Equaliz Phase 1 Successful */ 1027 #define PCIE_LCSR2_EQP2_SUC __BIT(3 + 16) /* Equaliz Phase 2 Successful */ 1028 #define PCIE_LCSR2_EQP3_SUC __BIT(4 + 16) /* Equaliz Phase 3 Successful */ 1029 #define PCIE_LCSR2_LNKEQ_REQ __BIT(5 + 16) /* Link Equalization Request */ 1030 1031 #define PCIE_SLCAP2 0x34 /* Slot Capabilities 2 Register */ 1032 #define PCIE_SLCSR2 0x38 /* Slot Control & Status 2 Register */ 1033 1034 /* 1035 * Capability ID: 0x11 1036 * MSIX 1037 */ 1038 1039 #define PCI_MSIX_CTL 0x00 1040 #define PCI_MSIX_CTL_ENABLE 0x80000000 1041 #define PCI_MSIX_CTL_FUNCMASK 0x40000000 1042 #define PCI_MSIX_CTL_TBLSIZE_MASK 0x07ff0000 1043 #define PCI_MSIX_CTL_TBLSIZE_SHIFT 16 1044 #define PCI_MSIX_CTL_TBLSIZE(ofs) ((((ofs) & PCI_MSIX_CTL_TBLSIZE_MASK) \ 1045 >> PCI_MSIX_CTL_TBLSIZE_SHIFT) + 1) 1046 /* 1047 * 2nd DWORD is the Table Offset 1048 */ 1049 #define PCI_MSIX_TBLOFFSET 0x04 1050 #define PCI_MSIX_TBLOFFSET_MASK 0xfffffff8 1051 #define PCI_MSIX_TBLBIR_MASK 0x00000007 1052 /* 1053 * 3rd DWORD is the Pending Bitmap Array Offset 1054 */ 1055 #define PCI_MSIX_PBAOFFSET 0x08 1056 #define PCI_MSIX_PBAOFFSET_MASK 0xfffffff8 1057 #define PCI_MSIX_PBABIR_MASK 0x00000007 1058 1059 #define PCI_MSIX_TABLE_ENTRY_SIZE 16 1060 #define PCI_MSIX_TABLE_ENTRY_ADDR_LO 0x0 1061 #define PCI_MSIX_TABLE_ENTRY_ADDR_HI 0x4 1062 #define PCI_MSIX_TABLE_ENTRY_DATA 0x8 1063 #define PCI_MSIX_TABLE_ENTRY_VECTCTL 0xc 1064 struct pci_msix_table_entry { 1065 uint32_t pci_msix_addr_lo; 1066 uint32_t pci_msix_addr_hi; 1067 uint32_t pci_msix_value; 1068 uint32_t pci_msix_vector_control; 1069 }; 1070 #define PCI_MSIX_VECTCTL_HWMASK_MASK 0x00000001 1071 1072 /* 1073 * Capability ID: 0x12 1074 * SATA 1075 */ 1076 1077 /* 1078 * Capability ID: 0x13 1079 * Advanced Feature 1080 */ 1081 #define PCI_AFCAPR 0x00 /* Capabilities */ 1082 #define PCI_AFCAPR_MASK __BITS(31, 24) 1083 #define PCI_AF_TP_CAP __BIT(24) /* Transaction Pending */ 1084 #define PCI_AF_FLR_CAP __BIT(25) /* Function Level Reset */ 1085 #define PCI_AFCSR 0x04 /* Control & Status register */ 1086 #define PCI_AFCR_INITIATE_FLR __BIT(0) /* Initiate Function LVL RST */ 1087 #define PCI_AFSR_TP __BIT(8) /* Transaction Pending */ 1088 1089 1090 /* 1091 * Interrupt Configuration Register; contains interrupt pin and line. 1092 */ 1093 #define PCI_INTERRUPT_REG 0x3c 1094 1095 typedef u_int8_t pci_intr_latency_t; 1096 typedef u_int8_t pci_intr_grant_t; 1097 typedef u_int8_t pci_intr_pin_t; 1098 typedef u_int8_t pci_intr_line_t; 1099 1100 #define PCI_MAX_LAT_SHIFT 24 1101 #define PCI_MAX_LAT_MASK 0xff 1102 #define PCI_MAX_LAT(icr) \ 1103 (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK) 1104 1105 #define PCI_MIN_GNT_SHIFT 16 1106 #define PCI_MIN_GNT_MASK 0xff 1107 #define PCI_MIN_GNT(icr) \ 1108 (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK) 1109 1110 #define PCI_INTERRUPT_GRANT_SHIFT 24 1111 #define PCI_INTERRUPT_GRANT_MASK 0xff 1112 #define PCI_INTERRUPT_GRANT(icr) \ 1113 (((icr) >> PCI_INTERRUPT_GRANT_SHIFT) & PCI_INTERRUPT_GRANT_MASK) 1114 1115 #define PCI_INTERRUPT_LATENCY_SHIFT 16 1116 #define PCI_INTERRUPT_LATENCY_MASK 0xff 1117 #define PCI_INTERRUPT_LATENCY(icr) \ 1118 (((icr) >> PCI_INTERRUPT_LATENCY_SHIFT) & PCI_INTERRUPT_LATENCY_MASK) 1119 1120 #define PCI_INTERRUPT_PIN_SHIFT 8 1121 #define PCI_INTERRUPT_PIN_MASK 0xff 1122 #define PCI_INTERRUPT_PIN(icr) \ 1123 (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK) 1124 1125 #define PCI_INTERRUPT_LINE_SHIFT 0 1126 #define PCI_INTERRUPT_LINE_MASK 0xff 1127 #define PCI_INTERRUPT_LINE(icr) \ 1128 (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK) 1129 1130 #define PCI_INTERRUPT_CODE(lat,gnt,pin,line) \ 1131 ((((lat)&PCI_INTERRUPT_LATENCY_MASK)<<PCI_INTERRUPT_LATENCY_SHIFT)| \ 1132 (((gnt)&PCI_INTERRUPT_GRANT_MASK) <<PCI_INTERRUPT_GRANT_SHIFT) | \ 1133 (((pin)&PCI_INTERRUPT_PIN_MASK) <<PCI_INTERRUPT_PIN_SHIFT) | \ 1134 (((line)&PCI_INTERRUPT_LINE_MASK) <<PCI_INTERRUPT_LINE_SHIFT)) 1135 1136 #define PCI_INTERRUPT_PIN_NONE 0x00 1137 #define PCI_INTERRUPT_PIN_A 0x01 1138 #define PCI_INTERRUPT_PIN_B 0x02 1139 #define PCI_INTERRUPT_PIN_C 0x03 1140 #define PCI_INTERRUPT_PIN_D 0x04 1141 #define PCI_INTERRUPT_PIN_MAX 0x04 1142 1143 /* Header Type 1 (Bridge) configuration registers */ 1144 #define PCI_BRIDGE_BUS_REG 0x18 1145 #define PCI_BRIDGE_BUS_EACH_MASK 0xff 1146 #define PCI_BRIDGE_BUS_PRIMARY_SHIFT 0 1147 #define PCI_BRIDGE_BUS_SECONDARY_SHIFT 8 1148 #define PCI_BRIDGE_BUS_SUBORDINATE_SHIFT 16 1149 #define PCI_BRIDGE_BUS_SEC_LATTIMER_SHIFT 24 1150 #define PCI_BRIDGE_BUS_PRIMARY(reg) \ 1151 (((reg) >> PCI_BRIDGE_BUS_PRIMARY_SHIFT) & PCI_BRIDGE_BUS_EACH_MASK) 1152 #define PCI_BRIDGE_BUS_SECONDARY(reg) \ 1153 (((reg) >> PCI_BRIDGE_BUS_SECONDARY_SHIFT) & PCI_BRIDGE_BUS_EACH_MASK) 1154 #define PCI_BRIDGE_BUS_SUBORDINATE(reg) \ 1155 (((reg) >> PCI_BRIDGE_BUS_SUBORDINATE_SHIFT) &PCI_BRIDGE_BUS_EACH_MASK) 1156 #define PCI_BRIDGE_BUS_SEC_LATTIMER(reg) \ 1157 (((reg) >> PCI_BRIDGE_BUS_SEC_LATTIMER_SHIFT)&PCI_BRIDGE_BUS_EACH_MASK) 1158 1159 1160 #define PCI_BRIDGE_STATIO_REG 0x1C 1161 #define PCI_BRIDGE_STATIO_IOBASE_SHIFT 0 1162 #define PCI_BRIDGE_STATIO_IOLIMIT_SHIFT 8 1163 #define PCI_BRIDGE_STATIO_STATUS_SHIFT 16 1164 #define PCI_BRIDGE_STATIO_IOBASE_MASK 0xf0 1165 #define PCI_BRIDGE_STATIO_IOLIMIT_MASK 0xf0 1166 #define PCI_BRIDGE_STATIO_STATUS_MASK 0xffff 1167 #define PCI_BRIDGE_IO_32BITS(reg) (((reg) & 0xf) == 1) 1168 1169 #define PCI_BRIDGE_MEMORY_REG 0x20 1170 #define PCI_BRIDGE_MEMORY_BASE_SHIFT 4 1171 #define PCI_BRIDGE_MEMORY_LIMIT_SHIFT 20 1172 #define PCI_BRIDGE_MEMORY_BASE_MASK 0x0fff 1173 #define PCI_BRIDGE_MEMORY_LIMIT_MASK 0x0fff 1174 1175 #define PCI_BRIDGE_PREFETCHMEM_REG 0x24 1176 #define PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT 4 1177 #define PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT 20 1178 #define PCI_BRIDGE_PREFETCHMEM_BASE_MASK 0x0fff 1179 #define PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK 0x0fff 1180 #define PCI_BRIDGE_PREFETCHMEM_64BITS(reg) ((reg) & 0xf) 1181 1182 #define PCI_BRIDGE_PREFETCHBASE32_REG 0x28 1183 #define PCI_BRIDGE_PREFETCHLIMIT32_REG 0x2C 1184 1185 #define PCI_BRIDGE_IOHIGH_REG 0x30 1186 #define PCI_BRIDGE_IOHIGH_BASE_SHIFT 0 1187 #define PCI_BRIDGE_IOHIGH_LIMIT_SHIFT 16 1188 #define PCI_BRIDGE_IOHIGH_BASE_MASK 0xffff 1189 #define PCI_BRIDGE_IOHIGH_LIMIT_MASK 0xffff 1190 1191 #define PCI_BRIDGE_CONTROL_REG 0x3C 1192 #define PCI_BRIDGE_CONTROL_SHIFT 16 1193 #define PCI_BRIDGE_CONTROL_MASK 0xffff 1194 #define PCI_BRIDGE_CONTROL_PERE (1 << 0) 1195 #define PCI_BRIDGE_CONTROL_SERR (1 << 1) 1196 #define PCI_BRIDGE_CONTROL_ISA (1 << 2) 1197 #define PCI_BRIDGE_CONTROL_VGA (1 << 3) 1198 /* Reserved (1 << 4) */ 1199 #define PCI_BRIDGE_CONTROL_MABRT (1 << 5) 1200 #define PCI_BRIDGE_CONTROL_SECBR (1 << 6) 1201 #define PCI_BRIDGE_CONTROL_SECFASTB2B (1 << 7) 1202 #define PCI_BRIDGE_CONTROL_PRI_DISC_TIMER (1 << 8) 1203 #define PCI_BRIDGE_CONTROL_SEC_DISC_TIMER (1 << 9) 1204 #define PCI_BRIDGE_CONTROL_DISC_TIMER_STAT (1 << 10) 1205 #define PCI_BRIDGE_CONTROL_DISC_TIMER_SERR (1 << 11) 1206 /* Reserved (1 << 12) - (1 << 15) */ 1207 1208 /* 1209 * Vital Product Data resource tags. 1210 */ 1211 struct pci_vpd_smallres { 1212 uint8_t vpdres_byte0; /* length of data + tag */ 1213 /* Actual data. */ 1214 } __packed; 1215 1216 struct pci_vpd_largeres { 1217 uint8_t vpdres_byte0; 1218 uint8_t vpdres_len_lsb; /* length of data only */ 1219 uint8_t vpdres_len_msb; 1220 /* Actual data. */ 1221 } __packed; 1222 1223 #define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) 1224 1225 #define PCI_VPDRES_SMALL_LENGTH(x) ((x) & 0x7) 1226 #define PCI_VPDRES_SMALL_NAME(x) (((x) >> 3) & 0xf) 1227 1228 #define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) 1229 1230 #define PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID 0x3 /* small */ 1231 #define PCI_VPDRES_TYPE_VENDOR_DEFINED 0xe /* small */ 1232 #define PCI_VPDRES_TYPE_END_TAG 0xf /* small */ 1233 1234 #define PCI_VPDRES_TYPE_IDENTIFIER_STRING 0x02 /* large */ 1235 #define PCI_VPDRES_TYPE_VPD 0x10 /* large */ 1236 1237 struct pci_vpd { 1238 uint8_t vpd_key0; 1239 uint8_t vpd_key1; 1240 uint8_t vpd_len; /* length of data only */ 1241 /* Actual data. */ 1242 } __packed; 1243 1244 /* 1245 * Recommended VPD fields: 1246 * 1247 * PN Part number of assembly 1248 * FN FRU part number 1249 * EC EC level of assembly 1250 * MN Manufacture ID 1251 * SN Serial Number 1252 * 1253 * Conditionally recommended VPD fields: 1254 * 1255 * LI Load ID 1256 * RL ROM Level 1257 * RM Alterable ROM Level 1258 * NA Network Address 1259 * DD Device Driver Level 1260 * DG Diagnostic Level 1261 * LL Loadable Microcode Level 1262 * VI Vendor ID/Device ID 1263 * FU Function Number 1264 * SI Subsystem Vendor ID/Subsystem ID 1265 * 1266 * Additional VPD fields: 1267 * 1268 * Z0-ZZ User/Product Specific 1269 */ 1270 1271 /* 1272 * PCI Expansion Rom 1273 */ 1274 1275 struct pci_rom_header { 1276 uint16_t romh_magic; /* 0xAA55 little endian */ 1277 uint8_t romh_reserved[22]; 1278 uint16_t romh_data_ptr; /* pointer to pci_rom struct */ 1279 } __packed; 1280 1281 #define PCI_ROM_HEADER_MAGIC 0xAA55 /* little endian */ 1282 1283 struct pci_rom { 1284 uint32_t rom_signature; 1285 pci_vendor_id_t rom_vendor; 1286 pci_product_id_t rom_product; 1287 uint16_t rom_vpd_ptr; /* reserved in PCI 2.2 */ 1288 uint16_t rom_data_len; 1289 uint8_t rom_data_rev; 1290 pci_interface_t rom_interface; /* the class reg is 24-bits */ 1291 pci_subclass_t rom_subclass; /* in little endian */ 1292 pci_class_t rom_class; 1293 uint16_t rom_len; /* code length / 512 byte */ 1294 uint16_t rom_rev; /* code revision level */ 1295 uint8_t rom_code_type; /* type of code */ 1296 uint8_t rom_indicator; 1297 uint16_t rom_reserved; 1298 /* Actual data. */ 1299 } __packed; 1300 1301 #define PCI_ROM_SIGNATURE 0x52494350 /* "PCIR", endian reversed */ 1302 #define PCI_ROM_CODE_TYPE_X86 0 /* Intel x86 BIOS */ 1303 #define PCI_ROM_CODE_TYPE_OFW 1 /* Open Firmware */ 1304 #define PCI_ROM_CODE_TYPE_HPPA 2 /* HP PA/RISC */ 1305 #define PCI_ROM_CODE_TYPE_EFI 3 /* EFI Image */ 1306 1307 #define PCI_ROM_INDICATOR_LAST 0x80 1308 1309 /* 1310 * Threshold below which 32bit PCI DMA needs bouncing. 1311 */ 1312 #define PCI32_DMA_BOUNCE_THRESHOLD 0x100000000ULL 1313 1314 /* 1315 * PCI-X 2.0 Extended Capability List 1316 */ 1317 1318 #define PCI_EXTCAPLIST_BASE 0x100 1319 1320 #define PCI_EXTCAPLIST_CAP(ecr) ((ecr) & 0xffff) 1321 #define PCI_EXTCAPLIST_VERSION(ecr) (((ecr) >> 16) & 0xf) 1322 #define PCI_EXTCAPLIST_NEXT(ecr) (((ecr) >> 20) & 0xfff) 1323 1324 /* 1325 * Local constants 1326 */ 1327 #define PCI_INTRSTR_LEN 64 1328 1329 #endif /* _DEV_PCI_PCIREG_H_ */ 1330