1 /* $NetBSD: pcireg.h,v 1.137 2018/02/01 09:09:14 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1999, 2000 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _DEV_PCI_PCIREG_H_ 35 #define _DEV_PCI_PCIREG_H_ 36 37 /* 38 * Standardized PCI configuration information 39 */ 40 41 /* 42 * Size of each function's configuration space. 43 */ 44 45 #define PCI_CONF_SIZE 0x100 46 #define PCI_EXTCONF_SIZE 0x1000 47 48 /* 49 * Device identification register; contains a vendor ID and a device ID. 50 */ 51 #define PCI_ID_REG 0x00 52 53 typedef u_int16_t pci_vendor_id_t; 54 typedef u_int16_t pci_product_id_t; 55 56 #define PCI_VENDOR_SHIFT 0 57 #define PCI_VENDOR_MASK 0xffff 58 #define PCI_VENDOR(id) \ 59 (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK) 60 61 #define PCI_PRODUCT_SHIFT 16 62 #define PCI_PRODUCT_MASK 0xffff 63 #define PCI_PRODUCT(id) \ 64 (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) 65 66 #define PCI_ID_CODE(vid,pid) \ 67 ((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) | \ 68 (((pid) & PCI_PRODUCT_MASK) << PCI_PRODUCT_SHIFT)) \ 69 70 /* 71 * Command and status register. 72 */ 73 #define PCI_COMMAND_STATUS_REG 0x04 74 #define PCI_COMMAND_SHIFT 0 75 #define PCI_COMMAND_MASK 0xffff 76 #define PCI_STATUS_SHIFT 16 77 #define PCI_STATUS_MASK 0xffff 78 79 #define PCI_COMMAND_STATUS_CODE(cmd,stat) \ 80 ((((cmd) & PCI_COMMAND_MASK) << PCI_COMMAND_SHIFT) | \ 81 (((stat) & PCI_STATUS_MASK) << PCI_STATUS_SHIFT)) \ 82 83 #define PCI_COMMAND_IO_ENABLE 0x00000001 84 #define PCI_COMMAND_MEM_ENABLE 0x00000002 85 #define PCI_COMMAND_MASTER_ENABLE 0x00000004 86 #define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 87 #define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 88 #define PCI_COMMAND_PALETTE_ENABLE 0x00000020 89 #define PCI_COMMAND_PARITY_ENABLE 0x00000040 90 #define PCI_COMMAND_STEPPING_ENABLE 0x00000080 91 #define PCI_COMMAND_SERR_ENABLE 0x00000100 92 #define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 93 #define PCI_COMMAND_INTERRUPT_DISABLE 0x00000400 94 95 #define PCI_STATUS_IMMD_READNESS __BIT(0+16) 96 #define PCI_STATUS_INT_STATUS 0x00080000 97 #define PCI_STATUS_CAPLIST_SUPPORT 0x00100000 98 #define PCI_STATUS_66MHZ_SUPPORT 0x00200000 99 #define PCI_STATUS_UDF_SUPPORT 0x00400000 100 #define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000 101 #define PCI_STATUS_PARITY_ERROR 0x01000000 102 #define PCI_STATUS_DEVSEL_FAST 0x00000000 103 #define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 104 #define PCI_STATUS_DEVSEL_SLOW 0x04000000 105 #define PCI_STATUS_DEVSEL_MASK 0x06000000 106 #define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 107 #define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 108 #define PCI_STATUS_MASTER_ABORT 0x20000000 109 #define PCI_STATUS_SPECIAL_ERROR 0x40000000 110 #define PCI_STATUS_PARITY_DETECT 0x80000000 111 112 /* 113 * PCI Class and Revision Register; defines type and revision of device. 114 */ 115 #define PCI_CLASS_REG 0x08 116 117 typedef u_int8_t pci_class_t; 118 typedef u_int8_t pci_subclass_t; 119 typedef u_int8_t pci_interface_t; 120 typedef u_int8_t pci_revision_t; 121 122 #define PCI_CLASS_SHIFT 24 123 #define PCI_CLASS_MASK 0xff 124 #define PCI_CLASS(cr) \ 125 (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) 126 127 #define PCI_SUBCLASS_SHIFT 16 128 #define PCI_SUBCLASS_MASK 0xff 129 #define PCI_SUBCLASS(cr) \ 130 (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) 131 132 #define PCI_INTERFACE_SHIFT 8 133 #define PCI_INTERFACE_MASK 0xff 134 #define PCI_INTERFACE(cr) \ 135 (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) 136 137 #define PCI_REVISION_SHIFT 0 138 #define PCI_REVISION_MASK 0xff 139 #define PCI_REVISION(cr) \ 140 (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) 141 142 #define PCI_CLASS_CODE(mainclass, subclass, interface) \ 143 ((((mainclass) & PCI_CLASS_MASK) << PCI_CLASS_SHIFT) | \ 144 (((subclass) & PCI_SUBCLASS_MASK) << PCI_SUBCLASS_SHIFT) | \ 145 (((interface) & PCI_INTERFACE_MASK) << PCI_INTERFACE_SHIFT)) 146 147 /* base classes */ 148 #define PCI_CLASS_PREHISTORIC 0x00 149 #define PCI_CLASS_MASS_STORAGE 0x01 150 #define PCI_CLASS_NETWORK 0x02 151 #define PCI_CLASS_DISPLAY 0x03 152 #define PCI_CLASS_MULTIMEDIA 0x04 153 #define PCI_CLASS_MEMORY 0x05 154 #define PCI_CLASS_BRIDGE 0x06 155 #define PCI_CLASS_COMMUNICATIONS 0x07 156 #define PCI_CLASS_SYSTEM 0x08 157 #define PCI_CLASS_INPUT 0x09 158 #define PCI_CLASS_DOCK 0x0a 159 #define PCI_CLASS_PROCESSOR 0x0b 160 #define PCI_CLASS_SERIALBUS 0x0c 161 #define PCI_CLASS_WIRELESS 0x0d 162 #define PCI_CLASS_I2O 0x0e 163 #define PCI_CLASS_SATCOM 0x0f 164 #define PCI_CLASS_CRYPTO 0x10 165 #define PCI_CLASS_DASP 0x11 166 #define PCI_CLASS_ACCEL 0x12 167 #define PCI_CLASS_INSTRUMENT 0x13 168 #define PCI_CLASS_UNDEFINED 0xff 169 170 /* 0x00 prehistoric subclasses */ 171 #define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 172 #define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 173 174 /* 0x01 mass storage subclasses */ 175 #define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 176 #define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 177 #define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 178 #define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 179 #define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04 180 #define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05 181 #define PCI_INTERFACE_ATA_SINGLEDMA 0x20 182 #define PCI_INTERFACE_ATA_CHAINEDDMA 0x30 183 #define PCI_SUBCLASS_MASS_STORAGE_SATA 0x06 184 #define PCI_INTERFACE_SATA_VND 0x00 185 #define PCI_INTERFACE_SATA_AHCI10 0x01 186 #define PCI_INTERFACE_SATA_SSBI 0x02 187 #define PCI_SUBCLASS_MASS_STORAGE_SAS 0x07 188 #define PCI_SUBCLASS_MASS_STORAGE_NVM 0x08 189 #define PCI_INTERFACE_NVM_VND 0x00 190 #define PCI_INTERFACE_NVM_NVMHCI10 0x01 191 #define PCI_INTERFACE_NVM_NVME 0x02 192 #define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 193 194 /* 0x02 network subclasses */ 195 #define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 196 #define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 197 #define PCI_SUBCLASS_NETWORK_FDDI 0x02 198 #define PCI_SUBCLASS_NETWORK_ATM 0x03 199 #define PCI_SUBCLASS_NETWORK_ISDN 0x04 200 #define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05 201 #define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06 202 #define PCI_SUBCLASS_NETWORK_INFINIBAND 0x07 203 #define PCI_SUBCLASS_NETWORK_MISC 0x80 204 205 /* 0x03 display subclasses */ 206 #define PCI_SUBCLASS_DISPLAY_VGA 0x00 207 #define PCI_INTERFACE_VGA_VGA 0x00 208 #define PCI_INTERFACE_VGA_8514 0x01 209 #define PCI_SUBCLASS_DISPLAY_XGA 0x01 210 #define PCI_SUBCLASS_DISPLAY_3D 0x02 211 #define PCI_SUBCLASS_DISPLAY_MISC 0x80 212 213 /* 0x04 multimedia subclasses */ 214 #define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 215 #define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 216 #define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02 217 #define PCI_SUBCLASS_MULTIMEDIA_HDAUDIO 0x03 218 #define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 219 220 /* 0x05 memory subclasses */ 221 #define PCI_SUBCLASS_MEMORY_RAM 0x00 222 #define PCI_SUBCLASS_MEMORY_FLASH 0x01 223 #define PCI_SUBCLASS_MEMORY_MISC 0x80 224 225 /* 0x06 bridge subclasses */ 226 #define PCI_SUBCLASS_BRIDGE_HOST 0x00 227 #define PCI_SUBCLASS_BRIDGE_ISA 0x01 228 #define PCI_SUBCLASS_BRIDGE_EISA 0x02 229 #define PCI_SUBCLASS_BRIDGE_MC 0x03 /* XXX _MCA */ 230 #define PCI_SUBCLASS_BRIDGE_PCI 0x04 231 #define PCI_INTERFACE_BRIDGE_PCI_PCI 0x00 232 #define PCI_INTERFACE_BRIDGE_PCI_SUBDEC 0x01 233 #define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 234 #define PCI_SUBCLASS_BRIDGE_NUBUS 0x06 235 #define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 236 #define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08 237 /* bit0 == 0 ? "transparent mode" : "endpoint mode" */ 238 #define PCI_SUBCLASS_BRIDGE_STPCI 0x09 239 #define PCI_INTERFACE_STPCI_PRIMARY 0x40 240 #define PCI_INTERFACE_STPCI_SECONDARY 0x80 241 #define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a 242 #define PCI_SUBCLASS_BRIDGE_ADVSW 0x0b 243 #define PCI_INTERFACE_ADVSW_CUSTOM 0x00 244 #define PCI_INTERFACE_ADVSW_ASISIG 0x01 245 #define PCI_SUBCLASS_BRIDGE_MISC 0x80 246 247 /* 0x07 communications subclasses */ 248 #define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 249 #define PCI_INTERFACE_SERIAL_XT 0x00 250 #define PCI_INTERFACE_SERIAL_16450 0x01 251 #define PCI_INTERFACE_SERIAL_16550 0x02 252 #define PCI_INTERFACE_SERIAL_16650 0x03 253 #define PCI_INTERFACE_SERIAL_16750 0x04 254 #define PCI_INTERFACE_SERIAL_16850 0x05 255 #define PCI_INTERFACE_SERIAL_16950 0x06 256 #define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 257 #define PCI_INTERFACE_PARALLEL 0x00 258 #define PCI_INTERFACE_PARALLEL_BIDIRECTIONAL 0x01 259 #define PCI_INTERFACE_PARALLEL_ECP1X 0x02 260 #define PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL 0x03 261 #define PCI_INTERFACE_PARALLEL_IEEE1284_TGT 0xfe 262 #define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02 263 #define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03 264 #define PCI_INTERFACE_MODEM 0x00 265 #define PCI_INTERFACE_MODEM_HAYES16450 0x01 266 #define PCI_INTERFACE_MODEM_HAYES16550 0x02 267 #define PCI_INTERFACE_MODEM_HAYES16650 0x03 268 #define PCI_INTERFACE_MODEM_HAYES16750 0x04 269 #define PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04 270 #define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05 271 #define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 272 273 /* 0x08 system subclasses */ 274 #define PCI_SUBCLASS_SYSTEM_PIC 0x00 275 #define PCI_INTERFACE_PIC_8259 0x00 276 #define PCI_INTERFACE_PIC_ISA 0x01 277 #define PCI_INTERFACE_PIC_EISA 0x02 278 #define PCI_INTERFACE_PIC_IOAPIC 0x10 279 #define PCI_INTERFACE_PIC_IOXAPIC 0x20 280 #define PCI_SUBCLASS_SYSTEM_DMA 0x01 281 #define PCI_INTERFACE_DMA_8237 0x00 282 #define PCI_INTERFACE_DMA_ISA 0x01 283 #define PCI_INTERFACE_DMA_EISA 0x02 284 #define PCI_SUBCLASS_SYSTEM_TIMER 0x02 285 #define PCI_INTERFACE_TIMER_8254 0x00 286 #define PCI_INTERFACE_TIMER_ISA 0x01 287 #define PCI_INTERFACE_TIMER_EISA 0x02 288 #define PCI_INTERFACE_TIMER_HPET 0x03 289 #define PCI_SUBCLASS_SYSTEM_RTC 0x03 290 #define PCI_INTERFACE_RTC_GENERIC 0x00 291 #define PCI_INTERFACE_RTC_ISA 0x01 292 #define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04 293 #define PCI_SUBCLASS_SYSTEM_SDHC 0x05 294 #define PCI_SUBCLASS_SYSTEM_IOMMU 0x06 /* or RCEC in old spec */ 295 #define PCI_SUBCLASS_SYSTEM_RCEC 0x07 296 #define PCI_SUBCLASS_SYSTEM_MISC 0x80 297 298 /* 0x09 input subclasses */ 299 #define PCI_SUBCLASS_INPUT_KEYBOARD 0x00 300 #define PCI_SUBCLASS_INPUT_DIGITIZER 0x01 301 #define PCI_SUBCLASS_INPUT_MOUSE 0x02 302 #define PCI_SUBCLASS_INPUT_SCANNER 0x03 303 #define PCI_SUBCLASS_INPUT_GAMEPORT 0x04 304 #define PCI_INTERFACE_GAMEPORT_GENERIC 0x00 305 #define PCI_INTERFACE_GAMEPORT_LEGACY 0x10 306 #define PCI_SUBCLASS_INPUT_MISC 0x80 307 308 /* 0x0a dock subclasses */ 309 #define PCI_SUBCLASS_DOCK_GENERIC 0x00 310 #define PCI_SUBCLASS_DOCK_MISC 0x80 311 312 /* 0x0b processor subclasses */ 313 #define PCI_SUBCLASS_PROCESSOR_386 0x00 314 #define PCI_SUBCLASS_PROCESSOR_486 0x01 315 #define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02 316 #define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10 317 #define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20 318 #define PCI_SUBCLASS_PROCESSOR_MIPS 0x30 319 #define PCI_SUBCLASS_PROCESSOR_COPROC 0x40 320 #define PCI_SUBCLASS_PROCESSOR_MISC 0x80 321 322 /* 0x0c serial bus subclasses */ 323 #define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00 324 #define PCI_INTERFACE_IEEE1394_FIREWIRE 0x00 325 #define PCI_INTERFACE_IEEE1394_OPENHCI 0x10 326 #define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01 327 #define PCI_SUBCLASS_SERIALBUS_SSA 0x02 328 #define PCI_SUBCLASS_SERIALBUS_USB 0x03 329 #define PCI_INTERFACE_USB_UHCI 0x00 330 #define PCI_INTERFACE_USB_OHCI 0x10 331 #define PCI_INTERFACE_USB_EHCI 0x20 332 #define PCI_INTERFACE_USB_XHCI 0x30 333 #define PCI_INTERFACE_USB_OTHERHC 0x80 334 #define PCI_INTERFACE_USB_DEVICE 0xfe 335 #define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 /* XXX _FIBRECHANNEL */ 336 #define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05 337 #define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06 /* Deprecated */ 338 #define PCI_SUBCLASS_SERIALBUS_IPMI 0x07 339 #define PCI_INTERFACE_IPMI_SMIC 0x00 340 #define PCI_INTERFACE_IPMI_KBD 0x01 341 #define PCI_INTERFACE_IPMI_BLOCKXFER 0x02 342 #define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08 343 #define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09 344 #define PCI_SUBCLASS_SERIALBUS_MISC 0x80 345 346 /* 0x0d wireless subclasses */ 347 #define PCI_SUBCLASS_WIRELESS_IRDA 0x00 348 #define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01 349 #define PCI_INTERFACE_CONSUMERIR 0x00 350 #define PCI_INTERFACE_UWB 0x10 351 #define PCI_SUBCLASS_WIRELESS_RF 0x10 352 #define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11 353 #define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12 354 #define PCI_SUBCLASS_WIRELESS_802_11A 0x20 355 #define PCI_SUBCLASS_WIRELESS_802_11B 0x21 356 #define PCI_SUBCLASS_WIRELESS_MISC 0x80 357 358 /* 0x0e I2O (Intelligent I/O) subclasses */ 359 #define PCI_SUBCLASS_I2O_STANDARD 0x00 360 #define PCI_INTERFACE_I2O_FIFOAT40 0x00 361 /* others for I2O spec */ 362 #define PCI_SUBCLASS_I2O_MISC 0x80 363 364 /* 0x0f satellite communication subclasses */ 365 /* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */ 366 #define PCI_SUBCLASS_SATCOM_TV 0x01 367 #define PCI_SUBCLASS_SATCOM_AUDIO 0x02 368 #define PCI_SUBCLASS_SATCOM_VOICE 0x03 369 #define PCI_SUBCLASS_SATCOM_DATA 0x04 370 #define PCI_SUBCLASS_SATCOM_MISC 0x80 371 372 /* 0x10 encryption/decryption subclasses */ 373 #define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00 374 #define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10 375 #define PCI_SUBCLASS_CRYPTO_MISC 0x80 376 377 /* 0x11 data acquisition and signal processing subclasses */ 378 #define PCI_SUBCLASS_DASP_DPIO 0x00 379 #define PCI_SUBCLASS_DASP_TIMEFREQ 0x01 /* performance counters */ 380 #define PCI_SUBCLASS_DASP_SYNC 0x10 381 #define PCI_SUBCLASS_DASP_MGMT 0x20 382 #define PCI_SUBCLASS_DASP_MISC 0x80 383 384 /* 385 * PCI BIST/Header Type/Latency Timer/Cache Line Size Register. 386 */ 387 #define PCI_BHLC_REG 0x0c 388 389 #define PCI_BIST_SHIFT 24 390 #define PCI_BIST_MASK 0xff 391 #define PCI_BIST(bhlcr) \ 392 (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK) 393 394 #define PCI_HDRTYPE_SHIFT 16 395 #define PCI_HDRTYPE_MASK 0xff 396 #define PCI_HDRTYPE(bhlcr) \ 397 (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK) 398 399 #define PCI_HDRTYPE_TYPE(bhlcr) \ 400 (PCI_HDRTYPE(bhlcr) & 0x7f) 401 #define PCI_HDRTYPE_MULTIFN(bhlcr) \ 402 ((PCI_HDRTYPE(bhlcr) & 0x80) != 0) 403 404 #define PCI_LATTIMER_SHIFT 8 405 #define PCI_LATTIMER_MASK 0xff 406 #define PCI_LATTIMER(bhlcr) \ 407 (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK) 408 409 #define PCI_CACHELINE_SHIFT 0 410 #define PCI_CACHELINE_MASK 0xff 411 #define PCI_CACHELINE(bhlcr) \ 412 (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK) 413 414 #define PCI_BHLC_CODE(bist,type,multi,latency,cacheline) \ 415 ((((bist) & PCI_BIST_MASK) << PCI_BIST_SHIFT) | \ 416 (((type) & PCI_HDRTYPE_MASK) << PCI_HDRTYPE_SHIFT) | \ 417 (((multi)?0x80:0) << PCI_HDRTYPE_SHIFT) | \ 418 (((latency) & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT) | \ 419 (((cacheline) & PCI_CACHELINE_MASK) << PCI_CACHELINE_SHIFT)) 420 421 /* 422 * PCI header type 423 */ 424 #define PCI_HDRTYPE_DEVICE 0 /* PCI/PCIX/Cardbus */ 425 #define PCI_HDRTYPE_PPB 1 /* PCI/PCIX/Cardbus */ 426 #define PCI_HDRTYPE_PCB 2 /* PCI/PCIX/Cardbus */ 427 #define PCI_HDRTYPE_EP 0 /* PCI Express */ 428 #define PCI_HDRTYPE_RC 1 /* PCI Express */ 429 430 431 /* 432 * Mapping registers 433 */ 434 #define PCI_MAPREG_START 0x10 435 #define PCI_MAPREG_END 0x28 436 #define PCI_MAPREG_ROM 0x30 437 #define PCI_MAPREG_PPB_END 0x18 438 #define PCI_MAPREG_PCB_END 0x14 439 440 #define PCI_BAR0 0x10 441 #define PCI_BAR1 0x14 442 #define PCI_BAR2 0x18 443 #define PCI_BAR3 0x1C 444 #define PCI_BAR4 0x20 445 #define PCI_BAR5 0x24 446 447 #define PCI_BAR(__n) (PCI_MAPREG_START + 4 * (__n)) 448 449 #define PCI_MAPREG_TYPE(mr) \ 450 ((mr) & PCI_MAPREG_TYPE_MASK) 451 #define PCI_MAPREG_TYPE_MASK 0x00000001 452 453 #define PCI_MAPREG_TYPE_MEM 0x00000000 454 #define PCI_MAPREG_TYPE_ROM 0x00000000 455 #define PCI_MAPREG_TYPE_IO 0x00000001 456 #define PCI_MAPREG_ROM_ENABLE 0x00000001 457 458 #define PCI_MAPREG_MEM_TYPE(mr) \ 459 ((mr) & PCI_MAPREG_MEM_TYPE_MASK) 460 #define PCI_MAPREG_MEM_TYPE_MASK 0x00000006 461 462 #define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000 463 #define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002 464 #define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 465 466 #define PCI_MAPREG_MEM_PREFETCHABLE(mr) \ 467 (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0) 468 #define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008 469 470 #define PCI_MAPREG_MEM_ADDR(mr) \ 471 ((mr) & PCI_MAPREG_MEM_ADDR_MASK) 472 #define PCI_MAPREG_MEM_SIZE(mr) \ 473 (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr)) 474 #define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 475 476 #define PCI_MAPREG_MEM64_ADDR(mr) \ 477 ((mr) & PCI_MAPREG_MEM64_ADDR_MASK) 478 #define PCI_MAPREG_MEM64_SIZE(mr) \ 479 (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr)) 480 #define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL 481 482 #define PCI_MAPREG_IO_ADDR(mr) \ 483 ((mr) & PCI_MAPREG_IO_ADDR_MASK) 484 #define PCI_MAPREG_IO_SIZE(mr) \ 485 (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) 486 #define PCI_MAPREG_IO_ADDR_MASK 0xfffffffc 487 488 #define PCI_MAPREG_ROM_ADDR(mr) \ 489 ((mr) & PCI_MAPREG_ROM_ADDR_MASK) 490 #define PCI_MAPREG_ROM_VALID_STAT __BITS(3, 1) /* Validation Status */ 491 #define PCI_MAPREG_ROM_VSTAT_NOTSUPP 0x0 /* Validation not supported */ 492 #define PCI_MAPREG_ROM_VSTAT_INPROG 0x1 /* Validation in Progress */ 493 #define PCI_MAPREG_ROM_VSTAT_VPASS 0x2 /* Valid contnt, trust test nperf*/ 494 #define PCI_MAPREG_ROM_VSTAT_VPASSTRUST 0x3 /* Valid and trusted contents */ 495 #define PCI_MAPREG_ROM_VSTAT_VFAIL 0x4 /* Invaild contents */ 496 #define PCI_MAPREG_ROM_VSTAT_VFAILUNTRUST 0x5 /* Vaild but untrusted contents*/ 497 #define PCI_MAPREG_ROM_VSTAT_WPASS 0x6 /* VPASS + warning */ 498 #define PCI_MAPREG_ROM_VSTAT_WPASSTRUST 0x7 /* VPASSTRUST + warning */ 499 #define PCI_MAPREG_ROM_VALID_DETAIL __BITS(7, 4) /* Validation Details */ 500 #define PCI_MAPREG_ROM_ADDR_MASK __BITS(31, 11) 501 502 #define PCI_MAPREG_SIZE_TO_MASK(size) \ 503 (-(size)) 504 505 #define PCI_MAPREG_NUM(offset) \ 506 (((unsigned)(offset)-PCI_MAPREG_START)/4) 507 508 509 /* 510 * Cardbus CIS pointer (PCI rev. 2.1) 511 */ 512 #define PCI_CARDBUS_CIS_REG 0x28 513 514 /* 515 * Subsystem identification register; contains a vendor ID and a device ID. 516 * Types/macros for PCI_ID_REG apply. 517 * (PCI rev. 2.1) 518 */ 519 #define PCI_SUBSYS_ID_REG 0x2c 520 521 #define PCI_SUBSYS_VENDOR_MASK __BITS(15, 0) 522 #define PCI_SUBSYS_ID_MASK __BITS(31, 16) 523 524 #define PCI_SUBSYS_VENDOR(__subsys_id) \ 525 __SHIFTOUT(__subsys_id, PCI_SUBSYS_VENDOR_MASK) 526 527 #define PCI_SUBSYS_ID(__subsys_id) \ 528 __SHIFTOUT(__subsys_id, PCI_SUBSYS_ID_MASK) 529 530 /* 531 * Capabilities link list (PCI rev. 2.2) 532 */ 533 #define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */ 534 #define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */ 535 #define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff) 536 #define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff) 537 #define PCI_CAPLIST_CAP(cr) ((cr) & 0xff) 538 539 #define PCI_CAP_RESERVED0 0x00 540 #define PCI_CAP_PWRMGMT 0x01 541 #define PCI_CAP_AGP 0x02 542 #define PCI_CAP_VPD 0x03 543 #define PCI_CAP_SLOTID 0x04 544 #define PCI_CAP_MSI 0x05 545 #define PCI_CAP_CPCI_HOTSWAP 0x06 546 #define PCI_CAP_PCIX 0x07 547 #define PCI_CAP_LDT 0x08 /* HyperTransport */ 548 #define PCI_CAP_VENDSPEC 0x09 549 #define PCI_CAP_DEBUGPORT 0x0a 550 #define PCI_CAP_CPCI_RSRCCTL 0x0b 551 #define PCI_CAP_HOTPLUG 0x0c /* Standard Hot-Plug Controller(SHPC)*/ 552 #define PCI_CAP_SUBVENDOR 0x0d 553 #define PCI_CAP_AGP8 0x0e 554 #define PCI_CAP_SECURE 0x0f 555 #define PCI_CAP_PCIEXPRESS 0x10 556 #define PCI_CAP_MSIX 0x11 557 #define PCI_CAP_SATA 0x12 558 #define PCI_CAP_PCIAF 0x13 559 #define PCI_CAP_EA 0x14 /* Enhanced Allocation (EA) */ 560 #define PCI_CAP_FPB 0x15 /* Flattening Portal Bridge (FPB) */ 561 562 /* 563 * Capability ID: 0x01 564 * Power Management Capability; access via capability pointer. 565 */ 566 567 /* Power Management Capability Register */ 568 #define PCI_PMCR 0x02 569 #define PCI_PMCR_SHIFT 16 570 #define PCI_PMCR_VERSION_MASK 0x0007 571 #define PCI_PMCR_VERSION_10 0x0001 572 #define PCI_PMCR_VERSION_11 0x0002 573 #define PCI_PMCR_VERSION_12 0x0003 574 #define PCI_PMCR_PME_CLOCK 0x0008 575 #define PCI_PMCR_DSI 0x0020 576 #define PCI_PMCR_AUXCUR_MASK 0x01c0 577 #define PCI_PMCR_AUXCUR_0 0x0000 578 #define PCI_PMCR_AUXCUR_55 0x0040 579 #define PCI_PMCR_AUXCUR_100 0x0080 580 #define PCI_PMCR_AUXCUR_160 0x00c0 581 #define PCI_PMCR_AUXCUR_220 0x0100 582 #define PCI_PMCR_AUXCUR_270 0x0140 583 #define PCI_PMCR_AUXCUR_320 0x0180 584 #define PCI_PMCR_AUXCUR_375 0x01c0 585 #define PCI_PMCR_D1SUPP 0x0200 586 #define PCI_PMCR_D2SUPP 0x0400 587 #define PCI_PMCR_PME_D0 0x0800 588 #define PCI_PMCR_PME_D1 0x1000 589 #define PCI_PMCR_PME_D2 0x2000 590 #define PCI_PMCR_PME_D3HOT 0x4000 591 #define PCI_PMCR_PME_D3COLD 0x8000 592 /* 593 * Power Management Control Status Register, Bridge Support Extensions Register 594 * and Data Register. 595 */ 596 #define PCI_PMCSR 0x04 597 #define PCI_PMCSR_STATE_MASK 0x00000003 598 #define PCI_PMCSR_STATE_D0 0x00000000 599 #define PCI_PMCSR_STATE_D1 0x00000001 600 #define PCI_PMCSR_STATE_D2 0x00000002 601 #define PCI_PMCSR_STATE_D3 0x00000003 602 #define PCI_PMCSR_NO_SOFTRST 0x00000008 603 #define PCI_PMCSR_PME_EN 0x00000100 604 #define PCI_PMCSR_DATASEL_MASK 0x00001e00 605 #define PCI_PMCSR_DATASCL_MASK 0x00006000 606 #define PCI_PMCSR_PME_STS 0x00008000 607 #define PCI_PMCSR_B2B3_SUPPORT 0x00400000 608 #define PCI_PMCSR_BPCC_EN 0x00800000 609 #define PCI_PMCSR_DATA 0xff000000 610 611 612 /* 613 * Capability ID: 0x02 614 * AGP 615 */ 616 #define PCI_CAP_AGP_MAJOR(cr) (((cr) >> 20) & 0xf) 617 #define PCI_CAP_AGP_MINOR(cr) (((cr) >> 16) & 0xf) 618 #define PCI_AGP_STATUS 0x04 619 #define PCI_AGP_COMMAND 0x08 620 /* Definitions for STATUS and COMMAND register bits */ 621 #define AGP_MODE_RQ __BITS(31, 24) 622 #define AGP_MODE_ARQSZ __BITS(15, 13) 623 #define AGP_MODE_CAL __BITS(12, 10) 624 #define AGP_MODE_SBA __BIT(9) 625 #define AGP_MODE_AGP __BIT(8) 626 #define AGP_MODE_HTRANS __BIT(6) 627 #define AGP_MODE_4G __BIT(5) 628 #define AGP_MODE_FW __BIT(4) 629 #define AGP_MODE_MODE_3 __BIT(3) 630 #define AGP_MODE_RATE __BITS(2, 0) 631 #define AGP_MODE_V2_RATE_1x 0x1 632 #define AGP_MODE_V2_RATE_2x 0x2 633 #define AGP_MODE_V2_RATE_4x 0x4 634 #define AGP_MODE_V3_RATE_4x 0x1 635 #define AGP_MODE_V3_RATE_8x 0x2 636 #define AGP_MODE_V3_RATE_RSVD 0x4 637 638 639 /* 640 * Capability ID: 0x03 641 * Vital Product Data; access via capability pointer (PCI rev 2.2). 642 */ 643 #define PCI_VPD_ADDRESS_MASK 0x7fff 644 #define PCI_VPD_ADDRESS_SHIFT 16 645 #define PCI_VPD_ADDRESS(ofs) \ 646 (((ofs) & PCI_VPD_ADDRESS_MASK) << PCI_VPD_ADDRESS_SHIFT) 647 #define PCI_VPD_DATAREG(ofs) ((ofs) + 4) 648 #define PCI_VPD_OPFLAG 0x80000000 649 650 /* 651 * Capability ID: 0x04 652 * Slot ID 653 */ 654 655 /* 656 * Capability ID: 0x05 657 * MSI 658 */ 659 660 #define PCI_MSI_CTL 0x0 /* Message Control Register offset */ 661 #define PCI_MSI_MADDR 0x4 /* Message Address Register (least 662 * significant bits) offset 663 */ 664 #define PCI_MSI_MADDR64_LO 0x4 /* 64-bit Message Address Register 665 * (least significant bits) offset 666 */ 667 #define PCI_MSI_MADDR64_HI 0x8 /* 64-bit Message Address Register 668 * (most significant bits) offset 669 */ 670 #define PCI_MSI_MDATA 0x8 /* Message Data Register offset */ 671 #define PCI_MSI_MDATA64 0xc /* 64-bit Message Data Register 672 * offset 673 */ 674 #define PCI_MSI_MASK 0x10 /* Vector Mask register */ 675 #define PCI_MSI_PENDING 0x14 /* Vector Pending register */ 676 677 #define PCI_MSI_CTL_MASK __BITS(31, 16) 678 #define PCI_MSI_CTL_EXTMDATA_EN __SHIFTIN(__BIT(10), PCI_MSI_CTL_MASK) 679 #define PCI_MSI_CTL_EXTMDATA_CAP __SHIFTIN(__BIT(9), PCI_MSI_CTL_MASK) 680 #define PCI_MSI_CTL_PERVEC_MASK __SHIFTIN(__BIT(8), PCI_MSI_CTL_MASK) 681 #define PCI_MSI_CTL_64BIT_ADDR __SHIFTIN(__BIT(7), PCI_MSI_CTL_MASK) 682 #define PCI_MSI_CTL_MME_MASK __SHIFTIN(__BITS(6, 4), PCI_MSI_CTL_MASK) 683 #define PCI_MSI_CTL_MME(reg) __SHIFTOUT(reg, PCI_MSI_CTL_MME_MASK) 684 #define PCI_MSI_CTL_MMC_MASK __SHIFTIN(__BITS(3, 1), PCI_MSI_CTL_MASK) 685 #define PCI_MSI_CTL_MMC(reg) __SHIFTOUT(reg, PCI_MSI_CTL_MMC_MASK) 686 #define PCI_MSI_CTL_MSI_ENABLE __SHIFTIN(__BIT(0), PCI_MSI_CTL_MASK) 687 688 /* 689 * MSI Message Address is at offset 4. 690 * MSI Message Upper Address (if 64bit) is at offset 8. 691 * MSI Message data is at offset 8 or 12 and is lower 16 bits. 692 * MSI Extended Message data is at offset 8 or 12 and is upper 16 bits. 693 * MSI Mask Bits (32 bit field) 694 * MSI Pending Bits (32 bit field) 695 */ 696 697 /* Max number of MSI vectors. See PCI-SIG specification. */ 698 #define PCI_MSI_MAX_VECTORS 32 699 700 /* 701 * Capability ID: 0x07 702 * PCI-X capability. 703 * 704 * PCI-X capability register has two different layouts. One is for bridge 705 * function. Another is for non-bridge functions. 706 */ 707 708 709 /* For non-bridge functions */ 710 711 /* 712 * Command. 16 bits at offset 2 (e.g. upper 16 bits of the first 32-bit 713 * word at the capability; the lower 16 bits are the capability ID and 714 * next capability pointer). 715 * 716 * Since we always read PCI config space in 32-bit words, we define these 717 * as 32-bit values, offset and shifted appropriately. Make sure you perform 718 * the appropriate R/M/W cycles! 719 */ 720 #define PCIX_CMD 0x00 721 #define PCIX_CMD_PERR_RECOVER 0x00010000 722 #define PCIX_CMD_RELAXED_ORDER 0x00020000 723 #define PCIX_CMD_BYTECNT_MASK 0x000c0000 724 #define PCIX_CMD_BYTECNT_SHIFT 18 725 #define PCIX_CMD_BYTECNT(reg) \ 726 (512 << (((reg) & PCIX_CMD_BYTECNT_MASK) >> PCIX_CMD_BYTECNT_SHIFT)) 727 #define PCIX_CMD_BCNT_512 0x00000000 728 #define PCIX_CMD_BCNT_1024 0x00040000 729 #define PCIX_CMD_BCNT_2048 0x00080000 730 #define PCIX_CMD_BCNT_4096 0x000c0000 731 #define PCIX_CMD_SPLTRANS_MASK 0x00700000 732 #define PCIX_CMD_SPLTRANS_SHIFT 20 733 #define PCIX_CMD_SPLTRANS_1 0x00000000 734 #define PCIX_CMD_SPLTRANS_2 0x00100000 735 #define PCIX_CMD_SPLTRANS_3 0x00200000 736 #define PCIX_CMD_SPLTRANS_4 0x00300000 737 #define PCIX_CMD_SPLTRANS_8 0x00400000 738 #define PCIX_CMD_SPLTRANS_12 0x00500000 739 #define PCIX_CMD_SPLTRANS_16 0x00600000 740 #define PCIX_CMD_SPLTRANS_32 0x00700000 741 742 /* 743 * Status. 32 bits at offset 4. 744 */ 745 #define PCIX_STATUS 0x04 746 #define PCIX_STATUS_FN_MASK 0x00000007 747 #define PCIX_STATUS_DEV_MASK 0x000000f8 748 #define PCIX_STATUS_DEV_SHIFT 3 749 #define PCIX_STATUS_BUS_MASK 0x0000ff00 750 #define PCIX_STATUS_BUS_SHIFT 8 751 #define PCIX_STATUS_FN(val) ((val) & PCIX_STATUS_FN_MASK) 752 #define PCIX_STATUS_DEV(val) \ 753 (((val) & PCIX_STATUS_DEV_MASK) >> PCIX_STATUS_DEV_SHIFT) 754 #define PCIX_STATUS_BUS(val) \ 755 (((val) & PCIX_STATUS_BUS_MASK) >> PCIX_STATUS_BUS_SHIFT) 756 #define PCIX_STATUS_64BIT 0x00010000 /* 64bit device */ 757 #define PCIX_STATUS_133 0x00020000 /* 133MHz capable */ 758 #define PCIX_STATUS_SPLDISC 0x00040000 /* Split completion discarded*/ 759 #define PCIX_STATUS_SPLUNEX 0x00080000 /* Unexpected split complet. */ 760 #define PCIX_STATUS_DEVCPLX 0x00100000 /* Device Complexity */ 761 #define PCIX_STATUS_MAXB_MASK 0x00600000 /* MAX memory read Byte count*/ 762 #define PCIX_STATUS_MAXB_SHIFT 21 763 #define PCIX_STATUS_MAXB_512 0x00000000 764 #define PCIX_STATUS_MAXB_1024 0x00200000 765 #define PCIX_STATUS_MAXB_2048 0x00400000 766 #define PCIX_STATUS_MAXB_4096 0x00600000 767 #define PCIX_STATUS_MAXST_MASK 0x03800000 /* MAX outstand. Split Trans.*/ 768 #define PCIX_STATUS_MAXST_SHIFT 23 769 #define PCIX_STATUS_MAXST_1 0x00000000 770 #define PCIX_STATUS_MAXST_2 0x00800000 771 #define PCIX_STATUS_MAXST_3 0x01000000 772 #define PCIX_STATUS_MAXST_4 0x01800000 773 #define PCIX_STATUS_MAXST_8 0x02000000 774 #define PCIX_STATUS_MAXST_12 0x02800000 775 #define PCIX_STATUS_MAXST_16 0x03000000 776 #define PCIX_STATUS_MAXST_32 0x03800000 777 #define PCIX_STATUS_MAXRS_MASK 0x1c000000 /* MAX cumulative Read Size */ 778 #define PCIX_STATUS_MAXRS_SHIFT 26 779 #define PCIX_STATUS_MAXRS_1K 0x00000000 780 #define PCIX_STATUS_MAXRS_2K 0x04000000 781 #define PCIX_STATUS_MAXRS_4K 0x08000000 782 #define PCIX_STATUS_MAXRS_8K 0x0c000000 783 #define PCIX_STATUS_MAXRS_16K 0x10000000 784 #define PCIX_STATUS_MAXRS_32K 0x14000000 785 #define PCIX_STATUS_MAXRS_64K 0x18000000 786 #define PCIX_STATUS_MAXRS_128K 0x1c000000 787 #define PCIX_STATUS_SCERR 0x20000000 /* rcv. Split Completion ERR.*/ 788 #define PCIX_STATUS_266 0x40000000 /* 266MHz capable */ 789 #define PCIX_STATUS_533 0x80000000 /* 533MHz capable */ 790 791 /* For bridge function */ 792 793 #define PCIX_BRIDGE_2ND_STATUS 0x00 794 #define PCIX_BRIDGE_ST_64BIT 0x00010000 /* Same as PCIX_STATUS (nonb)*/ 795 #define PCIX_BRIDGE_ST_133 0x00020000 /* Same as PCIX_STATUS (nonb)*/ 796 #define PCIX_BRIDGE_ST_SPLDISC 0x00040000 /* Same as PCIX_STATUS (nonb)*/ 797 #define PCIX_BRIDGE_ST_SPLUNEX 0x00080000 /* Same as PCIX_STATUS (nonb)*/ 798 #define PCIX_BRIDGE_ST_SPLOVRN 0x00100000 /* Split completion overrun */ 799 #define PCIX_BRIDGE_ST_SPLRQDL 0x00200000 /* Split request delayed */ 800 #define PCIX_BRIDGE_2NDST_CLKF 0x03c00000 /* Secondary clock frequency */ 801 #define PCIX_BRIDGE_2NDST_CLKF_SHIFT 22 802 #define PCIX_BRIDGE_2NDST_VER_MASK 0x30000000 /* Version */ 803 #define PCIX_BRIDGE_2NDST_VER_SHIFT 28 804 #define PCIX_BRIDGE_ST_266 0x40000000 /* Same as PCIX_STATUS (nonb)*/ 805 #define PCIX_BRIDGE_ST_533 0x80000000 /* Same as PCIX_STATUS (nonb)*/ 806 807 #define PCIX_BRIDGE_PRI_STATUS 0x04 808 /* Bit 0 to 15 are the same as PCIX_STATUS */ 809 /* Bit 16 to 21 are the same as PCIX_BRIDGE_2ND_STATUS */ 810 /* Bit 30 and 31 are the same as PCIX_BRIDGE_2ND_STATUS */ 811 812 #define PCIX_BRIDGE_UP_STCR 0x08 /* Upstream Split Transaction Control */ 813 #define PCIX_BRIDGE_DOWN_STCR 0x0c /* Downstream Split Transaction Control */ 814 /* The layouts of above two registers are the same */ 815 #define PCIX_BRIDGE_STCAP 0x0000ffff /* Sp. Tr. Capacity */ 816 #define PCIX_BRIDGE_STCLIM 0xffff0000 /* Sp. Tr. Commitment Limit */ 817 #define PCIX_BRIDGE_STCLIM_SHIFT 16 818 819 /* 820 * Capability ID: 0x08 821 * HyperTransport 822 */ 823 824 #define PCI_HT_CMD 0x00 /* Capability List & Command Register */ 825 #define PCI_HT_CMD_MASK __BITS(31, 16) 826 #define PCI_HT_CAP(cr) ((((cr) >> 27) < 0x08) ? \ 827 (((cr) >> 27) & 0x1c) : (((cr) >> 27) & 0x1f)) 828 #define PCI_HT_CAPMASK __BITS(31, 27) 829 #define PCI_HT_CAP_SLAVE 0b00000 /* 000xx */ 830 #define PCI_HT_CAP_HOST 0b00100 /* 001xx */ 831 #define PCI_HT_CAP_SWITCH 0b01000 832 #define PCI_HT_CAP_INTERRUPT 0b10000 833 #define PCI_HT_CAP_REVID 0b10001 834 #define PCI_HT_CAP_UNITID_CLUMP 0b10010 835 #define PCI_HT_CAP_EXTCNFSPACE 0b10011 836 #define PCI_HT_CAP_ADDRMAP 0b10100 837 #define PCI_HT_CAP_MSIMAP 0b10101 838 #define PCI_HT_CAP_DIRECTROUTE 0b10110 839 #define PCI_HT_CAP_VCSET 0b10111 840 #define PCI_HT_CAP_RETRYMODE 0b11000 841 #define PCI_HT_CAP_X86ENCODE 0b11001 842 #define PCI_HT_CAP_GEN3 0b11010 843 #define PCI_HT_CAP_FLE 0b11011 844 #define PCI_HT_CAP_PM 0b11100 845 #define PCI_HT_CAP_HIGHNODECNT 0b11101 846 847 /* 848 * HT Cap ID: 0b10101 849 * MSI Mapping 850 */ 851 852 /* Command register bits (31-16)*/ 853 #define PCI_HT_MSI_ENABLED __BIT(16) 854 #define PCI_HT_MSI_FIXED __BIT(17) 855 856 #define PCI_HT_MSI_ADDR_LO 0x04 /* Address register (low) */ 857 #define PCI_HT_MSI_ADDR_LO_MASK __BITS(31, 20) 858 #define PCI_HT_MSI_FIXED_ADDR 0xfee00000UL 859 #define PCI_HT_MSI_ADDR_HI 0x08 /* Address Register (high) */ 860 861 /* 862 * Capability ID: 0x09 863 * Vendor Specific 864 */ 865 #define PCI_VENDORSPECIFIC 0x02 866 #define PCI_VENDORSPECIFIC_SHIFT 16 867 868 /* 869 * Capability ID: 0x0a 870 * Debug Port 871 */ 872 #define PCI_DEBUG_BASER 0x00 /* Debug Base Register */ 873 #define PCI_DEBUG_BASER_SHIFT 16 874 #define PCI_DEBUG_PORTOFF_SHIFT 16 875 #define PCI_DEBUG_PORTOFF_MASK 0x1fff0000 /* Debug port offset */ 876 #define PCI_DEBUG_BARNUM_SHIFT 29 877 #define PCI_DEBUG_BARNUM_MASK 0xe0000000 /* BAR number */ 878 879 /* 880 * Capability ID: 0x0b 881 * Compact PCI 882 */ 883 884 /* 885 * Capability ID: 0x0c 886 * Hotplug 887 */ 888 889 /* 890 * Capability ID: 0x0d 891 * Subsystem 892 */ 893 #define PCI_CAP_SUBSYS_ID 0x04 894 /* bit field layout is the same as PCI_SUBSYS_ID_REG's one */ 895 896 /* 897 * Capability ID: 0x0e 898 * AGP8 899 */ 900 901 /* 902 * Capability ID: 0x0f 903 * Secure Device 904 * 905 * Reference: AMD I/O Virtualization Technology(IOMMU) Specification (#48882) 906 * Revision 3.00. 907 */ 908 #define PCI_SECURE_CAP 0x00 /* Capability Header */ 909 #define PCI_SECURE_CAP_TYPE __BITS(18, 16) /* Capability block type */ 910 #define PCI_SECURE_CAP_TYPE_IOMMU 0x3 /* IOMMU Cap */ 911 #define PCI_SECURE_CAP_REV __BITS(23, 19) /* Capability revision */ 912 #define PCI_SECURE_CAP_REV_IOMMU 0x01 /* IOMMU interface */ 913 /* For IOMMU only */ 914 #define PCI_SECURE_CAP_IOTLBSUP __BIT(24) /* IOTLB */ 915 #define PCI_SECURE_CAP_HTTUNNEL __BIT(25) /* HT tunnel translation */ 916 #define PCI_SECURE_CAP_NPCACHE __BIT(26) /* Not present table entries cahced*/ 917 #define PCI_SECURE_CAP_EFRSUP __BIT(27) /* IOMMU Ext-Feature Reg */ 918 #define PCI_SECURE_CAP_EXT __BIT(28) /* IOMMU Misc Info Reg 1 */ 919 #define PCI_SECURE_IOMMU_BAL 0x04 /* Base Address Low */ 920 #define PCI_SECURE_IOMMU_BAL_EN __BIT(0) /* Enable */ 921 #define PCI_SECURE_IOMMU_BAL_L __BITS(18, 14) /* Base Addr [18:14] */ 922 #define PCI_SECURE_IOMMU_BAL_H __BITS(31, 19) /* Base Addr [31:19] */ 923 #define PCI_SECURE_IOMMU_BAH 0x08 /* Base Address High */ 924 #define PCI_SECURE_IOMMU_RANGE 0x0c /* IOMMU Range */ 925 #define PCI_SECURE_IOMMU_RANGE_UNITID __BITS(4, 0) /* HT UnitID */ 926 #define PCI_SECURE_IOMMU_RANGE_RNGVALID __BIT(7) /* Range valid */ 927 #define PCI_SECURE_IOMMU_RANGE_BUSNUM __BITS(15, 8) /* bus number */ 928 #define PCI_SECURE_IOMMU_RANGE_FIRSTDEV __BITS(23, 16) /* First device */ 929 #define PCI_SECURE_IOMMU_RANGE_LASTDEV __BITS(31, 24) /* Last device */ 930 #define PCI_SECURE_IOMMU_MISC0 0x10 /* IOMMU Miscellaneous Information 0 */ 931 #define PCI_SECURE_IOMMU_MISC0_MSINUM __BITS(4, 0) /* MSI Message number */ 932 #define PCI_SECURE_IOMMU_MISC0_GVASIZE __BITS(7, 5) /* Guest Virtual Adr siz */ 933 #define PCI_SECURE_IOMMU_MISC0_GVASIZE_48B 0x2 /* 48bits */ 934 #define PCI_SECURE_IOMMU_MISC0_PASIZE __BITS(14, 8) /* Physical Address siz */ 935 #define PCI_SECURE_IOMMU_MISC0_VASIZE __BITS(21, 15)/* Virtual Address size */ 936 #define PCI_SECURE_IOMMU_MISC0_ATSRESV __BIT(22) /* ATS resp addr range rsvd */ 937 #define PCI_SECURE_IOMMU_MISC0_MISNPPR __BITS(31, 27)/* Periph Pg Rq MSI Msgn*/ 938 #define PCI_SECURE_IOMMU_MISC1 0x14 /* IOMMU Miscellaneous Information 1 */ 939 #define PCI_SECURE_IOMMU_MISC1_MSINUM __BITS(4, 0) /* MSI Messsage number(GA)*/ 940 941 /* 942 * Capability ID: 0x10 943 * PCI Express; access via capability pointer. 944 */ 945 #define PCIE_XCAP 0x00 /* Capability List & Capabilities Register */ 946 #define PCIE_XCAP_MASK __BITS(31, 16) 947 /* Capability Version */ 948 #define PCIE_XCAP_VER_MASK __SHIFTIN(__BITS(3, 0), PCIE_XCAP_MASK) 949 #define PCIE_XCAP_VER(x) __SHIFTOUT((x), PCIE_XCAP_VER_MASK) 950 #define PCIE_XCAP_VER_1 1 951 #define PCIE_XCAP_VER_2 2 952 #define PCIE_XCAP_TYPE_MASK __SHIFTIN(__BITS(7, 4), PCIE_XCAP_MASK) 953 #define PCIE_XCAP_TYPE(x) __SHIFTOUT((x), PCIE_XCAP_TYPE_MASK) 954 #define PCIE_XCAP_TYPE_PCIE_DEV 0x0 955 #define PCIE_XCAP_TYPE_PCI_DEV 0x1 956 #define PCIE_XCAP_TYPE_ROOT 0x4 957 #define PCIE_XCAP_TYPE_UP 0x5 958 #define PCIE_XCAP_TYPE_DOWN 0x6 959 #define PCIE_XCAP_TYPE_PCIE2PCI 0x7 960 #define PCIE_XCAP_TYPE_PCI2PCIE 0x8 961 #define PCIE_XCAP_TYPE_ROOT_INTEP 0x9 962 #define PCIE_XCAP_TYPE_ROOT_EVNTC 0xa 963 #define PCIE_XCAP_SI __SHIFTIN(__BIT(8), PCIE_XCAP_MASK) /* Slot Implemented */ 964 #define PCIE_XCAP_IRQ __SHIFTIN(__BITS(13, 9), PCIE_XCAP_MASK) 965 #define PCIE_DCAP 0x04 /* Device Capabilities Register */ 966 #define PCIE_DCAP_MAX_PAYLOAD __BITS(2, 0) /* Max Payload Size Supported */ 967 #define PCIE_DCAP_PHANTOM_FUNCS __BITS(4, 3) /* Phantom Functions Supported*/ 968 #define PCIE_DCAP_EXT_TAG_FIELD __BIT(5) /* Extended Tag Field Support */ 969 #define PCIE_DCAP_L0S_LATENCY __BITS(8, 6) /* Endpoint L0 Accptbl Latency*/ 970 #define PCIE_DCAP_L1_LATENCY __BITS(11, 9) /* Endpoint L1 Accptbl Latency*/ 971 #define PCIE_DCAP_ATTN_BUTTON __BIT(12) /* Attention Indicator Button */ 972 #define PCIE_DCAP_ATTN_IND __BIT(13) /* Attention Indicator Present*/ 973 #define PCIE_DCAP_PWR_IND __BIT(14) /* Power Indicator Present */ 974 #define PCIE_DCAP_ROLE_ERR_RPT __BIT(15) /* Role-Based Error Reporting */ 975 #define PCIE_DCAP_SLOT_PWR_LIM_VAL __BITS(25, 18) /* Cap. Slot PWR Limit Val */ 976 #define PCIE_DCAP_SLOT_PWR_LIM_SCALE __BITS(27, 26) /* Cap. SlotPWRLimit Scl */ 977 #define PCIE_DCAP_FLR __BIT(28) /* Function-Level Reset Cap. */ 978 #define PCIE_DCSR 0x08 /* Device Control & Status Register */ 979 #define PCIE_DCSR_ENA_COR_ERR __BIT(0) /* Correctable Error Report En*/ 980 #define PCIE_DCSR_ENA_NFER __BIT(1) /* Non-Fatal Error Report En. */ 981 #define PCIE_DCSR_ENA_FER __BIT(2) /* Fatal Error Reporting Enabl*/ 982 #define PCIE_DCSR_ENA_URR __BIT(3) /* Unsupported Request Rpt En */ 983 #define PCIE_DCSR_ENA_RELAX_ORD __BIT(4) /* Enable Relaxed Ordering */ 984 #define PCIE_DCSR_MAX_PAYLOAD __BITS(7, 5) /* Max Payload Size */ 985 #define PCIE_DCSR_EXT_TAG_FIELD __BIT(8) /* Extended Tag Field Enable */ 986 #define PCIE_DCSR_PHANTOM_FUNCS __BIT(9) /* Phantom Functions Enable */ 987 #define PCIE_DCSR_AUX_POWER_PM __BIT(10) /* Aux Power PM Enable */ 988 #define PCIE_DCSR_ENA_NO_SNOOP __BIT(11) /* Enable No Snoop */ 989 #define PCIE_DCSR_MAX_READ_REQ __BITS(14, 12) /* Max Read Request Size */ 990 #define PCIE_DCSR_BRDG_CFG_RETRY __BIT(15) /* Bridge Config Retry Enable */ 991 #define PCIE_DCSR_INITIATE_FLR __BIT(15) /* Initiate Function-Level Rst*/ 992 #define PCIE_DCSR_CED __BIT(0 + 16) /* Correctable Error Detected */ 993 #define PCIE_DCSR_NFED __BIT(1 + 16) /* Non-Fatal Error Detected */ 994 #define PCIE_DCSR_FED __BIT(2 + 16) /* Fatal Error Detected */ 995 #define PCIE_DCSR_URD __BIT(3 + 16) /* Unsupported Req. Detected */ 996 #define PCIE_DCSR_AUX_PWR __BIT(4 + 16) /* Aux Power Detected */ 997 #define PCIE_DCSR_TRANSACTION_PND __BIT(5 + 16) /* Transaction Pending */ 998 #define PCIE_DCSR_EMGPWRREDD __BIT(6 + 16) /* Emg. Pwr. Reduct. Detected */ 999 #define PCIE_LCAP 0x0c /* Link Capabilities Register */ 1000 #define PCIE_LCAP_MAX_SPEED __BITS(3, 0) /* Max Link Speed */ 1001 #define PCIE_LCAP_MAX_WIDTH __BITS(9, 4) /* Maximum Link Width */ 1002 #define PCIE_LCAP_ASPM __BITS(11, 10) /* Active State Link PM Supp. */ 1003 #define PCIE_LCAP_L0S_EXIT __BITS(14, 12) /* L0s Exit Latency */ 1004 #define PCIE_LCAP_L1_EXIT __BITS(17, 15) /* L1 Exit Latency */ 1005 #define PCIE_LCAP_CLOCK_PM __BIT(18) /* Clock Power Management */ 1006 #define PCIE_LCAP_SURPRISE_DOWN __BIT(19) /* Surprise Down Err Rpt Cap. */ 1007 #define PCIE_LCAP_DL_ACTIVE __BIT(20) /* Data Link Layer Link Active*/ 1008 #define PCIE_LCAP_LINK_BW_NOTIFY __BIT(21) /* Link BW Notification Capabl*/ 1009 #define PCIE_LCAP_ASPM_COMPLIANCE __BIT(22) /* ASPM Optionally Compliance */ 1010 #define PCIE_LCAP_PORT __BITS(31, 24) /* Port Number */ 1011 #define PCIE_LCSR 0x10 /* Link Control & Status Register */ 1012 #define PCIE_LCSR_ASPM_L0S __BIT(0) /* Active State PM Control L0s*/ 1013 #define PCIE_LCSR_ASPM_L1 __BIT(1) /* Active State PM Control L1 */ 1014 #define PCIE_LCSR_RCB __BIT(3) /* Read Completion Boundry Ctl*/ 1015 #define PCIE_LCSR_LINK_DIS __BIT(4) /* Link Disable */ 1016 #define PCIE_LCSR_RETRAIN __BIT(5) /* Retrain Link */ 1017 #define PCIE_LCSR_COMCLKCFG __BIT(6) /* Common Clock Configuration */ 1018 #define PCIE_LCSR_EXTNDSYNC __BIT(7) /* Extended Synch */ 1019 #define PCIE_LCSR_ENCLKPM __BIT(8) /* Enable Clock Power Managmt */ 1020 #define PCIE_LCSR_HAWD __BIT(9) /* HW Autonomous Width Disable*/ 1021 #define PCIE_LCSR_LBMIE __BIT(10) /* Link BW Management Intr En */ 1022 #define PCIE_LCSR_LABIE __BIT(11) /* Link Autonomous BW Intr En */ 1023 #define PCIE_LCSR_DRSSGNL __BITS(15, 14) /* DRS Signaling */ 1024 #define PCIE_LCSR_LINKSPEED __BITS(19, 16) /* Link Speed */ 1025 #define PCIE_LCSR_NLW __BITS(25, 20) /* Negotiated Link Width */ 1026 #define PCIE_LCSR_LINKTRAIN_ERR __BIT(10 + 16) /* Link Training Error */ 1027 #define PCIE_LCSR_LINKTRAIN __BIT(11 + 16) /* Link Training */ 1028 #define PCIE_LCSR_SLOTCLKCFG __BIT(12 + 16) /* Slot Clock Configuration */ 1029 #define PCIE_LCSR_DLACTIVE __BIT(13 + 16) /* Data Link Layer Link Active*/ 1030 #define PCIE_LCSR_LINK_BW_MGMT __BIT(14 + 16) /* Link BW Management Status */ 1031 #define PCIE_LCSR_LINK_AUTO_BW __BIT(15 + 16) /* Link Autonomous BW Status */ 1032 #define PCIE_SLCAP 0x14 /* Slot Capabilities Register */ 1033 #define PCIE_SLCAP_ABP __BIT(0) /* Attention Button Present */ 1034 #define PCIE_SLCAP_PCP __BIT(1) /* Power Controller Present */ 1035 #define PCIE_SLCAP_MSP __BIT(2) /* MRL Sensor Present */ 1036 #define PCIE_SLCAP_AIP __BIT(3) /* Attention Indicator Present*/ 1037 #define PCIE_SLCAP_PIP __BIT(4) /* Power Indicator Present */ 1038 #define PCIE_SLCAP_HPS __BIT(5) /* Hot-Plug Surprise */ 1039 #define PCIE_SLCAP_HPC __BIT(6) /* Hot-Plug Capable */ 1040 #define PCIE_SLCAP_SPLV __BITS(14, 7) /* Slot Power Limit Value */ 1041 #define PCIE_SLCAP_SPLS __BITS(16, 15) /* Slot Power Limit Scale */ 1042 #define PCIE_SLCAP_EIP __BIT(17) /* Electromechanical Interlock*/ 1043 #define PCIE_SLCAP_NCCS __BIT(18) /* No Command Completed Supp. */ 1044 #define PCIE_SLCAP_PSN __BITS(31, 19) /* Physical Slot Number */ 1045 #define PCIE_SLCSR 0x18 /* Slot Control & Status Register */ 1046 #define PCIE_SLCSR_ABE __BIT(0) /* Attention Button Pressed En*/ 1047 #define PCIE_SLCSR_PFE __BIT(1) /* Power Button Pressed Enable*/ 1048 #define PCIE_SLCSR_MSE __BIT(2) /* MRL Sensor Changed Enable */ 1049 #define PCIE_SLCSR_PDE __BIT(3) /* Presence Detect Changed Ena*/ 1050 #define PCIE_SLCSR_CCE __BIT(4) /* Command Completed Intr. En */ 1051 #define PCIE_SLCSR_HPE __BIT(5) /* Hot Plug Interrupt Enable */ 1052 #define PCIE_SLCSR_AIC __BITS(7, 6) /* Attention Indicator Control*/ 1053 #define PCIE_SLCSR_PIC __BITS(9, 8) /* Power Indicator Control */ 1054 #define PCIE_SLCSR_IND_ON 0x1 /* Attn/Power Indicator On */ 1055 #define PCIE_SLCSR_IND_BLINK 0x2 /* Attn/Power Indicator Blink */ 1056 #define PCIE_SLCSR_IND_OFF 0x3 /* Attn/Power Indicator Off */ 1057 #define PCIE_SLCSR_PCC __BIT(10) /* 1058 * Power Controller Control: 1059 * 0: Power on, 1: Power off. 1060 */ 1061 #define PCIE_SLCSR_EIC __BIT(11) /* Electromechanical Interlock*/ 1062 #define PCIE_SLCSR_DLLSCE __BIT(12) /* DataLinkLayer State Changed*/ 1063 #define PCIE_SLCSR_AUTOSPLDIS __BIT(13) /* Auto Slot Power Limit Dis. */ 1064 #define PCIE_SLCSR_ABP __BIT(0 + 16) /* Attention Button Pressed */ 1065 #define PCIE_SLCSR_PFD __BIT(1 + 16) /* Power Fault Detected */ 1066 #define PCIE_SLCSR_MSC __BIT(2 + 16) /* MRL Sensor Changed */ 1067 #define PCIE_SLCSR_PDC __BIT(3 + 16) /* Presence Detect Changed */ 1068 #define PCIE_SLCSR_CC __BIT(4 + 16) /* Command Completed */ 1069 #define PCIE_SLCSR_MS __BIT(5 + 16) /* MRL Sensor State */ 1070 #define PCIE_SLCSR_PDS __BIT(6 + 16) /* Presence Detect State */ 1071 #define PCIE_SLCSR_EIS __BIT(7 + 16) /* Electromechanical Interlock*/ 1072 #define PCIE_SLCSR_LACS __BIT(8 + 16) /* Data Link Layer State Chg. */ 1073 #define PCIE_RCR 0x1c /* Root Control & Capabilities Reg. */ 1074 #define PCIE_RCR_SERR_CER __BIT(0) /* SERR on Correctable Err. En*/ 1075 #define PCIE_RCR_SERR_NFER __BIT(1) /* SERR on Non-Fatal Error En */ 1076 #define PCIE_RCR_SERR_FER __BIT(2) /* SERR on Fatal Error Enable */ 1077 #define PCIE_RCR_PME_IE __BIT(3) /* PME Interrupt Enable */ 1078 #define PCIE_RCR_CRS_SVE __BIT(4) /* CRS Software Visibility En */ 1079 #define PCIE_RCR_CRS_SV __BIT(16) /* CRS Software Visibility */ 1080 #define PCIE_RSR 0x20 /* Root Status Register */ 1081 #define PCIE_RSR_PME_REQESTER __BITS(15, 0) /* PME Requester ID */ 1082 #define PCIE_RSR_PME_STAT __BIT(16) /* PME Status */ 1083 #define PCIE_RSR_PME_PEND __BIT(17) /* PME Pending */ 1084 #define PCIE_DCAP2 0x24 /* Device Capabilities 2 Register */ 1085 #define PCIE_DCAP2_COMPT_RANGE __BITS(3,0) /* Compl. Timeout Ranges Supp */ 1086 #define PCIE_DCAP2_COMPT_DIS __BIT(4) /* Compl. Timeout Disable Supp*/ 1087 #define PCIE_DCAP2_ARI_FWD __BIT(5) /* ARI Forward Supported */ 1088 #define PCIE_DCAP2_ATOM_ROUT __BIT(6) /* AtomicOp Routing Supported */ 1089 #define PCIE_DCAP2_32ATOM __BIT(7) /* 32bit AtomicOp Compl. Supp */ 1090 #define PCIE_DCAP2_64ATOM __BIT(8) /* 64bit AtomicOp Compl. Supp */ 1091 #define PCIE_DCAP2_128CAS __BIT(9) /* 128bit Cas Completer Supp. */ 1092 #define PCIE_DCAP2_NO_ROPR_PASS __BIT(10) /* No RO-enabled PR-PR Passng */ 1093 #define PCIE_DCAP2_LTR_MEC __BIT(11) /* LTR Mechanism Supported */ 1094 #define PCIE_DCAP2_TPH_COMP __BITS(13, 12) /* TPH Completer Supported */ 1095 #define PCIE_DCAP2_LNSYSCLS __BITS(15, 14) /* LN System CLS */ 1096 #define PCIE_DCAP2_OBFF __BITS(19, 18) /* Optimized Buffer Flush/Fill*/ 1097 #define PCIE_DCAP2_EXTFMT_FLD __BIT(20) /* Extended Fmt Field Support */ 1098 #define PCIE_DCAP2_EETLP_PREF __BIT(21) /* End-End TLP Prefix Support */ 1099 #define PCIE_DCAP2_MAX_EETLP __BITS(23, 22) /* Max End-End TLP Prefix Sup */ 1100 #define PCIE_DCAP2_EMGPWRRED __BITS(25, 24) /* Emergency Power Reduc. Sup */ 1101 #define PCIE_DCAP2_EMGPWRRED_INI __BIT(26) /* Emrg. Pwr. Reduc. Ini. Req */ 1102 #define PCIE_DCAP2_FRS __BIT(31) /* FRS Supported */ 1103 #define PCIE_DCSR2 0x28 /* Device Control & Status 2 Register */ 1104 #define PCIE_DCSR2_COMPT_VAL __BITS(3, 0) /* Completion Timeout Value */ 1105 #define PCIE_DCSR2_COMPT_DIS __BIT(4) /* Completion Timeout Disable */ 1106 #define PCIE_DCSR2_ARI_FWD __BIT(5) /* ARI Forwarding Enable */ 1107 #define PCIE_DCSR2_ATOM_REQ __BIT(6) /* AtomicOp Requester Enable */ 1108 #define PCIE_DCSR2_ATOM_EBLK __BIT(7) /* AtomicOp Egress Blocking */ 1109 #define PCIE_DCSR2_IDO_REQ __BIT(8) /* IDO Request Enable */ 1110 #define PCIE_DCSR2_IDO_COMP __BIT(9) /* IDO Completion Enable */ 1111 #define PCIE_DCSR2_LTR_MEC __BIT(10) /* LTR Mechanism Enable */ 1112 #define PCIE_DCSR2_EMGPWRRED_REQ __BIT(11) /* Emergency Power Reduc. Req */ 1113 #define PCIE_DCSR2_OBFF_EN __BITS(14, 13) /* OBFF Enable */ 1114 #define PCIE_DCSR2_EETLP __BIT(15) /* End-End TLP Prefix Blcking */ 1115 #define PCIE_LCAP2 0x2c /* Link Capabilities 2 Register */ 1116 #define PCIE_LCAP2_SUP_LNKSV __BITS(7, 1) /* Supported Link Speeds Vect */ 1117 #define PCIE_LCAP2_CROSSLNK __BIT(8) /* Crosslink Supported */ 1118 #define PCIE_LCAP2_LOWSKPOS_GENSUPPSV __BITS(15, 9) 1119 /* Lower SKP OS Generation Supp. Spd. Vect */ 1120 #define PCIE_LCAP2_LOWSKPOS_RECSUPPSV __BITS(22, 16) 1121 /* Lower SKP OS Reception Supp. Spd. Vect */ 1122 #define PCIE_LCAP2_RETIMERPD __BIT(23) /* Retimer Presence Detect */ 1123 #define PCIE_LCAP2_DRS __BIT(31) /* DRS Supported */ 1124 #define PCIE_LCSR2 0x30 /* Link Control & Status 2 Register */ 1125 #define PCIE_LCSR2_TGT_LSPEED __BITS(3, 0) /* Target Link Speed */ 1126 #define PCIE_LCSR2_ENT_COMPL __BIT(4) /* Enter Compliance */ 1127 #define PCIE_LCSR2_HW_AS_DIS __BIT(5) /* HW Autonomous Speed Disabl */ 1128 #define PCIE_LCSR2_SEL_DEEMP __BIT(6) /* Selectable De-emphasis */ 1129 #define PCIE_LCSR2_TX_MARGIN __BITS(9, 7) /* Transmit Margin */ 1130 #define PCIE_LCSR2_EN_MCOMP __BIT(10) /* Enter Modified Compliance */ 1131 #define PCIE_LCSR2_COMP_SOS __BIT(11) /* Compliance SOS */ 1132 #define PCIE_LCSR2_COMP_DEEMP __BITS(15, 12) /* Compliance Present/De-emph */ 1133 #define PCIE_LCSR2_DEEMP_LVL __BIT(0 + 16) /* Current De-emphasis Level */ 1134 #define PCIE_LCSR2_EQ_COMPL __BIT(1 + 16) /* Equalization Complete */ 1135 #define PCIE_LCSR2_EQP1_SUC __BIT(2 + 16) /* Equaliz Phase 1 Successful */ 1136 #define PCIE_LCSR2_EQP2_SUC __BIT(3 + 16) /* Equaliz Phase 2 Successful */ 1137 #define PCIE_LCSR2_EQP3_SUC __BIT(4 + 16) /* Equaliz Phase 3 Successful */ 1138 #define PCIE_LCSR2_LNKEQ_REQ __BIT(5 + 16) /* Link Equalization Request */ 1139 #define PCIE_LCSR2_RETIMERPD __BIT(6 + 16) /* Retimer Presence Detected */ 1140 #define PCIE_LCSR2_DSCOMPN __BITS(30, 28) /* Downstream Component Pres. */ 1141 #define PCIE_DSCOMPN_DOWN_NOTDETERM 0x00 /* LD: Presence Not Determin.*/ 1142 #define PCIE_DSCOMPN_DOWN_NOTPRES 0x01 /* LD: Component Not Present */ 1143 #define PCIE_DSCOMPN_DOWN_PRES 0x02 /* LD: Component Present */ 1144 /* 0x03 is reserved */ 1145 #define PCIE_DSCOMPN_UP_PRES 0x04 /* LU: Component Present */ 1146 #define PCIE_DSCOMPN_UP_PRES_DRS 0x05 /* LU: Comp Pres and DRS RCV */ 1147 #define PCIE_LCSR2_DRSRCV __BIT(15 + 16) /* DRS Message Received */ 1148 1149 #define PCIE_SLCAP2 0x34 /* Slot Capabilities 2 Register */ 1150 #define PCIE_SLCSR2 0x38 /* Slot Control & Status 2 Register */ 1151 1152 /* 1153 * Capability ID: 0x11 1154 * MSIX 1155 */ 1156 1157 #define PCI_MSIX_CTL 0x00 1158 #define PCI_MSIX_CTL_ENABLE 0x80000000 1159 #define PCI_MSIX_CTL_FUNCMASK 0x40000000 1160 #define PCI_MSIX_CTL_TBLSIZE_MASK 0x07ff0000 1161 #define PCI_MSIX_CTL_TBLSIZE_SHIFT 16 1162 #define PCI_MSIX_CTL_TBLSIZE(ofs) ((((ofs) & PCI_MSIX_CTL_TBLSIZE_MASK) \ 1163 >> PCI_MSIX_CTL_TBLSIZE_SHIFT) + 1) 1164 /* 1165 * 2nd DWORD is the Table Offset 1166 */ 1167 #define PCI_MSIX_TBLOFFSET 0x04 1168 #define PCI_MSIX_TBLOFFSET_MASK __BITS(31, 3) 1169 #define PCI_MSIX_TBLBIR_MASK __BITS(2, 0) 1170 /* 1171 * 3rd DWORD is the Pending Bitmap Array Offset 1172 */ 1173 #define PCI_MSIX_PBAOFFSET 0x08 1174 #define PCI_MSIX_PBAOFFSET_MASK __BITS(31, 3) 1175 #define PCI_MSIX_PBABIR_MASK __BITS(2, 0) 1176 1177 #define PCI_MSIX_TABLE_ENTRY_SIZE 16 1178 #define PCI_MSIX_TABLE_ENTRY_ADDR_LO 0x0 1179 #define PCI_MSIX_TABLE_ENTRY_ADDR_HI 0x4 1180 #define PCI_MSIX_TABLE_ENTRY_DATA 0x8 1181 #define PCI_MSIX_TABLE_ENTRY_VECTCTL 0xc 1182 struct pci_msix_table_entry { 1183 uint32_t pci_msix_addr_lo; 1184 uint32_t pci_msix_addr_hi; 1185 uint32_t pci_msix_value; 1186 uint32_t pci_msix_vector_control; 1187 }; 1188 #define PCI_MSIX_VECTCTL_MASK __BIT(0) 1189 #define PCI_MSIX_VECTCTL_STLO __BITS(23, 16) 1190 #define PCI_MSIX_VECTCTL_STUP __BITS(31, 24) 1191 1192 /* Max number of MSI-X vectors. See PCI-SIG specification. */ 1193 #define PCI_MSIX_MAX_VECTORS 2048 1194 1195 /* 1196 * Capability ID: 0x12 1197 * SATA 1198 */ 1199 #define PCI_SATA_REV 0x00 /* Revision Register */ 1200 #define PCI_SATA_REV_MINOR __BITS(19, 16) /* Minor Revision */ 1201 #define PCI_SATA_REV_MAJOR __BITS(23, 20) /* Major Revision */ 1202 #define PCI_SATA_BAR 0x04 /* BAR Register */ 1203 #define PCI_SATA_BAR_SPEC __BITS(3, 0) /* BAR Specifier */ 1204 #define PCI_SATA_BAR_INCONF __BITS(3, 0) /* All 1 = in config space */ 1205 #define PCI_SATA_BAR_NUM(x) (__SHIFTOUT((x), PCI_SATA_BAR_SPEC) - 4) 1206 #define PCI_SATA_BAR_OFFSET __BITS(23, 4) /* BAR Offset */ 1207 1208 /* 1209 * Capability ID: 0x13 1210 * Advanced Feature 1211 */ 1212 #define PCI_AFCAPR 0x00 /* Capabilities */ 1213 #define PCI_AFCAPR_MASK __BITS(31, 24) 1214 #define PCI_AF_LENGTH __BITS(23, 16) /* Structure Length */ 1215 #define PCI_AF_TP_CAP __BIT(24) /* Transaction Pending */ 1216 #define PCI_AF_FLR_CAP __BIT(25) /* Function Level Reset */ 1217 #define PCI_AFCSR 0x04 /* Control & Status register */ 1218 #define PCI_AFCR_INITIATE_FLR __BIT(0) /* Initiate Function LVL RST */ 1219 #define PCI_AFSR_TP __BIT(8) /* Transaction Pending */ 1220 1221 1222 /* 1223 * Interrupt Configuration Register; contains interrupt pin and line. 1224 */ 1225 #define PCI_INTERRUPT_REG 0x3c 1226 1227 typedef u_int8_t pci_intr_latency_t; 1228 typedef u_int8_t pci_intr_grant_t; 1229 typedef u_int8_t pci_intr_pin_t; 1230 typedef u_int8_t pci_intr_line_t; 1231 1232 #define PCI_MAX_LAT_SHIFT 24 1233 #define PCI_MAX_LAT_MASK 0xff 1234 #define PCI_MAX_LAT(icr) \ 1235 (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK) 1236 1237 #define PCI_MIN_GNT_SHIFT 16 1238 #define PCI_MIN_GNT_MASK 0xff 1239 #define PCI_MIN_GNT(icr) \ 1240 (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK) 1241 1242 #define PCI_INTERRUPT_GRANT_SHIFT 24 1243 #define PCI_INTERRUPT_GRANT_MASK 0xff 1244 #define PCI_INTERRUPT_GRANT(icr) \ 1245 (((icr) >> PCI_INTERRUPT_GRANT_SHIFT) & PCI_INTERRUPT_GRANT_MASK) 1246 1247 #define PCI_INTERRUPT_LATENCY_SHIFT 16 1248 #define PCI_INTERRUPT_LATENCY_MASK 0xff 1249 #define PCI_INTERRUPT_LATENCY(icr) \ 1250 (((icr) >> PCI_INTERRUPT_LATENCY_SHIFT) & PCI_INTERRUPT_LATENCY_MASK) 1251 1252 #define PCI_INTERRUPT_PIN_SHIFT 8 1253 #define PCI_INTERRUPT_PIN_MASK 0xff 1254 #define PCI_INTERRUPT_PIN(icr) \ 1255 (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK) 1256 1257 #define PCI_INTERRUPT_LINE_SHIFT 0 1258 #define PCI_INTERRUPT_LINE_MASK 0xff 1259 #define PCI_INTERRUPT_LINE(icr) \ 1260 (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK) 1261 1262 #define PCI_INTERRUPT_CODE(lat,gnt,pin,line) \ 1263 ((((lat)&PCI_INTERRUPT_LATENCY_MASK)<<PCI_INTERRUPT_LATENCY_SHIFT)| \ 1264 (((gnt)&PCI_INTERRUPT_GRANT_MASK) <<PCI_INTERRUPT_GRANT_SHIFT) | \ 1265 (((pin)&PCI_INTERRUPT_PIN_MASK) <<PCI_INTERRUPT_PIN_SHIFT) | \ 1266 (((line)&PCI_INTERRUPT_LINE_MASK) <<PCI_INTERRUPT_LINE_SHIFT)) 1267 1268 #define PCI_INTERRUPT_PIN_NONE 0x00 1269 #define PCI_INTERRUPT_PIN_A 0x01 1270 #define PCI_INTERRUPT_PIN_B 0x02 1271 #define PCI_INTERRUPT_PIN_C 0x03 1272 #define PCI_INTERRUPT_PIN_D 0x04 1273 #define PCI_INTERRUPT_PIN_MAX 0x04 1274 1275 /* Header Type 1 (Bridge) configuration registers */ 1276 #define PCI_BRIDGE_BUS_REG 0x18 1277 #define PCI_BRIDGE_BUS_EACH_MASK 0xff 1278 #define PCI_BRIDGE_BUS_PRIMARY_SHIFT 0 1279 #define PCI_BRIDGE_BUS_SECONDARY_SHIFT 8 1280 #define PCI_BRIDGE_BUS_SUBORDINATE_SHIFT 16 1281 #define PCI_BRIDGE_BUS_SEC_LATTIMER_SHIFT 24 1282 #define PCI_BRIDGE_BUS_PRIMARY(reg) \ 1283 (((reg) >> PCI_BRIDGE_BUS_PRIMARY_SHIFT) & PCI_BRIDGE_BUS_EACH_MASK) 1284 #define PCI_BRIDGE_BUS_SECONDARY(reg) \ 1285 (((reg) >> PCI_BRIDGE_BUS_SECONDARY_SHIFT) & PCI_BRIDGE_BUS_EACH_MASK) 1286 #define PCI_BRIDGE_BUS_SUBORDINATE(reg) \ 1287 (((reg) >> PCI_BRIDGE_BUS_SUBORDINATE_SHIFT) &PCI_BRIDGE_BUS_EACH_MASK) 1288 #define PCI_BRIDGE_BUS_SEC_LATTIMER(reg) \ 1289 (((reg) >> PCI_BRIDGE_BUS_SEC_LATTIMER_SHIFT)&PCI_BRIDGE_BUS_EACH_MASK) 1290 1291 1292 #define PCI_BRIDGE_STATIO_REG 0x1C 1293 #define PCI_BRIDGE_STATIO_IOBASE_SHIFT 0 1294 #define PCI_BRIDGE_STATIO_IOLIMIT_SHIFT 8 1295 #define PCI_BRIDGE_STATIO_STATUS_SHIFT 16 1296 #define PCI_BRIDGE_STATIO_IOBASE_MASK 0xf0 1297 #define PCI_BRIDGE_STATIO_IOLIMIT_MASK 0xf0 1298 #define PCI_BRIDGE_STATIO_STATUS_MASK 0xffff 1299 #define PCI_BRIDGE_IO_32BITS(reg) (((reg) & 0xf) == 1) 1300 1301 #define PCI_BRIDGE_MEMORY_REG 0x20 1302 #define PCI_BRIDGE_MEMORY_BASE_SHIFT 4 1303 #define PCI_BRIDGE_MEMORY_LIMIT_SHIFT 20 1304 #define PCI_BRIDGE_MEMORY_BASE_MASK 0x0fff 1305 #define PCI_BRIDGE_MEMORY_LIMIT_MASK 0x0fff 1306 1307 #define PCI_BRIDGE_PREFETCHMEM_REG 0x24 1308 #define PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT 4 1309 #define PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT 20 1310 #define PCI_BRIDGE_PREFETCHMEM_BASE_MASK 0x0fff 1311 #define PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK 0x0fff 1312 #define PCI_BRIDGE_PREFETCHMEM_64BITS(reg) ((reg) & 0xf) 1313 1314 #define PCI_BRIDGE_PREFETCHBASE32_REG 0x28 1315 #define PCI_BRIDGE_PREFETCHLIMIT32_REG 0x2c 1316 1317 #define PCI_BRIDGE_IOHIGH_REG 0x30 1318 #define PCI_BRIDGE_IOHIGH_BASE_SHIFT 0 1319 #define PCI_BRIDGE_IOHIGH_LIMIT_SHIFT 16 1320 #define PCI_BRIDGE_IOHIGH_BASE_MASK 0xffff 1321 #define PCI_BRIDGE_IOHIGH_LIMIT_MASK 0xffff 1322 1323 #define PCI_BRIDGE_CONTROL_REG 0x3c 1324 #define PCI_BRIDGE_CONTROL_SHIFT 16 1325 #define PCI_BRIDGE_CONTROL_MASK 0xffff 1326 #define PCI_BRIDGE_CONTROL_PERE (1 << 0) 1327 #define PCI_BRIDGE_CONTROL_SERR (1 << 1) 1328 #define PCI_BRIDGE_CONTROL_ISA (1 << 2) 1329 #define PCI_BRIDGE_CONTROL_VGA (1 << 3) 1330 #define PCI_BRIDGE_CONTROL_VGA16 (1 << 3) 1331 #define PCI_BRIDGE_CONTROL_MABRT (1 << 5) 1332 #define PCI_BRIDGE_CONTROL_SECBR (1 << 6) 1333 #define PCI_BRIDGE_CONTROL_SECFASTB2B (1 << 7) 1334 #define PCI_BRIDGE_CONTROL_PRI_DISC_TIMER (1 << 8) 1335 #define PCI_BRIDGE_CONTROL_SEC_DISC_TIMER (1 << 9) 1336 #define PCI_BRIDGE_CONTROL_DISC_TIMER_STAT (1 << 10) 1337 #define PCI_BRIDGE_CONTROL_DISC_TIMER_SERR (1 << 11) 1338 /* Reserved (1 << 12) - (1 << 15) */ 1339 1340 /* 1341 * Vital Product Data resource tags. 1342 */ 1343 struct pci_vpd_smallres { 1344 uint8_t vpdres_byte0; /* length of data + tag */ 1345 /* Actual data. */ 1346 } __packed; 1347 1348 struct pci_vpd_largeres { 1349 uint8_t vpdres_byte0; 1350 uint8_t vpdres_len_lsb; /* length of data only */ 1351 uint8_t vpdres_len_msb; 1352 /* Actual data. */ 1353 } __packed; 1354 1355 #define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) 1356 1357 #define PCI_VPDRES_SMALL_LENGTH(x) ((x) & 0x7) 1358 #define PCI_VPDRES_SMALL_NAME(x) (((x) >> 3) & 0xf) 1359 1360 #define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) 1361 1362 #define PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID 0x3 /* small */ 1363 #define PCI_VPDRES_TYPE_VENDOR_DEFINED 0xe /* small */ 1364 #define PCI_VPDRES_TYPE_END_TAG 0xf /* small */ 1365 1366 #define PCI_VPDRES_TYPE_IDENTIFIER_STRING 0x02 /* large */ 1367 #define PCI_VPDRES_TYPE_VPD 0x10 /* large */ 1368 1369 struct pci_vpd { 1370 uint8_t vpd_key0; 1371 uint8_t vpd_key1; 1372 uint8_t vpd_len; /* length of data only */ 1373 /* Actual data. */ 1374 } __packed; 1375 1376 /* 1377 * Recommended VPD fields: 1378 * 1379 * PN Part number of assembly 1380 * FN FRU part number 1381 * EC EC level of assembly 1382 * MN Manufacture ID 1383 * SN Serial Number 1384 * 1385 * Conditionally recommended VPD fields: 1386 * 1387 * LI Load ID 1388 * RL ROM Level 1389 * RM Alterable ROM Level 1390 * NA Network Address 1391 * DD Device Driver Level 1392 * DG Diagnostic Level 1393 * LL Loadable Microcode Level 1394 * VI Vendor ID/Device ID 1395 * FU Function Number 1396 * SI Subsystem Vendor ID/Subsystem ID 1397 * 1398 * Additional VPD fields: 1399 * 1400 * Z0-ZZ User/Product Specific 1401 */ 1402 1403 /* 1404 * PCI Expansion Rom 1405 */ 1406 1407 struct pci_rom_header { 1408 uint16_t romh_magic; /* 0xAA55 little endian */ 1409 uint8_t romh_reserved[22]; 1410 uint16_t romh_data_ptr; /* pointer to pci_rom struct */ 1411 } __packed; 1412 1413 #define PCI_ROM_HEADER_MAGIC 0xAA55 /* little endian */ 1414 1415 struct pci_rom { 1416 uint32_t rom_signature; 1417 pci_vendor_id_t rom_vendor; 1418 pci_product_id_t rom_product; 1419 uint16_t rom_vpd_ptr; /* reserved in PCI 2.2 */ 1420 uint16_t rom_data_len; 1421 uint8_t rom_data_rev; 1422 pci_interface_t rom_interface; /* the class reg is 24-bits */ 1423 pci_subclass_t rom_subclass; /* in little endian */ 1424 pci_class_t rom_class; 1425 uint16_t rom_len; /* code length / 512 byte */ 1426 uint16_t rom_rev; /* code revision level */ 1427 uint8_t rom_code_type; /* type of code */ 1428 uint8_t rom_indicator; 1429 uint16_t rom_reserved; 1430 /* Actual data. */ 1431 } __packed; 1432 1433 #define PCI_ROM_SIGNATURE 0x52494350 /* "PCIR", endian reversed */ 1434 #define PCI_ROM_CODE_TYPE_X86 0 /* Intel x86 BIOS */ 1435 #define PCI_ROM_CODE_TYPE_OFW 1 /* Open Firmware */ 1436 #define PCI_ROM_CODE_TYPE_HPPA 2 /* HP PA/RISC */ 1437 #define PCI_ROM_CODE_TYPE_EFI 3 /* EFI Image */ 1438 1439 #define PCI_ROM_INDICATOR_LAST 0x80 1440 1441 /* 1442 * Threshold below which 32bit PCI DMA needs bouncing. 1443 */ 1444 #define PCI32_DMA_BOUNCE_THRESHOLD 0x100000000ULL 1445 1446 /* 1447 * PCI-X 2.0/ PCI-express Extended Capability List 1448 */ 1449 1450 #define PCI_EXTCAPLIST_BASE 0x100 1451 1452 #define PCI_EXTCAPLIST_CAP(ecr) ((ecr) & 0xffff) 1453 #define PCI_EXTCAPLIST_VERSION(ecr) (((ecr) >> 16) & 0xf) 1454 #define PCI_EXTCAPLIST_NEXT(ecr) (((ecr) >> 20) & 0xfff) 1455 1456 /* Extended Capability Identification Numbers */ 1457 1458 #define PCI_EXTCAP_AER 0x0001 /* Advanced Error Reporting */ 1459 #define PCI_EXTCAP_VC 0x0002 /* Virtual Channel if MFVC Ext Cap not set */ 1460 #define PCI_EXTCAP_SERNUM 0x0003 /* Device Serial Number */ 1461 #define PCI_EXTCAP_PWRBDGT 0x0004 /* Power Budgeting */ 1462 #define PCI_EXTCAP_RCLINK_DCL 0x0005 /* Root Complex Link Declaration */ 1463 #define PCI_EXTCAP_RCLINK_CTL 0x0006 /* Root Complex Internal Link Control */ 1464 #define PCI_EXTCAP_RCEC_ASSOC 0x0007 /* Root Complex Event Collector Association */ 1465 #define PCI_EXTCAP_MFVC 0x0008 /* Multi-Function Virtual Channel */ 1466 #define PCI_EXTCAP_VC2 0x0009 /* Virtual Channel if MFVC Ext Cap set */ 1467 #define PCI_EXTCAP_RCRB 0x000a /* RCRB Header */ 1468 #define PCI_EXTCAP_VENDOR 0x000b /* Vendor Unique */ 1469 #define PCI_EXTCAP_CAC 0x000c /* Configuration Access Correction -- obsolete */ 1470 #define PCI_EXTCAP_ACS 0x000d /* Access Control Services */ 1471 #define PCI_EXTCAP_ARI 0x000e /* Alternative Routing-ID Interpretation */ 1472 #define PCI_EXTCAP_ATS 0x000f /* Address Translation Services */ 1473 #define PCI_EXTCAP_SRIOV 0x0010 /* Single Root IO Virtualization */ 1474 #define PCI_EXTCAP_MRIOV 0x0011 /* Multiple Root IO Virtualization */ 1475 #define PCI_EXTCAP_MCAST 0x0012 /* Multicast */ 1476 #define PCI_EXTCAP_PAGE_REQ 0x0013 /* Page Request */ 1477 #define PCI_EXTCAP_AMD 0x0014 /* Reserved for AMD */ 1478 #define PCI_EXTCAP_RESIZBAR 0x0015 /* Resizable BAR */ 1479 #define PCI_EXTCAP_DPA 0x0016 /* Dynamic Power Allocation */ 1480 #define PCI_EXTCAP_TPH_REQ 0x0017 /* TPH Requester */ 1481 #define PCI_EXTCAP_LTR 0x0018 /* Latency Tolerance Reporting */ 1482 #define PCI_EXTCAP_SEC_PCIE 0x0019 /* Secondary PCI Express */ 1483 #define PCI_EXTCAP_PMUX 0x001a /* Protocol Multiplexing */ 1484 #define PCI_EXTCAP_PASID 0x001b /* Process Address Space ID */ 1485 #define PCI_EXTCAP_LNR 0x001c /* LN Requester */ 1486 #define PCI_EXTCAP_DPC 0x001d /* Downstream Port Containment */ 1487 #define PCI_EXTCAP_L1PM 0x001e /* L1 PM Substates */ 1488 #define PCI_EXTCAP_PTM 0x001f /* Precision Time Management */ 1489 #define PCI_EXTCAP_MPCIE 0x0020 /* M-PCIe */ 1490 #define PCI_EXTCAP_FRSQ 0x0021 /* Function Reading Status Queueing */ 1491 #define PCI_EXTCAP_RTR 0x0022 /* Readiness Time Reporting */ 1492 #define PCI_EXTCAP_DESIGVNDSP 0x0023 /* Designated Vendor-Specific */ 1493 #define PCI_EXTCAP_VF_RESIZBAR 0x0024 /* VF Resizable BAR */ 1494 #define PCI_EXTCAP_HIERARCHYID 0x0028 /* Hierarchy ID */ 1495 #define PCI_EXTCAP_NPEM 0x0029 /* Native PCIe Enclosure Management */ 1496 1497 /* 1498 * Extended capability ID: 0x0001 1499 * Advanced Error Reporting 1500 */ 1501 #define PCI_AER_UC_STATUS 0x04 /* Uncorrectable Error Status Reg. */ 1502 #define PCI_AER_UC_UNDEFINED __BIT(0) 1503 #define PCI_AER_UC_DL_PROTOCOL_ERROR __BIT(4) 1504 #define PCI_AER_UC_SURPRISE_DOWN_ERROR __BIT(5) 1505 #define PCI_AER_UC_POISONED_TLP __BIT(12) 1506 #define PCI_AER_UC_FC_PROTOCOL_ERROR __BIT(13) 1507 #define PCI_AER_UC_COMPLETION_TIMEOUT __BIT(14) 1508 #define PCI_AER_UC_COMPLETER_ABORT __BIT(15) 1509 #define PCI_AER_UC_UNEXPECTED_COMPLETION __BIT(16) 1510 #define PCI_AER_UC_RECEIVER_OVERFLOW __BIT(17) 1511 #define PCI_AER_UC_MALFORMED_TLP __BIT(18) 1512 #define PCI_AER_UC_ECRC_ERROR __BIT(19) 1513 #define PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR __BIT(20) 1514 #define PCI_AER_UC_ACS_VIOLATION __BIT(21) 1515 #define PCI_AER_UC_INTERNAL_ERROR __BIT(22) 1516 #define PCI_AER_UC_MC_BLOCKED_TLP __BIT(23) 1517 #define PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED __BIT(24) 1518 #define PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR __BIT(25) 1519 #define PCI_AER_UC_POISONTLP_EGRESS_BLOCKED __BIT(26) 1520 #define PCI_AER_UC_MASK 0x08 /* Uncorrectable Error Mask Register */ 1521 /* Shares bits with UC_STATUS */ 1522 #define PCI_AER_UC_SEVERITY 0x0c /* Uncorrectable Error Severity Reg. */ 1523 /* Shares bits with UC_STATUS */ 1524 #define PCI_AER_COR_STATUS 0x10 /* Correctable Error Status Register */ 1525 #define PCI_AER_COR_RECEIVER_ERROR __BIT(0) 1526 #define PCI_AER_COR_BAD_TLP __BIT(6) 1527 #define PCI_AER_COR_BAD_DLLP __BIT(7) 1528 #define PCI_AER_COR_REPLAY_NUM_ROLLOVER __BIT(8) 1529 #define PCI_AER_COR_REPLAY_TIMER_TIMEOUT __BIT(12) 1530 #define PCI_AER_COR_ADVISORY_NF_ERROR __BIT(13) 1531 #define PCI_AER_COR_INTERNAL_ERROR __BIT(14) 1532 #define PCI_AER_COR_HEADER_LOG_OVERFLOW __BIT(15) 1533 #define PCI_AER_COR_MASK 0x14 /* Correctable Error Mask Register */ 1534 /* Shares bits with COR_STATUS */ 1535 #define PCI_AER_CAP_CONTROL 0x18 /* AE Capabilities and Control Reg. */ 1536 #define PCI_AER_FIRST_ERROR_PTR __BITS(4, 0) 1537 #define PCI_AER_FIRST_ERROR_PTR_S 0 1538 #define PCI_AER_FIRST_ERROR_PTR_M 0x1f 1539 #define PCI_AER_ECRC_GEN_CAPABLE __BIT(5) 1540 #define PCI_AER_ECRC_GEN_ENABLE __BIT(6) 1541 #define PCI_AER_ECRC_CHECK_CAPABLE __BIT(7) 1542 #define PCI_AER_ECRC_CHECK_ENABLE __BIT(8) 1543 #define PCI_AER_MULT_HDR_CAPABLE __BIT(9) 1544 #define PCI_AER_MULT_HDR_ENABLE __BIT(10) 1545 #define PCI_AER_TLP_PREFIX_LOG_PRESENT __BIT(11) 1546 #define PCI_AER_COMPTOUTPRFXHDRLOG_CAP __BIT(12) 1547 #define PCI_AER_HEADER_LOG 0x1c /* Header Log Register */ 1548 #define PCI_AER_ROOTERR_CMD 0x2c /* Root Error Command Register */ 1549 /* Only for root complex ports */ 1550 #define PCI_AER_ROOTERR_COR_ENABLE __BIT(0) 1551 #define PCI_AER_ROOTERR_NF_ENABLE __BIT(1) 1552 #define PCI_AER_ROOTERR_F_ENABLE __BIT(2) 1553 #define PCI_AER_ROOTERR_STATUS 0x30 /* Root Error Status Register */ 1554 /* Only for root complex ports */ 1555 #define PCI_AER_ROOTERR_COR_ERR __BIT(0) 1556 #define PCI_AER_ROOTERR_MULTI_COR_ERR __BIT(1) 1557 #define PCI_AER_ROOTERR_UC_ERR __BIT(2) 1558 #define PCI_AER_ROOTERR_MULTI_UC_ERR __BIT(3) 1559 #define PCI_AER_ROOTERR_FIRST_UC_FATAL __BIT(4) 1560 #define PCI_AER_ROOTERR_NF_ERR __BIT(5) 1561 #define PCI_AER_ROOTERR_F_ERR __BIT(6) 1562 #define PCI_AER_ROOTERR_INT_MESSAGE __BITS(31, 27) 1563 #define PCI_AER_ROOTERR_INT_MESSAGE_S 27 1564 #define PCI_AER_ROOTERR_INT_MESSAGE_M 0x1f 1565 #define PCI_AER_ERRSRC_ID 0x34 /* Error Source Identification Reg. */ 1566 #define PCI_AER_ERRSRC_ID_ERR_COR __BITS(15, 0) 1567 #define PCI_AER_ERRSRC_ID_ERR_COR_S 0 1568 #define PCI_AER_ERRSRC_ID_ERR_COR_M 0xffff 1569 #define PCI_AER_ERRSRC_ID_ERR_UC __BITS(31, 16) 1570 #define PCI_AER_ERRSRC_ID_ERR_UC_S 16 1571 #define PCI_AER_ERRSRC_ID_ERR_UC_M 0xffff 1572 /* Only for root complex ports */ 1573 #define PCI_AER_TLP_PREFIX_LOG 0x38 /*TLP Prefix Log Register */ 1574 /* Only for TLP prefix functions */ 1575 1576 /* 1577 * Extended capability ID: 0x0002, 0x0009 1578 * Virtual Channel 1579 */ 1580 #define PCI_VC_CAP1 0x04 /* Port VC Capability Register 1 */ 1581 #define PCI_VC_CAP1_EXT_COUNT __BITS(2, 0) 1582 #define PCI_VC_CAP1_EXT_COUNT_S 0 1583 #define PCI_VC_CAP1_EXT_COUNT_M 0x7 1584 #define PCI_VC_CAP1_LOWPRI_EXT_COUNT __BITS(6, 4) 1585 #define PCI_VC_CAP1_LOWPRI_EXT_COUNT_S 4 1586 #define PCI_VC_CAP1_LOWPRI_EXT_COUNT_M 0x7 1587 #define PCI_VC_CAP1_REFCLK __BITS(9, 8) 1588 #define PCI_VC_CAP1_REFCLK_S 8 1589 #define PCI_VC_CAP1_REFCLK_M 0x3 1590 #define PCI_VC_CAP1_REFCLK_100NS 0x0 1591 #define PCI_VC_CAP1_PORT_ARB_TABLE_SIZE __BITS(11, 10) 1592 #define PCI_VC_CAP1_PORT_ARB_TABLE_SIZE_S 10 1593 #define PCI_VC_CAP1_PORT_ARB_TABLE_SIZE_M 0x3 1594 #define PCI_VC_CAP2 0x08 /* Port VC Capability Register 2 */ 1595 #define PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME __BIT(0) 1596 #define PCI_VC_CAP2_ARB_CAP_WRR_32 __BIT(1) 1597 #define PCI_VC_CAP2_ARB_CAP_WRR_64 __BIT(2) 1598 #define PCI_VC_CAP2_ARB_CAP_WRR_128 __BIT(3) 1599 #define PCI_VC_CAP2_ARB_TABLE_OFFSET __BITS(31, 24) 1600 #define PCI_VC_CAP2_ARB_TABLE_OFFSET_S 24 1601 #define PCI_VC_CAP2_ARB_TABLE_OFFSET_M 0xff 1602 #define PCI_VC_CONTROL 0x0c /* Port VC Control Register (16bit) */ 1603 #define PCI_VC_CONTROL_LOAD_VC_ARB_TABLE __BIT(0) 1604 #define PCI_VC_CONTROL_VC_ARB_SELECT __BITS(3, 1) 1605 #define PCI_VC_CONTROL_VC_ARB_SELECT_S 1 1606 #define PCI_VC_CONTROL_VC_ARB_SELECT_M 0x7 1607 #define PCI_VC_STATUS 0x0e /* Port VC Status Register (16bit) */ 1608 #define PCI_VC_STATUS_LOAD_VC_ARB_TABLE __BIT(0) 1609 #define PCI_VC_RESOURCE_CAP(n) (0x10 + ((n) * 0x0c)) /* VC Resource Capability Register */ 1610 #define PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME __BIT(0) 1611 #define PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32 __BIT(1) 1612 #define PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64 __BIT(2) 1613 #define PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128 __BIT(3) 1614 #define PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128 __BIT(4) 1615 #define PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256 __BIT(5) 1616 #define PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH __BIT(14) 1617 #define PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS __BIT(15) 1618 #define PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS __BITS(22, 16) 1619 #define PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS_S 16 1620 #define PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS_M 0x7f 1621 #define PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET __BITS(31, 24) 1622 #define PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S 24 1623 #define PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_M 0xff 1624 #define PCI_VC_RESOURCE_CTL(n) (0x14 + ((n) * 0x0c)) /* VC Resource Control Register */ 1625 #define PCI_VC_RESOURCE_CTL_TCVC_MAP __BITS(7, 0) 1626 #define PCI_VC_RESOURCE_CTL_TCVC_MAP_S 0 1627 #define PCI_VC_RESOURCE_CTL_TCVC_MAP_M 0xff 1628 #define PCI_VC_RESOURCE_CTL_LOAD_PORT_ARB_TABLE __BIT(16) 1629 #define PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT __BITS(19, 17) 1630 #define PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT_S 17 1631 #define PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT_M 0x7 1632 #define PCI_VC_RESOURCE_CTL_VC_ID __BITS(26, 24) 1633 #define PCI_VC_RESOURCE_CTL_VC_ID_S 24 1634 #define PCI_VC_RESOURCE_CTL_VC_ID_M 0x7 1635 #define PCI_VC_RESOURCE_CTL_VC_ENABLE __BIT(31) 1636 #define PCI_VC_RESOURCE_STA(n) (0x18 + ((n) * 0x0c)) /* VC Resource Status Register */ 1637 #define PCI_VC_RESOURCE_STA_PORT_ARB_TABLE __BIT(0) 1638 #define PCI_VC_RESOURCE_STA_VC_NEG_PENDING __BIT(1) 1639 1640 /* 1641 * Extended capability ID: 0x0003 1642 * Serial Number 1643 */ 1644 #define PCI_SERIAL_LOW 0x04 1645 #define PCI_SERIAL_HIGH 0x08 1646 1647 /* 1648 * Extended capability ID: 0x0004 1649 * Power Budgeting 1650 */ 1651 #define PCI_PWRBDGT_DSEL 0x04 /* Data Select */ 1652 #define PCI_PWRBDGT_DATA 0x08 /* Data */ 1653 #define PCI_PWRBDGT_DATA_BASEPWR __BITS(7, 0) /* Base Power */ 1654 #define PCI_PWRBDGT_DATA_SCALE __BITS(9, 8) /* Data Scale */ 1655 #define PCI_PWRBDGT_PM_SUBSTAT __BITS(12, 10) /* PM Sub State */ 1656 #define PCI_PWRBDGT_PM_STAT __BITS(14, 13) /* PM State */ 1657 #define PCI_PWRBDGT_TYPE __BITS(17, 15) /* Type */ 1658 #define PCI_PWRBDGT_PWRRAIL __BITS(20, 18) /* Power Rail */ 1659 #define PCI_PWRBDGT_CAP 0x0c /* Capability */ 1660 #define PCI_PWRBDGT_CAP_SYSALLOC __BIT(0) /* System Allocated */ 1661 1662 /* 1663 * Extended capability ID: 0x0005 1664 * Root Complex Link Declaration 1665 */ 1666 #define PCI_RCLINK_DCL_ESDESC 0x04 /* Element Self Description */ 1667 #define PCI_RCLINK_DCL_ESDESC_ELMTYPE __BITS(3, 0) /* Element Type */ 1668 #define PCI_RCLINK_DCL_ESDESC_NUMLINKENT __BITS(15, 8) /* Num of Link Entries*/ 1669 #define PCI_RCLINK_DCL_ESDESC_COMPID __BITS(23, 16) /* Component ID */ 1670 #define PCI_RCLINK_DCL_ESDESC_PORTNUM __BITS(31, 24) /* Port Number */ 1671 #define PCI_RCLINK_DCL_LINKENTS 0x10 /* Link Entries */ 1672 #define PCI_RCLINK_DCL_LINKDESC(x) /* Link Description */ \ 1673 (PCI_RCLINK_DCL_LINKENTS + ((x) * 16)) 1674 #define PCI_RCLINK_DCL_LINKDESC_LVALID __BIT(0) /* Link Valid */ 1675 #define PCI_RCLINK_DCL_LINKDESC_LTYPE __BIT(1) /* Link Type */ 1676 #define PCI_RCLINK_DCL_LINKDESC_ARCRBH __BIT(2) /* Associate RCRB Header */ 1677 #define PCI_RCLINK_DCL_LINKDESC_TCOMPID __BITS(23, 16) /* Target Component ID*/ 1678 #define PCI_RCLINK_DCL_LINKDESC_TPNUM __BITS(31, 24) /* Target Port Number */ 1679 #define PCI_RCLINK_DCL_LINKADDR_LT0_LO(x) /* LT0: Link Address Low */ \ 1680 (PCI_RCLINK_DCL_LINKENTS + ((x) * 16) + 0x08) 1681 #define PCI_RCLINK_DCL_LINKADDR_LT0_HI(x) /* LT0: Link Address High */ \ 1682 (PCI_RCLINK_DCL_LINKENTS + ((x) * 16) + 0x0c) 1683 #define PCI_RCLINK_DCL_LINKADDR_LT1_LO(x) /* LT1: Config Space (low) */ \ 1684 (PCI_RCLINK_DCL_LINKENTS + ((x) * 16) + 0x08) 1685 #define PCI_RCLINK_DCL_LINKADDR_LT1_N __BITS(2, 0) /* N */ 1686 #define PCI_RCLINK_DCL_LINKADDR_LT1_FUNC __BITS(14, 12) /* Function Number */ 1687 #define PCI_RCLINK_DCL_LINKADDR_LT1_DEV __BITS(19, 15) /* Device Number */ 1688 #define PCI_RCLINK_DCL_LINKADDR_LT1_BUS(N) __BITS(19 + (N), 20) /* Bus Number*/ 1689 #define PCI_RCLINK_DCL_LINKADDR_LT1_BAL(N) __BITS(31, 20 + (N)) /* BAddr(L) */ 1690 #define PCI_RCLINK_DCL_LINKADDR_LT1_HI(x) /* LT1: Config Space Base Addr(H) */\ 1691 (PCI_RCLINK_DCL_LINKENTS + ((x) * 16) + 0x0c) 1692 1693 /* 1694 * Extended capability ID: 0x0006 1695 * Root Complex Internal Link Control 1696 */ 1697 1698 /* 1699 * Extended capability ID: 0x0007 1700 * Root Complex Event Collector Association 1701 */ 1702 #define PCI_RCEC_ASSOC_ASSOCBITMAP 0x04 1703 1704 /* 1705 * Extended capability ID: 0x0008 1706 * Multi-Function Virtual Channel 1707 */ 1708 1709 /* 1710 * Extended capability ID: 0x0009 1711 * Virtual Channel if MFVC Ext Cap set 1712 */ 1713 1714 /* 1715 * Extended capability ID: 0x000a 1716 * RCRB Header 1717 */ 1718 1719 /* 1720 * Extended capability ID: 0x000b 1721 * Vendor Unique 1722 */ 1723 1724 /* 1725 * Extended capability ID: 0x000c 1726 * Configuration Access Correction 1727 */ 1728 1729 /* 1730 * Extended capability ID: 0x000d 1731 * Access Control Services 1732 */ 1733 #define PCI_ACS_CAP 0x04 /* Capability Register */ 1734 #define PCI_ACS_CAP_V __BIT(0) /* Source Validation */ 1735 #define PCI_ACS_CAP_B __BIT(1) /* Transaction Blocking */ 1736 #define PCI_ACS_CAP_R __BIT(2) /* P2P Request Redirect */ 1737 #define PCI_ACS_CAP_C __BIT(3) /* P2P Completion Redirect */ 1738 #define PCI_ACS_CAP_U __BIT(4) /* Upstream Forwarding */ 1739 #define PCI_ACS_CAP_E __BIT(5) /* Egress Control */ 1740 #define PCI_ACS_CAP_T __BIT(6) /* Direct Translated P2P */ 1741 #define PCI_ACS_CAP_ECVSIZE __BITS(15, 8) /* Egress Control Vector Size */ 1742 #define PCI_ACS_CTL 0x04 /* Control Register */ 1743 #define PCI_ACS_CTL_V __BIT(0 + 16) /* Source Validation Enable */ 1744 #define PCI_ACS_CTL_B __BIT(1 + 16) /* Transaction Blocking Enable */ 1745 #define PCI_ACS_CTL_R __BIT(2 + 16) /* P2P Request Redirect Enable */ 1746 #define PCI_ACS_CTL_C __BIT(3 + 16) /* P2P Completion Redirect Enable */ 1747 #define PCI_ACS_CTL_U __BIT(4 + 16) /* Upstream Forwarding Enable */ 1748 #define PCI_ACS_CTL_E __BIT(5 + 16) /* Egress Control Enable */ 1749 #define PCI_ACS_CTL_T __BIT(6 + 16) /* Direct Translated P2P Enable */ 1750 #define PCI_ACS_ECV 0x08 /* Egress Control Vector */ 1751 1752 /* 1753 * Extended capability ID: 0x000e 1754 * ARI 1755 */ 1756 #define PCI_ARI_CAP 0x04 /* Capability Register */ 1757 #define PCI_ARI_CAP_M __BIT(0) /* MFVC Function Groups Cap. */ 1758 #define PCI_ARI_CAP_A __BIT(1) /* ACS Function Groups Cap. */ 1759 #define PCI_ARI_CAP_NXTFN __BITS(15, 8) /* Next Function Number */ 1760 #define PCI_ARI_CTL 0x04 /* Control Register */ 1761 #define PCI_ARI_CTL_M __BIT(16) /* MFVC Function Groups Ena. */ 1762 #define PCI_ARI_CTL_A __BIT(17) /* ACS Function Groups Ena. */ 1763 #define PCI_ARI_CTL_FUNCGRP __BITS(22, 20) /* Function Group */ 1764 1765 /* 1766 * Extended capability ID: 0x000f 1767 * Address Translation Services 1768 */ 1769 #define PCI_ATS_CAP 0x04 /* Capability Register */ 1770 #define PCI_ATS_CAP_INVQDEPTH __BITS(4, 0) /* Invalidate Queue Depth */ 1771 #define PCI_ATS_CAP_PALIGNREQ __BIT(5) /* Page Aligned Request */ 1772 #define PCI_ATS_CAP_GLOBALINVL __BIT(6) /* Global Invalidate Support */ 1773 #define PCI_ATS_CTL 0x04 /* Control Register */ 1774 #define PCI_ATS_CTL_STU __BITS(20, 16) /* Smallest Translation Unit */ 1775 #define PCI_ATS_CTL_EN __BIT(31) /* Enable */ 1776 1777 /* 1778 * Extended capability ID: 0x0010 1779 * SR-IOV 1780 */ 1781 #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ 1782 #define PCI_SRIOV_CAP_VF_MIGRATION __BIT(0) 1783 #define PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED __BIT(1) 1784 #define PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N __BITS(31, 21) 1785 #define PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N_S 21 1786 #define PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N_M 0x7ff 1787 #define PCI_SRIOV_CTL 0x08 /* SR-IOV Control (16bit) */ 1788 #define PCI_SRIOV_CTL_VF_ENABLE __BIT(0) 1789 #define PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT __BIT(1) 1790 #define PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE __BIT(2) 1791 #define PCI_SRIOV_CTL_VF_MSE __BIT(3) 1792 #define PCI_SRIOV_CTL_ARI_CAP_HIER __BIT(4) 1793 #define PCI_SRIOV_STA 0x0a /* SR-IOV Status (16bit) */ 1794 #define PCI_SRIOV_STA_VF_MIGRATION __BIT(0) 1795 #define PCI_SRIOV_INITIAL_VFS 0x0c /* InitialVFs (16bit) */ 1796 #define PCI_SRIOV_TOTAL_VFS 0x0e /* TotalVFs (16bit) */ 1797 #define PCI_SRIOV_NUM_VFS 0x10 /* NumVFs (16bit) */ 1798 #define PCI_SRIOV_FUNC_DEP_LINK 0x12 /* Function Dependency Link (16bit) */ 1799 #define PCI_SRIOV_VF_OFF 0x14 /* First VF Offset (16bit) */ 1800 #define PCI_SRIOV_VF_STRIDE 0x16 /* VF Stride (16bit) */ 1801 #define PCI_SRIOV_VF_DID 0x1a /* VF Device ID (16bit) */ 1802 #define PCI_SRIOV_PAGE_CAP 0x1c /* Supported Page Sizes */ 1803 #define PCI_SRIOV_PAGE_SIZE 0x20 /* System Page Size */ 1804 #define PCI_SRIOV_BASE_PAGE_SHIFT 12 1805 #define PCI_SRIOV_BARS 0x24 /* VF BAR0-5 */ 1806 #define PCI_SRIOV_BAR(x) (PCI_SRIOV_BARS + ((x) * 4)) 1807 #define PCI_SRIOV_VF_MIG_STA_AR 0x3c /* VF Migration State Array Offset */ 1808 #define PCI_SRIOV_VF_MIG_STA_OFFSET __BITS(31, 3) 1809 #define PCI_SRIOV_VF_MIG_STA_OFFSET_S 3 1810 #define PCI_SRIOV_VF_MIG_STA_OFFSET_M 0x1fffffff 1811 #define PCI_SRIOV_VF_MIG_STA_BIR __BITS(2, 0) 1812 #define PCI_SRIOV_VF_MIG_STA_BIR_S 0 1813 #define PCI_SRIOV_VF_MIG_STA_BIR_M 0x7 1814 1815 /* 1816 * Extended capability ID: 0x0011 1817 * Multiple Root IO Virtualization 1818 */ 1819 1820 /* 1821 * Extended capability ID: 0x0012 1822 * Multicast 1823 */ 1824 #define PCI_MCAST_CAP 0x04 /* Capability Register */ 1825 #define PCI_MCAST_CAP_MAXGRP __BITS(5, 0) /* Max Group */ 1826 #define PCI_MCAST_CAP_WINSIZEREQ __BITS(13, 8) /* Window Size Requested */ 1827 #define PCI_MCAST_CAP_ECRCREGEN __BIT(15) /* ECRC Regen. Supported */ 1828 #define PCI_MCAST_CTL 0x04 /* Control Register */ 1829 #define PCI_MCAST_CTL_NUMGRP __BITS(5+16, 16) /* Num Group */ 1830 #define PCI_MCAST_CTL_ENA __BIT(15+16) /* Enable */ 1831 #define PCI_MCAST_BARL 0x08 /* Base Address Register (low) */ 1832 #define PCI_MCAST_BARL_INDPOS __BITS(5, 0) /* Index Position */ 1833 #define PCI_MCAST_BARL_ADDR __BITS(31, 12) /* Base Address Register(low)*/ 1834 #define PCI_MCAST_BARH 0x0c /* Base Address Register (high) */ 1835 #define PCI_MCAST_RECVL 0x10 /* Receive Register (low) */ 1836 #define PCI_MCAST_RECVH 0x14 /* Receive Register (high) */ 1837 #define PCI_MCAST_BLOCKALLL 0x18 /* Block All Register (low) */ 1838 #define PCI_MCAST_BLOCKALLH 0x1c /* Block All Register (high) */ 1839 #define PCI_MCAST_BLOCKUNTRNSL 0x20 /* Block Untranslated Register (low) */ 1840 #define PCI_MCAST_BLOCKUNTRNSH 0x24 /* Block Untranslated Register (high) */ 1841 #define PCI_MCAST_OVERLAYL 0x28 /* Overlay BAR (low) */ 1842 #define PCI_MCAST_OVERLAYL_SIZE __BITS(5, 0) /* Overlay Size */ 1843 #define PCI_MCAST_OVERLAYL_ADDR __BITS(31, 6) /* Overlay BAR (low) */ 1844 #define PCI_MCAST_OVERLAYH 0x2c /* Overlay BAR (high) */ 1845 1846 /* 1847 * Extended capability ID: 0x0013 1848 * Page Request 1849 */ 1850 #define PCI_PAGE_REQ_CTL 0x04 /* Control Register */ 1851 #define PCI_PAGE_REQ_CTL_E __BIT(0) /* Enalbe */ 1852 #define PCI_PAGE_REQ_CTL_R __BIT(1) /* Reset */ 1853 #define PCI_PAGE_REQ_STA 0x04 /* Status Register */ 1854 #define PCI_PAGE_REQ_STA_RF __BIT(0+16) /* Response Failure */ 1855 #define PCI_PAGE_REQ_STA_UPRGI __BIT(1+16) /* Unexpected Page Req Grp Idx */ 1856 #define PCI_PAGE_REQ_STA_S __BIT(8+16) /* Stopped */ 1857 #define PCI_PAGE_REQ_STA_PASIDR __BIT(15+16) /* PRG Response PASID Required */ 1858 #define PCI_PAGE_REQ_OUTSTCAPA 0x08 /* Outstanding Page Request Capacity */ 1859 #define PCI_PAGE_REQ_OUTSTALLOC 0x0c /* Outstanding Page Request Allocation */ 1860 1861 /* 1862 * Extended capability ID: 0x0014 1863 * Enhanced Allocation 1864 */ 1865 1866 /* 1867 * Extended capability ID: 0x0015 1868 * Resizable BAR 1869 */ 1870 #define PCI_RESIZBAR_CAP0 0x04 /* Capability Register(0) */ 1871 #define PCI_RESIZBAR_CAP(x) (PCI_RESIZBAR_CAP0 + ((x) * 8)) 1872 #define PCI_RESIZBAR_CAP_SIZEMASK __BITS(23, 4) /* BAR size bitmask */ 1873 #define PCI_RESIZBAR_CTL0 0x08 /* Control Register(0) */ 1874 #define PCI_RESIZBAR_CTL(x) (PCI_RESIZBAR_CTL0 + ((x) * 8)) 1875 #define PCI_RESIZBAR_CTL_BARIDX __BITS(2, 0) 1876 #define PCI_RESIZBAR_CTL_NUMBAR __BITS(7, 5) 1877 #define PCI_RESIZBAR_CTL_BARSIZ __BITS(12, 8) 1878 1879 /* 1880 * Extended capability ID: 0x0016 1881 * Dynamic Power Allocation 1882 */ 1883 #define PCI_DPA_CAP 0x04 /* Capability */ 1884 #define PCI_DPA_CAP_SUBSTMAX __BITS(4, 0) /* Substate Max */ 1885 #define PCI_DPA_CAP_TLUINT __BITS(9, 8) /* Transition Latency Unit */ 1886 #define PCI_DPA_CAP_PAS __BITS(13, 12) /* Power Allocation Scale */ 1887 #define PCI_DPA_CAP_XLCY0 __BITS(23, 16) /* Transition Latency Value0 */ 1888 #define PCI_DPA_CAP_XLCY1 __BITS(31, 24) /* Transition Latency Value1 */ 1889 #define PCI_DPA_LATIND 0x08 /* Latency Indicator */ 1890 #define PCI_DPA_CS 0x0c /* Control and Status */ 1891 #define PCI_DPA_CS_SUBSTSTAT __BITS(4, 0) /* Substate Status */ 1892 #define PCI_DPA_CS_SUBSTCTLEN __BIT(8) /* Substate Control Enabled */ 1893 #define PCI_DPA_CS_SUBSTCTL __BITS(20, 16) /* Substate Control */ 1894 #define PCI_DPA_PWRALLOC 0x10 /* Start address of Power Allocation Array */ 1895 #define PCI_DPA_SUBST_MAXNUM 32 /* Max number of Substates (0 to 31) */ 1896 1897 /* 1898 * Extended capability ID: 0x0017 1899 * TPH Requester 1900 */ 1901 #define PCI_TPH_REQ_CAP 0x04 /* TPH Requester Capability */ 1902 #define PCI_TPH_REQ_CAP_NOST __BIT(0) /* No ST Mode Supported */ 1903 #define PCI_TPH_REQ_CAP_INTVEC __BIT(1) /* Intr Vec Mode Supported */ 1904 #define PCI_TPH_REQ_CAP_DEVSPEC __BIT(2) /* Device Specific Mode Supported */ 1905 #define PCI_TPH_REQ_CAP_XTPHREQ __BIT(8) /* Extend TPH Reqester Supported */ 1906 #define PCI_TPH_REQ_CAP_STTBLLOC __BITS(10, 9) /* ST Table Location */ 1907 #define PCI_TPH_REQ_STTBLLOC_NONE 0 /* not present */ 1908 #define PCI_TPH_REQ_STTBLLOC_TPHREQ 1 /* in the TPHREQ cap */ 1909 #define PCI_TPH_REQ_STTBLLOC_MSIX 2 /* in the MSI-X table */ 1910 #define PCI_TPH_REQ_CAP_STTBLSIZ __BITS(26, 16) /* ST Table Size */ 1911 #define PCI_TPH_REQ_CTL 0x08 /* TPH Requester Control */ 1912 #define PCI_TPH_REQ_CTL_STSEL __BITS(2, 0) /* ST Mode Select */ 1913 #define PCI_TPH_REQ_CTL_STSEL_NO 0 /* No ST Mode */ 1914 #define PCI_TPH_REQ_CTL_STSEL_IV 1 /* Interrupt Vector Mode */ 1915 #define PCI_TPH_REQ_CTL_STSEL_DS 2 /* Device Specific Mode */ 1916 #define PCI_TPH_REQ_CTL_TPHREQEN __BITS(9, 8) /* TPH Requester Enable */ 1917 #define PCI_TPH_REQ_CTL_TPHREQEN_NO 0 /* Not permitted */ 1918 #define PCI_TPH_REQ_CTL_TPHREQEN_TPH 1 /* TPH and no extended TPH */ 1919 #define PCI_TPH_REQ_CTL_TPHREQEN_RSVD 2 /* Reserved */ 1920 #define PCI_TPH_REQ_CTL_TPHREQEN_ETPH 3 /* TPH and Extended TPH */ 1921 #define PCI_TPH_REQ_STTBL 0x0c /* TPH ST Table */ 1922 1923 /* 1924 * Extended capability ID: 0x0018 1925 * Latency Tolerance Reporting 1926 */ 1927 #define PCI_LTR_MAXSNOOPLAT 0x04 /* Max Snoop Latency */ 1928 #define PCI_LTR_MAXSNOOPLAT_VAL __BITS(9, 0) /* Max Snoop LatencyValue */ 1929 #define PCI_LTR_MAXSNOOPLAT_SCALE __BITS(12, 10) /* Max Snoop LatencyScale */ 1930 #define PCI_LTR_MAXNOSNOOPLAT 0x04 /* Max No-Snoop Latency */ 1931 #define PCI_LTR_MAXNOSNOOPLAT_VAL __BITS(25, 16) /* Max No-Snoop LatencyValue*/ 1932 #define PCI_LTR_MAXNOSNOOPLAT_SCALE __BITS(28, 26) /*Max NoSnoop LatencyScale*/ 1933 #define PCI_LTR_SCALETONS(x) (1 << ((x) * 5)) 1934 1935 /* 1936 * Extended capability ID: 0x0019 1937 * Seconday PCI Express Extended Capability 1938 */ 1939 #define PCI_SECPCIE_LCTL3 0x04 /* Link Control 3 */ 1940 #define PCI_SECPCIE_LCTL3_PERFEQ __BIT(0) /* Perform Equalization */ 1941 #define PCI_SECPCIE_LCTL3_LINKEQREQ_IE __BIT(1) /* Link Eq. Req. Int. Ena. */ 1942 #define PCI_SECPCIE_LCTL3_ELSKPOSGENV __BITS(15, 9) /* En. Lo. SKP OS Gen V*/ 1943 #define PCI_SECPCIE_LANEERR_STA 0x08 /* Lane Error Status */ 1944 #define PCI_SECPCIE_EQCTLS 0x0c /* Equalization Control [0-maxlane] */ 1945 #define PCI_SECPCIE_EQCTL(x) (PCI_SECPCIE_EQCTLS + ((x) * 2)) 1946 #define PCI_SECPCIE_EQCTL_DP_XMIT_PRESET __BITS(3, 0) /* DwnStPort Xmit Pres */ 1947 #define PCI_SECPCIE_EQCTL_DP_RCV_HINT __BITS(6, 4) /* DwnStPort Rcv PreHnt */ 1948 #define PCI_SECPCIE_EQCTL_UP_XMIT_PRESET __BITS(11, 8) /* UpStPort Xmit Pres */ 1949 #define PCI_SECPCIE_EQCTL_UP_RCV_HINT __BITS(14, 12) /* UpStPort Rcv PreHnt*/ 1950 1951 /* 1952 * Extended capability ID: 0x001a 1953 * Protocol Multiplexing 1954 */ 1955 1956 /* 1957 * Extended capability ID: 0x001b 1958 * Process Address Space ID 1959 */ 1960 #define PCI_PASID_CAP 0x04 /* Capability Register */ 1961 #define PCI_PASID_CAP_XPERM __BIT(1) /* Execute Permission Supported */ 1962 #define PCI_PASID_CAP_PRIVMODE __BIT(2) /* Privileged Mode Supported */ 1963 #define PCI_PASID_CAP_MAXPASIDW __BITS(12, 8) /* Max PASID Width */ 1964 #define PCI_PASID_CTL 0x04 /* Control Register */ 1965 #define PCI_PASID_CTL_PASID_EN __BIT(0+16) /* PASID Enable */ 1966 #define PCI_PASID_CTL_XPERM_EN __BIT(1+16) /* Execute Permission Enable */ 1967 #define PCI_PASID_CTL_PRIVMODE_EN __BIT(2+16) /* Privileged Mode Enable */ 1968 1969 /* 1970 * Extended capability ID: 0x001c 1971 * LN Requester 1972 */ 1973 #define PCI_LNR_CAP 0x04 /* Capability Register */ 1974 #define PCI_LNR_CAP_64 __BIT(0) /* LNR-64 Supported */ 1975 #define PCI_LNR_CAP_128 __BIT(1) /* LNR-128 Supported */ 1976 #define PCI_LNR_CAP_REGISTMAX __BITS(12, 8) /* LNR Registration MAX */ 1977 #define PCI_LNR_CTL 0x04 /* Control Register */ 1978 #define PCI_LNR_CTL_EN __BIT(0+16) /* LNR Enable */ 1979 #define PCI_LNR_CTL_CLS __BIT(1+16) /* LNR CLS */ 1980 #define PCI_LNR_CTL_REGISTLIM __BITS(28, 24) /* LNR Registration Limit */ 1981 1982 /* 1983 * Extended capability ID: 0x001d 1984 * Downstream Port Containment 1985 */ 1986 1987 #define PCI_DPC_CCR 0x04 /* Capability and Control Register */ 1988 #define PCI_DPCCAP_IMSGN __BITS(4, 0) /* Interrupt Message Number */ 1989 #define PCI_DPCCAP_RPEXT __BIT(5) /* RP Extensions for DPC */ 1990 #define PCI_DPCCAP_POISONTLPEB __BIT(6) /* Poisoned TLP Egress Blckng.*/ 1991 #define PCI_DPCCAP_SWTRIG __BIT(7) /* DPC Software Triggering */ 1992 #define PCI_DPCCAP_RPPIOLOGSZ __BITS(11, 8) /* RP PIO Log Size */ 1993 #define PCI_DPCCAP_DLACTECORS __BIT(12) /* DL_Active ERR_COR Signaling*/ 1994 #define PCI_DPCCTL_TIRGEN __BITS(17, 16) /* DPC Trigger Enable */ 1995 #define PCI_DPCCTL_COMPCTL __BIT(18) /* DPC Completion Control */ 1996 #define PCI_DPCCTL_IE __BIT(19) /* DPC Interrupt Enable */ 1997 #define PCI_DPCCTL_ERRCOREN __BIT(20) /* DPC ERR_COR enable */ 1998 #define PCI_DPCCTL_POISONTLPEB __BIT(21) /* Poisoned TLP Egress Blckng.*/ 1999 #define PCI_DPCCTL_SWTRIG __BIT(22) /* DPC Software Trigger */ 2000 #define PCI_DPCCTL_DLACTECOR __BIT(23) /* DL_Active ERR_COR Enable */ 2001 2002 #define PCI_DPC_STATESID 0x08 /* Status and Error Source ID Register */ 2003 #define PCI_DPCSTAT_TSTAT __BIT(0) /* DPC Trigger Staus */ 2004 #define PCI_DPCSTAT_TREASON __BITS(2, 1) /* DPC Trigger Reason */ 2005 #define PCI_DPCSTAT_ISTAT __BIT(3) /* DPC Interrupt Status */ 2006 #define PCI_DPCSTAT_RPBUSY __BIT(4) /* DPC RP Busy */ 2007 #define PCI_DPCSTAT_TRIGREXT __BITS(6, 5) /* DPC Trigger Reason Extntn. */ 2008 #define PCI_DPCSTAT_RPPIOFEP __BITS(12, 8) /* RP PIO First Error Pointer */ 2009 #define PCI_DPCESID __BITS(31, 16) /* DPC Error Source ID */ 2010 2011 #define PCI_DPC_RPPIO_STAT 0x0c /* RP PIO Status Register */ 2012 #define PCI_DPC_RPPIO_CFGUR_CPL __BIT(0) /* CfgReq received UR Complt. */ 2013 #define PCI_DPC_RPPIO_CFGCA_CPL __BIT(1) /* CfgReq received CA Complt. */ 2014 #define PCI_DPC_RPPIO_CFG_CTO __BIT(2) /* CfgReq Completion Timeout */ 2015 #define PCI_DPC_RPPIO_IOUR_CPL __BIT(8) /* I/OReq received UR Complt. */ 2016 #define PCI_DPC_RPPIO_IOCA_CPL __BIT(9) /* I/OReq received CA Complt. */ 2017 #define PCI_DPC_RPPIO_IO_CTO __BIT(10) /* I/OReq Completion Timeout */ 2018 #define PCI_DPC_RPPIO_MEMUR_CPL __BIT(16) /* MemReq received UR Complt. */ 2019 #define PCI_DPC_RPPIO_MEMCA_CPL __BIT(17) /* MemReq received CA Complt. */ 2020 #define PCI_DPC_RPPIO_MEM_CTO __BIT(18) /* MemReq Completion Timeout */ 2021 2022 #define PCI_DPC_RPPIO_MASK 0x10 /* RP PIO Mask Register */ 2023 /* Bits are the same as RP PIO Status Register */ 2024 #define PCI_DPC_RPPIO_SEVE 0x14 /* RP PIO Severity Register */ 2025 /* Same */ 2026 #define PCI_DPC_RPPIO_SYSERR 0x18 /* RP PIO SysError Register */ 2027 /* Same */ 2028 #define PCI_DPC_RPPIO_EXCPT 0x1c /* RP PIO Exception Register */ 2029 /* Same */ 2030 #define PCI_DPC_RPPIO_HLOG 0x20 /* RP PIO Header Log Register */ 2031 #define PCI_DPC_RPPIO_IMPSLOG 0x30 /* RP PIO ImpSpec Log Register */ 2032 #define PCI_DPC_RPPIO_TLPPLOG 0x34 /* RP PIO TPL Prefix Log Register */ 2033 2034 /* 2035 * Extended capability ID: 0x001e 2036 * L1 PM Substates 2037 */ 2038 #define PCI_L1PM_CAP 0x04 /* Capabilities Register */ 2039 #define PCI_L1PM_CAP_PCIPM12 __BIT(0) /* PCI-PM L1.2 Supported */ 2040 #define PCI_L1PM_CAP_PCIPM11 __BIT(1) /* PCI-PM L1.1 Supported */ 2041 #define PCI_L1PM_CAP_ASPM12 __BIT(2) /* ASPM L1.2 Supported */ 2042 #define PCI_L1PM_CAP_ASPM11 __BIT(3) /* ASPM L1.1 Supported */ 2043 #define PCI_L1PM_CAP_L1PM __BIT(4) /* L1 PM Substates Supported */ 2044 #define PCI_L1PM_CAP_LA __BIT(5) /* Link Activation Supported */ 2045 #define PCI_L1PM_CAP_PCMRT __BITS(15, 8) /*Port Common Mode Restore Time*/ 2046 #define PCI_L1PM_CAP_PTPOSCALE __BITS(17, 16) /* Port T_POWER_ON Scale */ 2047 #define PCI_L1PM_CAP_PTPOVAL __BITS(23, 19) /* Port T_POWER_ON Value */ 2048 #define PCI_L1PM_CTL1 0x08 /* Control Register 1 */ 2049 #define PCI_L1PM_CTL1_PCIPM12_EN __BIT(0) /* PCI-PM L1.2 Enable */ 2050 #define PCI_L1PM_CTL1_PCIPM11_EN __BIT(1) /* PCI-PM L1.1 Enable */ 2051 #define PCI_L1PM_CTL1_ASPM12_EN __BIT(2) /* ASPM L1.2 Enable */ 2052 #define PCI_L1PM_CTL1_ASPM11_EN __BIT(3) /* ASPM L1.1 Enable */ 2053 #define PCI_L1PM_CTL1_LAIE __BIT(4) /* Link Activation Int. En. */ 2054 #define PCI_L1PM_CTL1_LA __BIT(5) /* Link Activation Control */ 2055 #define PCI_L1PM_CTL1_CMRT __BITS(15, 8) /* Common Mode Restore Time */ 2056 #define PCI_L1PM_CTL1_LTRTHVAL __BITS(25, 16) /* LTR L1.2 THRESHOLD Value */ 2057 #define PCI_L1PM_CTL1_LTRTHSCALE __BITS(31, 29) /* LTR L1.2 THRESHOLD Scale */ 2058 #define PCI_L1PM_CTL2 0x0c /* Control Register 2 */ 2059 #define PCI_L1PM_CTL2_TPOSCALE __BITS(1, 0) /* T_POWER_ON Scale */ 2060 #define PCI_L1PM_CTL2_TPOVAL __BITS(7, 3) /* T_POWER_ON Value */ 2061 #define PCI_L1PM_STAT 0x10 /* Status Register */ 2062 #define PCI_L1PM_STAT_LA __BIT(0) /* Link Activation Status */ 2063 2064 /* 2065 * Extended capability ID: 0x001f 2066 * Precision Time Management 2067 */ 2068 #define PCI_PTM_CAP 0x04 /* Capabilities Register */ 2069 #define PCI_PTM_CAP_REQ __BIT(0) /* PTM Requester Capable */ 2070 #define PCI_PTM_CAP_RESP __BIT(1) /* PTM Responder Capable */ 2071 #define PCI_PTM_CAP_ROOT __BIT(2) /* PTM Root Capable */ 2072 #define PCI_PTM_CAP_LCLCLKGRNL __BITS(15, 8) /* Local Clock Granularity */ 2073 #define PCI_PTM_CTL 0x08 /* Control Register */ 2074 #define PCI_PTM_CTL_EN __BIT(0) /* PTM Enable */ 2075 #define PCI_PTM_CTL_ROOTSEL __BIT(1) /* Root Select */ 2076 #define PCI_PTM_CTL_EFCTGRNL __BITS(15, 8) /* Effective Granularity */ 2077 2078 /* 2079 * Extended capability ID: 0x0020 2080 * M-PCIe 2081 */ 2082 2083 /* 2084 * Extended capability ID: 0x0021 2085 * Function Reading Status Queueing 2086 */ 2087 2088 /* 2089 * Extended capability ID: 0x0022 2090 * Readiness Time Reporting 2091 */ 2092 2093 /* 2094 * Extended capability ID: 0x0023 2095 * Designated Vendor-Specific 2096 */ 2097 2098 /* 2099 * Extended capability ID: 0x0024 2100 * VF Resizable BAR 2101 */ 2102 2103 /* 2104 * Extended capability ID: 0x0028 2105 * Hierarchy ID 2106 */ 2107 2108 /* 2109 * Extended capability ID: 0x0029 2110 * Native PCIe Enclosure Management 2111 */ 2112 2113 #endif /* _DEV_PCI_PCIREG_H_ */ 2114