1 /* $NetBSD: pcireg.h,v 1.2 1994/10/27 04:21:41 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Charles Hannum. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Charles Hannum. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Standardized PCI configuration information 34 * 35 * XXX 36 * This is not complete. 37 */ 38 39 /* 40 * Device identification register; contains a vendor ID and a device ID. 41 * We have little need to distinguish the two parts. 42 */ 43 #define PCI_ID_REG 0x00 44 45 /* 46 * Command and status register. 47 */ 48 #define PCI_COMMAND_STATUS_REG 0x04 49 50 #define PCI_COMMAND_IO_ENABLE 0x00000001 51 #define PCI_COMMAND_MEM_ENABLE 0x00000002 52 #define PCI_COMMAND_MASTER_ENABLE 0x00000004 53 #define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 54 #define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 55 #define PCI_COMMAND_PALETTE_ENABLE 0x00000020 56 #define PCI_COMMAND_PARITY_ENABLE 0x00000040 57 #define PCI_COMMAND_STEPPING_ENABLE 0x00000080 58 #define PCI_COMMAND_SERR_ENABLE 0x00000100 59 #define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 60 61 #define PCI_STATUS_BACKTOBACK_OKAY 0x00800000 62 #define PCI_STATUS_PARITY_ERROR 0x01000000 63 #define PCI_STATUS_DEVSEL_FAST 0x00000000 64 #define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 65 #define PCI_STATUS_DEVSEL_SLOW 0x04000000 66 #define PCI_STATUS_DEVSEL_MASK 0x06000000 67 #define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 68 #define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 69 #define PCI_STATUS_MASTER_ABORT 0x20000000 70 #define PCI_STATUS_SPECIAL_ERROR 0x40000000 71 #define PCI_STATUS_PARITY_DETECT 0x80000000 72 73 /* 74 * Class register; defines basic type of device. 75 */ 76 #define PCI_CLASS_REG 0x08 77 78 #define PCI_CLASS_MASK 0xff000000 79 #define PCI_SUBCLASS_MASK 0x00ff0000 80 81 /* base classes */ 82 #define PCI_CLASS_PREHISTORIC 0x00000000 83 #define PCI_CLASS_MASS_STORAGE 0x01000000 84 #define PCI_CLASS_NETWORK 0x02000000 85 #define PCI_CLASS_DISPLAY 0x03000000 86 #define PCI_CLASS_MULTIMEDIA 0x04000000 87 #define PCI_CLASS_MEMORY 0x05000000 88 #define PCI_CLASS_BRIDGE 0x06000000 89 #define PCI_CLASS_UNDEFINED 0xff000000 90 91 /* 0x00 prehistoric subclasses */ 92 #define PCI_SUBCLASS_PREHISTORIC_MISC 0x00000000 93 #define PCI_SUBCLASS_PREHISTORIC_VGA 0x00010000 94 95 /* 0x01 mass storage subclasses */ 96 #define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00000000 97 #define PCI_SUBCLASS_MASS_STORAGE_IDE 0x00010000 98 #define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x00020000 99 #define PCI_SUBCLASS_MASS_STORAGE_IPI 0x00030000 100 #define PCI_SUBCLASS_MASS_STORAGE_MISC 0x00800000 101 102 /* 0x02 network subclasses */ 103 #define PCI_SUBCLASS_NETWORK_ETHERNET 0x00000000 104 #define PCI_SUBCLASS_NETWORK_TOKENRING 0x00010000 105 #define PCI_SUBCLASS_NETWORK_FDDI 0x00020000 106 #define PCI_SUBCLASS_NETWORK_MISC 0x00800000 107 108 /* 0x03 display subclasses */ 109 #define PCI_SUBCLASS_DISPLAY_VGA 0x00000000 110 #define PCI_SUBCLASS_DISPLAY_XGA 0x00010000 111 #define PCI_SUBCLASS_DISPLAY_MISC 0x00800000 112 113 /* 0x04 multimedia subclasses */ 114 #define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00000000 115 #define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x00010000 116 #define PCI_SUBCLASS_MULTIMEDIA_MISC 0x00800000 117 118 /* 0x05 memory subclasses */ 119 #define PCI_SUBCLASS_MEMORY_RAM 0x00000000 120 #define PCI_SUBCLASS_MEMORY_FLASH 0x00010000 121 #define PCI_SUBCLASS_MEMORY_MISC 0x00800000 122 123 /* 0x06 bridge subclasses */ 124 #define PCI_SUBCLASS_BRIDGE_HOST 0x00000000 125 #define PCI_SUBCLASS_BRIDGE_ISA 0x00010000 126 #define PCI_SUBCLASS_BRIDGE_EISA 0x00020000 127 #define PCI_SUBCLASS_BRIDGE_MC 0x00030000 128 #define PCI_SUBCLASS_BRIDGE_PCI 0x00040000 129 #define PCI_SUBCLASS_BRIDGE_PCMCIA 0x00050000 130 #define PCI_SUBCLASS_BRIDGE_MISC 0x00800000 131 132 /* 133 * Mapping registers 134 */ 135 #define PCI_MAP_REG_START 0x10 136 #define PCI_MAP_REG_END 0x28 137 138 #define PCI_MAP_MEMORY 0x00000000 139 #define PCI_MAP_IO 0x00000001 140 141 #define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000 142 #define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002 143 #define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004 144 #define PCI_MAP_MEMORY_TYPE_MASK 0x00000006 145 #define PCI_MAP_MEMORY_CACHABLE 0x00000008 146 #define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0 147 148 /* 149 * Interrupt configuration register 150 */ 151 #define PCI_INTERRUPT_REG 0x3c 152 153 #define PCI_INTERRUPT_PIN_MASK 0x0000ff00 154 #define PCI_INTERRUPT_PIN_EXTRACT(x) ((((x) & PCI_INTERRUPT_PIN_MASK) >> 8) & 0xff) 155 #define PCI_INTERRUPT_PIN_NONE 0x00 156 #define PCI_INTERRUPT_PIN_A 0x01 157 #define PCI_INTERRUPT_PIN_B 0x02 158 #define PCI_INTERRUPT_PIN_C 0x03 159 #define PCI_INTERRUPT_PIN_D 0x04 160 161 #define PCI_INTERRUPT_LINE_MASK 0x000000ff 162 #define PCI_INTERRUPT_LINE_EXTRACT(x) ((((x) & PCI_INTERRUPT_LINE_MASK) >> 0) & 0xff) 163 #define PCI_INTERRUPT_LINE_INSERT(x,v) (((x) & ~PCI_INTERRUPT_LINE_MASK) | ((v) << 0)) 164