1 /* $NetBSD: pcireg.h,v 1.73 2011/08/17 00:59:47 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1999, 2000 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _DEV_PCI_PCIREG_H_ 35 #define _DEV_PCI_PCIREG_H_ 36 37 /* 38 * Standardized PCI configuration information 39 * 40 * XXX This is not complete. 41 */ 42 43 /* 44 * Size of each function's configuration space. 45 */ 46 47 #define PCI_CONF_SIZE 0x100 48 #define PCI_EXTCONF_SIZE 0x1000 49 50 /* 51 * Device identification register; contains a vendor ID and a device ID. 52 */ 53 #define PCI_ID_REG 0x00 54 55 typedef u_int16_t pci_vendor_id_t; 56 typedef u_int16_t pci_product_id_t; 57 58 #define PCI_VENDOR_SHIFT 0 59 #define PCI_VENDOR_MASK 0xffff 60 #define PCI_VENDOR(id) \ 61 (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK) 62 63 #define PCI_PRODUCT_SHIFT 16 64 #define PCI_PRODUCT_MASK 0xffff 65 #define PCI_PRODUCT(id) \ 66 (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) 67 68 #define PCI_ID_CODE(vid,pid) \ 69 ((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) | \ 70 (((pid) & PCI_PRODUCT_MASK) << PCI_PRODUCT_SHIFT)) \ 71 72 /* 73 * Command and status register. 74 */ 75 #define PCI_COMMAND_STATUS_REG 0x04 76 #define PCI_COMMAND_SHIFT 0 77 #define PCI_COMMAND_MASK 0xffff 78 #define PCI_STATUS_SHIFT 16 79 #define PCI_STATUS_MASK 0xffff 80 81 #define PCI_COMMAND_STATUS_CODE(cmd,stat) \ 82 ((((cmd) & PCI_COMMAND_MASK) << PCI_COMMAND_SHIFT) | \ 83 (((stat) & PCI_STATUS_MASK) << PCI_STATUS_SHIFT)) \ 84 85 #define PCI_COMMAND_IO_ENABLE 0x00000001 86 #define PCI_COMMAND_MEM_ENABLE 0x00000002 87 #define PCI_COMMAND_MASTER_ENABLE 0x00000004 88 #define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 89 #define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 90 #define PCI_COMMAND_PALETTE_ENABLE 0x00000020 91 #define PCI_COMMAND_PARITY_ENABLE 0x00000040 92 #define PCI_COMMAND_STEPPING_ENABLE 0x00000080 93 #define PCI_COMMAND_SERR_ENABLE 0x00000100 94 #define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 95 #define PCI_COMMAND_INTERRUPT_DISABLE 0x00000400 96 97 #define PCI_STATUS_INT_STATUS 0x00080000 98 #define PCI_STATUS_CAPLIST_SUPPORT 0x00100000 99 #define PCI_STATUS_66MHZ_SUPPORT 0x00200000 100 #define PCI_STATUS_UDF_SUPPORT 0x00400000 101 #define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000 102 #define PCI_STATUS_PARITY_ERROR 0x01000000 103 #define PCI_STATUS_DEVSEL_FAST 0x00000000 104 #define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 105 #define PCI_STATUS_DEVSEL_SLOW 0x04000000 106 #define PCI_STATUS_DEVSEL_MASK 0x06000000 107 #define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 108 #define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 109 #define PCI_STATUS_MASTER_ABORT 0x20000000 110 #define PCI_STATUS_SPECIAL_ERROR 0x40000000 111 #define PCI_STATUS_PARITY_DETECT 0x80000000 112 113 /* 114 * PCI Class and Revision Register; defines type and revision of device. 115 */ 116 #define PCI_CLASS_REG 0x08 117 118 typedef u_int8_t pci_class_t; 119 typedef u_int8_t pci_subclass_t; 120 typedef u_int8_t pci_interface_t; 121 typedef u_int8_t pci_revision_t; 122 123 #define PCI_CLASS_SHIFT 24 124 #define PCI_CLASS_MASK 0xff 125 #define PCI_CLASS(cr) \ 126 (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) 127 128 #define PCI_SUBCLASS_SHIFT 16 129 #define PCI_SUBCLASS_MASK 0xff 130 #define PCI_SUBCLASS(cr) \ 131 (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) 132 133 #define PCI_INTERFACE_SHIFT 8 134 #define PCI_INTERFACE_MASK 0xff 135 #define PCI_INTERFACE(cr) \ 136 (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) 137 138 #define PCI_REVISION_SHIFT 0 139 #define PCI_REVISION_MASK 0xff 140 #define PCI_REVISION(cr) \ 141 (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) 142 143 #define PCI_CLASS_CODE(mainclass, subclass, interface) \ 144 ((((mainclass) & PCI_CLASS_MASK) << PCI_CLASS_SHIFT) | \ 145 (((subclass) & PCI_SUBCLASS_MASK) << PCI_SUBCLASS_SHIFT) | \ 146 (((interface) & PCI_INTERFACE_MASK) << PCI_INTERFACE_SHIFT)) 147 148 /* base classes */ 149 #define PCI_CLASS_PREHISTORIC 0x00 150 #define PCI_CLASS_MASS_STORAGE 0x01 151 #define PCI_CLASS_NETWORK 0x02 152 #define PCI_CLASS_DISPLAY 0x03 153 #define PCI_CLASS_MULTIMEDIA 0x04 154 #define PCI_CLASS_MEMORY 0x05 155 #define PCI_CLASS_BRIDGE 0x06 156 #define PCI_CLASS_COMMUNICATIONS 0x07 157 #define PCI_CLASS_SYSTEM 0x08 158 #define PCI_CLASS_INPUT 0x09 159 #define PCI_CLASS_DOCK 0x0a 160 #define PCI_CLASS_PROCESSOR 0x0b 161 #define PCI_CLASS_SERIALBUS 0x0c 162 #define PCI_CLASS_WIRELESS 0x0d 163 #define PCI_CLASS_I2O 0x0e 164 #define PCI_CLASS_SATCOM 0x0f 165 #define PCI_CLASS_CRYPTO 0x10 166 #define PCI_CLASS_DASP 0x11 167 #define PCI_CLASS_UNDEFINED 0xff 168 169 /* 0x00 prehistoric subclasses */ 170 #define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 171 #define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 172 173 /* 0x01 mass storage subclasses */ 174 #define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 175 #define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 176 #define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 177 #define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 178 #define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04 179 #define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05 180 #define PCI_SUBCLASS_MASS_STORAGE_SATA 0x06 181 #define PCI_SUBCLASS_MASS_STORAGE_SAS 0x07 182 #define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 183 184 /* 0x02 network subclasses */ 185 #define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 186 #define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 187 #define PCI_SUBCLASS_NETWORK_FDDI 0x02 188 #define PCI_SUBCLASS_NETWORK_ATM 0x03 189 #define PCI_SUBCLASS_NETWORK_ISDN 0x04 190 #define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05 191 #define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06 192 #define PCI_SUBCLASS_NETWORK_MISC 0x80 193 194 /* 0x03 display subclasses */ 195 #define PCI_SUBCLASS_DISPLAY_VGA 0x00 196 #define PCI_SUBCLASS_DISPLAY_XGA 0x01 197 #define PCI_SUBCLASS_DISPLAY_3D 0x02 198 #define PCI_SUBCLASS_DISPLAY_MISC 0x80 199 200 /* 0x04 multimedia subclasses */ 201 #define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 202 #define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 203 #define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02 204 #define PCI_SUBCLASS_MULTIMEDIA_HDAUDIO 0x03 205 #define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 206 207 /* 0x05 memory subclasses */ 208 #define PCI_SUBCLASS_MEMORY_RAM 0x00 209 #define PCI_SUBCLASS_MEMORY_FLASH 0x01 210 #define PCI_SUBCLASS_MEMORY_MISC 0x80 211 212 /* 0x06 bridge subclasses */ 213 #define PCI_SUBCLASS_BRIDGE_HOST 0x00 214 #define PCI_SUBCLASS_BRIDGE_ISA 0x01 215 #define PCI_SUBCLASS_BRIDGE_EISA 0x02 216 #define PCI_SUBCLASS_BRIDGE_MC 0x03 /* XXX _MCA? */ 217 #define PCI_SUBCLASS_BRIDGE_PCI 0x04 218 #define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 219 #define PCI_SUBCLASS_BRIDGE_NUBUS 0x06 220 #define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 221 #define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08 222 #define PCI_SUBCLASS_BRIDGE_STPCI 0x09 223 #define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a 224 #define PCI_SUBCLASS_BRIDGE_MISC 0x80 225 226 /* 0x07 communications subclasses */ 227 #define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 228 #define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 229 #define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02 230 #define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03 231 #define PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04 232 #define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05 233 #define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 234 235 /* 0x08 system subclasses */ 236 #define PCI_SUBCLASS_SYSTEM_PIC 0x00 237 #define PCI_SUBCLASS_SYSTEM_DMA 0x01 238 #define PCI_SUBCLASS_SYSTEM_TIMER 0x02 239 #define PCI_SUBCLASS_SYSTEM_RTC 0x03 240 #define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04 241 #define PCI_SUBCLASS_SYSTEM_SDHC 0x05 242 #define PCI_SUBCLASS_SYSTEM_MISC 0x80 243 244 /* 0x09 input subclasses */ 245 #define PCI_SUBCLASS_INPUT_KEYBOARD 0x00 246 #define PCI_SUBCLASS_INPUT_DIGITIZER 0x01 247 #define PCI_SUBCLASS_INPUT_MOUSE 0x02 248 #define PCI_SUBCLASS_INPUT_SCANNER 0x03 249 #define PCI_SUBCLASS_INPUT_GAMEPORT 0x04 250 #define PCI_SUBCLASS_INPUT_MISC 0x80 251 252 /* 0x0a dock subclasses */ 253 #define PCI_SUBCLASS_DOCK_GENERIC 0x00 254 #define PCI_SUBCLASS_DOCK_MISC 0x80 255 256 /* 0x0b processor subclasses */ 257 #define PCI_SUBCLASS_PROCESSOR_386 0x00 258 #define PCI_SUBCLASS_PROCESSOR_486 0x01 259 #define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02 260 #define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10 261 #define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20 262 #define PCI_SUBCLASS_PROCESSOR_MIPS 0x30 263 #define PCI_SUBCLASS_PROCESSOR_COPROC 0x40 264 265 /* 0x0c serial bus subclasses */ 266 #define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00 267 #define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01 268 #define PCI_SUBCLASS_SERIALBUS_SSA 0x02 269 #define PCI_SUBCLASS_SERIALBUS_USB 0x03 270 #define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 /* XXX _FIBRECHANNEL */ 271 #define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05 272 #define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06 273 #define PCI_SUBCLASS_SERIALBUS_IPMI 0x07 274 #define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08 275 #define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09 276 277 /* 0x0d wireless subclasses */ 278 #define PCI_SUBCLASS_WIRELESS_IRDA 0x00 279 #define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01 280 #define PCI_SUBCLASS_WIRELESS_RF 0x10 281 #define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11 282 #define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12 283 #define PCI_SUBCLASS_WIRELESS_802_11A 0x20 284 #define PCI_SUBCLASS_WIRELESS_802_11B 0x21 285 #define PCI_SUBCLASS_WIRELESS_MISC 0x80 286 287 /* 0x0e I2O (Intelligent I/O) subclasses */ 288 #define PCI_SUBCLASS_I2O_STANDARD 0x00 289 290 /* 0x0f satellite communication subclasses */ 291 /* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */ 292 #define PCI_SUBCLASS_SATCOM_TV 0x01 293 #define PCI_SUBCLASS_SATCOM_AUDIO 0x02 294 #define PCI_SUBCLASS_SATCOM_VOICE 0x03 295 #define PCI_SUBCLASS_SATCOM_DATA 0x04 296 297 /* 0x10 encryption/decryption subclasses */ 298 #define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00 299 #define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10 300 #define PCI_SUBCLASS_CRYPTO_MISC 0x80 301 302 /* 0x11 data acquisition and signal processing subclasses */ 303 #define PCI_SUBCLASS_DASP_DPIO 0x00 304 #define PCI_SUBCLASS_DASP_TIMEFREQ 0x01 305 #define PCI_SUBCLASS_DASP_SYNC 0x10 306 #define PCI_SUBCLASS_DASP_MGMT 0x20 307 #define PCI_SUBCLASS_DASP_MISC 0x80 308 309 /* 310 * PCI BIST/Header Type/Latency Timer/Cache Line Size Register. 311 */ 312 #define PCI_BHLC_REG 0x0c 313 314 #define PCI_BIST_SHIFT 24 315 #define PCI_BIST_MASK 0xff 316 #define PCI_BIST(bhlcr) \ 317 (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK) 318 319 #define PCI_HDRTYPE_SHIFT 16 320 #define PCI_HDRTYPE_MASK 0xff 321 #define PCI_HDRTYPE(bhlcr) \ 322 (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK) 323 324 #define PCI_HDRTYPE_TYPE(bhlcr) \ 325 (PCI_HDRTYPE(bhlcr) & 0x7f) 326 #define PCI_HDRTYPE_MULTIFN(bhlcr) \ 327 ((PCI_HDRTYPE(bhlcr) & 0x80) != 0) 328 329 #define PCI_LATTIMER_SHIFT 8 330 #define PCI_LATTIMER_MASK 0xff 331 #define PCI_LATTIMER(bhlcr) \ 332 (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK) 333 334 #define PCI_CACHELINE_SHIFT 0 335 #define PCI_CACHELINE_MASK 0xff 336 #define PCI_CACHELINE(bhlcr) \ 337 (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK) 338 339 #define PCI_BHLC_CODE(bist,type,multi,latency,cacheline) \ 340 ((((bist) & PCI_BIST_MASK) << PCI_BIST_SHIFT) | \ 341 (((type) & PCI_HDRTYPE_MASK) << PCI_HDRTYPE_SHIFT) | \ 342 (((multi)?0x80:0) << PCI_HDRTYPE_SHIFT) | \ 343 (((latency) & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT) | \ 344 (((cacheline) & PCI_CACHELINE_MASK) << PCI_CACHELINE_SHIFT)) 345 346 /* 347 * PCI header type 348 */ 349 #define PCI_HDRTYPE_DEVICE 0 /* PCI/PCIX/Cardbus */ 350 #define PCI_HDRTYPE_PPB 1 /* PCI/PCIX/Cardbus */ 351 #define PCI_HDRTYPE_PCB 2 /* PCI/PCIX/Cardbus */ 352 #define PCI_HDRTYPE_EP 0 /* PCI Express */ 353 #define PCI_HDRTYPE_RC 1 /* PCI Express */ 354 355 356 /* 357 * Mapping registers 358 */ 359 #define PCI_MAPREG_START 0x10 360 #define PCI_MAPREG_END 0x28 361 #define PCI_MAPREG_ROM 0x30 362 #define PCI_MAPREG_PPB_END 0x18 363 #define PCI_MAPREG_PCB_END 0x14 364 365 #define PCI_BAR0 0x10 366 #define PCI_BAR1 0x14 367 #define PCI_BAR2 0x18 368 #define PCI_BAR3 0x1C 369 #define PCI_BAR4 0x20 370 #define PCI_BAR5 0x24 371 372 #define PCI_BAR(__n) (PCI_MAPREG_START + 4 * (__n)) 373 374 #define PCI_MAPREG_TYPE(mr) \ 375 ((mr) & PCI_MAPREG_TYPE_MASK) 376 #define PCI_MAPREG_TYPE_MASK 0x00000001 377 378 #define PCI_MAPREG_TYPE_MEM 0x00000000 379 #define PCI_MAPREG_TYPE_ROM 0x00000000 380 #define PCI_MAPREG_TYPE_IO 0x00000001 381 #define PCI_MAPREG_ROM_ENABLE 0x00000001 382 383 #define PCI_MAPREG_MEM_TYPE(mr) \ 384 ((mr) & PCI_MAPREG_MEM_TYPE_MASK) 385 #define PCI_MAPREG_MEM_TYPE_MASK 0x00000006 386 387 #define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000 388 #define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002 389 #define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 390 391 #define PCI_MAPREG_MEM_PREFETCHABLE(mr) \ 392 (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0) 393 #define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008 394 395 #define PCI_MAPREG_MEM_ADDR(mr) \ 396 ((mr) & PCI_MAPREG_MEM_ADDR_MASK) 397 #define PCI_MAPREG_MEM_SIZE(mr) \ 398 (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr)) 399 #define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 400 401 #define PCI_MAPREG_MEM64_ADDR(mr) \ 402 ((mr) & PCI_MAPREG_MEM64_ADDR_MASK) 403 #define PCI_MAPREG_MEM64_SIZE(mr) \ 404 (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr)) 405 #define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL 406 407 #define PCI_MAPREG_IO_ADDR(mr) \ 408 ((mr) & PCI_MAPREG_IO_ADDR_MASK) 409 #define PCI_MAPREG_IO_SIZE(mr) \ 410 (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) 411 #define PCI_MAPREG_IO_ADDR_MASK 0xfffffffc 412 413 #define PCI_MAPREG_SIZE_TO_MASK(size) \ 414 (-(size)) 415 416 #define PCI_MAPREG_NUM(offset) \ 417 (((unsigned)(offset)-PCI_MAPREG_START)/4) 418 419 420 /* 421 * Cardbus CIS pointer (PCI rev. 2.1) 422 */ 423 #define PCI_CARDBUS_CIS_REG 0x28 424 425 /* 426 * Subsystem identification register; contains a vendor ID and a device ID. 427 * Types/macros for PCI_ID_REG apply. 428 * (PCI rev. 2.1) 429 */ 430 #define PCI_SUBSYS_ID_REG 0x2c 431 432 #define PCI_SUBSYS_VENDOR_MASK __BITS(15, 0) 433 #define PCI_SUBSYS_ID_MASK __BITS(31, 16) 434 435 #define PCI_SUBSYS_VENDOR(__subsys_id) \ 436 __SHIFTOUT(__subsys_id, PCI_SUBSYS_VENDOR_MASK) 437 438 #define PCI_SUBSYS_ID(__subsys_id) \ 439 __SHIFTOUT(__subsys_id, PCI_SUBSYS_ID_MASK) 440 441 /* 442 * Capabilities link list (PCI rev. 2.2) 443 */ 444 #define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */ 445 #define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */ 446 #define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff) 447 #define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff) 448 #define PCI_CAPLIST_CAP(cr) ((cr) & 0xff) 449 450 #define PCI_CAP_RESERVED0 0x00 451 #define PCI_CAP_PWRMGMT 0x01 452 #define PCI_CAP_AGP 0x02 453 #define PCI_CAP_AGP_MAJOR(cr) (((cr) >> 20) & 0xf) 454 #define PCI_CAP_AGP_MINOR(cr) (((cr) >> 16) & 0xf) 455 #define PCI_CAP_VPD 0x03 456 #define PCI_CAP_SLOTID 0x04 457 #define PCI_CAP_MSI 0x05 458 #define PCI_CAP_CPCI_HOTSWAP 0x06 459 #define PCI_CAP_PCIX 0x07 460 #define PCI_CAP_LDT 0x08 461 #define PCI_CAP_VENDSPEC 0x09 462 #define PCI_CAP_DEBUGPORT 0x0a 463 #define PCI_CAP_CPCI_RSRCCTL 0x0b 464 #define PCI_CAP_HOTPLUG 0x0c 465 #define PCI_CAP_AGP8 0x0e 466 #define PCI_CAP_SECURE 0x0f 467 #define PCI_CAP_PCIEXPRESS 0x10 468 #define PCI_CAP_MSIX 0x11 469 #define PCI_CAP_SATA 0x12 470 #define PCI_CAP_PCIAF 0x13 471 472 /* 473 * Vital Product Data; access via capability pointer (PCI rev 2.2). 474 */ 475 #define PCI_VPD_ADDRESS_MASK 0x7fff 476 #define PCI_VPD_ADDRESS_SHIFT 16 477 #define PCI_VPD_ADDRESS(ofs) \ 478 (((ofs) & PCI_VPD_ADDRESS_MASK) << PCI_VPD_ADDRESS_SHIFT) 479 #define PCI_VPD_DATAREG(ofs) ((ofs) + 4) 480 #define PCI_VPD_OPFLAG 0x80000000 481 482 #define PCI_MSI_CTL 0x0 /* Message Control Register offset */ 483 #define PCI_MSI_MADDR 0x4 /* Message Address Register (least 484 * significant bits) offset 485 */ 486 #define PCI_MSI_MADDR64_LO 0x4 /* 64-bit Message Address Register 487 * (least significant bits) offset 488 */ 489 #define PCI_MSI_MADDR64_HI 0x8 /* 64-bit Message Address Register 490 * (most significant bits) offset 491 */ 492 #define PCI_MSI_MDATA 0x8 /* Message Data Register offset */ 493 #define PCI_MSI_MDATA64 0xC /* 64-bit Message Data Register 494 * offset 495 */ 496 497 #define PCI_MSI_CTL_MASK __BITS(31, 16) 498 #define PCI_MSI_CTL_PERVEC_MASK __SHIFTIN(__BIT(8), PCI_MSI_CTL_MASK) 499 #define PCI_MSI_CTL_64BIT_ADDR __SHIFTIN(__BIT(7), PCI_MSI_CTL_MASK) 500 #define PCI_MSI_CTL_MME_MASK __SHIFTIN(__BITS(6, 4), PCI_MSI_CTL_MASK) 501 #define PCI_MSI_CTL_MMC_MASK __SHIFTIN(__BITS(3, 1), PCI_MSI_CTL_MASK) 502 #define PCI_MSI_CTL_MSI_ENABLE __SHIFTIN(__BIT(0), PCI_MSI_CTL_MASK) 503 504 /* 505 * MSI Message Address is at offset 4. 506 * MSI Message Upper Address (if 64bit) is at offset 8. 507 * MSI Message data is at offset 8 or 12 and is 16 bits. 508 * [16 bit reserved field] 509 * MSI Mask Bits (32 bit field) 510 * MSI Pending Bits (32 bit field) 511 */ 512 513 #define PCI_MSIX_CTL_ENABLE 0x80000000 514 #define PCI_MSIX_CTL_FUNCMASK 0x40000000 515 #define PCI_MSIX_CTL_TBLSIZE_MASK 0x07ff0000 516 #define PCI_MSIX_CTL_TBLSIZE_SHIFT 16 517 #define PCI_MSIX_CTL_TBLSIZE(ofs) (((ofs) >> PCI_MSIX_CTL_TBLSIZE_SHIFT) & PCI_MSIX_CTL_TBLSIZE_MASK) 518 /* 519 * 2nd DWORD is the Table Offset 520 */ 521 #define PCI_MSIX_TBLOFFSET_MASK 0xfffffff8 522 #define PCI_MSIX_TBLBIR_MASK 0x00000007 523 /* 524 * 3rd DWORD is the Pending Bitmap Array Offset 525 */ 526 #define PCI_MSIX_PBAOFFSET_MASK 0xfffffff8 527 #define PCI_MSIX_PBABIR_MASK 0x00000007 528 529 struct pci_msix_table_entry { 530 uint32_t pci_msix_addr_lo; 531 uint32_t pci_msix_addr_hi; 532 uint32_t pci_msix_value; 533 uint32_t pci_msix_vendor_control; 534 }; 535 #define PCI_MSIX_VENDCTL_MASK 0x00000001 536 537 538 /* 539 * Power Management Capability; access via capability pointer. 540 */ 541 542 /* Power Management Capability Register */ 543 #define PCI_PMCR_SHIFT 16 544 #define PCI_PMCR 0x02 545 #define PCI_PMCR_D1SUPP 0x0200 546 #define PCI_PMCR_D2SUPP 0x0400 547 /* Power Management Control Status Register */ 548 #define PCI_PMCSR 0x04 549 #define PCI_PMCSR_PME_EN 0x100 550 #define PCI_PMCSR_STATE_MASK 0x03 551 #define PCI_PMCSR_STATE_D0 0x00 552 #define PCI_PMCSR_STATE_D1 0x01 553 #define PCI_PMCSR_STATE_D2 0x02 554 #define PCI_PMCSR_STATE_D3 0x03 555 #define PCI_PMCSR_PME_STS 0x8000 556 557 /* 558 * PCI-X capability. 559 */ 560 561 /* 562 * Command. 16 bits at offset 2 (e.g. upper 16 bits of the first 32-bit 563 * word at the capability; the lower 16 bits are the capability ID and 564 * next capability pointer). 565 * 566 * Since we always read PCI config space in 32-bit words, we define these 567 * as 32-bit values, offset and shifted appropriately. Make sure you perform 568 * the appropriate R/M/W cycles! 569 */ 570 #define PCI_PCIX_CMD 0x00 571 #define PCI_PCIX_CMD_PERR_RECOVER 0x00010000 572 #define PCI_PCIX_CMD_RELAXED_ORDER 0x00020000 573 #define PCI_PCIX_CMD_BYTECNT_MASK 0x000c0000 574 #define PCI_PCIX_CMD_BYTECNT_SHIFT 18 575 #define PCI_PCIX_CMD_BCNT_512 0x00000000 576 #define PCI_PCIX_CMD_BCNT_1024 0x00040000 577 #define PCI_PCIX_CMD_BCNT_2048 0x00080000 578 #define PCI_PCIX_CMD_BCNT_4096 0x000c0000 579 #define PCI_PCIX_CMD_SPLTRANS_MASK 0x00700000 580 #define PCI_PCIX_CMD_SPLTRANS_1 0x00000000 581 #define PCI_PCIX_CMD_SPLTRANS_2 0x00100000 582 #define PCI_PCIX_CMD_SPLTRANS_3 0x00200000 583 #define PCI_PCIX_CMD_SPLTRANS_4 0x00300000 584 #define PCI_PCIX_CMD_SPLTRANS_8 0x00400000 585 #define PCI_PCIX_CMD_SPLTRANS_12 0x00500000 586 #define PCI_PCIX_CMD_SPLTRANS_16 0x00600000 587 #define PCI_PCIX_CMD_SPLTRANS_32 0x00700000 588 589 /* 590 * Status. 32 bits at offset 4. 591 */ 592 #define PCI_PCIX_STATUS 0x04 593 #define PCI_PCIX_STATUS_FN_MASK 0x00000007 594 #define PCI_PCIX_STATUS_DEV_MASK 0x000000f8 595 #define PCI_PCIX_STATUS_BUS_MASK 0x0000ff00 596 #define PCI_PCIX_STATUS_64BIT 0x00010000 597 #define PCI_PCIX_STATUS_133 0x00020000 598 #define PCI_PCIX_STATUS_SPLDISC 0x00040000 599 #define PCI_PCIX_STATUS_SPLUNEX 0x00080000 600 #define PCI_PCIX_STATUS_DEVCPLX 0x00100000 601 #define PCI_PCIX_STATUS_MAXB_MASK 0x00600000 602 #define PCI_PCIX_STATUS_MAXB_SHIFT 21 603 #define PCI_PCIX_STATUS_MAXB_512 0x00000000 604 #define PCI_PCIX_STATUS_MAXB_1024 0x00200000 605 #define PCI_PCIX_STATUS_MAXB_2048 0x00400000 606 #define PCI_PCIX_STATUS_MAXB_4096 0x00600000 607 #define PCI_PCIX_STATUS_MAXST_MASK 0x03800000 608 #define PCI_PCIX_STATUS_MAXST_1 0x00000000 609 #define PCI_PCIX_STATUS_MAXST_2 0x00800000 610 #define PCI_PCIX_STATUS_MAXST_3 0x01000000 611 #define PCI_PCIX_STATUS_MAXST_4 0x01800000 612 #define PCI_PCIX_STATUS_MAXST_8 0x02000000 613 #define PCI_PCIX_STATUS_MAXST_12 0x02800000 614 #define PCI_PCIX_STATUS_MAXST_16 0x03000000 615 #define PCI_PCIX_STATUS_MAXST_32 0x03800000 616 #define PCI_PCIX_STATUS_MAXRS_MASK 0x1c000000 617 #define PCI_PCIX_STATUS_MAXRS_1K 0x00000000 618 #define PCI_PCIX_STATUS_MAXRS_2K 0x04000000 619 #define PCI_PCIX_STATUS_MAXRS_4K 0x08000000 620 #define PCI_PCIX_STATUS_MAXRS_8K 0x0c000000 621 #define PCI_PCIX_STATUS_MAXRS_16K 0x10000000 622 #define PCI_PCIX_STATUS_MAXRS_32K 0x14000000 623 #define PCI_PCIX_STATUS_MAXRS_64K 0x18000000 624 #define PCI_PCIX_STATUS_MAXRS_128K 0x1c000000 625 #define PCI_PCIX_STATUS_SCERR 0x20000000 626 627 /* 628 * PCI Express; access via capability pointer. 629 */ 630 #define PCI_PCIE_XCAP 0x00 /* Capability List & Capabilities 631 * Register 632 */ 633 #define PCI_PCIE_XCAP_MASK __BITS(31, 16) 634 /* Capability Version */ 635 #define PCI_PCIE_XCAP_VER_MASK __SHIFTIN(__BITS(3, 0), PCI_PCIE_XCAP_MASK) 636 #define PCI_PCIE_XCAP_VER_1_0 __SHIFTIN(1, PCI_PCIE_XCAP_VER_MASK) 637 #define PCI_PCIE_XCAP_VER_2_0 __SHIFTIN(2, PCI_PCIE_XCAP_VER_MASK) 638 #define PCI_PCIE_XCAP_TYPE_MASK __SHIFTIN(__BITS(7, 4), PCI_PCIE_XCAP_MASK) 639 #define PCI_PCIE_XCAP_TYPE_PCIE_DEV __SHIFTIN(0x0, PCI_PCIE_XCAP_TYPE_MASK) 640 #define PCI_PCIE_XCAP_TYPE_PCI_DEV __SHIFTIN(0x1, PCI_PCIE_XCAP_TYPE_MASK) 641 #define PCI_PCIE_XCAP_TYPE_ROOT __SHIFTIN(0x4, PCI_PCIE_XCAP_TYPE_MASK) 642 #define PCI_PCIE_XCAP_TYPE_UP __SHIFTIN(0x5, PCI_PCIE_XCAP_TYPE_MASK) 643 #define PCI_PCIE_XCAP_TYPE_DOWN __SHIFTIN(0x6, PCI_PCIE_XCAP_TYPE_MASK) 644 #define PCI_PCIE_XCAP_TYPE_PCIE2PCI __SHIFTIN(0x7, PCI_PCIE_XCAP_TYPE_MASK) 645 #define PCI_PCIE_XCAP_TYPE_PCI2PCIE __SHIFTIN(0x8, PCI_PCIE_XCAP_TYPE_MASK) 646 #define PCI_PCIE_XCAP_SI __SHIFTIN(__BIT(8), PCI_PCIE_XCAP_MASK) /* Slot Implemented */ 647 #define PCI_PCIE_DCAP 0x04 /* Device Capabilities Register */ 648 #define PCI_PCIE_DCSR 0x08 /* Device Control & Status Register */ 649 #define PCI_PCIE_DCSR_MAX_READ_REQ __BITS(14, 12) 650 #define PCI_PCIE_DCSR_ENA_NO_SNOOP __BIT(11) 651 #define PCI_PCIE_DCSR_CED __BIT(0 + 16) 652 #define PCI_PCIE_DCSR_NFED __BIT(1 + 16) 653 #define PCI_PCIE_DCSR_FED __BIT(2 + 16) 654 #define PCI_PCIE_DCSR_URD __BIT(3 + 16) 655 #define PCI_PCIE_LCAP 0x0c 656 #define PCI_PCIE_LCSR 0x10 /* Link Control & Status Register */ 657 #define PCI_PCIE_LCSR_ASPM_L0S __BIT(0) 658 #define PCI_PCIE_LCSR_ASPM_L1 __BIT(1) 659 #define PCI_PCIE_SLCAP 0x14 /* Slot Capabilities Register */ 660 #define PCI_PCIE_SLCAP_ABP __BIT(0) /* Attention Button Present */ 661 #define PCI_PCIE_SLCAP_PCP __BIT(1) /* Power Controller Present */ 662 #define PCI_PCIE_SLCAP_MSP __BIT(2) /* MRL Sensor Present */ 663 #define PCI_PCIE_SLCAP_AIP __BIT(3) /* Attention Indicator 664 * Present 665 */ 666 #define PCI_PCIE_SLCAP_PIP __BIT(4) /* Power Indicator Present */ 667 #define PCI_PCIE_SLCAP_HPS __BIT(5) /* Hot-Plug Surprise */ 668 #define PCI_PCIE_SLCAP_HPC __BIT(6) /* Hot-Plug Capable */ 669 #define PCI_PCIE_SLCSR 0x18 670 #define PCI_PCIE_SLCSR_ABE __BIT(0) 671 #define PCI_PCIE_SLCSR_PFE __BIT(1) 672 #define PCI_PCIE_SLCSR_MSE __BIT(2) 673 #define PCI_PCIE_SLCSR_PDE __BIT(3) 674 #define PCI_PCIE_SLCSR_CCE __BIT(4) 675 #define PCI_PCIE_SLCSR_HPE __BIT(5) 676 #define PCI_PCIE_SLCSR_ABP __BIT(0 + 16) 677 #define PCI_PCIE_SLCSR_PFD __BIT(1 + 16) 678 #define PCI_PCIE_SLCSR_MSC __BIT(2 + 16) 679 #define PCI_PCIE_SLCSR_PDC __BIT(3 + 16) 680 #define PCI_PCIE_SLCSR_CC __BIT(4 + 16) 681 #define PCI_PCIE_SLCSR_MS __BIT(5 + 16) 682 #define PCI_PCIE_SLCSR_PDS __BIT(6 + 16) 683 #define PCI_PCIE_SLCSR_LACS __BIT(8 + 16) 684 #define PCI_PCIE_RCR 0x1c 685 #define PCI_PCIE_RSR 0x20 686 #define PCI_PCIE_DCAP2 0x24 687 #define PCI_PCIE_DCSR2 0x28 688 #define PCI_PCIE_LCAP2 0x2c 689 #define PCI_PCIE_LCSR2 0x30 690 #define PCI_PCIE_SLCAP2 0x34 691 #define PCI_PCIE_SLCSR2 0x38 692 693 /* 694 * Interrupt Configuration Register; contains interrupt pin and line. 695 */ 696 #define PCI_INTERRUPT_REG 0x3c 697 698 typedef u_int8_t pci_intr_latency_t; 699 typedef u_int8_t pci_intr_grant_t; 700 typedef u_int8_t pci_intr_pin_t; 701 typedef u_int8_t pci_intr_line_t; 702 703 #define PCI_MAX_LAT_SHIFT 24 704 #define PCI_MAX_LAT_MASK 0xff 705 #define PCI_MAX_LAT(icr) \ 706 (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK) 707 708 #define PCI_MIN_GNT_SHIFT 16 709 #define PCI_MIN_GNT_MASK 0xff 710 #define PCI_MIN_GNT(icr) \ 711 (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK) 712 713 #define PCI_INTERRUPT_GRANT_SHIFT 24 714 #define PCI_INTERRUPT_GRANT_MASK 0xff 715 #define PCI_INTERRUPT_GRANT(icr) \ 716 (((icr) >> PCI_INTERRUPT_GRANT_SHIFT) & PCI_INTERRUPT_GRANT_MASK) 717 718 #define PCI_INTERRUPT_LATENCY_SHIFT 16 719 #define PCI_INTERRUPT_LATENCY_MASK 0xff 720 #define PCI_INTERRUPT_LATENCY(icr) \ 721 (((icr) >> PCI_INTERRUPT_LATENCY_SHIFT) & PCI_INTERRUPT_LATENCY_MASK) 722 723 #define PCI_INTERRUPT_PIN_SHIFT 8 724 #define PCI_INTERRUPT_PIN_MASK 0xff 725 #define PCI_INTERRUPT_PIN(icr) \ 726 (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK) 727 728 #define PCI_INTERRUPT_LINE_SHIFT 0 729 #define PCI_INTERRUPT_LINE_MASK 0xff 730 #define PCI_INTERRUPT_LINE(icr) \ 731 (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK) 732 733 #define PCI_INTERRUPT_CODE(lat,gnt,pin,line) \ 734 ((((lat)&PCI_INTERRUPT_LATENCY_MASK)<<PCI_INTERRUPT_LATENCY_SHIFT)| \ 735 (((gnt)&PCI_INTERRUPT_GRANT_MASK) <<PCI_INTERRUPT_GRANT_SHIFT) | \ 736 (((pin)&PCI_INTERRUPT_PIN_MASK) <<PCI_INTERRUPT_PIN_SHIFT) | \ 737 (((line)&PCI_INTERRUPT_LINE_MASK) <<PCI_INTERRUPT_LINE_SHIFT)) 738 739 #define PCI_INTERRUPT_PIN_NONE 0x00 740 #define PCI_INTERRUPT_PIN_A 0x01 741 #define PCI_INTERRUPT_PIN_B 0x02 742 #define PCI_INTERRUPT_PIN_C 0x03 743 #define PCI_INTERRUPT_PIN_D 0x04 744 #define PCI_INTERRUPT_PIN_MAX 0x04 745 746 /* Header Type 1 (Bridge) configuration registers */ 747 #define PCI_BRIDGE_BUS_REG 0x18 748 #define PCI_BRIDGE_BUS_PRIMARY_SHIFT 0 749 #define PCI_BRIDGE_BUS_SECONDARY_SHIFT 8 750 #define PCI_BRIDGE_BUS_SUBORDINATE_SHIFT 16 751 752 #define PCI_BRIDGE_STATIO_REG 0x1C 753 #define PCI_BRIDGE_STATIO_IOBASE_SHIFT 0 754 #define PCI_BRIDGE_STATIO_IOLIMIT_SHIFT 8 755 #define PCI_BRIDGE_STATIO_STATUS_SHIFT 16 756 #define PCI_BRIDGE_STATIO_IOBASE_MASK 0xf0 757 #define PCI_BRIDGE_STATIO_IOLIMIT_MASK 0xf0 758 #define PCI_BRIDGE_STATIO_STATUS_MASK 0xffff 759 #define PCI_BRIDGE_IO_32BITS(reg) (((reg) & 0xf) == 1) 760 761 #define PCI_BRIDGE_MEMORY_REG 0x20 762 #define PCI_BRIDGE_MEMORY_BASE_SHIFT 4 763 #define PCI_BRIDGE_MEMORY_LIMIT_SHIFT 20 764 #define PCI_BRIDGE_MEMORY_BASE_MASK 0x0fff 765 #define PCI_BRIDGE_MEMORY_LIMIT_MASK 0x0fff 766 767 #define PCI_BRIDGE_PREFETCHMEM_REG 0x24 768 #define PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT 4 769 #define PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT 20 770 #define PCI_BRIDGE_PREFETCHMEM_BASE_MASK 0x0fff 771 #define PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK 0x0fff 772 #define PCI_BRIDGE_PREFETCHMEM_64BITS(reg) ((reg) & 0xf) 773 774 #define PCI_BRIDGE_PREFETCHBASE32_REG 0x28 775 #define PCI_BRIDGE_PREFETCHLIMIT32_REG 0x2C 776 777 #define PCI_BRIDGE_IOHIGH_REG 0x30 778 #define PCI_BRIDGE_IOHIGH_BASE_SHIFT 0 779 #define PCI_BRIDGE_IOHIGH_LIMIT_SHIFT 16 780 #define PCI_BRIDGE_IOHIGH_BASE_MASK 0xffff 781 #define PCI_BRIDGE_IOHIGH_LIMIT_MASK 0xffff 782 783 #define PCI_BRIDGE_CONTROL_REG 0x3C 784 #define PCI_BRIDGE_CONTROL_SHIFT 16 785 #define PCI_BRIDGE_CONTROL_MASK 0xffff 786 #define PCI_BRIDGE_CONTROL_PERE (1 << 0) 787 #define PCI_BRIDGE_CONTROL_SERR (1 << 1) 788 #define PCI_BRIDGE_CONTROL_ISA (1 << 2) 789 #define PCI_BRIDGE_CONTROL_VGA (1 << 3) 790 /* Reserved (1 << 4) */ 791 #define PCI_BRIDGE_CONTROL_MABRT (1 << 5) 792 #define PCI_BRIDGE_CONTROL_SECBR (1 << 6) 793 #define PCI_BRIDGE_CONTROL_SECFASTB2B (1 << 7) 794 #define PCI_BRIDGE_CONTROL_PRI_DISC_TIMER (1 << 8) 795 #define PCI_BRIDGE_CONTROL_SEC_DISC_TIMER (1 << 9) 796 #define PCI_BRIDGE_CONTROL_DISC_TIMER_STAT (1 << 10) 797 #define PCI_BRIDGE_CONTROL_DISC_TIMER_SERR (1 << 11) 798 /* Reserved (1 << 12) - (1 << 15) */ 799 800 /* 801 * Vital Product Data resource tags. 802 */ 803 struct pci_vpd_smallres { 804 uint8_t vpdres_byte0; /* length of data + tag */ 805 /* Actual data. */ 806 } __packed; 807 808 struct pci_vpd_largeres { 809 uint8_t vpdres_byte0; 810 uint8_t vpdres_len_lsb; /* length of data only */ 811 uint8_t vpdres_len_msb; 812 /* Actual data. */ 813 } __packed; 814 815 #define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) 816 817 #define PCI_VPDRES_SMALL_LENGTH(x) ((x) & 0x7) 818 #define PCI_VPDRES_SMALL_NAME(x) (((x) >> 3) & 0xf) 819 820 #define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) 821 822 #define PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID 0x3 /* small */ 823 #define PCI_VPDRES_TYPE_VENDOR_DEFINED 0xe /* small */ 824 #define PCI_VPDRES_TYPE_END_TAG 0xf /* small */ 825 826 #define PCI_VPDRES_TYPE_IDENTIFIER_STRING 0x02 /* large */ 827 #define PCI_VPDRES_TYPE_VPD 0x10 /* large */ 828 829 struct pci_vpd { 830 uint8_t vpd_key0; 831 uint8_t vpd_key1; 832 uint8_t vpd_len; /* length of data only */ 833 /* Actual data. */ 834 } __packed; 835 836 /* 837 * Recommended VPD fields: 838 * 839 * PN Part number of assembly 840 * FN FRU part number 841 * EC EC level of assembly 842 * MN Manufacture ID 843 * SN Serial Number 844 * 845 * Conditionally recommended VPD fields: 846 * 847 * LI Load ID 848 * RL ROM Level 849 * RM Alterable ROM Level 850 * NA Network Address 851 * DD Device Driver Level 852 * DG Diagnostic Level 853 * LL Loadable Microcode Level 854 * VI Vendor ID/Device ID 855 * FU Function Number 856 * SI Subsystem Vendor ID/Subsystem ID 857 * 858 * Additional VPD fields: 859 * 860 * Z0-ZZ User/Product Specific 861 */ 862 863 /* 864 * PCI Expansion Rom 865 */ 866 867 struct pci_rom_header { 868 uint16_t romh_magic; /* 0xAA55 little endian */ 869 uint8_t romh_reserved[22]; 870 uint16_t romh_data_ptr; /* pointer to pci_rom struct */ 871 } __packed; 872 873 #define PCI_ROM_HEADER_MAGIC 0xAA55 /* little endian */ 874 875 struct pci_rom { 876 uint32_t rom_signature; 877 pci_vendor_id_t rom_vendor; 878 pci_product_id_t rom_product; 879 uint16_t rom_vpd_ptr; /* reserved in PCI 2.2 */ 880 uint16_t rom_data_len; 881 uint8_t rom_data_rev; 882 pci_interface_t rom_interface; /* the class reg is 24-bits */ 883 pci_subclass_t rom_subclass; /* in little endian */ 884 pci_class_t rom_class; 885 uint16_t rom_len; /* code length / 512 byte */ 886 uint16_t rom_rev; /* code revision level */ 887 uint8_t rom_code_type; /* type of code */ 888 uint8_t rom_indicator; 889 uint16_t rom_reserved; 890 /* Actual data. */ 891 } __packed; 892 893 #define PCI_ROM_SIGNATURE 0x52494350 /* "PCIR", endian reversed */ 894 #define PCI_ROM_CODE_TYPE_X86 0 /* Intel x86 BIOS */ 895 #define PCI_ROM_CODE_TYPE_OFW 1 /* Open Firmware */ 896 #define PCI_ROM_CODE_TYPE_HPPA 2 /* HP PA/RISC */ 897 #define PCI_ROM_CODE_TYPE_EFI 3 /* EFI Image */ 898 899 #define PCI_ROM_INDICATOR_LAST 0x80 900 901 /* 902 * Threshold below which 32bit PCI DMA needs bouncing. 903 */ 904 #define PCI32_DMA_BOUNCE_THRESHOLD 0x100000000ULL 905 906 /* 907 * PCI-X 2.0 Extended Capability List 908 */ 909 910 #define PCI_EXTCAPLIST_BASE 0x100 911 912 #define PCI_EXTCAPLIST_CAP(ecr) ((ecr) & 0xffff) 913 #define PCI_EXTCAPLIST_VERSION(ecr) (((ecr) >> 16) & 0xf) 914 #define PCI_EXTCAPLIST_NEXT(ecr) (((ecr) >> 20) & 0xfff) 915 916 #endif /* _DEV_PCI_PCIREG_H_ */ 917