1 /* $NetBSD: pcireg.h,v 1.56 2007/11/28 04:03:16 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1999, 2000 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _DEV_PCI_PCIREG_H_ 35 #define _DEV_PCI_PCIREG_H_ 36 37 /* 38 * Standardized PCI configuration information 39 * 40 * XXX This is not complete. 41 */ 42 43 /* 44 * Device identification register; contains a vendor ID and a device ID. 45 */ 46 #define PCI_ID_REG 0x00 47 48 typedef u_int16_t pci_vendor_id_t; 49 typedef u_int16_t pci_product_id_t; 50 51 #define PCI_VENDOR_SHIFT 0 52 #define PCI_VENDOR_MASK 0xffff 53 #define PCI_VENDOR(id) \ 54 (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK) 55 56 #define PCI_PRODUCT_SHIFT 16 57 #define PCI_PRODUCT_MASK 0xffff 58 #define PCI_PRODUCT(id) \ 59 (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) 60 61 #define PCI_ID_CODE(vid,pid) \ 62 ((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) | \ 63 (((pid) & PCI_PRODUCT_MASK) << PCI_PRODUCT_SHIFT)) \ 64 65 /* 66 * Command and status register. 67 */ 68 #define PCI_COMMAND_STATUS_REG 0x04 69 #define PCI_COMMAND_SHIFT 0 70 #define PCI_COMMAND_MASK 0xffff 71 #define PCI_STATUS_SHIFT 16 72 #define PCI_STATUS_MASK 0xffff 73 74 #define PCI_COMMAND_STATUS_CODE(cmd,stat) \ 75 ((((cmd) & PCI_COMMAND_MASK) << PCI_COMMAND_SHIFT) | \ 76 (((stat) & PCI_STATUS_MASK) << PCI_STATUS_SHIFT)) \ 77 78 #define PCI_COMMAND_IO_ENABLE 0x00000001 79 #define PCI_COMMAND_MEM_ENABLE 0x00000002 80 #define PCI_COMMAND_MASTER_ENABLE 0x00000004 81 #define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 82 #define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 83 #define PCI_COMMAND_PALETTE_ENABLE 0x00000020 84 #define PCI_COMMAND_PARITY_ENABLE 0x00000040 85 #define PCI_COMMAND_STEPPING_ENABLE 0x00000080 86 #define PCI_COMMAND_SERR_ENABLE 0x00000100 87 #define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 88 #define PCI_COMMAND_INTERRUPT_DISABLE 0x00000400 89 90 #define PCI_STATUS_CAPLIST_SUPPORT 0x00100000 91 #define PCI_STATUS_66MHZ_SUPPORT 0x00200000 92 #define PCI_STATUS_UDF_SUPPORT 0x00400000 93 #define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000 94 #define PCI_STATUS_PARITY_ERROR 0x01000000 95 #define PCI_STATUS_DEVSEL_FAST 0x00000000 96 #define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 97 #define PCI_STATUS_DEVSEL_SLOW 0x04000000 98 #define PCI_STATUS_DEVSEL_MASK 0x06000000 99 #define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 100 #define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 101 #define PCI_STATUS_MASTER_ABORT 0x20000000 102 #define PCI_STATUS_SPECIAL_ERROR 0x40000000 103 #define PCI_STATUS_PARITY_DETECT 0x80000000 104 105 /* 106 * PCI Class and Revision Register; defines type and revision of device. 107 */ 108 #define PCI_CLASS_REG 0x08 109 110 typedef u_int8_t pci_class_t; 111 typedef u_int8_t pci_subclass_t; 112 typedef u_int8_t pci_interface_t; 113 typedef u_int8_t pci_revision_t; 114 115 #define PCI_CLASS_SHIFT 24 116 #define PCI_CLASS_MASK 0xff 117 #define PCI_CLASS(cr) \ 118 (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) 119 120 #define PCI_SUBCLASS_SHIFT 16 121 #define PCI_SUBCLASS_MASK 0xff 122 #define PCI_SUBCLASS(cr) \ 123 (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) 124 125 #define PCI_INTERFACE_SHIFT 8 126 #define PCI_INTERFACE_MASK 0xff 127 #define PCI_INTERFACE(cr) \ 128 (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) 129 130 #define PCI_REVISION_SHIFT 0 131 #define PCI_REVISION_MASK 0xff 132 #define PCI_REVISION(cr) \ 133 (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) 134 135 #define PCI_CLASS_CODE(mainclass, subclass, interface) \ 136 ((((mainclass) & PCI_CLASS_MASK) << PCI_CLASS_SHIFT) | \ 137 (((subclass) & PCI_SUBCLASS_MASK) << PCI_SUBCLASS_SHIFT) | \ 138 (((interface) & PCI_INTERFACE_MASK) << PCI_INTERFACE_SHIFT)) 139 140 /* base classes */ 141 #define PCI_CLASS_PREHISTORIC 0x00 142 #define PCI_CLASS_MASS_STORAGE 0x01 143 #define PCI_CLASS_NETWORK 0x02 144 #define PCI_CLASS_DISPLAY 0x03 145 #define PCI_CLASS_MULTIMEDIA 0x04 146 #define PCI_CLASS_MEMORY 0x05 147 #define PCI_CLASS_BRIDGE 0x06 148 #define PCI_CLASS_COMMUNICATIONS 0x07 149 #define PCI_CLASS_SYSTEM 0x08 150 #define PCI_CLASS_INPUT 0x09 151 #define PCI_CLASS_DOCK 0x0a 152 #define PCI_CLASS_PROCESSOR 0x0b 153 #define PCI_CLASS_SERIALBUS 0x0c 154 #define PCI_CLASS_WIRELESS 0x0d 155 #define PCI_CLASS_I2O 0x0e 156 #define PCI_CLASS_SATCOM 0x0f 157 #define PCI_CLASS_CRYPTO 0x10 158 #define PCI_CLASS_DASP 0x11 159 #define PCI_CLASS_UNDEFINED 0xff 160 161 /* 0x00 prehistoric subclasses */ 162 #define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 163 #define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 164 165 /* 0x01 mass storage subclasses */ 166 #define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 167 #define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 168 #define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 169 #define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 170 #define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04 171 #define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05 172 #define PCI_SUBCLASS_MASS_STORAGE_SATA 0x06 173 #define PCI_SUBCLASS_MASS_STORAGE_SAS 0x07 174 #define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 175 176 /* 0x02 network subclasses */ 177 #define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 178 #define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 179 #define PCI_SUBCLASS_NETWORK_FDDI 0x02 180 #define PCI_SUBCLASS_NETWORK_ATM 0x03 181 #define PCI_SUBCLASS_NETWORK_ISDN 0x04 182 #define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05 183 #define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06 184 #define PCI_SUBCLASS_NETWORK_MISC 0x80 185 186 /* 0x03 display subclasses */ 187 #define PCI_SUBCLASS_DISPLAY_VGA 0x00 188 #define PCI_SUBCLASS_DISPLAY_XGA 0x01 189 #define PCI_SUBCLASS_DISPLAY_3D 0x02 190 #define PCI_SUBCLASS_DISPLAY_MISC 0x80 191 192 /* 0x04 multimedia subclasses */ 193 #define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 194 #define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 195 #define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02 196 #define PCI_SUBCLASS_MULTIMEDIA_HDAUDIO 0x03 197 #define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 198 199 /* 0x05 memory subclasses */ 200 #define PCI_SUBCLASS_MEMORY_RAM 0x00 201 #define PCI_SUBCLASS_MEMORY_FLASH 0x01 202 #define PCI_SUBCLASS_MEMORY_MISC 0x80 203 204 /* 0x06 bridge subclasses */ 205 #define PCI_SUBCLASS_BRIDGE_HOST 0x00 206 #define PCI_SUBCLASS_BRIDGE_ISA 0x01 207 #define PCI_SUBCLASS_BRIDGE_EISA 0x02 208 #define PCI_SUBCLASS_BRIDGE_MC 0x03 /* XXX _MCA? */ 209 #define PCI_SUBCLASS_BRIDGE_PCI 0x04 210 #define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 211 #define PCI_SUBCLASS_BRIDGE_NUBUS 0x06 212 #define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 213 #define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08 214 #define PCI_SUBCLASS_BRIDGE_STPCI 0x09 215 #define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a 216 #define PCI_SUBCLASS_BRIDGE_MISC 0x80 217 218 /* 0x07 communications subclasses */ 219 #define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 220 #define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 221 #define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02 222 #define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03 223 #define PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04 224 #define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05 225 #define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 226 227 /* 0x08 system subclasses */ 228 #define PCI_SUBCLASS_SYSTEM_PIC 0x00 229 #define PCI_SUBCLASS_SYSTEM_DMA 0x01 230 #define PCI_SUBCLASS_SYSTEM_TIMER 0x02 231 #define PCI_SUBCLASS_SYSTEM_RTC 0x03 232 #define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04 233 #define PCI_SUBCLASS_SYSTEM_SDHC 0x05 234 #define PCI_SUBCLASS_SYSTEM_MISC 0x80 235 236 /* 0x09 input subclasses */ 237 #define PCI_SUBCLASS_INPUT_KEYBOARD 0x00 238 #define PCI_SUBCLASS_INPUT_DIGITIZER 0x01 239 #define PCI_SUBCLASS_INPUT_MOUSE 0x02 240 #define PCI_SUBCLASS_INPUT_SCANNER 0x03 241 #define PCI_SUBCLASS_INPUT_GAMEPORT 0x04 242 #define PCI_SUBCLASS_INPUT_MISC 0x80 243 244 /* 0x0a dock subclasses */ 245 #define PCI_SUBCLASS_DOCK_GENERIC 0x00 246 #define PCI_SUBCLASS_DOCK_MISC 0x80 247 248 /* 0x0b processor subclasses */ 249 #define PCI_SUBCLASS_PROCESSOR_386 0x00 250 #define PCI_SUBCLASS_PROCESSOR_486 0x01 251 #define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02 252 #define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10 253 #define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20 254 #define PCI_SUBCLASS_PROCESSOR_MIPS 0x30 255 #define PCI_SUBCLASS_PROCESSOR_COPROC 0x40 256 257 /* 0x0c serial bus subclasses */ 258 #define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00 259 #define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01 260 #define PCI_SUBCLASS_SERIALBUS_SSA 0x02 261 #define PCI_SUBCLASS_SERIALBUS_USB 0x03 262 #define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 /* XXX _FIBRECHANNEL */ 263 #define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05 264 #define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06 265 #define PCI_SUBCLASS_SERIALBUS_IPMI 0x07 266 #define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08 267 #define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09 268 269 /* 0x0d wireless subclasses */ 270 #define PCI_SUBCLASS_WIRELESS_IRDA 0x00 271 #define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01 272 #define PCI_SUBCLASS_WIRELESS_RF 0x10 273 #define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11 274 #define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12 275 #define PCI_SUBCLASS_WIRELESS_802_11A 0x20 276 #define PCI_SUBCLASS_WIRELESS_802_11B 0x21 277 #define PCI_SUBCLASS_WIRELESS_MISC 0x80 278 279 /* 0x0e I2O (Intelligent I/O) subclasses */ 280 #define PCI_SUBCLASS_I2O_STANDARD 0x00 281 282 /* 0x0f satellite communication subclasses */ 283 /* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */ 284 #define PCI_SUBCLASS_SATCOM_TV 0x01 285 #define PCI_SUBCLASS_SATCOM_AUDIO 0x02 286 #define PCI_SUBCLASS_SATCOM_VOICE 0x03 287 #define PCI_SUBCLASS_SATCOM_DATA 0x04 288 289 /* 0x10 encryption/decryption subclasses */ 290 #define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00 291 #define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10 292 #define PCI_SUBCLASS_CRYPTO_MISC 0x80 293 294 /* 0x11 data acquisition and signal processing subclasses */ 295 #define PCI_SUBCLASS_DASP_DPIO 0x00 296 #define PCI_SUBCLASS_DASP_TIMEFREQ 0x01 297 #define PCI_SUBCLASS_DASP_SYNC 0x10 298 #define PCI_SUBCLASS_DASP_MGMT 0x20 299 #define PCI_SUBCLASS_DASP_MISC 0x80 300 301 /* 302 * PCI BIST/Header Type/Latency Timer/Cache Line Size Register. 303 */ 304 #define PCI_BHLC_REG 0x0c 305 306 #define PCI_BIST_SHIFT 24 307 #define PCI_BIST_MASK 0xff 308 #define PCI_BIST(bhlcr) \ 309 (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK) 310 311 #define PCI_HDRTYPE_SHIFT 16 312 #define PCI_HDRTYPE_MASK 0xff 313 #define PCI_HDRTYPE(bhlcr) \ 314 (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK) 315 316 #define PCI_HDRTYPE_TYPE(bhlcr) \ 317 (PCI_HDRTYPE(bhlcr) & 0x7f) 318 #define PCI_HDRTYPE_MULTIFN(bhlcr) \ 319 ((PCI_HDRTYPE(bhlcr) & 0x80) != 0) 320 321 #define PCI_LATTIMER_SHIFT 8 322 #define PCI_LATTIMER_MASK 0xff 323 #define PCI_LATTIMER(bhlcr) \ 324 (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK) 325 326 #define PCI_CACHELINE_SHIFT 0 327 #define PCI_CACHELINE_MASK 0xff 328 #define PCI_CACHELINE(bhlcr) \ 329 (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK) 330 331 #define PCI_BHLC_CODE(bist,type,multi,latency,cacheline) \ 332 ((((bist) & PCI_BIST_MASK) << PCI_BIST_SHIFT) | \ 333 (((type) & PCI_HDRTYPE_MASK) << PCI_HDRTYPE_SHIFT) | \ 334 (((multi)?0x80:0) << PCI_HDRTYPE_SHIFT) | \ 335 (((latency) & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT) | \ 336 (((cacheline) & PCI_CACHELINE_MASK) << PCI_CACHELINE_SHIFT)) 337 338 /* 339 * PCI header type 340 */ 341 #define PCI_HDRTYPE_DEVICE 0 342 #define PCI_HDRTYPE_PPB 1 343 #define PCI_HDRTYPE_PCB 2 344 345 /* 346 * Mapping registers 347 */ 348 #define PCI_MAPREG_START 0x10 349 #define PCI_MAPREG_END 0x28 350 #define PCI_MAPREG_ROM 0x30 351 #define PCI_MAPREG_PPB_END 0x18 352 #define PCI_MAPREG_PCB_END 0x14 353 354 #define PCI_MAPREG_TYPE(mr) \ 355 ((mr) & PCI_MAPREG_TYPE_MASK) 356 #define PCI_MAPREG_TYPE_MASK 0x00000001 357 358 #define PCI_MAPREG_TYPE_MEM 0x00000000 359 #define PCI_MAPREG_TYPE_ROM 0x00000000 360 #define PCI_MAPREG_TYPE_IO 0x00000001 361 #define PCI_MAPREG_ROM_ENABLE 0x00000001 362 363 #define PCI_MAPREG_MEM_TYPE(mr) \ 364 ((mr) & PCI_MAPREG_MEM_TYPE_MASK) 365 #define PCI_MAPREG_MEM_TYPE_MASK 0x00000006 366 367 #define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000 368 #define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002 369 #define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 370 371 #define PCI_MAPREG_MEM_PREFETCHABLE(mr) \ 372 (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0) 373 #define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008 374 375 #define PCI_MAPREG_MEM_ADDR(mr) \ 376 ((mr) & PCI_MAPREG_MEM_ADDR_MASK) 377 #define PCI_MAPREG_MEM_SIZE(mr) \ 378 (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr)) 379 #define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 380 381 #define PCI_MAPREG_MEM64_ADDR(mr) \ 382 ((mr) & PCI_MAPREG_MEM64_ADDR_MASK) 383 #define PCI_MAPREG_MEM64_SIZE(mr) \ 384 (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr)) 385 #define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL 386 387 #define PCI_MAPREG_IO_ADDR(mr) \ 388 ((mr) & PCI_MAPREG_IO_ADDR_MASK) 389 #define PCI_MAPREG_IO_SIZE(mr) \ 390 (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) 391 #define PCI_MAPREG_IO_ADDR_MASK 0xfffffffc 392 393 #define PCI_MAPREG_SIZE_TO_MASK(size) \ 394 (-(size)) 395 396 #define PCI_MAPREG_NUM(offset) \ 397 (((unsigned)(offset)-PCI_MAPREG_START)/4) 398 399 400 /* 401 * Cardbus CIS pointer (PCI rev. 2.1) 402 */ 403 #define PCI_CARDBUS_CIS_REG 0x28 404 405 /* 406 * Subsystem identification register; contains a vendor ID and a device ID. 407 * Types/macros for PCI_ID_REG apply. 408 * (PCI rev. 2.1) 409 */ 410 #define PCI_SUBSYS_ID_REG 0x2c 411 412 /* 413 * Capabilities link list (PCI rev. 2.2) 414 */ 415 #define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */ 416 #define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */ 417 #define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff) 418 #define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff) 419 #define PCI_CAPLIST_CAP(cr) ((cr) & 0xff) 420 421 #define PCI_CAP_RESERVED0 0x00 422 #define PCI_CAP_PWRMGMT 0x01 423 #define PCI_CAP_AGP 0x02 424 #define PCI_CAP_AGP_MAJOR(cr) (((cr) >> 20) & 0xf) 425 #define PCI_CAP_AGP_MINOR(cr) (((cr) >> 16) & 0xf) 426 #define PCI_CAP_VPD 0x03 427 #define PCI_CAP_SLOTID 0x04 428 #define PCI_CAP_MSI 0x05 429 #define PCI_CAP_CPCI_HOTSWAP 0x06 430 #define PCI_CAP_PCIX 0x07 431 #define PCI_CAP_LDT 0x08 432 #define PCI_CAP_VENDSPEC 0x09 433 #define PCI_CAP_DEBUGPORT 0x0a 434 #define PCI_CAP_CPCI_RSRCCTL 0x0b 435 #define PCI_CAP_HOTPLUG 0x0c 436 #define PCI_CAP_AGP8 0x0e 437 #define PCI_CAP_SECURE 0x0f 438 #define PCI_CAP_PCIEXPRESS 0x10 439 #define PCI_CAP_MSIX 0x11 440 441 /* 442 * Vital Product Data; access via capability pointer (PCI rev 2.2). 443 */ 444 #define PCI_VPD_ADDRESS_MASK 0x7fff 445 #define PCI_VPD_ADDRESS_SHIFT 16 446 #define PCI_VPD_ADDRESS(ofs) \ 447 (((ofs) & PCI_VPD_ADDRESS_MASK) << PCI_VPD_ADDRESS_SHIFT) 448 #define PCI_VPD_DATAREG(ofs) ((ofs) + 4) 449 #define PCI_VPD_OPFLAG 0x80000000 450 451 /* 452 * Power Management Capability; access via capability pointer. 453 */ 454 455 /* Power Management Capability Register */ 456 #define PCI_PMCR_SHIFT 16 457 #define PCI_PMCR 0x02 458 #define PCI_PMCR_D1SUPP 0x0200 459 #define PCI_PMCR_D2SUPP 0x0400 460 /* Power Management Control Status Register */ 461 #define PCI_PMCSR 0x04 462 #define PCI_PMCSR_PME_EN 0x100 463 #define PCI_PMCSR_STATE_MASK 0x03 464 #define PCI_PMCSR_STATE_D0 0x00 465 #define PCI_PMCSR_STATE_D1 0x01 466 #define PCI_PMCSR_STATE_D2 0x02 467 #define PCI_PMCSR_STATE_D3 0x03 468 469 /* 470 * PCI-X capability. 471 */ 472 473 /* 474 * Command. 16 bits at offset 2 (e.g. upper 16 bits of the first 32-bit 475 * word at the capability; the lower 16 bits are the capability ID and 476 * next capability pointer). 477 * 478 * Since we always read PCI config space in 32-bit words, we define these 479 * as 32-bit values, offset and shifted appropriately. Make sure you perform 480 * the appropriate R/M/W cycles! 481 */ 482 #define PCI_PCIX_CMD 0x00 483 #define PCI_PCIX_CMD_PERR_RECOVER 0x00010000 484 #define PCI_PCIX_CMD_RELAXED_ORDER 0x00020000 485 #define PCI_PCIX_CMD_BYTECNT_MASK 0x000c0000 486 #define PCI_PCIX_CMD_BYTECNT_SHIFT 18 487 #define PCI_PCIX_CMD_BCNT_512 0x00000000 488 #define PCI_PCIX_CMD_BCNT_1024 0x00040000 489 #define PCI_PCIX_CMD_BCNT_2048 0x00080000 490 #define PCI_PCIX_CMD_BCNT_4096 0x000c0000 491 #define PCI_PCIX_CMD_SPLTRANS_MASK 0x00700000 492 #define PCI_PCIX_CMD_SPLTRANS_1 0x00000000 493 #define PCI_PCIX_CMD_SPLTRANS_2 0x00100000 494 #define PCI_PCIX_CMD_SPLTRANS_3 0x00200000 495 #define PCI_PCIX_CMD_SPLTRANS_4 0x00300000 496 #define PCI_PCIX_CMD_SPLTRANS_8 0x00400000 497 #define PCI_PCIX_CMD_SPLTRANS_12 0x00500000 498 #define PCI_PCIX_CMD_SPLTRANS_16 0x00600000 499 #define PCI_PCIX_CMD_SPLTRANS_32 0x00700000 500 501 /* 502 * Status. 32 bits at offset 4. 503 */ 504 #define PCI_PCIX_STATUS 0x04 505 #define PCI_PCIX_STATUS_FN_MASK 0x00000007 506 #define PCI_PCIX_STATUS_DEV_MASK 0x000000f8 507 #define PCI_PCIX_STATUS_BUS_MASK 0x0000ff00 508 #define PCI_PCIX_STATUS_64BIT 0x00010000 509 #define PCI_PCIX_STATUS_133 0x00020000 510 #define PCI_PCIX_STATUS_SPLDISC 0x00040000 511 #define PCI_PCIX_STATUS_SPLUNEX 0x00080000 512 #define PCI_PCIX_STATUS_DEVCPLX 0x00100000 513 #define PCI_PCIX_STATUS_MAXB_MASK 0x00600000 514 #define PCI_PCIX_STATUS_MAXB_SHIFT 21 515 #define PCI_PCIX_STATUS_MAXB_512 0x00000000 516 #define PCI_PCIX_STATUS_MAXB_1024 0x00200000 517 #define PCI_PCIX_STATUS_MAXB_2048 0x00400000 518 #define PCI_PCIX_STATUS_MAXB_4096 0x00600000 519 #define PCI_PCIX_STATUS_MAXST_MASK 0x03800000 520 #define PCI_PCIX_STATUS_MAXST_1 0x00000000 521 #define PCI_PCIX_STATUS_MAXST_2 0x00800000 522 #define PCI_PCIX_STATUS_MAXST_3 0x01000000 523 #define PCI_PCIX_STATUS_MAXST_4 0x01800000 524 #define PCI_PCIX_STATUS_MAXST_8 0x02000000 525 #define PCI_PCIX_STATUS_MAXST_12 0x02800000 526 #define PCI_PCIX_STATUS_MAXST_16 0x03000000 527 #define PCI_PCIX_STATUS_MAXST_32 0x03800000 528 #define PCI_PCIX_STATUS_MAXRS_MASK 0x1c000000 529 #define PCI_PCIX_STATUS_MAXRS_1K 0x00000000 530 #define PCI_PCIX_STATUS_MAXRS_2K 0x04000000 531 #define PCI_PCIX_STATUS_MAXRS_4K 0x08000000 532 #define PCI_PCIX_STATUS_MAXRS_8K 0x0c000000 533 #define PCI_PCIX_STATUS_MAXRS_16K 0x10000000 534 #define PCI_PCIX_STATUS_MAXRS_32K 0x14000000 535 #define PCI_PCIX_STATUS_MAXRS_64K 0x18000000 536 #define PCI_PCIX_STATUS_MAXRS_128K 0x1c000000 537 #define PCI_PCIX_STATUS_SCERR 0x20000000 538 539 540 /* 541 * Interrupt Configuration Register; contains interrupt pin and line. 542 */ 543 #define PCI_INTERRUPT_REG 0x3c 544 545 typedef u_int8_t pci_intr_latency_t; 546 typedef u_int8_t pci_intr_grant_t; 547 typedef u_int8_t pci_intr_pin_t; 548 typedef u_int8_t pci_intr_line_t; 549 550 #define PCI_MAX_LAT_SHIFT 24 551 #define PCI_MAX_LAT_MASK 0xff 552 #define PCI_MAX_LAT(icr) \ 553 (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK) 554 555 #define PCI_MIN_GNT_SHIFT 16 556 #define PCI_MIN_GNT_MASK 0xff 557 #define PCI_MIN_GNT(icr) \ 558 (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK) 559 560 #define PCI_INTERRUPT_GRANT_SHIFT 24 561 #define PCI_INTERRUPT_GRANT_MASK 0xff 562 #define PCI_INTERRUPT_GRANT(icr) \ 563 (((icr) >> PCI_INTERRUPT_GRANT_SHIFT) & PCI_INTERRUPT_GRANT_MASK) 564 565 #define PCI_INTERRUPT_LATENCY_SHIFT 16 566 #define PCI_INTERRUPT_LATENCY_MASK 0xff 567 #define PCI_INTERRUPT_LATENCY(icr) \ 568 (((icr) >> PCI_INTERRUPT_LATENCY_SHIFT) & PCI_INTERRUPT_LATENCY_MASK) 569 570 #define PCI_INTERRUPT_PIN_SHIFT 8 571 #define PCI_INTERRUPT_PIN_MASK 0xff 572 #define PCI_INTERRUPT_PIN(icr) \ 573 (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK) 574 575 #define PCI_INTERRUPT_LINE_SHIFT 0 576 #define PCI_INTERRUPT_LINE_MASK 0xff 577 #define PCI_INTERRUPT_LINE(icr) \ 578 (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK) 579 580 #define PCI_INTERRUPT_CODE(lat,gnt,pin,line) \ 581 ((((lat)&PCI_INTERRUPT_LATENCY_MASK)<<PCI_INTERRUPT_LATENCY_SHIFT)| \ 582 (((gnt)&PCI_INTERRUPT_GRANT_MASK) <<PCI_INTERRUPT_GRANT_SHIFT) | \ 583 (((pin)&PCI_INTERRUPT_PIN_MASK) <<PCI_INTERRUPT_PIN_SHIFT) | \ 584 (((line)&PCI_INTERRUPT_LINE_MASK) <<PCI_INTERRUPT_LINE_SHIFT)) 585 586 #define PCI_INTERRUPT_PIN_NONE 0x00 587 #define PCI_INTERRUPT_PIN_A 0x01 588 #define PCI_INTERRUPT_PIN_B 0x02 589 #define PCI_INTERRUPT_PIN_C 0x03 590 #define PCI_INTERRUPT_PIN_D 0x04 591 #define PCI_INTERRUPT_PIN_MAX 0x04 592 593 /* Header Type 1 (Bridge) configuration registers */ 594 #define PCI_BRIDGE_BUS_REG 0x18 595 #define PCI_BRIDGE_BUS_PRIMARY_SHIFT 0 596 #define PCI_BRIDGE_BUS_SECONDARY_SHIFT 8 597 #define PCI_BRIDGE_BUS_SUBORDINATE_SHIFT 16 598 599 #define PCI_BRIDGE_STATIO_REG 0x1C 600 #define PCI_BRIDGE_STATIO_IOBASE_SHIFT 0 601 #define PCI_BRIDGE_STATIO_IOLIMIT_SHIFT 8 602 #define PCI_BRIDGE_STATIO_STATUS_SHIFT 16 603 #define PCI_BRIDGE_STATIO_IOBASE_MASK 0xf0 604 #define PCI_BRIDGE_STATIO_IOLIMIT_MASK 0xf0 605 #define PCI_BRIDGE_STATIO_STATUS_MASK 0xffff 606 #define PCI_BRIDGE_IO_32BITS(reg) (((reg) & 0xf) == 1) 607 608 #define PCI_BRIDGE_MEMORY_REG 0x20 609 #define PCI_BRIDGE_MEMORY_BASE_SHIFT 4 610 #define PCI_BRIDGE_MEMORY_LIMIT_SHIFT 20 611 #define PCI_BRIDGE_MEMORY_BASE_MASK 0x0fff 612 #define PCI_BRIDGE_MEMORY_LIMIT_MASK 0x0fff 613 614 #define PCI_BRIDGE_PREFETCHMEM_REG 0x24 615 #define PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT 4 616 #define PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT 20 617 #define PCI_BRIDGE_PREFETCHMEM_BASE_MASK 0x0fff 618 #define PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK 0x0fff 619 #define PCI_BRIDGE_PREFETCHMEM_64BITS(reg) ((reg) & 0xf) 620 621 #define PCI_BRIDGE_PREFETCHBASE32_REG 0x28 622 #define PCI_BRIDGE_PREFETCHLIMIT32_REG 0x2C 623 624 #define PCI_BRIDGE_IOHIGH_REG 0x30 625 #define PCI_BRIDGE_IOHIGH_BASE_SHIFT 0 626 #define PCI_BRIDGE_IOHIGH_LIMIT_SHIFT 16 627 #define PCI_BRIDGE_IOHIGH_BASE_MASK 0xffff 628 #define PCI_BRIDGE_IOHIGH_LIMIT_MASK 0xffff 629 630 #define PCI_BRIDGE_CONTROL_REG 0x3C 631 #define PCI_BRIDGE_CONTROL_SHIFT 16 632 #define PCI_BRIDGE_CONTROL_MASK 0xffff 633 #define PCI_BRIDGE_CONTROL_PERE (1 << 0) 634 #define PCI_BRIDGE_CONTROL_SERR (1 << 1) 635 #define PCI_BRIDGE_CONTROL_ISA (1 << 2) 636 #define PCI_BRIDGE_CONTROL_VGA (1 << 3) 637 /* Reserved (1 << 4) */ 638 #define PCI_BRIDGE_CONTROL_MABRT (1 << 5) 639 #define PCI_BRIDGE_CONTROL_SECBR (1 << 6) 640 #define PCI_BRIDGE_CONTROL_SECFASTB2B (1 << 7) 641 #define PCI_BRIDGE_CONTROL_PRI_DISC_TIMER (1 << 8) 642 #define PCI_BRIDGE_CONTROL_SEC_DISC_TIMER (1 << 9) 643 #define PCI_BRIDGE_CONTROL_DISC_TIMER_STAT (1 << 10) 644 #define PCI_BRIDGE_CONTROL_DISC_TIMER_SERR (1 << 11) 645 /* Reserved (1 << 12) - (1 << 15) */ 646 647 /* 648 * Vital Product Data resource tags. 649 */ 650 struct pci_vpd_smallres { 651 uint8_t vpdres_byte0; /* length of data + tag */ 652 /* Actual data. */ 653 } __attribute__((__packed__)); 654 655 struct pci_vpd_largeres { 656 uint8_t vpdres_byte0; 657 uint8_t vpdres_len_lsb; /* length of data only */ 658 uint8_t vpdres_len_msb; 659 /* Actual data. */ 660 } __attribute__((__packed__)); 661 662 #define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) 663 664 #define PCI_VPDRES_SMALL_LENGTH(x) ((x) & 0x7) 665 #define PCI_VPDRES_SMALL_NAME(x) (((x) >> 3) & 0xf) 666 667 #define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) 668 669 #define PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID 0x3 /* small */ 670 #define PCI_VPDRES_TYPE_VENDOR_DEFINED 0xe /* small */ 671 #define PCI_VPDRES_TYPE_END_TAG 0xf /* small */ 672 673 #define PCI_VPDRES_TYPE_IDENTIFIER_STRING 0x02 /* large */ 674 #define PCI_VPDRES_TYPE_VPD 0x10 /* large */ 675 676 struct pci_vpd { 677 uint8_t vpd_key0; 678 uint8_t vpd_key1; 679 uint8_t vpd_len; /* length of data only */ 680 /* Actual data. */ 681 } __attribute__((__packed__)); 682 683 /* 684 * Recommended VPD fields: 685 * 686 * PN Part number of assembly 687 * FN FRU part number 688 * EC EC level of assembly 689 * MN Manufacture ID 690 * SN Serial Number 691 * 692 * Conditionally recommended VPD fields: 693 * 694 * LI Load ID 695 * RL ROM Level 696 * RM Alterable ROM Level 697 * NA Network Address 698 * DD Device Driver Level 699 * DG Diagnostic Level 700 * LL Loadable Microcode Level 701 * VI Vendor ID/Device ID 702 * FU Function Number 703 * SI Subsystem Vendor ID/Subsystem ID 704 * 705 * Additional VPD fields: 706 * 707 * Z0-ZZ User/Product Specific 708 */ 709 710 /* 711 * PCI Expansion Rom 712 */ 713 714 struct pci_rom_header { 715 uint16_t romh_magic; /* 0xAA55 little endian */ 716 uint8_t romh_reserved[22]; 717 uint16_t romh_data_ptr; /* pointer to pci_rom struct */ 718 } __attribute__((__packed__)); 719 720 #define PCI_ROM_HEADER_MAGIC 0xAA55 /* little endian */ 721 722 struct pci_rom { 723 uint32_t rom_signature; 724 pci_vendor_id_t rom_vendor; 725 pci_product_id_t rom_product; 726 uint16_t rom_vpd_ptr; /* reserved in PCI 2.2 */ 727 uint16_t rom_data_len; 728 uint8_t rom_data_rev; 729 pci_interface_t rom_interface; /* the class reg is 24-bits */ 730 pci_subclass_t rom_subclass; /* in little endian */ 731 pci_class_t rom_class; 732 uint16_t rom_len; /* code length / 512 byte */ 733 uint16_t rom_rev; /* code revision level */ 734 uint8_t rom_code_type; /* type of code */ 735 uint8_t rom_indicator; 736 uint16_t rom_reserved; 737 /* Actual data. */ 738 } __attribute__((__packed__)); 739 740 #define PCI_ROM_SIGNATURE 0x52494350 /* "PCIR", endian reversed */ 741 #define PCI_ROM_CODE_TYPE_X86 0 /* Intel x86 BIOS */ 742 #define PCI_ROM_CODE_TYPE_OFW 1 /* Open Firmware */ 743 #define PCI_ROM_CODE_TYPE_HPPA 2 /* HP PA/RISC */ 744 745 #define PCI_ROM_INDICATOR_LAST 0x80 746 747 /* 748 * Threshold below which 32bit PCI DMA needs bouncing. 749 */ 750 #define PCI32_DMA_BOUNCE_THRESHOLD 0x100000000ULL 751 752 /* 753 * Common PCI register for PCI transmit handling. 754 */ 755 #define PCI_RETRY_TIMEOUT_REG 0x40 756 #define PCI_RETRY_TIMEOUT_REG_MASK 0x0000ff00 757 758 #endif /* _DEV_PCI_PCIREG_H_ */ 759