1 /* $NetBSD: pcireg.h,v 1.63 2010/02/01 05:38:36 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1999, 2000 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _DEV_PCI_PCIREG_H_ 35 #define _DEV_PCI_PCIREG_H_ 36 37 /* 38 * Standardized PCI configuration information 39 * 40 * XXX This is not complete. 41 */ 42 43 /* 44 * Size of each function's configuration space. 45 */ 46 47 #define PCI_CONF_SIZE 0x100 48 #define PCI_EXTCONF_SIZE 0x1000 49 50 /* 51 * Device identification register; contains a vendor ID and a device ID. 52 */ 53 #define PCI_ID_REG 0x00 54 55 typedef u_int16_t pci_vendor_id_t; 56 typedef u_int16_t pci_product_id_t; 57 58 #define PCI_VENDOR_SHIFT 0 59 #define PCI_VENDOR_MASK 0xffff 60 #define PCI_VENDOR(id) \ 61 (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK) 62 63 #define PCI_PRODUCT_SHIFT 16 64 #define PCI_PRODUCT_MASK 0xffff 65 #define PCI_PRODUCT(id) \ 66 (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) 67 68 #define PCI_ID_CODE(vid,pid) \ 69 ((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) | \ 70 (((pid) & PCI_PRODUCT_MASK) << PCI_PRODUCT_SHIFT)) \ 71 72 /* 73 * Command and status register. 74 */ 75 #define PCI_COMMAND_STATUS_REG 0x04 76 #define PCI_COMMAND_SHIFT 0 77 #define PCI_COMMAND_MASK 0xffff 78 #define PCI_STATUS_SHIFT 16 79 #define PCI_STATUS_MASK 0xffff 80 81 #define PCI_COMMAND_STATUS_CODE(cmd,stat) \ 82 ((((cmd) & PCI_COMMAND_MASK) << PCI_COMMAND_SHIFT) | \ 83 (((stat) & PCI_STATUS_MASK) << PCI_STATUS_SHIFT)) \ 84 85 #define PCI_COMMAND_IO_ENABLE 0x00000001 86 #define PCI_COMMAND_MEM_ENABLE 0x00000002 87 #define PCI_COMMAND_MASTER_ENABLE 0x00000004 88 #define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 89 #define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 90 #define PCI_COMMAND_PALETTE_ENABLE 0x00000020 91 #define PCI_COMMAND_PARITY_ENABLE 0x00000040 92 #define PCI_COMMAND_STEPPING_ENABLE 0x00000080 93 #define PCI_COMMAND_SERR_ENABLE 0x00000100 94 #define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 95 #define PCI_COMMAND_INTERRUPT_DISABLE 0x00000400 96 97 #define PCI_STATUS_CAPLIST_SUPPORT 0x00100000 98 #define PCI_STATUS_66MHZ_SUPPORT 0x00200000 99 #define PCI_STATUS_UDF_SUPPORT 0x00400000 100 #define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000 101 #define PCI_STATUS_PARITY_ERROR 0x01000000 102 #define PCI_STATUS_DEVSEL_FAST 0x00000000 103 #define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 104 #define PCI_STATUS_DEVSEL_SLOW 0x04000000 105 #define PCI_STATUS_DEVSEL_MASK 0x06000000 106 #define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 107 #define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 108 #define PCI_STATUS_MASTER_ABORT 0x20000000 109 #define PCI_STATUS_SPECIAL_ERROR 0x40000000 110 #define PCI_STATUS_PARITY_DETECT 0x80000000 111 112 /* 113 * PCI Class and Revision Register; defines type and revision of device. 114 */ 115 #define PCI_CLASS_REG 0x08 116 117 typedef u_int8_t pci_class_t; 118 typedef u_int8_t pci_subclass_t; 119 typedef u_int8_t pci_interface_t; 120 typedef u_int8_t pci_revision_t; 121 122 #define PCI_CLASS_SHIFT 24 123 #define PCI_CLASS_MASK 0xff 124 #define PCI_CLASS(cr) \ 125 (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) 126 127 #define PCI_SUBCLASS_SHIFT 16 128 #define PCI_SUBCLASS_MASK 0xff 129 #define PCI_SUBCLASS(cr) \ 130 (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) 131 132 #define PCI_INTERFACE_SHIFT 8 133 #define PCI_INTERFACE_MASK 0xff 134 #define PCI_INTERFACE(cr) \ 135 (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) 136 137 #define PCI_REVISION_SHIFT 0 138 #define PCI_REVISION_MASK 0xff 139 #define PCI_REVISION(cr) \ 140 (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) 141 142 #define PCI_CLASS_CODE(mainclass, subclass, interface) \ 143 ((((mainclass) & PCI_CLASS_MASK) << PCI_CLASS_SHIFT) | \ 144 (((subclass) & PCI_SUBCLASS_MASK) << PCI_SUBCLASS_SHIFT) | \ 145 (((interface) & PCI_INTERFACE_MASK) << PCI_INTERFACE_SHIFT)) 146 147 /* base classes */ 148 #define PCI_CLASS_PREHISTORIC 0x00 149 #define PCI_CLASS_MASS_STORAGE 0x01 150 #define PCI_CLASS_NETWORK 0x02 151 #define PCI_CLASS_DISPLAY 0x03 152 #define PCI_CLASS_MULTIMEDIA 0x04 153 #define PCI_CLASS_MEMORY 0x05 154 #define PCI_CLASS_BRIDGE 0x06 155 #define PCI_CLASS_COMMUNICATIONS 0x07 156 #define PCI_CLASS_SYSTEM 0x08 157 #define PCI_CLASS_INPUT 0x09 158 #define PCI_CLASS_DOCK 0x0a 159 #define PCI_CLASS_PROCESSOR 0x0b 160 #define PCI_CLASS_SERIALBUS 0x0c 161 #define PCI_CLASS_WIRELESS 0x0d 162 #define PCI_CLASS_I2O 0x0e 163 #define PCI_CLASS_SATCOM 0x0f 164 #define PCI_CLASS_CRYPTO 0x10 165 #define PCI_CLASS_DASP 0x11 166 #define PCI_CLASS_UNDEFINED 0xff 167 168 /* 0x00 prehistoric subclasses */ 169 #define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 170 #define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 171 172 /* 0x01 mass storage subclasses */ 173 #define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 174 #define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 175 #define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 176 #define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 177 #define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04 178 #define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05 179 #define PCI_SUBCLASS_MASS_STORAGE_SATA 0x06 180 #define PCI_SUBCLASS_MASS_STORAGE_SAS 0x07 181 #define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 182 183 /* 0x02 network subclasses */ 184 #define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 185 #define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 186 #define PCI_SUBCLASS_NETWORK_FDDI 0x02 187 #define PCI_SUBCLASS_NETWORK_ATM 0x03 188 #define PCI_SUBCLASS_NETWORK_ISDN 0x04 189 #define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05 190 #define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06 191 #define PCI_SUBCLASS_NETWORK_MISC 0x80 192 193 /* 0x03 display subclasses */ 194 #define PCI_SUBCLASS_DISPLAY_VGA 0x00 195 #define PCI_SUBCLASS_DISPLAY_XGA 0x01 196 #define PCI_SUBCLASS_DISPLAY_3D 0x02 197 #define PCI_SUBCLASS_DISPLAY_MISC 0x80 198 199 /* 0x04 multimedia subclasses */ 200 #define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 201 #define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 202 #define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02 203 #define PCI_SUBCLASS_MULTIMEDIA_HDAUDIO 0x03 204 #define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 205 206 /* 0x05 memory subclasses */ 207 #define PCI_SUBCLASS_MEMORY_RAM 0x00 208 #define PCI_SUBCLASS_MEMORY_FLASH 0x01 209 #define PCI_SUBCLASS_MEMORY_MISC 0x80 210 211 /* 0x06 bridge subclasses */ 212 #define PCI_SUBCLASS_BRIDGE_HOST 0x00 213 #define PCI_SUBCLASS_BRIDGE_ISA 0x01 214 #define PCI_SUBCLASS_BRIDGE_EISA 0x02 215 #define PCI_SUBCLASS_BRIDGE_MC 0x03 /* XXX _MCA? */ 216 #define PCI_SUBCLASS_BRIDGE_PCI 0x04 217 #define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 218 #define PCI_SUBCLASS_BRIDGE_NUBUS 0x06 219 #define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 220 #define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08 221 #define PCI_SUBCLASS_BRIDGE_STPCI 0x09 222 #define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a 223 #define PCI_SUBCLASS_BRIDGE_MISC 0x80 224 225 /* 0x07 communications subclasses */ 226 #define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 227 #define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 228 #define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02 229 #define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03 230 #define PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04 231 #define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05 232 #define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 233 234 /* 0x08 system subclasses */ 235 #define PCI_SUBCLASS_SYSTEM_PIC 0x00 236 #define PCI_SUBCLASS_SYSTEM_DMA 0x01 237 #define PCI_SUBCLASS_SYSTEM_TIMER 0x02 238 #define PCI_SUBCLASS_SYSTEM_RTC 0x03 239 #define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04 240 #define PCI_SUBCLASS_SYSTEM_SDHC 0x05 241 #define PCI_SUBCLASS_SYSTEM_MISC 0x80 242 243 /* 0x09 input subclasses */ 244 #define PCI_SUBCLASS_INPUT_KEYBOARD 0x00 245 #define PCI_SUBCLASS_INPUT_DIGITIZER 0x01 246 #define PCI_SUBCLASS_INPUT_MOUSE 0x02 247 #define PCI_SUBCLASS_INPUT_SCANNER 0x03 248 #define PCI_SUBCLASS_INPUT_GAMEPORT 0x04 249 #define PCI_SUBCLASS_INPUT_MISC 0x80 250 251 /* 0x0a dock subclasses */ 252 #define PCI_SUBCLASS_DOCK_GENERIC 0x00 253 #define PCI_SUBCLASS_DOCK_MISC 0x80 254 255 /* 0x0b processor subclasses */ 256 #define PCI_SUBCLASS_PROCESSOR_386 0x00 257 #define PCI_SUBCLASS_PROCESSOR_486 0x01 258 #define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02 259 #define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10 260 #define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20 261 #define PCI_SUBCLASS_PROCESSOR_MIPS 0x30 262 #define PCI_SUBCLASS_PROCESSOR_COPROC 0x40 263 264 /* 0x0c serial bus subclasses */ 265 #define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00 266 #define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01 267 #define PCI_SUBCLASS_SERIALBUS_SSA 0x02 268 #define PCI_SUBCLASS_SERIALBUS_USB 0x03 269 #define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 /* XXX _FIBRECHANNEL */ 270 #define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05 271 #define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06 272 #define PCI_SUBCLASS_SERIALBUS_IPMI 0x07 273 #define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08 274 #define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09 275 276 /* 0x0d wireless subclasses */ 277 #define PCI_SUBCLASS_WIRELESS_IRDA 0x00 278 #define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01 279 #define PCI_SUBCLASS_WIRELESS_RF 0x10 280 #define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11 281 #define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12 282 #define PCI_SUBCLASS_WIRELESS_802_11A 0x20 283 #define PCI_SUBCLASS_WIRELESS_802_11B 0x21 284 #define PCI_SUBCLASS_WIRELESS_MISC 0x80 285 286 /* 0x0e I2O (Intelligent I/O) subclasses */ 287 #define PCI_SUBCLASS_I2O_STANDARD 0x00 288 289 /* 0x0f satellite communication subclasses */ 290 /* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */ 291 #define PCI_SUBCLASS_SATCOM_TV 0x01 292 #define PCI_SUBCLASS_SATCOM_AUDIO 0x02 293 #define PCI_SUBCLASS_SATCOM_VOICE 0x03 294 #define PCI_SUBCLASS_SATCOM_DATA 0x04 295 296 /* 0x10 encryption/decryption subclasses */ 297 #define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00 298 #define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10 299 #define PCI_SUBCLASS_CRYPTO_MISC 0x80 300 301 /* 0x11 data acquisition and signal processing subclasses */ 302 #define PCI_SUBCLASS_DASP_DPIO 0x00 303 #define PCI_SUBCLASS_DASP_TIMEFREQ 0x01 304 #define PCI_SUBCLASS_DASP_SYNC 0x10 305 #define PCI_SUBCLASS_DASP_MGMT 0x20 306 #define PCI_SUBCLASS_DASP_MISC 0x80 307 308 /* 309 * PCI BIST/Header Type/Latency Timer/Cache Line Size Register. 310 */ 311 #define PCI_BHLC_REG 0x0c 312 313 #define PCI_BIST_SHIFT 24 314 #define PCI_BIST_MASK 0xff 315 #define PCI_BIST(bhlcr) \ 316 (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK) 317 318 #define PCI_HDRTYPE_SHIFT 16 319 #define PCI_HDRTYPE_MASK 0xff 320 #define PCI_HDRTYPE(bhlcr) \ 321 (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK) 322 323 #define PCI_HDRTYPE_TYPE(bhlcr) \ 324 (PCI_HDRTYPE(bhlcr) & 0x7f) 325 #define PCI_HDRTYPE_MULTIFN(bhlcr) \ 326 ((PCI_HDRTYPE(bhlcr) & 0x80) != 0) 327 328 #define PCI_LATTIMER_SHIFT 8 329 #define PCI_LATTIMER_MASK 0xff 330 #define PCI_LATTIMER(bhlcr) \ 331 (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK) 332 333 #define PCI_CACHELINE_SHIFT 0 334 #define PCI_CACHELINE_MASK 0xff 335 #define PCI_CACHELINE(bhlcr) \ 336 (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK) 337 338 #define PCI_BHLC_CODE(bist,type,multi,latency,cacheline) \ 339 ((((bist) & PCI_BIST_MASK) << PCI_BIST_SHIFT) | \ 340 (((type) & PCI_HDRTYPE_MASK) << PCI_HDRTYPE_SHIFT) | \ 341 (((multi)?0x80:0) << PCI_HDRTYPE_SHIFT) | \ 342 (((latency) & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT) | \ 343 (((cacheline) & PCI_CACHELINE_MASK) << PCI_CACHELINE_SHIFT)) 344 345 /* 346 * PCI header type 347 */ 348 #define PCI_HDRTYPE_DEVICE 0 349 #define PCI_HDRTYPE_PPB 1 350 #define PCI_HDRTYPE_PCB 2 351 352 /* 353 * Mapping registers 354 */ 355 #define PCI_MAPREG_START 0x10 356 #define PCI_MAPREG_END 0x28 357 #define PCI_MAPREG_ROM 0x30 358 #define PCI_MAPREG_PPB_END 0x18 359 #define PCI_MAPREG_PCB_END 0x14 360 361 #define PCI_MAPREG_TYPE(mr) \ 362 ((mr) & PCI_MAPREG_TYPE_MASK) 363 #define PCI_MAPREG_TYPE_MASK 0x00000001 364 365 #define PCI_MAPREG_TYPE_MEM 0x00000000 366 #define PCI_MAPREG_TYPE_ROM 0x00000000 367 #define PCI_MAPREG_TYPE_IO 0x00000001 368 #define PCI_MAPREG_ROM_ENABLE 0x00000001 369 370 #define PCI_MAPREG_MEM_TYPE(mr) \ 371 ((mr) & PCI_MAPREG_MEM_TYPE_MASK) 372 #define PCI_MAPREG_MEM_TYPE_MASK 0x00000006 373 374 #define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000 375 #define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002 376 #define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 377 378 #define PCI_MAPREG_MEM_PREFETCHABLE(mr) \ 379 (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0) 380 #define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008 381 382 #define PCI_MAPREG_MEM_ADDR(mr) \ 383 ((mr) & PCI_MAPREG_MEM_ADDR_MASK) 384 #define PCI_MAPREG_MEM_SIZE(mr) \ 385 (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr)) 386 #define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 387 388 #define PCI_MAPREG_MEM64_ADDR(mr) \ 389 ((mr) & PCI_MAPREG_MEM64_ADDR_MASK) 390 #define PCI_MAPREG_MEM64_SIZE(mr) \ 391 (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr)) 392 #define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL 393 394 #define PCI_MAPREG_IO_ADDR(mr) \ 395 ((mr) & PCI_MAPREG_IO_ADDR_MASK) 396 #define PCI_MAPREG_IO_SIZE(mr) \ 397 (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) 398 #define PCI_MAPREG_IO_ADDR_MASK 0xfffffffc 399 400 #define PCI_MAPREG_SIZE_TO_MASK(size) \ 401 (-(size)) 402 403 #define PCI_MAPREG_NUM(offset) \ 404 (((unsigned)(offset)-PCI_MAPREG_START)/4) 405 406 407 /* 408 * Cardbus CIS pointer (PCI rev. 2.1) 409 */ 410 #define PCI_CARDBUS_CIS_REG 0x28 411 412 /* 413 * Subsystem identification register; contains a vendor ID and a device ID. 414 * Types/macros for PCI_ID_REG apply. 415 * (PCI rev. 2.1) 416 */ 417 #define PCI_SUBSYS_ID_REG 0x2c 418 419 /* 420 * Capabilities link list (PCI rev. 2.2) 421 */ 422 #define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */ 423 #define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */ 424 #define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff) 425 #define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff) 426 #define PCI_CAPLIST_CAP(cr) ((cr) & 0xff) 427 428 #define PCI_CAP_RESERVED0 0x00 429 #define PCI_CAP_PWRMGMT 0x01 430 #define PCI_CAP_AGP 0x02 431 #define PCI_CAP_AGP_MAJOR(cr) (((cr) >> 20) & 0xf) 432 #define PCI_CAP_AGP_MINOR(cr) (((cr) >> 16) & 0xf) 433 #define PCI_CAP_VPD 0x03 434 #define PCI_CAP_SLOTID 0x04 435 #define PCI_CAP_MSI 0x05 436 #define PCI_CAP_CPCI_HOTSWAP 0x06 437 #define PCI_CAP_PCIX 0x07 438 #define PCI_CAP_LDT 0x08 439 #define PCI_CAP_VENDSPEC 0x09 440 #define PCI_CAP_DEBUGPORT 0x0a 441 #define PCI_CAP_CPCI_RSRCCTL 0x0b 442 #define PCI_CAP_HOTPLUG 0x0c 443 #define PCI_CAP_AGP8 0x0e 444 #define PCI_CAP_SECURE 0x0f 445 #define PCI_CAP_PCIEXPRESS 0x10 446 #define PCI_CAP_MSIX 0x11 447 448 /* 449 * Vital Product Data; access via capability pointer (PCI rev 2.2). 450 */ 451 #define PCI_VPD_ADDRESS_MASK 0x7fff 452 #define PCI_VPD_ADDRESS_SHIFT 16 453 #define PCI_VPD_ADDRESS(ofs) \ 454 (((ofs) & PCI_VPD_ADDRESS_MASK) << PCI_VPD_ADDRESS_SHIFT) 455 #define PCI_VPD_DATAREG(ofs) ((ofs) + 4) 456 #define PCI_VPD_OPFLAG 0x80000000 457 458 /* 459 * Power Management Capability; access via capability pointer. 460 */ 461 462 /* Power Management Capability Register */ 463 #define PCI_PMCR_SHIFT 16 464 #define PCI_PMCR 0x02 465 #define PCI_PMCR_D1SUPP 0x0200 466 #define PCI_PMCR_D2SUPP 0x0400 467 /* Power Management Control Status Register */ 468 #define PCI_PMCSR 0x04 469 #define PCI_PMCSR_PME_EN 0x100 470 #define PCI_PMCSR_STATE_MASK 0x03 471 #define PCI_PMCSR_STATE_D0 0x00 472 #define PCI_PMCSR_STATE_D1 0x01 473 #define PCI_PMCSR_STATE_D2 0x02 474 #define PCI_PMCSR_STATE_D3 0x03 475 #define PCI_PMCSR_PME_STS 0x8000 476 477 /* 478 * PCI-X capability. 479 */ 480 481 /* 482 * Command. 16 bits at offset 2 (e.g. upper 16 bits of the first 32-bit 483 * word at the capability; the lower 16 bits are the capability ID and 484 * next capability pointer). 485 * 486 * Since we always read PCI config space in 32-bit words, we define these 487 * as 32-bit values, offset and shifted appropriately. Make sure you perform 488 * the appropriate R/M/W cycles! 489 */ 490 #define PCI_PCIX_CMD 0x00 491 #define PCI_PCIX_CMD_PERR_RECOVER 0x00010000 492 #define PCI_PCIX_CMD_RELAXED_ORDER 0x00020000 493 #define PCI_PCIX_CMD_BYTECNT_MASK 0x000c0000 494 #define PCI_PCIX_CMD_BYTECNT_SHIFT 18 495 #define PCI_PCIX_CMD_BCNT_512 0x00000000 496 #define PCI_PCIX_CMD_BCNT_1024 0x00040000 497 #define PCI_PCIX_CMD_BCNT_2048 0x00080000 498 #define PCI_PCIX_CMD_BCNT_4096 0x000c0000 499 #define PCI_PCIX_CMD_SPLTRANS_MASK 0x00700000 500 #define PCI_PCIX_CMD_SPLTRANS_1 0x00000000 501 #define PCI_PCIX_CMD_SPLTRANS_2 0x00100000 502 #define PCI_PCIX_CMD_SPLTRANS_3 0x00200000 503 #define PCI_PCIX_CMD_SPLTRANS_4 0x00300000 504 #define PCI_PCIX_CMD_SPLTRANS_8 0x00400000 505 #define PCI_PCIX_CMD_SPLTRANS_12 0x00500000 506 #define PCI_PCIX_CMD_SPLTRANS_16 0x00600000 507 #define PCI_PCIX_CMD_SPLTRANS_32 0x00700000 508 509 /* 510 * Status. 32 bits at offset 4. 511 */ 512 #define PCI_PCIX_STATUS 0x04 513 #define PCI_PCIX_STATUS_FN_MASK 0x00000007 514 #define PCI_PCIX_STATUS_DEV_MASK 0x000000f8 515 #define PCI_PCIX_STATUS_BUS_MASK 0x0000ff00 516 #define PCI_PCIX_STATUS_64BIT 0x00010000 517 #define PCI_PCIX_STATUS_133 0x00020000 518 #define PCI_PCIX_STATUS_SPLDISC 0x00040000 519 #define PCI_PCIX_STATUS_SPLUNEX 0x00080000 520 #define PCI_PCIX_STATUS_DEVCPLX 0x00100000 521 #define PCI_PCIX_STATUS_MAXB_MASK 0x00600000 522 #define PCI_PCIX_STATUS_MAXB_SHIFT 21 523 #define PCI_PCIX_STATUS_MAXB_512 0x00000000 524 #define PCI_PCIX_STATUS_MAXB_1024 0x00200000 525 #define PCI_PCIX_STATUS_MAXB_2048 0x00400000 526 #define PCI_PCIX_STATUS_MAXB_4096 0x00600000 527 #define PCI_PCIX_STATUS_MAXST_MASK 0x03800000 528 #define PCI_PCIX_STATUS_MAXST_1 0x00000000 529 #define PCI_PCIX_STATUS_MAXST_2 0x00800000 530 #define PCI_PCIX_STATUS_MAXST_3 0x01000000 531 #define PCI_PCIX_STATUS_MAXST_4 0x01800000 532 #define PCI_PCIX_STATUS_MAXST_8 0x02000000 533 #define PCI_PCIX_STATUS_MAXST_12 0x02800000 534 #define PCI_PCIX_STATUS_MAXST_16 0x03000000 535 #define PCI_PCIX_STATUS_MAXST_32 0x03800000 536 #define PCI_PCIX_STATUS_MAXRS_MASK 0x1c000000 537 #define PCI_PCIX_STATUS_MAXRS_1K 0x00000000 538 #define PCI_PCIX_STATUS_MAXRS_2K 0x04000000 539 #define PCI_PCIX_STATUS_MAXRS_4K 0x08000000 540 #define PCI_PCIX_STATUS_MAXRS_8K 0x0c000000 541 #define PCI_PCIX_STATUS_MAXRS_16K 0x10000000 542 #define PCI_PCIX_STATUS_MAXRS_32K 0x14000000 543 #define PCI_PCIX_STATUS_MAXRS_64K 0x18000000 544 #define PCI_PCIX_STATUS_MAXRS_128K 0x1c000000 545 #define PCI_PCIX_STATUS_SCERR 0x20000000 546 547 /* 548 * PCI Express; access via capability pointer. 549 */ 550 #define PCI_PCIE_XCAP 0x00 551 #define PCI_PCIE_XCAP_SI 0x01000000 552 #define PCI_PCIE_DCAP 0x04 553 #define PCI_PCIE_DCSR 0x08 554 #define PCI_PCIE_DCSR_MAX_READ_REQ 0x7000 555 #define PCI_PCIE_DCSR_ENA_NO_SNOOP 0x00000800 556 #define PCI_PCIE_DCSR_CED 0x00010000 557 #define PCI_PCIE_DCSR_NFED 0x00020000 558 #define PCI_PCIE_DCSR_FED 0x00040000 559 #define PCI_PCIE_DCSR_URD 0x00080000 560 #define PCI_PCIE_LCAP 0x0c 561 #define PCI_PCIE_LCSR 0x10 562 #define PCI_PCIE_LCSR_ASPM_L0S 0x00000001 563 #define PCI_PCIE_LCSR_ASPM_L1 0x00000002 564 #define PCI_PCIE_SLCAP 0x14 565 #define PCI_PCIE_SLCAP_ABP 0x00000001 566 #define PCI_PCIE_SLCAP_PCP 0x00000002 567 #define PCI_PCIE_SLCAP_MSP 0x00000004 568 #define PCI_PCIE_SLCAP_AIP 0x00000008 569 #define PCI_PCIE_SLCAP_PIP 0x00000010 570 #define PCI_PCIE_SLCAP_HPS 0x00000020 571 #define PCI_PCIE_SLCAP_HPC 0x00000040 572 #define PCI_PCIE_SLCSR 0x18 573 #define PCI_PCIE_SLCSR_ABE 0x00000001 574 #define PCI_PCIE_SLCSR_PFE 0x00000002 575 #define PCI_PCIE_SLCSR_MSE 0x00000004 576 #define PCI_PCIE_SLCSR_PDE 0x00000008 577 #define PCI_PCIE_SLCSR_CCE 0x00000010 578 #define PCI_PCIE_SLCSR_HPE 0x00000020 579 #define PCI_PCIE_SLCSR_ABP 0x00010000 580 #define PCI_PCIE_SLCSR_PFD 0x00020000 581 #define PCI_PCIE_SLCSR_MSC 0x00040000 582 #define PCI_PCIE_SLCSR_PDC 0x00080000 583 #define PCI_PCIE_SLCSR_CC 0x00100000 584 #define PCI_PCIE_SLCSR_MS 0x00200000 585 #define PCI_PCIE_SLCSR_PDS 0x00400000 586 #define PCI_PCIE_SLCSR_LACS 0x01000000 587 #define PCI_PCIE_RCSR 0x1c 588 589 /* 590 * Interrupt Configuration Register; contains interrupt pin and line. 591 */ 592 #define PCI_INTERRUPT_REG 0x3c 593 594 typedef u_int8_t pci_intr_latency_t; 595 typedef u_int8_t pci_intr_grant_t; 596 typedef u_int8_t pci_intr_pin_t; 597 typedef u_int8_t pci_intr_line_t; 598 599 #define PCI_MAX_LAT_SHIFT 24 600 #define PCI_MAX_LAT_MASK 0xff 601 #define PCI_MAX_LAT(icr) \ 602 (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK) 603 604 #define PCI_MIN_GNT_SHIFT 16 605 #define PCI_MIN_GNT_MASK 0xff 606 #define PCI_MIN_GNT(icr) \ 607 (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK) 608 609 #define PCI_INTERRUPT_GRANT_SHIFT 24 610 #define PCI_INTERRUPT_GRANT_MASK 0xff 611 #define PCI_INTERRUPT_GRANT(icr) \ 612 (((icr) >> PCI_INTERRUPT_GRANT_SHIFT) & PCI_INTERRUPT_GRANT_MASK) 613 614 #define PCI_INTERRUPT_LATENCY_SHIFT 16 615 #define PCI_INTERRUPT_LATENCY_MASK 0xff 616 #define PCI_INTERRUPT_LATENCY(icr) \ 617 (((icr) >> PCI_INTERRUPT_LATENCY_SHIFT) & PCI_INTERRUPT_LATENCY_MASK) 618 619 #define PCI_INTERRUPT_PIN_SHIFT 8 620 #define PCI_INTERRUPT_PIN_MASK 0xff 621 #define PCI_INTERRUPT_PIN(icr) \ 622 (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK) 623 624 #define PCI_INTERRUPT_LINE_SHIFT 0 625 #define PCI_INTERRUPT_LINE_MASK 0xff 626 #define PCI_INTERRUPT_LINE(icr) \ 627 (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK) 628 629 #define PCI_INTERRUPT_CODE(lat,gnt,pin,line) \ 630 ((((lat)&PCI_INTERRUPT_LATENCY_MASK)<<PCI_INTERRUPT_LATENCY_SHIFT)| \ 631 (((gnt)&PCI_INTERRUPT_GRANT_MASK) <<PCI_INTERRUPT_GRANT_SHIFT) | \ 632 (((pin)&PCI_INTERRUPT_PIN_MASK) <<PCI_INTERRUPT_PIN_SHIFT) | \ 633 (((line)&PCI_INTERRUPT_LINE_MASK) <<PCI_INTERRUPT_LINE_SHIFT)) 634 635 #define PCI_INTERRUPT_PIN_NONE 0x00 636 #define PCI_INTERRUPT_PIN_A 0x01 637 #define PCI_INTERRUPT_PIN_B 0x02 638 #define PCI_INTERRUPT_PIN_C 0x03 639 #define PCI_INTERRUPT_PIN_D 0x04 640 #define PCI_INTERRUPT_PIN_MAX 0x04 641 642 /* Header Type 1 (Bridge) configuration registers */ 643 #define PCI_BRIDGE_BUS_REG 0x18 644 #define PCI_BRIDGE_BUS_PRIMARY_SHIFT 0 645 #define PCI_BRIDGE_BUS_SECONDARY_SHIFT 8 646 #define PCI_BRIDGE_BUS_SUBORDINATE_SHIFT 16 647 648 #define PCI_BRIDGE_STATIO_REG 0x1C 649 #define PCI_BRIDGE_STATIO_IOBASE_SHIFT 0 650 #define PCI_BRIDGE_STATIO_IOLIMIT_SHIFT 8 651 #define PCI_BRIDGE_STATIO_STATUS_SHIFT 16 652 #define PCI_BRIDGE_STATIO_IOBASE_MASK 0xf0 653 #define PCI_BRIDGE_STATIO_IOLIMIT_MASK 0xf0 654 #define PCI_BRIDGE_STATIO_STATUS_MASK 0xffff 655 #define PCI_BRIDGE_IO_32BITS(reg) (((reg) & 0xf) == 1) 656 657 #define PCI_BRIDGE_MEMORY_REG 0x20 658 #define PCI_BRIDGE_MEMORY_BASE_SHIFT 4 659 #define PCI_BRIDGE_MEMORY_LIMIT_SHIFT 20 660 #define PCI_BRIDGE_MEMORY_BASE_MASK 0x0fff 661 #define PCI_BRIDGE_MEMORY_LIMIT_MASK 0x0fff 662 663 #define PCI_BRIDGE_PREFETCHMEM_REG 0x24 664 #define PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT 4 665 #define PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT 20 666 #define PCI_BRIDGE_PREFETCHMEM_BASE_MASK 0x0fff 667 #define PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK 0x0fff 668 #define PCI_BRIDGE_PREFETCHMEM_64BITS(reg) ((reg) & 0xf) 669 670 #define PCI_BRIDGE_PREFETCHBASE32_REG 0x28 671 #define PCI_BRIDGE_PREFETCHLIMIT32_REG 0x2C 672 673 #define PCI_BRIDGE_IOHIGH_REG 0x30 674 #define PCI_BRIDGE_IOHIGH_BASE_SHIFT 0 675 #define PCI_BRIDGE_IOHIGH_LIMIT_SHIFT 16 676 #define PCI_BRIDGE_IOHIGH_BASE_MASK 0xffff 677 #define PCI_BRIDGE_IOHIGH_LIMIT_MASK 0xffff 678 679 #define PCI_BRIDGE_CONTROL_REG 0x3C 680 #define PCI_BRIDGE_CONTROL_SHIFT 16 681 #define PCI_BRIDGE_CONTROL_MASK 0xffff 682 #define PCI_BRIDGE_CONTROL_PERE (1 << 0) 683 #define PCI_BRIDGE_CONTROL_SERR (1 << 1) 684 #define PCI_BRIDGE_CONTROL_ISA (1 << 2) 685 #define PCI_BRIDGE_CONTROL_VGA (1 << 3) 686 /* Reserved (1 << 4) */ 687 #define PCI_BRIDGE_CONTROL_MABRT (1 << 5) 688 #define PCI_BRIDGE_CONTROL_SECBR (1 << 6) 689 #define PCI_BRIDGE_CONTROL_SECFASTB2B (1 << 7) 690 #define PCI_BRIDGE_CONTROL_PRI_DISC_TIMER (1 << 8) 691 #define PCI_BRIDGE_CONTROL_SEC_DISC_TIMER (1 << 9) 692 #define PCI_BRIDGE_CONTROL_DISC_TIMER_STAT (1 << 10) 693 #define PCI_BRIDGE_CONTROL_DISC_TIMER_SERR (1 << 11) 694 /* Reserved (1 << 12) - (1 << 15) */ 695 696 /* 697 * Vital Product Data resource tags. 698 */ 699 struct pci_vpd_smallres { 700 uint8_t vpdres_byte0; /* length of data + tag */ 701 /* Actual data. */ 702 } __packed; 703 704 struct pci_vpd_largeres { 705 uint8_t vpdres_byte0; 706 uint8_t vpdres_len_lsb; /* length of data only */ 707 uint8_t vpdres_len_msb; 708 /* Actual data. */ 709 } __packed; 710 711 #define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) 712 713 #define PCI_VPDRES_SMALL_LENGTH(x) ((x) & 0x7) 714 #define PCI_VPDRES_SMALL_NAME(x) (((x) >> 3) & 0xf) 715 716 #define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) 717 718 #define PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID 0x3 /* small */ 719 #define PCI_VPDRES_TYPE_VENDOR_DEFINED 0xe /* small */ 720 #define PCI_VPDRES_TYPE_END_TAG 0xf /* small */ 721 722 #define PCI_VPDRES_TYPE_IDENTIFIER_STRING 0x02 /* large */ 723 #define PCI_VPDRES_TYPE_VPD 0x10 /* large */ 724 725 struct pci_vpd { 726 uint8_t vpd_key0; 727 uint8_t vpd_key1; 728 uint8_t vpd_len; /* length of data only */ 729 /* Actual data. */ 730 } __packed; 731 732 /* 733 * Recommended VPD fields: 734 * 735 * PN Part number of assembly 736 * FN FRU part number 737 * EC EC level of assembly 738 * MN Manufacture ID 739 * SN Serial Number 740 * 741 * Conditionally recommended VPD fields: 742 * 743 * LI Load ID 744 * RL ROM Level 745 * RM Alterable ROM Level 746 * NA Network Address 747 * DD Device Driver Level 748 * DG Diagnostic Level 749 * LL Loadable Microcode Level 750 * VI Vendor ID/Device ID 751 * FU Function Number 752 * SI Subsystem Vendor ID/Subsystem ID 753 * 754 * Additional VPD fields: 755 * 756 * Z0-ZZ User/Product Specific 757 */ 758 759 /* 760 * PCI Expansion Rom 761 */ 762 763 struct pci_rom_header { 764 uint16_t romh_magic; /* 0xAA55 little endian */ 765 uint8_t romh_reserved[22]; 766 uint16_t romh_data_ptr; /* pointer to pci_rom struct */ 767 } __packed; 768 769 #define PCI_ROM_HEADER_MAGIC 0xAA55 /* little endian */ 770 771 struct pci_rom { 772 uint32_t rom_signature; 773 pci_vendor_id_t rom_vendor; 774 pci_product_id_t rom_product; 775 uint16_t rom_vpd_ptr; /* reserved in PCI 2.2 */ 776 uint16_t rom_data_len; 777 uint8_t rom_data_rev; 778 pci_interface_t rom_interface; /* the class reg is 24-bits */ 779 pci_subclass_t rom_subclass; /* in little endian */ 780 pci_class_t rom_class; 781 uint16_t rom_len; /* code length / 512 byte */ 782 uint16_t rom_rev; /* code revision level */ 783 uint8_t rom_code_type; /* type of code */ 784 uint8_t rom_indicator; 785 uint16_t rom_reserved; 786 /* Actual data. */ 787 } __packed; 788 789 #define PCI_ROM_SIGNATURE 0x52494350 /* "PCIR", endian reversed */ 790 #define PCI_ROM_CODE_TYPE_X86 0 /* Intel x86 BIOS */ 791 #define PCI_ROM_CODE_TYPE_OFW 1 /* Open Firmware */ 792 #define PCI_ROM_CODE_TYPE_HPPA 2 /* HP PA/RISC */ 793 #define PCI_ROM_CODE_TYPE_EFI 3 /* EFI Image */ 794 795 #define PCI_ROM_INDICATOR_LAST 0x80 796 797 /* 798 * Threshold below which 32bit PCI DMA needs bouncing. 799 */ 800 #define PCI32_DMA_BOUNCE_THRESHOLD 0x100000000ULL 801 802 /* 803 * Common PCI register for PCI transmit handling. 804 */ 805 #define PCI_RETRY_TIMEOUT_REG 0x40 806 #define PCI_RETRY_TIMEOUT_REG_MASK 0x0000ff00 807 808 /* 809 * PCI-X 2.0 Extended Capability List 810 */ 811 812 #define PCI_EXTCAPLIST_BASE 0x100 813 814 #define PCI_EXTCAPLIST_CAP(ecr) ((ecr) & 0xffff) 815 #define PCI_EXTCAPLIST_VERSION(ecr) (((ecr) >> 16) & 0xf) 816 #define PCI_EXTCAPLIST_NEXT(ecr) (((ecr) >> 20) & 0xfff) 817 818 #endif /* _DEV_PCI_PCIREG_H_ */ 819