1 /* $NetBSD: pcireg.h,v 1.11 1996/08/10 15:42:33 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved. 5 * Copyright (c) 1994, 1996 Charles Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _DEV_PCI_PCIREG_H_ 34 #define _DEV_PCI_PCIREG_H_ 35 36 /* 37 * Standardized PCI configuration information 38 * 39 * XXX This is not complete. 40 */ 41 42 /* 43 * Device identification register; contains a vendor ID and a device ID. 44 */ 45 #define PCI_ID_REG 0x00 46 47 typedef u_int16_t pci_vendor_id_t; 48 typedef u_int16_t pci_product_id_t; 49 50 #define PCI_VENDOR_SHIFT 0 51 #define PCI_VENDOR_MASK 0xffff 52 #define PCI_VENDOR(id) \ 53 (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK) 54 55 #define PCI_PRODUCT_SHIFT 16 56 #define PCI_PRODUCT_MASK 0xffff 57 #define PCI_PRODUCT(id) \ 58 (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) 59 60 /* 61 * Command and status register. 62 */ 63 #define PCI_COMMAND_STATUS_REG 0x04 64 65 #define PCI_COMMAND_IO_ENABLE 0x00000001 66 #define PCI_COMMAND_MEM_ENABLE 0x00000002 67 #define PCI_COMMAND_MASTER_ENABLE 0x00000004 68 #define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 69 #define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 70 #define PCI_COMMAND_PALETTE_ENABLE 0x00000020 71 #define PCI_COMMAND_PARITY_ENABLE 0x00000040 72 #define PCI_COMMAND_STEPPING_ENABLE 0x00000080 73 #define PCI_COMMAND_SERR_ENABLE 0x00000100 74 #define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 75 76 #define PCI_STATUS_BACKTOBACK_OKAY 0x00800000 77 #define PCI_STATUS_PARITY_ERROR 0x01000000 78 #define PCI_STATUS_DEVSEL_FAST 0x00000000 79 #define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 80 #define PCI_STATUS_DEVSEL_SLOW 0x04000000 81 #define PCI_STATUS_DEVSEL_MASK 0x06000000 82 #define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 83 #define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 84 #define PCI_STATUS_MASTER_ABORT 0x20000000 85 #define PCI_STATUS_SPECIAL_ERROR 0x40000000 86 #define PCI_STATUS_PARITY_DETECT 0x80000000 87 88 /* 89 * PCI Class and Revision Register; defines type and revision of device. 90 */ 91 #define PCI_CLASS_REG 0x08 92 93 typedef u_int8_t pci_class_t; 94 typedef u_int8_t pci_subclass_t; 95 typedef u_int8_t pci_interface_t; 96 typedef u_int8_t pci_revision_t; 97 98 #define PCI_CLASS_SHIFT 24 99 #define PCI_CLASS_MASK 0xff 100 #define PCI_CLASS(cr) \ 101 (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) 102 103 #define PCI_SUBCLASS_SHIFT 16 104 #define PCI_SUBCLASS_MASK 0xff 105 #define PCI_SUBCLASS(cr) \ 106 (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) 107 108 #define PCI_INTERFACE_SHIFT 8 109 #define PCI_INTERFACE_MASK 0xff 110 #define PCI_INTERFACE(cr) \ 111 (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) 112 113 #define PCI_REVISION_SHIFT 0 114 #define PCI_REVISION_MASK 0xff 115 #define PCI_REVISION(cr) \ 116 (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) 117 118 /* base classes */ 119 #define PCI_CLASS_PREHISTORIC 0x00 120 #define PCI_CLASS_MASS_STORAGE 0x01 121 #define PCI_CLASS_NETWORK 0x02 122 #define PCI_CLASS_DISPLAY 0x03 123 #define PCI_CLASS_MULTIMEDIA 0x04 124 #define PCI_CLASS_MEMORY 0x05 125 #define PCI_CLASS_BRIDGE 0x06 126 #define PCI_CLASS_UNDEFINED 0xff 127 128 /* 0x00 prehistoric subclasses */ 129 #define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 130 #define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 131 132 /* 0x01 mass storage subclasses */ 133 #define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 134 #define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 135 #define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 136 #define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 137 #define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 138 139 /* 0x02 network subclasses */ 140 #define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 141 #define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 142 #define PCI_SUBCLASS_NETWORK_FDDI 0x02 143 #define PCI_SUBCLASS_NETWORK_MISC 0x80 144 145 /* 0x03 display subclasses */ 146 #define PCI_SUBCLASS_DISPLAY_VGA 0x00 147 #define PCI_SUBCLASS_DISPLAY_XGA 0x01 148 #define PCI_SUBCLASS_DISPLAY_MISC 0x80 149 150 /* 0x04 multimedia subclasses */ 151 #define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 152 #define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 153 #define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 154 155 /* 0x05 memory subclasses */ 156 #define PCI_SUBCLASS_MEMORY_RAM 0x00 157 #define PCI_SUBCLASS_MEMORY_FLASH 0x01 158 #define PCI_SUBCLASS_MEMORY_MISC 0x80 159 160 /* 0x06 bridge subclasses */ 161 #define PCI_SUBCLASS_BRIDGE_HOST 0x00 162 #define PCI_SUBCLASS_BRIDGE_ISA 0x01 163 #define PCI_SUBCLASS_BRIDGE_EISA 0x02 164 #define PCI_SUBCLASS_BRIDGE_MC 0x03 165 #define PCI_SUBCLASS_BRIDGE_PCI 0x04 166 #define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 167 #define PCI_SUBCLASS_BRIDGE_MISC 0x80 168 169 /* 170 * PCI BIST/Header Type/Latency Timer/Cache Line Size Register. 171 */ 172 #define PCI_BHLC_REG 0x0c 173 174 #define PCI_BIST_SHIFT 24 175 #define PCI_BIST_MASK 0xff 176 #define PCI_BIST(bhlcr) \ 177 (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK) 178 179 #define PCI_HDRTYPE_SHIFT 24 180 #define PCI_HDRTYPE_MASK 0xff 181 #define PCI_HDRTYPE(bhlcr) \ 182 (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK) 183 184 #define PCI_HDRTYPE_MULTIFN(bhlcr) \ 185 ((PCI_HDRTYPE(bhlcr) & 0x80) != 0) 186 187 #define PCI_LATTIMER_SHIFT 24 188 #define PCI_LATTIMER_MASK 0xff 189 #define PCI_LATTIMER(bhlcr) \ 190 (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK) 191 192 #define PCI_CACHELINE_SHIFT 24 193 #define PCI_CACHELINE_MASK 0xff 194 #define PCI_CACHELINE(bhlcr) \ 195 (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK) 196 197 /* 198 * Mapping registers 199 */ 200 #define PCI_MAPREG_START 0x10 201 #define PCI_MAPREG_END 0x28 202 203 #define PCI_MAPREG_TYPE(mr) \ 204 ((mr) & PCI_MAPREG_TYPE_MASK) 205 #define PCI_MAPREG_TYPE_MASK 0x00000001 206 207 #define PCI_MAPREG_TYPE_MEM 0x00000000 208 #define PCI_MAPREG_TYPE_IO 0x00000001 209 210 #define PCI_MAPREG_MEM_TYPE(mr) \ 211 ((mr) & PCI_MAPREG_MEM_TYPE_MASK) 212 #define PCI_MAPREG_MEM_TYPE_MASK 0x00000006 213 214 #define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000 215 #define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002 216 #define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 217 218 #define PCI_MAPREG_MEM_CACHEABLE(mr) \ 219 (((mr) & PCI_MAPREG_MEM_CACHEABLE_MASK) != 0) 220 #define PCI_MAPREG_MEM_CACHEABLE_MASK 0x00000008 221 222 #define PCI_MAPREG_MEM_ADDR(mr) \ 223 ((mr) & PCI_MAPREG_MEM_ADDR_MASK) 224 #define PCI_MAPREG_MEM_SIZE(mr) \ 225 (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr)) 226 #define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 227 228 #define PCI_MAPREG_IO_ADDR(mr) \ 229 ((mr) & PCI_MAPREG_IO_ADDR_MASK) 230 #define PCI_MAPREG_IO_SIZE(mr) \ 231 (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) 232 #define PCI_MAPREG_IO_ADDR_MASK 0xfffffffe 233 234 /* 235 * Interrupt Configuration Register; contains interrupt pin and line. 236 */ 237 #define PCI_INTERRUPT_REG 0x3c 238 239 typedef u_int8_t pci_intr_pin_t; 240 typedef u_int8_t pci_intr_line_t; 241 242 #define PCI_INTERRUPT_PIN_SHIFT 8 243 #define PCI_INTERRUPT_PIN_MASK 0xff 244 #define PCI_INTERRUPT_PIN(icr) \ 245 (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK) 246 247 #define PCI_INTERRUPT_LINE_SHIFT 0 248 #define PCI_INTERRUPT_LINE_MASK 0xff 249 #define PCI_INTERRUPT_LINE(icr) \ 250 (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK) 251 252 #define PCI_INTERRUPT_PIN_NONE 0x00 253 #define PCI_INTERRUPT_PIN_A 0x01 254 #define PCI_INTERRUPT_PIN_B 0x02 255 #define PCI_INTERRUPT_PIN_C 0x03 256 #define PCI_INTERRUPT_PIN_D 0x04 257 258 #endif /* _DEV_PCI_PCIREG_H_ */ 259