1 /* $NetBSD: pciide_sis_reg.h,v 1.10 2003/03/14 22:46:06 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 /* 35 * Registers definitions for SiS SiS5597/98 PCI IDE controller. 36 * Available from http://www.sis.com.tw/html/databook.html 37 */ 38 39 /* IDE timing control registers (32 bits), for all but 96x */ 40 #define SIS_TIM(channel) (0x40 + (channel * 4)) 41 /* for 730, 630 and older (66, 100OLD) */ 42 #define SIS_TIM66_REC_OFF(drive) (16 * (drive)) 43 #define SIS_TIM66_ACT_OFF(drive) (8 + 16 * (drive)) 44 #define SIS_TIM66_UDMA_TIME_OFF(drive) (12 + 16 * (drive)) 45 /* for older than 96x (100NEW, 133OLD) */ 46 #define SIS_TIM100_REC_OFF(drive) (16 * (drive)) 47 #define SIS_TIM100_ACT_OFF(drive) (4 + 16 * (drive)) 48 #define SIS_TIM100_UDMA_TIME_OFF(drive) (8 + 16 * (drive)) 49 50 /* 51 * From FreeBSD: on 96x, the timing registers may start from 0x40 or 0x70 52 * depending on the value from register 0x57. 32bits of timing info for 53 * each drive. 54 */ 55 #define SIS_TIM133(reg57, channel, drive) \ 56 ((((reg57) & 0x40) ? 0x70 : 0x40) + ((channel) << 3) + ((drive) << 2)) 57 58 /* IDE general control register 0 (8 bits) */ 59 #define SIS_CTRL0 0x4a 60 #define SIS_CTRL0_PCIBURST 0x80 61 #define SIS_CTRL0_FAST_PW 0x20 62 #define SIS_CTRL0_BO 0x08 63 #define SIS_CTRL0_CHAN0_EN 0x02 /* manual (v2.0) is wrong!!! */ 64 #define SIS_CTRL0_CHAN1_EN 0x04 /* manual (v2.0) is wrong!!! */ 65 66 /* IDE general control register 1 (8 bits) */ 67 #define SIS_CTRL1 0x4b 68 #define SIS_CTRL1_POSTW_EN(chan, drv) (0x10 << ((drv) + 2 * (chan))) 69 #define SIS_CTRL1_PREFETCH_EN(chan, drv) (0x01 << ((drv) + 2 * (chan))) 70 71 /* IDE misc control register (8 bit) */ 72 #define SIS_MISC 0x52 73 #define SIS_MISC_TIM_SEL 0x08 74 #define SIS_MISC_GTC 0x04 75 #define SIS_MISC_FIFO_SIZE 0x01 76 77 /* following are from FreeBSD (sorry, no description) */ 78 #define SIS_REG_49 0x49 79 #define SIS_REG_50 0x50 80 #define SIS_REG_51 0x51 81 #define SIS_REG_52 0x52 82 #define SIS_REG_53 0x53 83 #define SIS_REG_57 0x57 84 85 #define SIS_REG_CBL 0x48 86 #define SIS_REG_CBL_33(channel) (0x10 << (channel)) 87 #define SIS96x_REG_CBL(channel) (0x51 + (channel) * 2) 88 #define SIS96x_REG_CBL_33 0x80 89 90 #define SIS_PRODUCT_5518 0x5518 91 92 /* timings values, mostly from FreeBSD */ 93 /* PIO timings, for all up to 133NEW */ 94 static const u_int8_t sis_pio_act[] __attribute__((__unused__)) = 95 {12, 6, 4, 3, 3}; 96 static const u_int8_t sis_pio_rec[] __attribute__((__unused__)) = 97 {11, 7, 4, 3, 1}; 98 /* DMA timings for 66 and 100OLD */ 99 static const u_int8_t sis_udma66_tim[] __attribute__((__unused__)) = 100 {15, 13, 11, 10, 9, 8}; 101 /* DMA timings for 100NEW */ 102 static const u_int8_t sis_udma100new_tim[] __attribute__((__unused__)) = 103 {0x8b, 0x87, 0x85, 0x84, 0x82, 0x81}; 104 /* DMA timings for 133OLD */ 105 static const u_int8_t sis_udma133old_tim[] __attribute__((__unused__)) = 106 {0x8f, 0x8a, 0x87, 0x85, 0x83, 0x82, 0x81}; 107 /* PIO, DMA and UDMA timings for 133NEW */ 108 static const u_int32_t sis_pio133new_tim[] __attribute__((__unused__)) = 109 {0x28269008, 0x0c266008, 0x4263008, 0x0c0a3008, 0x05093008}; 110 static const u_int32_t sis_dma133new_tim[] __attribute__((__unused__)) = 111 {0x22196008, 0x0c0a3008, 0x05093008}; 112 static const u_int32_t sis_udma133new_tim[] __attribute__((__unused__)) = 113 {0x9f4, 0x64a, 0x474, 0x254, 0x234, 0x224, 0x214}; 114