1 /* $NetBSD: pciide_piix_reg.h,v 1.6 2001/10/21 18:49:20 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Berkeley and its contributors. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /* 36 * Registers definitions for Intel's PIIX serie PCI IDE controllers. 37 * See Intel's 38 * "82371FB (PIIX) and 82371SB (PIIX3) PCI ISA IDE XCELERATOR" 39 * "82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)" and 40 * "Intel 82801AA (ICH) and Intel 82801AB (ICH0) I/O Controller Hub" 41 * available from http://developers.intel.com/ 42 */ 43 44 /* 45 * Bus master interface base address register 46 */ 47 #define PIIX_BMIBA 0x20 48 #define PIIX_BMIBA_ADDR(x) (x & 0x0000FFFF0) 49 #define PIIX_BMIBA_RTE(x) (x & 0x000000001) 50 #define PIIX_BMIBA_RTE_IO 0x000000001 /* base addr maps to I/O space */ 51 52 /* 53 * IDE timing register 54 * 0x40/0x41 is for primary, 0x42/0x43 for secondary channel 55 */ 56 #define PIIX_IDETIM 0x40 57 #define PIIX_IDETIM_READ(x, channel) (((x) >> (16 * (channel))) & 0x0000FFFF) 58 #define PIIX_IDETIM_SET(x, bytes, channel) \ 59 ((x) | ((bytes) << (16 * (channel)))) 60 #define PIIX_IDETIM_CLEAR(x, bytes, channel) \ 61 ((x) & ~((bytes) << (16 * (channel)))) 62 63 #define PIIX_IDETIM_IDE 0x8000 /* PIIX decode IDE registers */ 64 #define PIIX_IDETIM_SITRE 0x4000 /* slaves IDE timing registers 65 enabled (PIIX3/4 only) */ 66 #define PIIX_IDETIM_ISP_MASK 0x3000 /* IOrdy sample point */ 67 #define PIIX_IDETIM_ISP_SHIFT 12 68 #define PIIX_IDETIM_ISP_SET(x) ((x) << PIIX_IDETIM_ISP_SHIFT) 69 #define PIIX_IDETIM_RTC_MASK 0x0300 /* recovery time */ 70 #define PIIX_IDETIM_RTC_SHIFT 8 71 #define PIIX_IDETIM_RTC_SET(x) ((x) << PIIX_IDETIM_RTC_SHIFT) 72 #define PIIX_IDETIM_DTE(d) (0x0008 << (4 * (d))) /* DMA timing only */ 73 #define PIIX_IDETIM_PPE(d) (0x0004 << (4 * (d))) /* prefetch/posting */ 74 #define PIIX_IDETIM_IE(d) (0x0002 << (4 * (d))) /* IORDY enable */ 75 #define PIIX_IDETIM_TIME(d) (0x0001 << (4 * (d))) /* Fast timing enable */ 76 /* 77 * Slave IDE timing register (PIIX3/4 only) 78 * This register must be enabled via the PIIX_IDETIM_SITRE bit 79 */ 80 #define PIIX_SIDETIM 0x44 81 #define PIIX_SIDETIM_ISP_MASK(channel) (0x0c << ((channel) * 4)) 82 #define PIIX_SIDETIM_ISP_SHIFT 2 83 #define PIIX_SIDETIM_ISP_SET(x, channel) \ 84 (x << (PIIX_SIDETIM_ISP_SHIFT + ((channel) * 4))) 85 #define PIIX_SIDETIM_RTC_MASK(channel) (0x03 << ((channel) * 4)) 86 #define PIIX_SIDETIM_RTC_SHIFT 0 87 #define PIIX_SIDETIM_RTC_SET(x, channel) \ 88 (x << (PIIX_SIDETIM_RTC_SHIFT + ((channel) * 4))) 89 90 /* 91 * Ultra DMA/33 register (PIIX4 only) 92 */ 93 #define PIIX_UDMAREG 0x48 94 /* Control register */ 95 #define PIIX_UDMACTL_DRV_EN(channel, drive) (0x01 << ((channel) * 2 + (drive))) 96 /* Ultra DMA/33 timing register (PIIX4 only) */ 97 #define PIIX_UDMATIM_SHIFT 16 98 #define PIIX_UDMATIM_SET(x, channel, drive) \ 99 (((x) << ((channel * 8) + (drive * 4))) << PIIX_UDMATIM_SHIFT) 100 101 /* 102 * IDE config register (ICH/ICH0/ICH2 only) 103 */ 104 #define PIIX_CONFIG 0x54 105 #define PIIX_CONFIG_PINGPONG 0x0400 106 /* The following are only for the 82801AA (ICH) and 82801BA (ICH2) */ 107 #define PIIX_CONFIG_CR(channel, drive) (0x0010 << ((channel) * 2 + (drive))) 108 #define PIIX_CONFIG_UDMA66(channel, drive) (0x0001 << ((channel) * 2 + (drive))) 109 /* The following are only for the 82801BA (ICH2) */ 110 #define PIIX_CONFIG_UDMA100(channel, drive) (0x1000 << ((channel) * 2 + (drive))) 111 112 /* 113 * these tables define the differents values to upload to the 114 * ISP and RTC registers for the various PIO and DMA mode 115 * (from the PIIX4 doc). 116 */ 117 static const int8_t piix_isp_pio[] __attribute__((__unused__)) = 118 {0x00, 0x00, 0x01, 0x02, 0x02}; 119 static const int8_t piix_rtc_pio[] __attribute__((__unused__)) = 120 {0x00, 0x00, 0x00, 0x01, 0x03}; 121 static const int8_t piix_isp_dma[] __attribute__((__unused__)) = 122 {0x00, 0x02, 0x02}; 123 static const int8_t piix_rtc_dma[] __attribute__((__unused__)) = 124 {0x00, 0x02, 0x03}; 125 static const int8_t piix4_sct_udma[] __attribute__((__unused__)) = 126 {0x00, 0x01, 0x02, 0x01, 0x02, 0x01}; 127