1 /* $NetBSD: pciide_cmd_reg.h,v 1.11 2001/11/15 20:48:17 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Berkeley and its contributors. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /* 36 * Registers definitions for CMD Technologies's PCI 064x IDE controllers. 37 * Available from http://www.cmd.com/ 38 */ 39 40 /* Interesting revision of the 0646 */ 41 #define CMD0646U2_REV 0x05 42 #define CMD0646U_REV 0x03 43 44 /* Configuration (RO) */ 45 #define CMD_CONF 0x50 46 #define CMD_CONF_REV_MASK 0x03 /* 0640/3/6 only */ 47 #define CMD_CONF_DRV0_INTR 0x04 48 #define CMD_CONF_DEVID 0x18 /* 0640/3/6 only */ 49 #define CMD_CONF_VESAPRT 0x20 /* 0640/3/6 only */ 50 #define CMD_CONF_DSA1 0x40 51 #define CMD_CONF_DSA0 0x80 /* 0640/3/6 only */ 52 53 /* Control register (RW) */ 54 #define CMD_CTRL 0x51 55 #define CMD_CTRL_HR_FIFO 0x01 /* 0640/3/6 only */ 56 #define CMD_CTRL_HW_FIFO 0x02 /* 0640/3/6 only */ 57 #define CMD_CTRL_DEVSEL 0x04 58 #define CMD_CTRL_2PORT 0x08 59 #define CMD_CTRL_PAR 0x10 /* 0640/3/6 only */ 60 #define CMD_CTRL_HW_HLD 0x20 /* 0640/3/6 only */ 61 #define CMD_CTRL_DRV0_RAHEAD 0x40 62 #define CMD_CTRL_DRV1_RAHEAD 0x80 63 64 /* 65 * data read/write timing registers . 0640 uses the same for drive 0 and 1 66 * on the secondary channel 67 */ 68 #define CMD_DATA_TIM(chan, drive) \ 69 (((chan) == 0) ? \ 70 ((drive) == 0) ? 0x54: 0x56 \ 71 : \ 72 ((drive) == 0) ? 0x58 : 0x5b) 73 74 /* secondary channel status and addr timings */ 75 #define CMD_ARTTIM23 0x57 76 #define CMD_ARTTIM23_IRQ 0x10 77 #define CMD_ARTTIM23_RHAEAD(d) ((0x4) << (d)) 78 79 /* DMA master read mode select */ 80 #define CMD_DMA_MODE 0x71 81 #define CMD_DMA_MASK 0x03 82 #define CMD_DMA 0x00 83 #define CMD_DMA_MULTIPLE 0x01 84 #define CMD_DMA_LINE 0x03 85 /* the followings bits are only for 0646U/646U2/648/649 */ 86 #define CMD_DMA_IRQ(chan) (0x4 << (chan)) 87 #define CMD_DMA_IRQ_DIS(chan) (0x10 << (chan)) 88 #define CMD_DMA_RST 0x40 89 90 /* the followings are only for 0646U/646U2/648/649 */ 91 /* busmaster control/status register */ 92 #define CMD_BICSR 0x79 93 #define CMD_BICSR_80(chan) (0x01 << (chan)) 94 /* Ultra/DMA timings reg */ 95 #define CMD_UDMATIM(channel) (0x73 + (8 * (channel))) 96 #define CMD_UDMATIM_UDMA(drive) (0x01 << (drive)) 97 #define CMD_UDMATIM_UDMA33(drive) (0x04 << (drive)) 98 #define CMD_UDMATIM_TIM_MASK 0x3 99 #define CMD_UDMATIM_TIM_OFF(drive) (4 + ((drive) * 2)) 100 static const int8_t cmd0646_9_tim_udma[] __attribute__((__unused__)) = 101 {0x03, 0x02, 0x01, 0x02, 0x01, 0x00}; 102 103 /* 104 * timings values for the 0643/6/8/9 105 * for all dma_mode we have to have 106 * DMA_timings(dma_mode) >= PIO_timings(dma_mode + 2) 107 */ 108 static const int8_t cmd0643_9_data_tim_pio[] __attribute__((__unused__)) = 109 {0xA9, 0x57, 0x44, 0x32, 0x3F}; 110 static const int8_t cmd0643_9_data_tim_dma[] __attribute__((__unused__)) = 111 {0x87, 0x32, 0x3F}; 112