1 /* $NetBSD: pciide.c,v 1.6 1998/03/12 23:34:29 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Christopher G. Demetriou 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * PCI IDE controller driver. 35 * 36 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 37 * sys/dev/pci/ppb.c, revision 1.16). 38 * 39 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 40 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 41 * 5/16/94" from the PCI SIG. 42 * 43 * XXX Does not yet support DMA (but does map the Bus Master DMA regs). 44 * 45 * XXX Does not support serializing the two channels for broken (at least 46 * XXX according to linux and freebsd) controllers, e.g. CMD PCI0640. 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/device.h> 52 53 #include <dev/pci/pcireg.h> 54 #include <dev/pci/pcivar.h> 55 #include <dev/pci/pciidereg.h> 56 #include <dev/pci/pciidevar.h> 57 #include <dev/ic/wdcreg.h> 58 59 struct pciide_softc { 60 struct device sc_dev; 61 62 void *sc_pci_ih; /* PCI interrupt handle */ 63 int sc_dma_ok; /* bus-master DMA info */ 64 bus_space_tag_t sc_dma_iot; 65 bus_space_handle_t sc_dma_ioh; 66 67 struct pciide_channel { /* per-channel data */ 68 /* internal bookkeeping */ 69 int hw_ok; /* hardware mapped & OK? */ 70 struct device *dev; /* 'wdc' dev attached */ 71 int compat; /* is it compat? */ 72 void *ih; /* compat or pci handle */ 73 74 /* used by wdc attachment (read-only after init) */ 75 bus_space_tag_t cmd_iot, ctl_iot; 76 bus_space_handle_t cmd_ioh, ctl_ioh; 77 78 /* filled in by wdc attachment (written by wdc attach) */ 79 int (*ihand) __P((void *)); 80 void *ihandarg; 81 } sc_channels[PCIIDE_NUM_CHANNELS]; 82 }; 83 84 #define PCIIDE_CHANNEL_NAME(chan) ((chan) == 0 ? "primary" : "secondary") 85 86 #ifdef __BROKEN_INDIRECT_CONFIG 87 int pciide_match __P((struct device *, void *, void *)); 88 #else 89 int pciide_match __P((struct device *, struct cfdata *, void *)); 90 #endif 91 void pciide_attach __P((struct device *, struct device *, void *)); 92 93 struct cfattach pciide_ca = { 94 sizeof(struct pciide_softc), pciide_match, pciide_attach 95 }; 96 97 int pciide_map_channel_compat __P((struct pciide_softc *, 98 struct pci_attach_args *, int)); 99 const char *pciide_compat_channel_probe __P((struct pciide_softc *, 100 struct pci_attach_args *, int)); 101 int pciide_probe_wdc __P((struct pciide_channel *)); 102 int pciide_map_channel_native __P((struct pciide_softc *, 103 struct pci_attach_args *, int)); 104 int pciide_print __P((void *, const char *pnp)); 105 int pciide_compat_intr __P((void *)); 106 int pciide_pci_intr __P((void *)); 107 108 #define PCIIDE_PROBE_WDC_DELAY 100 /* 100us each */ 109 #define PCIIDE_PROBE_WDC_NDELAY 10000 /* wait up to 1s */ 110 111 int 112 pciide_match(parent, match, aux) 113 struct device *parent; 114 #ifdef __BROKEN_INDIRECT_CONFIG 115 void *match; 116 #else 117 struct cfdata *match; 118 #endif 119 void *aux; 120 { 121 struct pci_attach_args *pa = aux; 122 123 /* 124 * Check the ID register to see that it's a PCI IDE controller. 125 * If it is, we assume that we can deal with it; it _should_ 126 * work in a standardized way... 127 */ 128 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 129 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 130 return (1); 131 } 132 133 return (0); 134 } 135 136 void 137 pciide_attach(parent, self, aux) 138 struct device *parent, *self; 139 void *aux; 140 { 141 struct pci_attach_args *pa = aux; 142 pci_chipset_tag_t pc = pa->pa_pc; 143 struct pciide_softc *sc = (struct pciide_softc *)self; 144 struct pciide_attach_args aa; 145 struct pciide_channel *cp; 146 pcireg_t class, interface, csr; 147 pci_intr_handle_t intrhandle; 148 const char *intrstr; 149 char devinfo[256]; 150 int i; 151 152 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 153 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 154 155 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 156 csr = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 157 printf("%s: device disabled (at %s)\n", sc->sc_dev.dv_xname, 158 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? "device" : "bridge"); 159 return; 160 } 161 162 class = pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG); 163 interface = PCI_INTERFACE(class); 164 165 /* 166 * Set up PCI interrupt. 167 * 168 * If mapping fails, that's (probably) because there's no pin 169 * set to intr, which is (probably) because it's a compat-only 170 * device (or hard-wired in compatibility-only mode). Native-PCI 171 * channels will complain later if the interrupt was needed. 172 * 173 * If establishment fails, that's (probably) some other problem. 174 */ 175 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 176 pa->pa_intrline, &intrhandle) == 0) { 177 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 178 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, 179 IPL_BIO, pciide_pci_intr, sc); 180 181 if (sc->sc_pci_ih != NULL) { 182 printf("%s: using %s for native-PCI interrupt\n", 183 sc->sc_dev.dv_xname, 184 intrstr ? intrstr : "unknown interrupt"); 185 } else { 186 printf("%s: couldn't establish native-PCI interrupt", 187 sc->sc_dev.dv_xname); 188 if (intrstr != NULL) 189 printf(" at %s", intrstr); 190 printf("\n"); 191 } 192 } 193 194 /* 195 * Map DMA registers, if DMA is supported. 196 * 197 * Note that sc_dma_ok is the right variable to test to see if 198 * DMA can * be done. If the interface doesn't support DMA, 199 * sc_dma_ok * will never be non-zero. If the DMA regs couldn't 200 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 201 * non-zero if the interface supports DMA and the registers 202 * could be mapped. 203 * 204 * XXX Note that despite the fact that the Bus Master IDE specs 205 * XXX say that "The bus master IDE functoin uses 16 bytes of IO 206 * XXX space," some controllers (at least the United 207 * XXX Microelectronics UM8886BF) place it in memory space. 208 * XXX eventually, we should probably read the register and check 209 * XXX which type it is. Either that or 'quirk' certain devices. 210 */ 211 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 212 sc->sc_dma_ok = (pci_mapreg_map(pa, 213 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 0, 214 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 215 printf("%s: bus-master DMA support present, but unused (%s)\n", 216 sc->sc_dev.dv_xname, 217 sc->sc_dma_ok ? "no driver support" : 218 "couldn't map registers"); 219 } 220 221 for (i = 0; i < PCIIDE_NUM_CHANNELS; i++) { 222 cp = &sc->sc_channels[i]; 223 224 printf("%s: %s channel %s to %s mode\n", 225 sc->sc_dev.dv_xname, PCIIDE_CHANNEL_NAME(i), 226 (interface & PCIIDE_INTERFACE_SETTABLE(i)) ? 227 "configured" : "wired", 228 (interface & PCIIDE_INTERFACE_PCI(i)) ? "native-PCI" : 229 "compatibility"); 230 231 if (interface & PCIIDE_INTERFACE_PCI(i)) 232 cp->hw_ok = pciide_map_channel_native(sc, pa, i); 233 else 234 cp->hw_ok = pciide_map_channel_compat(sc, pa, i); 235 if (!cp->hw_ok) 236 continue; 237 238 aa.channel = i; 239 aa.cmd_iot = cp->cmd_iot; 240 aa.cmd_ioh = cp->cmd_ioh; 241 aa.ctl_iot = cp->ctl_iot; 242 aa.ctl_ioh = cp->ctl_ioh; 243 aa.ihandp = &cp->ihand; 244 aa.ihandargp = &cp->ihandarg; 245 cp->dev = config_found(self, &aa, pciide_print); 246 247 /* 248 * Note that if the 'wdc' device isn't configured, 249 * the controller's resources are still marked as 250 * being in use. This is a feature. 251 */ 252 } 253 } 254 255 int 256 pciide_map_channel_compat(sc, pa, chan) 257 struct pciide_softc *sc; 258 struct pci_attach_args *pa; 259 int chan; 260 { 261 struct pciide_channel *cp = &sc->sc_channels[chan]; 262 const char *probe_fail_reason; 263 int rv = 1; 264 265 cp->compat = 1; 266 267 cp->cmd_iot = pa->pa_iot; 268 if (bus_space_map(cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(chan), 269 PCIIDE_COMPAT_CMD_SIZE, 0, &cp->cmd_ioh) != 0) { 270 printf("%s: couldn't map %s channel cmd regs\n", 271 sc->sc_dev.dv_xname, PCIIDE_CHANNEL_NAME(chan)); 272 rv = 0; 273 } 274 275 cp->ctl_iot = pa->pa_iot; 276 if (bus_space_map(cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(chan), 277 PCIIDE_COMPAT_CTL_SIZE, 0, &cp->ctl_ioh) != 0) { 278 printf("%s: couldn't map %s channel ctl regs\n", 279 sc->sc_dev.dv_xname, PCIIDE_CHANNEL_NAME(chan)); 280 rv = 0; 281 } 282 283 /* 284 * If we weren't able to map the device successfully, 285 * we just give up now. Something else has already 286 * occupied those ports, indicating that the device has 287 * (probably) been completely disabled (by some nonstandard 288 * mechanism). 289 * 290 * XXX If we successfully map some ports, but not others, 291 * XXX it might make sense to unmap the ones that we mapped. 292 */ 293 if (rv == 0) 294 goto out; 295 296 /* 297 * If we were able to map the device successfully, try to 298 * make sure that there's a wdc there and that it's 299 * attributable to us. 300 * 301 * If there's not, then we assume that there's the device 302 * has been disabled and that other devices are free to use 303 * its ports. 304 */ 305 probe_fail_reason = pciide_compat_channel_probe(sc, pa, chan); 306 if (probe_fail_reason != NULL) { 307 printf("%s: %s channel ignored (%s)\n", sc->sc_dev.dv_xname, 308 PCIIDE_CHANNEL_NAME(chan), probe_fail_reason); 309 rv = 0; 310 311 bus_space_unmap(cp->cmd_iot, cp->cmd_ioh, 312 PCIIDE_COMPAT_CMD_SIZE); 313 bus_space_unmap(cp->ctl_iot, cp->ctl_ioh, 314 PCIIDE_COMPAT_CTL_SIZE); 315 316 goto out; 317 } 318 319 /* 320 * If we're here, we were able to map the device successfully 321 * and it really looks like there's a controller there. 322 * 323 * Unless those conditions are true, we don't map the 324 * compatibility interrupt. The spec indicates that if a 325 * channel is configured for compatibility mode and the PCI 326 * device's I/O space is enabled, the channel will be enabled. 327 * Hoewver, some devices seem to be able to disable invididual 328 * compatibility channels (via non-standard mechanisms). If 329 * the channel is disabled, the interrupt line can (probably) 330 * be used by other devices (and may be assigned to other 331 * devices by the BIOS). If we mapped the interrupt we might 332 * conflict with another interrupt assignment. 333 */ 334 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_dev, pa, 335 chan, pciide_compat_intr, cp); 336 if (cp->ih == NULL) { 337 printf("%s: no compatibility interrupt for use by %s channel\n", 338 sc->sc_dev.dv_xname, PCIIDE_CHANNEL_NAME(chan)); 339 rv = 0; 340 } 341 342 out: 343 return (rv); 344 } 345 346 const char * 347 pciide_compat_channel_probe(sc, pa, chan) 348 struct pciide_softc *sc; 349 struct pci_attach_args *pa; 350 { 351 pcireg_t csr; 352 const char *failreason = NULL; 353 354 /* 355 * Check to see if something appears to be there. 356 */ 357 if (!pciide_probe_wdc(&sc->sc_channels[chan])) { 358 failreason = "not responding; disabled or no drives?"; 359 goto out; 360 } 361 362 /* 363 * Now, make sure it's actually attributable to this PCI IDE 364 * channel by trying to access the channel again while the 365 * PCI IDE controller's I/O space is disabled. (If the 366 * channel no longer appears to be there, it belongs to 367 * this controller.) YUCK! 368 */ 369 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 370 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 371 csr & ~PCI_COMMAND_IO_ENABLE); 372 if (pciide_probe_wdc(&sc->sc_channels[chan])) 373 failreason = "other hardware responding at addresses"; 374 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr); 375 376 out: 377 return (failreason); 378 } 379 380 int 381 pciide_probe_wdc(cp) 382 struct pciide_channel *cp; 383 { 384 u_int8_t st0, st1; 385 int timeout; 386 387 /* 388 * Sanity check to see if the wdc channel responds at all. 389 * (Modeled on wdc_init_controller() and wdc_reset() in wdc.c.) 390 * 391 * Reset the channel, and make sure that it responds sanely 392 * after it's been reset. 393 */ 394 395 /* Reset the channel. */ 396 bus_space_write_1(cp->ctl_iot, cp->ctl_ioh, wd_aux_ctlr, 397 WDCTL_RST | WDCTL_IDS); 398 delay(1000); 399 bus_space_write_1(cp->ctl_iot, cp->ctl_ioh, wd_aux_ctlr, 400 WDCTL_IDS); 401 delay(1000); 402 (void)bus_space_read_1(cp->cmd_iot, cp->cmd_ioh, wd_error); 403 404 timeout = 0; 405 while (timeout++ < PCIIDE_PROBE_WDC_NDELAY) { 406 st0 = bus_space_read_1(cp->cmd_iot, cp->cmd_ioh, wd_status); 407 bus_space_write_1(cp->cmd_iot, cp->cmd_ioh, wd_sdh, 408 WDSD_IBM | 0x10); 409 st1 = bus_space_read_1(cp->cmd_iot, cp->cmd_ioh, wd_status); 410 411 if ((st0 & WDCS_BSY) == 0 || (st1 & WDCS_BSY) == 0) 412 return (1); 413 414 delay(PCIIDE_PROBE_WDC_DELAY); 415 } 416 /* timed out; nothing there */ 417 418 return (0); 419 } 420 421 int 422 pciide_map_channel_native(sc, pa, chan) 423 struct pciide_softc *sc; 424 struct pci_attach_args *pa; 425 int chan; 426 { 427 struct pciide_channel *cp = &sc->sc_channels[chan]; 428 int rv = 1; 429 430 cp->compat = 0; 431 432 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(chan), PCI_MAPREG_TYPE_IO, 433 0, &cp->cmd_iot, &cp->cmd_ioh, NULL, NULL) != 0) { 434 printf("%s: couldn't map %s channel cmd regs\n", 435 sc->sc_dev.dv_xname, PCIIDE_CHANNEL_NAME(chan)); 436 rv = 0; 437 } 438 439 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(chan), PCI_MAPREG_TYPE_IO, 440 0, &cp->ctl_iot, &cp->ctl_ioh, NULL, NULL) != 0) { 441 printf("%s: couldn't map %s channel ctl regs\n", 442 sc->sc_dev.dv_xname, PCIIDE_CHANNEL_NAME(chan)); 443 rv = 0; 444 } 445 446 if ((cp->ih = sc->sc_pci_ih) == NULL) { 447 printf("%s: no native-PCI interrupt for use by %s channel\n", 448 sc->sc_dev.dv_xname, PCIIDE_CHANNEL_NAME(chan)); 449 rv = 0; 450 } 451 452 return (rv); 453 } 454 455 int 456 pciide_print(aux, pnp) 457 void *aux; 458 const char *pnp; 459 { 460 struct pciide_attach_args *aa = aux; 461 462 /* only 'wdc's can attach to 'pciide's; easy. */ 463 if (pnp) 464 printf("wdc at %s", pnp); 465 printf(" channel %d", aa->channel); 466 return (UNCONF); 467 } 468 469 int 470 pciide_compat_intr(arg) 471 void *arg; 472 { 473 struct pciide_channel *cp = arg; 474 475 #ifdef DIAGNOSTIC 476 /* should only be called for a compat channel */ 477 if (cp->compat == 0) 478 panic("pciide compat intr called for non-compat chan %p\n", cp); 479 #endif 480 /* if there's no handler, that probably means no dev attached */ 481 if (cp->ihand == NULL) 482 return (0); 483 484 return ((*cp->ihand)(cp->ihandarg)); 485 } 486 487 int 488 pciide_pci_intr(arg) 489 void *arg; 490 { 491 struct pciide_softc *sc = arg; 492 struct pciide_channel *cp; 493 int i, rv, crv; 494 495 rv = 0; 496 for (i = 0; i < PCIIDE_NUM_CHANNELS; i++) { 497 cp = &sc->sc_channels[i]; 498 499 /* If a compat channel or there's no handler, skip. */ 500 if (cp->compat || cp->ihand == NULL) 501 continue; 502 503 crv = ((*cp->ihand)(cp->ihandarg)); 504 if (crv == 0) 505 ; /* leave rv alone */ 506 else if (crv == 1) 507 rv = 1; /* claim the intr */ 508 else if (rv == 0) /* crv should be -1 in this case */ 509 rv = crv; /* if we've done no better, take it */ 510 } 511 return (rv); 512 } 513