1 /* $NetBSD: pciconf.c,v 1.21 2003/03/31 21:04:40 augustss Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Allen Briggs for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 /* 38 * Derived in part from code from PMON/2000 (http://pmon.groupbsd.org/). 39 */ 40 41 /* 42 * To do: 43 * - Perform all data structure allocation dynamically, don't have 44 * statically-sized arrays ("oops, you lose because you have too 45 * many slots filled!") 46 * - Do this in 2 passes, with an MD hook to control the behavior: 47 * (1) Configure the bus (possibly including expansion 48 * ROMs. 49 * (2) Another pass to disable expansion ROMs if they're 50 * mapped (since you're not supposed to leave them 51 * mapped when you're not using them). 52 * This would facilitate MD code executing the expansion ROMs 53 * if necessary (possibly with an x86 emulator) to configure 54 * devices (e.g. VGA cards). 55 * - Deal with "anything can be hot-plugged" -- i.e., carry configuration 56 * information around & be able to reconfigure on the fly 57 * - Deal with segments (See IA64 System Abstraction Layer) 58 * - Deal with subtractive bridges (& non-spec positive/subtractive decode) 59 * - Deal with ISA/VGA/VGA palette snooping 60 * - Deal with device capabilities on bridges 61 * - Worry about changing a bridge to/from transparency 62 * From thorpej (05/25/01) 63 * - Try to handle devices that are already configured (perhaps using that 64 * as a hint to where we put other devices) 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: pciconf.c,v 1.21 2003/03/31 21:04:40 augustss Exp $"); 69 70 #include "opt_pci.h" 71 72 #include <sys/param.h> 73 #include <sys/extent.h> 74 #include <sys/queue.h> 75 #include <sys/systm.h> 76 #include <sys/malloc.h> 77 78 #include <dev/pci/pcivar.h> 79 #include <dev/pci/pciconf.h> 80 #include <dev/pci/pcidevs.h> 81 82 int pci_conf_debug = 0; 83 84 #if !defined(MIN) 85 #define MIN(a,b) (((a)<(b))?(a):(b)) 86 #define MAX(a,b) (((a)>(b))?(a):(b)) 87 #endif 88 89 /* per-bus constants. */ 90 #define MAX_CONF_DEV 32 /* Arbitrary */ 91 #define MAX_CONF_MEM (3 * MAX_CONF_DEV) /* Avg. 3 per device -- Arb. */ 92 #define MAX_CONF_IO (3 * MAX_CONF_DEV) /* Avg. 1 per device -- Arb. */ 93 94 struct _s_pciconf_bus_t; /* Forward declaration */ 95 96 typedef struct _s_pciconf_dev_t { 97 int ipin; 98 int iline; 99 int min_gnt; 100 int max_lat; 101 int enable; 102 pcitag_t tag; 103 pci_chipset_tag_t pc; 104 struct _s_pciconf_bus_t *ppb; /* I am really a bridge */ 105 } pciconf_dev_t; 106 107 typedef struct _s_pciconf_win_t { 108 pciconf_dev_t *dev; 109 int reg; /* 0 for busses */ 110 int align; 111 int prefetch; 112 u_int64_t size; 113 u_int64_t address; 114 } pciconf_win_t; 115 116 typedef struct _s_pciconf_bus_t { 117 int busno; 118 int next_busno; 119 int last_busno; 120 int max_mingnt; 121 int min_maxlat; 122 int cacheline_size; 123 int prefetch; 124 int fast_b2b; 125 int freq_66; 126 int def_ltim; 127 int max_ltim; 128 int bandwidth_used; 129 int swiz; 130 int io_32bit; 131 int pmem_64bit; 132 133 int ndevs; 134 pciconf_dev_t device[MAX_CONF_DEV]; 135 136 /* These should be sorted in order of decreasing size */ 137 int nmemwin; 138 pciconf_win_t pcimemwin[MAX_CONF_MEM]; 139 int niowin; 140 pciconf_win_t pciiowin[MAX_CONF_IO]; 141 142 bus_size_t io_total; 143 bus_size_t mem_total; 144 bus_size_t pmem_total; 145 146 struct extent *ioext; 147 struct extent *memext; 148 struct extent *pmemext; 149 150 pci_chipset_tag_t pc; 151 struct _s_pciconf_bus_t *parent_bus; 152 } pciconf_bus_t; 153 154 static int probe_bus(pciconf_bus_t *); 155 static void alloc_busno(pciconf_bus_t *, pciconf_bus_t *); 156 static void set_busreg(pci_chipset_tag_t, pcitag_t, int, int, int); 157 static int pci_do_device_query(pciconf_bus_t *, pcitag_t, int, int, int); 158 static int setup_iowins(pciconf_bus_t *); 159 static int setup_memwins(pciconf_bus_t *); 160 static int configure_bridge(pciconf_dev_t *); 161 static int configure_bus(pciconf_bus_t *); 162 static u_int64_t pci_allocate_range(struct extent *, u_int64_t, int); 163 static pciconf_win_t *get_io_desc(pciconf_bus_t *, bus_size_t); 164 static pciconf_win_t *get_mem_desc(pciconf_bus_t *, bus_size_t); 165 static pciconf_bus_t *query_bus(pciconf_bus_t *, pciconf_dev_t *, int); 166 167 static void print_tag(pci_chipset_tag_t, pcitag_t); 168 169 static void 170 print_tag(pci_chipset_tag_t pc, pcitag_t tag) 171 { 172 int bus, dev, func; 173 174 pci_decompose_tag(pc, tag, &bus, &dev, &func); 175 printf("PCI: bus %d, device %d, function %d: ", bus, dev, func); 176 } 177 178 /************************************************************************/ 179 /************************************************************************/ 180 /*********************** Bus probing routines ***********************/ 181 /************************************************************************/ 182 /************************************************************************/ 183 static pciconf_win_t * 184 get_io_desc(pciconf_bus_t *pb, bus_size_t size) 185 { 186 int i, n; 187 188 n = pb->niowin; 189 for (i=n; i > 0 && size > pb->pciiowin[i-1].size; i--) 190 pb->pciiowin[i] = pb->pciiowin[i-1]; /* struct copy */ 191 return &pb->pciiowin[i]; 192 } 193 194 static pciconf_win_t * 195 get_mem_desc(pciconf_bus_t *pb, bus_size_t size) 196 { 197 int i, n; 198 199 n = pb->nmemwin; 200 for (i=n; i > 0 && size > pb->pcimemwin[i-1].size; i--) 201 pb->pcimemwin[i] = pb->pcimemwin[i-1]; /* struct copy */ 202 return &pb->pcimemwin[i]; 203 } 204 205 /* 206 * Set up bus common stuff, then loop over devices & functions. 207 * If we find something, call pci_do_device_query()). 208 */ 209 static int 210 probe_bus(pciconf_bus_t *pb) 211 { 212 int device, maxdevs; 213 #ifdef __PCI_BUS_DEVORDER 214 char devs[32]; 215 int i; 216 #endif 217 218 maxdevs = pci_bus_maxdevs(pb->pc, pb->busno); 219 pb->ndevs = 0; 220 pb->niowin = 0; 221 pb->nmemwin = 0; 222 pb->freq_66 = 1; 223 #ifdef PCICONF_NO_FAST_B2B 224 pb->fast_b2b = 0; 225 #else 226 pb->fast_b2b = 1; 227 #endif 228 pb->prefetch = 1; 229 pb->max_mingnt = 0; /* we are looking for the maximum */ 230 pb->min_maxlat = 0x100; /* we are looking for the minimum */ 231 pb->bandwidth_used = 0; 232 233 #ifdef __PCI_BUS_DEVORDER 234 pci_bus_devorder(pb->pc, pb->busno, devs); 235 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) { 236 #else 237 for (device = 0; device < maxdevs; device++) { 238 #endif 239 pcitag_t tag; 240 pcireg_t id, bhlcr; 241 int function, nfunction; 242 int confmode; 243 244 tag = pci_make_tag(pb->pc, pb->busno, device, 0); 245 if (pci_conf_debug) { 246 print_tag(pb->pc, tag); 247 } 248 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 249 250 if (pci_conf_debug) { 251 printf("id=%x: Vendor=%x, Product=%x\n", 252 id, PCI_VENDOR(id),PCI_PRODUCT(id)); 253 } 254 /* Invalid vendor ID value? */ 255 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 256 continue; 257 258 bhlcr = pci_conf_read(pb->pc, tag, PCI_BHLC_REG); 259 nfunction = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 260 for (function = 0 ; function < nfunction ; function++) { 261 tag = pci_make_tag(pb->pc, pb->busno, device, function); 262 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 263 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 264 continue; 265 if (pb->ndevs+1 < MAX_CONF_DEV) { 266 if (pci_conf_debug) { 267 print_tag(pb->pc, tag); 268 printf("Found dev 0x%04x 0x%04x -- " 269 "really probing.\n", 270 PCI_VENDOR(id), PCI_PRODUCT(id)); 271 } 272 #ifdef __HAVE_PCI_CONF_HOOK 273 confmode = pci_conf_hook(pb->pc, pb->busno, 274 device, function, id); 275 if (confmode == 0) 276 continue; 277 #else 278 /* 279 * Don't enable expansion ROMS -- some cards 280 * share address decoders between the EXPROM 281 * and PCI memory space, and enabling the ROM 282 * when not needed will cause all sorts of 283 * lossage. 284 */ 285 confmode = PCI_CONF_ALL & ~PCI_CONF_MAP_ROM; 286 #endif 287 if (pci_do_device_query(pb, tag, device, 288 function, confmode)) 289 return -1; 290 pb->ndevs++; 291 } 292 } 293 } 294 return 0; 295 } 296 297 static void 298 alloc_busno(pciconf_bus_t *parent, pciconf_bus_t *pb) 299 { 300 pb->busno = parent->next_busno; 301 pb->next_busno = pb->busno + 1; 302 } 303 304 static void 305 set_busreg(pci_chipset_tag_t pc, pcitag_t tag, int prim, int sec, int sub) 306 { 307 pcireg_t busreg; 308 309 busreg = prim << PCI_BRIDGE_BUS_PRIMARY_SHIFT; 310 busreg |= sec << PCI_BRIDGE_BUS_SECONDARY_SHIFT; 311 busreg |= sub << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT; 312 pci_conf_write(pc, tag, PCI_BRIDGE_BUS_REG, busreg); 313 } 314 315 static pciconf_bus_t * 316 query_bus(pciconf_bus_t *parent, pciconf_dev_t *pd, int dev) 317 { 318 pciconf_bus_t *pb; 319 pcireg_t io, pmem; 320 pciconf_win_t *pi, *pm; 321 322 pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT); 323 if (!pb) 324 panic("Unable to allocate memory for PCI configuration."); 325 326 pb->cacheline_size = parent->cacheline_size; 327 pb->parent_bus = parent; 328 alloc_busno(parent, pb); 329 330 set_busreg(parent->pc, pd->tag, parent->busno, pb->busno, 0xff); 331 332 pb->swiz = parent->swiz + dev; 333 334 pb->ioext = NULL; 335 pb->memext = NULL; 336 pb->pmemext = NULL; 337 pb->pc = parent->pc; 338 pb->io_total = pb->mem_total = pb->pmem_total = 0; 339 340 pb->io_32bit = 0; 341 if (parent->io_32bit) { 342 io = pci_conf_read(parent->pc, pd->tag, PCI_BRIDGE_STATIO_REG); 343 if (PCI_BRIDGE_IO_32BITS(io)) { 344 pb->io_32bit = 1; 345 } 346 } 347 348 pb->pmem_64bit = 0; 349 if (parent->pmem_64bit) { 350 pmem = pci_conf_read(parent->pc, pd->tag, 351 PCI_BRIDGE_PREFETCHMEM_REG); 352 if (PCI_BRIDGE_PREFETCHMEM_64BITS(pmem)) { 353 pb->pmem_64bit = 1; 354 } 355 } 356 357 if (probe_bus(pb)) { 358 printf("Failed to probe bus %d\n", pb->busno); 359 goto err; 360 } 361 362 /* We have found all subordinate busses now, reprogram busreg. */ 363 pb->last_busno = pb->next_busno-1; 364 parent->next_busno = pb->next_busno; 365 set_busreg(parent->pc, pd->tag, parent->busno, pb->busno, 366 pb->last_busno); 367 if (pci_conf_debug) 368 printf("PCI bus bridge (parent %d) covers busses %d-%d\n", 369 parent->busno, pb->busno, pb->last_busno); 370 371 if (pb->io_total > 0) { 372 if (parent->niowin >= MAX_CONF_IO) { 373 printf("pciconf: too many I/O windows\n"); 374 goto err; 375 } 376 pb->io_total |= 0xfff; /* Round up */ 377 pi = get_io_desc(parent, pb->io_total); 378 pi->dev = pd; 379 pi->reg = 0; 380 pi->size = pb->io_total; 381 pi->align = 0x1000; /* 4K alignment */ 382 pi->prefetch = 0; 383 parent->niowin++; 384 parent->io_total += pb->io_total; 385 } 386 387 if (pb->mem_total > 0) { 388 if (parent->nmemwin >= MAX_CONF_MEM) { 389 printf("pciconf: too many MEM windows\n"); 390 goto err; 391 } 392 pb->mem_total |= 0xfffff; /* Round up */ 393 pm = get_mem_desc(parent, pb->mem_total); 394 pm->dev = pd; 395 pm->reg = 0; 396 pm->size = pb->mem_total; 397 pm->align = 0x100000; /* 1M alignment */ 398 pm->prefetch = 0; 399 parent->nmemwin++; 400 parent->mem_total += pb->mem_total; 401 } 402 403 if (pb->pmem_total > 0) { 404 if (parent->nmemwin >= MAX_CONF_MEM) { 405 printf("pciconf: too many MEM windows\n"); 406 goto err; 407 } 408 pb->pmem_total |= 0xfffff; /* Round up */ 409 pm = get_mem_desc(parent, pb->pmem_total); 410 pm->dev = pd; 411 pm->reg = 0; 412 pm->size = pb->pmem_total; 413 pm->align = 0x100000; /* 1M alignment */ 414 pm->prefetch = 1; 415 parent->nmemwin++; 416 parent->pmem_total += pb->pmem_total; 417 } 418 419 return pb; 420 err: 421 free(pb, M_DEVBUF); 422 return NULL; 423 } 424 425 static int 426 pci_do_device_query(pciconf_bus_t *pb, pcitag_t tag, int dev, int func, int mode) 427 { 428 pciconf_dev_t *pd; 429 pciconf_win_t *pi, *pm; 430 pcireg_t class, cmd, icr, bar, mask, bar64, mask64; 431 u_int64_t size; 432 int br, width; 433 434 pd = &pb->device[pb->ndevs]; 435 pd->pc = pb->pc; 436 pd->tag = tag; 437 pd->ppb = NULL; 438 pd->enable = mode; 439 440 class = pci_conf_read(pb->pc, tag, PCI_CLASS_REG); 441 442 cmd = pci_conf_read(pb->pc, tag, PCI_COMMAND_STATUS_REG); 443 444 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE) { 445 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 446 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 447 pci_conf_write(pb->pc, tag, PCI_COMMAND_STATUS_REG, cmd); 448 } else if (pci_conf_debug) { 449 print_tag(pb->pc, tag); 450 printf("device is a bridge; not clearing enables\n"); 451 } 452 453 if ((cmd & PCI_STATUS_BACKTOBACK_SUPPORT) == 0) 454 pb->fast_b2b = 0; 455 456 if ((cmd & PCI_STATUS_66MHZ_SUPPORT) == 0) 457 pb->freq_66 = 0; 458 459 if ( (PCI_CLASS(class) == PCI_CLASS_BRIDGE) 460 && (PCI_SUBCLASS(class) == PCI_SUBCLASS_BRIDGE_PCI)) { 461 pd->ppb = query_bus(pb, pd, dev); 462 if (pd->ppb == NULL) 463 return -1; 464 return 0; 465 } 466 467 icr = pci_conf_read(pb->pc, tag, PCI_INTERRUPT_REG); 468 pd->ipin = PCI_INTERRUPT_PIN(icr); 469 pd->iline = PCI_INTERRUPT_LINE(icr); 470 pd->min_gnt = PCI_MIN_GNT(icr); 471 pd->max_lat = PCI_MAX_LAT(icr); 472 if (pd->iline || pd->ipin) { 473 pci_conf_interrupt(pb->pc, pb->busno, dev, pd->ipin, pb->swiz, 474 &pd->iline); 475 icr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 476 icr |= (pd->iline << PCI_INTERRUPT_LINE_SHIFT); 477 pci_conf_write(pb->pc, tag, PCI_INTERRUPT_REG, icr); 478 } 479 480 if (pd->min_gnt != 0 || pd->max_lat != 0) { 481 if (pd->min_gnt != 0 && pd->min_gnt > pb->max_mingnt) 482 pb->max_mingnt = pd->min_gnt; 483 484 if (pd->max_lat != 0 && pd->max_lat < pb->min_maxlat) 485 pb->min_maxlat = pd->max_lat; 486 487 pb->bandwidth_used += pd->min_gnt * 4000000 / 488 (pd->min_gnt + pd->max_lat); 489 } 490 491 width = 4; 492 for (br = PCI_MAPREG_START; br < PCI_MAPREG_END; br += width) { 493 #if 0 494 /* XXX Should only ignore if IDE not in legacy mode? */ 495 if (PCI_CLASS(class) == PCI_CLASS_MASS_STORAGE && 496 PCI_SUBCLASS(class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 497 break; 498 } 499 #endif 500 bar = pci_conf_read(pb->pc, tag, br); 501 pci_conf_write(pb->pc, tag, br, 0xffffffff); 502 mask = pci_conf_read(pb->pc, tag, br); 503 pci_conf_write(pb->pc, tag, br, bar); 504 width = 4; 505 506 if ( (mode & PCI_CONF_MAP_IO) 507 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_IO)) { 508 /* 509 * Upper 16 bits must be one. Devices may hardwire 510 * them to zero, though, per PCI 2.2, 6.2.5.1, p 203. 511 */ 512 mask |= 0xffff0000; 513 514 size = PCI_MAPREG_IO_SIZE(mask); 515 if (size == 0) { 516 if (pci_conf_debug) { 517 print_tag(pb->pc, tag); 518 printf("I/O BAR 0x%x is void\n", br); 519 } 520 continue; 521 } 522 523 if (pb->niowin >= MAX_CONF_IO) { 524 printf("pciconf: too many I/O windows\n"); 525 return -1; 526 } 527 528 pi = get_io_desc(pb, size); 529 pi->dev = pd; 530 pi->reg = br; 531 pi->size = (u_int64_t) size; 532 pi->align = 4; 533 pi->prefetch = 0; 534 if (pci_conf_debug) { 535 print_tag(pb->pc, tag); 536 printf("Register 0x%x, I/O size %llu\n", 537 br, pi->size); 538 } 539 pb->niowin++; 540 pb->io_total += size; 541 } else if ((mode & PCI_CONF_MAP_MEM) 542 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_MEM)) { 543 switch (PCI_MAPREG_MEM_TYPE(mask)) { 544 case PCI_MAPREG_MEM_TYPE_32BIT: 545 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 546 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 547 break; 548 case PCI_MAPREG_MEM_TYPE_64BIT: 549 bar64 = pci_conf_read(pb->pc, tag, br + 4); 550 pci_conf_write(pb->pc, tag, br + 4, 0xffffffff); 551 mask64 = pci_conf_read(pb->pc, tag, br + 4); 552 pci_conf_write(pb->pc, tag, br + 4, bar64); 553 size = (u_int64_t) PCI_MAPREG_MEM64_SIZE( 554 (((u_int64_t) mask64) << 32) | mask); 555 width = 8; 556 break; 557 default: 558 print_tag(pb->pc, tag); 559 printf("reserved mapping type 0x%x\n", 560 PCI_MAPREG_MEM_TYPE(mask)); 561 continue; 562 } 563 564 if (size == 0) { 565 if (pci_conf_debug) { 566 print_tag(pb->pc, tag); 567 printf("MEM%d BAR 0x%x is void\n", 568 PCI_MAPREG_MEM_TYPE(mask) == 569 PCI_MAPREG_MEM_TYPE_64BIT ? 570 64 : 32, br); 571 } 572 continue; 573 } else { 574 if (pci_conf_debug) { 575 print_tag(pb->pc, tag); 576 printf("MEM%d BAR 0x%x has size %lx\n", 577 PCI_MAPREG_MEM_TYPE(mask) == 578 PCI_MAPREG_MEM_TYPE_64BIT ? 579 64 : 32, br, (unsigned long)size); 580 } 581 } 582 583 if (pb->nmemwin >= MAX_CONF_MEM) { 584 printf("pciconf: too many memory windows\n"); 585 return -1; 586 } 587 588 pm = get_mem_desc(pb, size); 589 pm->dev = pd; 590 pm->reg = br; 591 pm->size = size; 592 pm->align = 4; 593 pm->prefetch = PCI_MAPREG_MEM_PREFETCHABLE(mask); 594 if (pci_conf_debug) { 595 print_tag(pb->pc, tag); 596 printf("Register 0x%x, memory size %llu\n", 597 br, pm->size); 598 } 599 pb->nmemwin++; 600 if (pm->prefetch) { 601 pb->pmem_total += size; 602 } else { 603 pb->mem_total += size; 604 } 605 } 606 } 607 608 if (mode & PCI_CONF_MAP_ROM) { 609 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 610 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe); 611 mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 612 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, bar); 613 614 if (mask != 0 && mask != 0xffffffff) { 615 if (pb->nmemwin >= MAX_CONF_MEM) { 616 printf("pciconf: too many memory windows\n"); 617 return -1; 618 } 619 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 620 621 pm = get_mem_desc(pb, size); 622 pm->dev = pd; 623 pm->reg = PCI_MAPREG_ROM; 624 pm->size = size; 625 pm->align = 4; 626 pm->prefetch = 1; 627 if (pci_conf_debug) { 628 print_tag(pb->pc, tag); 629 printf("Expansion ROM memory size %llu\n", pm->size); 630 } 631 pb->nmemwin++; 632 pb->pmem_total += size; 633 } 634 } else { 635 /* Ensure ROM is disabled */ 636 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 637 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe); 638 mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 639 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 640 bar & ~PCI_MAPREG_ROM_ENABLE); 641 } 642 643 return 0; 644 } 645 646 /************************************************************************/ 647 /************************************************************************/ 648 /******************** Bus configuration routines ********************/ 649 /************************************************************************/ 650 /************************************************************************/ 651 static u_int64_t 652 pci_allocate_range(struct extent *ex, u_int64_t amt, int align) 653 { 654 int r; 655 u_long addr; 656 657 r = extent_alloc(ex, amt, align, 0, EX_NOWAIT, &addr); 658 if (r) { 659 addr = (u_long) -1; 660 printf("extent_alloc(%p, %llu, %d) returned %d\n", 661 ex, amt, align, r); 662 extent_print(ex); 663 } 664 return (pcireg_t) addr; 665 } 666 667 static int 668 setup_iowins(pciconf_bus_t *pb) 669 { 670 pciconf_win_t *pi; 671 pciconf_dev_t *pd; 672 673 for (pi=pb->pciiowin; pi < &pb->pciiowin[pb->niowin] ; pi++) { 674 if (pi->size == 0) 675 continue; 676 677 pd = pi->dev; 678 pi->address = pci_allocate_range(pb->ioext, pi->size, 679 pi->align); 680 if (pi->address == -1) { 681 print_tag(pd->pc, pd->tag); 682 printf("Failed to allocate PCI I/O space (%llu req)\n", 683 pi->size); 684 return -1; 685 } 686 if (!pb->io_32bit && pi->address > 0xFFFF) { 687 pi->address = 0; 688 pd->enable = 0; 689 } 690 if (pd->ppb && pi->reg == 0) { 691 pd->ppb->ioext = extent_create("pciconf", pi->address, 692 pi->address + pi->size, M_DEVBUF, NULL, 0, 693 EX_NOWAIT); 694 if (pd->ppb->ioext == NULL) { 695 print_tag(pd->pc, pd->tag); 696 printf("Failed to alloc I/O ext. for bus %d\n", 697 pd->ppb->busno); 698 return -1; 699 } 700 continue; 701 } 702 pd->enable |= PCI_CONF_ENABLE_IO; 703 if (pci_conf_debug) { 704 print_tag(pd->pc, pd->tag); 705 printf("Putting %llu I/O bytes @ %#llx (reg %x)\n", 706 pi->size, pi->address, pi->reg); 707 } 708 pci_conf_write(pd->pc, pd->tag, pi->reg, 709 PCI_MAPREG_IO_ADDR(pi->address) | PCI_MAPREG_TYPE_IO); 710 } 711 return 0; 712 } 713 714 static int 715 setup_memwins(pciconf_bus_t *pb) 716 { 717 pciconf_win_t *pm; 718 pciconf_dev_t *pd; 719 pcireg_t base; 720 struct extent *ex; 721 722 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 723 if (pm->size == 0) 724 continue; 725 726 pd = pm->dev; 727 ex = (pm->prefetch) ? pb->pmemext : pb->memext; 728 pm->address = pci_allocate_range(ex, pm->size, pm->align); 729 if (pm->address == -1) { 730 print_tag(pd->pc, pd->tag); 731 printf( 732 "Failed to allocate PCI memory space (%llu req)\n", 733 pm->size); 734 return -1; 735 } 736 if (pd->ppb && pm->reg == 0) { 737 ex = extent_create("pciconf", pm->address, 738 pm->address + pm->size, M_DEVBUF, NULL, 0, 739 EX_NOWAIT); 740 if (ex == NULL) { 741 print_tag(pd->pc, pd->tag); 742 printf("Failed to alloc MEM ext. for bus %d\n", 743 pd->ppb->busno); 744 return -1; 745 } 746 if (pm->prefetch) { 747 pd->ppb->pmemext = ex; 748 } else { 749 pd->ppb->memext = ex; 750 } 751 continue; 752 } 753 if (pm->prefetch && !pb->pmem_64bit && 754 pm->address > 0xFFFFFFFFULL) { 755 pm->address = 0; 756 pd->enable = 0; 757 } else { 758 pd->enable |= PCI_CONF_ENABLE_MEM; 759 } 760 if (pm->reg != PCI_MAPREG_ROM) { 761 if (pci_conf_debug) { 762 print_tag(pd->pc, pd->tag); 763 printf( 764 "Putting %llu MEM bytes @ %#llx (reg %x)\n", 765 pm->size, pm->address, pm->reg); 766 } 767 base = pci_conf_read(pd->pc, pd->tag, pm->reg); 768 base = PCI_MAPREG_MEM_ADDR(pm->address) | 769 PCI_MAPREG_MEM_TYPE(base); 770 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 771 if (PCI_MAPREG_MEM_TYPE(base) == 772 PCI_MAPREG_MEM_TYPE_64BIT) { 773 base = (pcireg_t) 774 (PCI_MAPREG_MEM64_ADDR(pm->address) >> 32); 775 pci_conf_write(pd->pc, pd->tag, pm->reg + 4, 776 base); 777 } 778 } 779 } 780 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 781 if (pm->reg == PCI_MAPREG_ROM && pm->address != -1) { 782 pd = pm->dev; 783 if (pci_conf_debug) { 784 print_tag(pd->pc, pd->tag); 785 printf( 786 "Putting %llu ROM bytes @ %#llx (reg %x)\n", 787 pm->size, pm->address, pm->reg); 788 } 789 base = (pcireg_t) (pm->address | PCI_MAPREG_ROM_ENABLE); 790 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 791 } 792 } 793 return 0; 794 } 795 796 /* 797 * Configure I/O, memory, and prefetcable memory spaces, then make 798 * a call to configure_bus(). 799 */ 800 static int 801 configure_bridge(pciconf_dev_t *pd) 802 { 803 unsigned long io_base, io_limit, mem_base, mem_limit; 804 pciconf_bus_t *pb; 805 pcireg_t io, iohigh, mem, cmd; 806 int rv; 807 808 pb = pd->ppb; 809 /* Configure I/O base & limit*/ 810 if (pb->ioext) { 811 io_base = pb->ioext->ex_start; 812 io_limit = pb->ioext->ex_end; 813 } else { 814 io_base = 0x1000; /* 4K */ 815 io_limit = 0x0000; 816 } 817 if (pb->io_32bit) { 818 iohigh = 819 ((io_base >> 16) << PCI_BRIDGE_IOHIGH_BASE_SHIFT) | 820 ((io_limit >> 16) << PCI_BRIDGE_IOHIGH_LIMIT_SHIFT); 821 } else { 822 if (io_limit > 0xFFFF) { 823 printf("Bus %d bridge does not support 32-bit I/O. ", 824 pb->busno); 825 printf("Disabling I/O accesses\n"); 826 io_base = 0x1000; /* 4K */ 827 io_limit = 0x0000; 828 } 829 iohigh = 0; 830 } 831 io = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG) & 832 (PCI_BRIDGE_STATIO_STATUS_MASK << PCI_BRIDGE_STATIO_STATUS_SHIFT); 833 io |= (((io_base >> 8) & PCI_BRIDGE_STATIO_IOBASE_MASK) 834 << PCI_BRIDGE_STATIO_IOBASE_SHIFT); 835 io |= (((io_limit >> 8) & PCI_BRIDGE_STATIO_IOLIMIT_MASK) 836 << PCI_BRIDGE_STATIO_IOLIMIT_SHIFT); 837 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG, io); 838 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_IOHIGH_REG, iohigh); 839 840 /* Configure mem base & limit */ 841 if (pb->memext) { 842 mem_base = pb->memext->ex_start; 843 mem_limit = pb->memext->ex_end; 844 } else { 845 mem_base = 0x100000; /* 1M */ 846 mem_limit = 0x000000; 847 } 848 #if ULONG_MAX > 0xffffffff 849 if (mem_limit > 0xFFFFFFFFULL) { 850 printf("Bus %d bridge MEM range out of range. ", pb->busno); 851 printf("Disabling MEM accesses\n"); 852 mem_base = 0x100000; /* 1M */ 853 mem_limit = 0x000000; 854 } 855 #endif 856 mem = (((mem_base >> 20) & PCI_BRIDGE_MEMORY_BASE_MASK) 857 << PCI_BRIDGE_MEMORY_BASE_SHIFT); 858 mem |= (((mem_limit >> 20) & PCI_BRIDGE_MEMORY_LIMIT_MASK) 859 << PCI_BRIDGE_MEMORY_LIMIT_SHIFT); 860 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_MEMORY_REG, mem); 861 862 /* Configure prefetchable mem base & limit */ 863 if (pb->pmemext) { 864 mem_base = pb->pmemext->ex_start; 865 mem_limit = pb->pmemext->ex_end; 866 } else { 867 mem_base = 0x100000; /* 1M */ 868 mem_limit = 0x000000; 869 } 870 mem = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG); 871 #if ULONG_MAX > 0xffffffff 872 if (!PCI_BRIDGE_PREFETCHMEM_64BITS(mem) && mem_limit > 0xFFFFFFFFULL) { 873 printf("Bus %d bridge does not support 64-bit PMEM. ", 874 pb->busno); 875 printf("Disabling prefetchable-MEM accesses\n"); 876 mem_base = 0x100000; /* 1M */ 877 mem_limit = 0x000000; 878 } 879 #endif 880 mem = (((mem_base >> 20) & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) 881 << PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT); 882 mem |= (((mem_limit >> 20) & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) 883 << PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT); 884 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG, mem); 885 /* 886 * XXX -- 64-bit systems need a lot more than just this... 887 */ 888 if (sizeof(u_long) > 4) { 889 mem_base = (int64_t) mem_base >> 32; 890 mem_limit = (int64_t) mem_limit >> 32; 891 } 892 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHBASE32_REG, 893 mem_base & 0xffffffff); 894 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHLIMIT32_REG, 895 mem_limit & 0xffffffff); 896 897 rv = configure_bus(pb); 898 899 if (pb->ioext) 900 extent_destroy(pb->ioext); 901 if (pb->memext) 902 extent_destroy(pb->memext); 903 if (pb->pmemext) 904 extent_destroy(pb->pmemext); 905 if (rv == 0) { 906 cmd = pci_conf_read(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG); 907 cmd &= PCI_BRIDGE_CONTROL_MASK; 908 cmd |= (PCI_BRIDGE_CONTROL_PERE | PCI_BRIDGE_CONTROL_SERR) 909 << PCI_BRIDGE_CONTROL_SHIFT; 910 if (pb->fast_b2b) { 911 cmd |= PCI_BRIDGE_CONTROL_SECFASTB2B 912 << PCI_BRIDGE_CONTROL_SHIFT; 913 } 914 pci_conf_write(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG, cmd); 915 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 916 cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 917 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 918 } 919 920 return rv; 921 } 922 923 /* 924 * Calculate latency values, allocate I/O and MEM segments, then set them 925 * up. If a PCI-PCI bridge is found, configure the bridge separately, 926 * which will cause a recursive call back here. 927 */ 928 static int 929 configure_bus(pciconf_bus_t *pb) 930 { 931 pciconf_dev_t *pd; 932 int def_ltim, max_ltim, band, bus_mhz; 933 934 if (pb->ndevs == 0) { 935 if (pci_conf_debug) 936 printf("PCI bus %d - no devices\n", pb->busno); 937 return (1); 938 } 939 bus_mhz = pb->freq_66 ? 66 : 33; 940 max_ltim = pb->max_mingnt * bus_mhz / 4; /* cvt to cycle count */ 941 band = 40000000; /* 0.25us cycles/sec */ 942 if (band < pb->bandwidth_used) { 943 printf("PCI bus %d: Warning: Total bandwidth exceeded!?\n", 944 pb->busno); 945 def_ltim = -1; 946 } else { 947 def_ltim = (band - pb->bandwidth_used) / pb->ndevs; 948 if (def_ltim > pb->min_maxlat) 949 def_ltim = pb->min_maxlat; 950 def_ltim = def_ltim * bus_mhz / 4; 951 } 952 def_ltim = (def_ltim + 7) & ~7; 953 max_ltim = (max_ltim + 7) & ~7; 954 955 pb->def_ltim = MIN( def_ltim, 255 ); 956 pb->max_ltim = MIN( MAX(max_ltim, def_ltim ), 255 ); 957 958 /* 959 * Now we have what we need to initialize the devices. 960 * It would probably be better if we could allocate all of these 961 * for all busses at once, but "not right now". First, get a list 962 * of free memory ranges from the m.d. system. 963 */ 964 if (setup_iowins(pb) || setup_memwins(pb)) { 965 printf("PCI bus configuration failed: "); 966 printf("unable to assign all I/O and memory ranges."); 967 return -1; 968 } 969 970 /* 971 * Configure the latency for the devices, and enable them. 972 */ 973 for (pd=pb->device ; pd < &pb->device[pb->ndevs] ; pd++) { 974 pcireg_t cmd, class, misc; 975 int ltim; 976 977 if (pci_conf_debug) { 978 print_tag(pd->pc, pd->tag); 979 printf("Configuring device.\n"); 980 } 981 class = pci_conf_read(pd->pc, pd->tag, PCI_CLASS_REG); 982 misc = pci_conf_read(pd->pc, pd->tag, PCI_BHLC_REG); 983 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 984 cmd |= PCI_COMMAND_SERR_ENABLE | PCI_COMMAND_PARITY_ENABLE; 985 if (pb->fast_b2b) 986 cmd |= PCI_COMMAND_BACKTOBACK_ENABLE; 987 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE || 988 PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_PCI) { 989 if (pd->enable & PCI_CONF_ENABLE_IO) 990 cmd |= PCI_COMMAND_IO_ENABLE; 991 if (pd->enable & PCI_CONF_ENABLE_MEM) 992 cmd |= PCI_COMMAND_MEM_ENABLE; 993 if (pd->enable & PCI_CONF_ENABLE_BM) 994 cmd |= PCI_COMMAND_MASTER_ENABLE; 995 ltim = pd->min_gnt * bus_mhz / 4; 996 ltim = MIN (MAX (pb->def_ltim, ltim), pb->max_ltim); 997 } else { 998 cmd |= PCI_COMMAND_MASTER_ENABLE; 999 ltim = MIN (pb->def_ltim, pb->max_ltim); 1000 } 1001 if (!(pd->enable)) { 1002 print_tag(pd->pc, pd->tag); 1003 printf("Disabled due to lack of resources.\n"); 1004 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 1005 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 1006 } 1007 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 1008 1009 misc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) | 1010 (PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT)); 1011 misc |= (ltim & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT; 1012 misc |= ((pb->cacheline_size >> 2) & PCI_CACHELINE_MASK) << 1013 PCI_CACHELINE_SHIFT; 1014 pci_conf_write(pd->pc, pd->tag, PCI_BHLC_REG, misc); 1015 1016 if (pd->ppb) { 1017 if (configure_bridge(pd) < 0) 1018 return -1; 1019 continue; 1020 } 1021 } 1022 1023 if (pci_conf_debug) { 1024 printf("PCI bus %d configured\n", pb->busno); 1025 } 1026 1027 return 0; 1028 } 1029 1030 /* 1031 * Let's configure the PCI bus. 1032 * This consists of basically scanning for all existing devices, 1033 * identifying their needs, and then making another pass over them 1034 * to set: 1035 * 1. I/O addresses 1036 * 2. Memory addresses (Prefetchable and not) 1037 * 3. PCI command register 1038 * 4. The latency part of the PCI BHLC (BIST (Built-In Self Test), 1039 * Header type, Latency timer, Cache line size) register 1040 * 1041 * The command register is set to enable fast back-to-back transactions 1042 * if the host bridge says it can handle it. We also configure 1043 * Master Enable, SERR enable, parity enable, and (if this is not a 1044 * PCI-PCI bridge) the I/O and Memory spaces. Apparently some devices 1045 * will not report some I/O space. 1046 * 1047 * The latency is computed to be a "fair share" of the bus bandwidth. 1048 * The bus bandwidth variable is initialized to the number of PCI cycles 1049 * in one second. The number of cycles taken for one transaction by each 1050 * device (MAX_LAT + MIN_GNT) is then subtracted from the bandwidth. 1051 * Care is taken to ensure that the latency timer won't be set such that 1052 * it would exceed the critical time for any device. 1053 * 1054 * This is complicated somewhat due to the presence of bridges. PCI-PCI 1055 * bridges are probed and configured recursively. 1056 */ 1057 int 1058 pci_configure_bus(pci_chipset_tag_t pc, struct extent *ioext, 1059 struct extent *memext, struct extent *pmemext, int firstbus, 1060 int cacheline_size) 1061 { 1062 pciconf_bus_t *pb; 1063 int rv; 1064 1065 pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT); 1066 pb->busno = firstbus; 1067 pb->next_busno = pb->busno + 1; 1068 pb->last_busno = 255; 1069 pb->cacheline_size = cacheline_size; 1070 pb->parent_bus = NULL; 1071 pb->swiz = 0; 1072 pb->io_32bit = 1; 1073 pb->pmem_64bit = 0; 1074 pb->ioext = ioext; 1075 pb->memext = memext; 1076 if (pmemext == NULL) { 1077 pb->pmemext = memext; 1078 } else { 1079 pb->pmemext = pmemext; 1080 } 1081 pb->pc = pc; 1082 pb->io_total = pb->mem_total = pb->pmem_total = 0; 1083 1084 rv = probe_bus(pb); 1085 pb->last_busno = pb->next_busno-1; 1086 if (rv == 0) { 1087 rv = configure_bus(pb); 1088 } 1089 1090 /* 1091 * All done! 1092 */ 1093 free(pb, M_DEVBUF); 1094 return rv; 1095 } 1096