1 /* $NetBSD: pci_subr.c,v 1.224 2020/05/30 10:43:46 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.224 2020/05/30 10:43:46 jdolecek Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #include <sys/kmem.h> 56 57 #define MALLOC(sz) kmem_alloc(sz, KM_SLEEP) 58 #define FREE(p, sz) kmem_free(p, sz) 59 60 #else 61 #include <pci.h> 62 #include <stdarg.h> 63 #include <stdbool.h> 64 #include <stdio.h> 65 #include <stdlib.h> 66 #include <string.h> 67 68 #define MALLOC(sz) malloc(sz) 69 #define FREE(p, sz) free(p) 70 71 #endif 72 73 #include <dev/pci/pcireg.h> 74 #ifdef _KERNEL 75 #include <dev/pci/pcivar.h> 76 #else 77 #include <dev/pci/pci_verbose.h> 78 #include <dev/pci/pcidevs.h> 79 #include <dev/pci/pcidevs_data.h> 80 #endif 81 82 static int pci_conf_find_cap(const pcireg_t *, unsigned int, int *); 83 static int pci_conf_find_extcap(const pcireg_t *, unsigned int, int *); 84 static void pci_conf_print_pcie_power(uint8_t, unsigned int); 85 #define PCIREG_SHIFTOUT(a, b) ((pcireg_t)__SHIFTOUT((a), (b))) 86 87 /* 88 * Descriptions of known PCI classes and subclasses. 89 * 90 * Subclasses are described in the same way as classes, but have a 91 * NULL subclass pointer. 92 */ 93 struct pci_class { 94 const char *name; 95 u_int val; /* as wide as pci_{,sub}class_t */ 96 const struct pci_class *subclasses; 97 }; 98 99 /* 100 * Class 0x00. 101 * Before rev. 2.0. 102 */ 103 static const struct pci_class pci_subclass_prehistoric[] = { 104 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 105 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 106 { NULL, 0, NULL, }, 107 }; 108 109 /* 110 * Class 0x01. 111 * Mass storage controller 112 */ 113 114 /* ATA programming interface */ 115 static const struct pci_class pci_interface_ata[] = { 116 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 117 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 118 { NULL, 0, NULL, }, 119 }; 120 121 /* SATA programming interface */ 122 static const struct pci_class pci_interface_sata[] = { 123 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 124 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 125 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 126 { NULL, 0, NULL, }, 127 }; 128 129 /* Flash programming interface */ 130 static const struct pci_class pci_interface_nvm[] = { 131 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 132 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 133 { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, }, 134 { NULL, 0, NULL, }, 135 }; 136 137 /* Subclasses */ 138 static const struct pci_class pci_subclass_mass_storage[] = { 139 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 140 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 141 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 142 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 143 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 144 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 145 pci_interface_ata, }, 146 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 147 pci_interface_sata, }, 148 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 149 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 150 pci_interface_nvm, }, 151 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 152 { NULL, 0, NULL, }, 153 }; 154 155 /* 156 * Class 0x02. 157 * Network controller. 158 */ 159 static const struct pci_class pci_subclass_network[] = { 160 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 161 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 162 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 163 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 164 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 165 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 166 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 167 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 168 { NULL, 0, NULL, }, 169 }; 170 171 /* 172 * Class 0x03. 173 * Display controller. 174 */ 175 176 /* VGA programming interface */ 177 static const struct pci_class pci_interface_vga[] = { 178 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 179 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 180 { NULL, 0, NULL, }, 181 }; 182 /* Subclasses */ 183 static const struct pci_class pci_subclass_display[] = { 184 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 185 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 186 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 187 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 188 { NULL, 0, NULL, }, 189 }; 190 191 /* 192 * Class 0x04. 193 * Multimedia device. 194 */ 195 static const struct pci_class pci_subclass_multimedia[] = { 196 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 197 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 198 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 199 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 200 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 201 { NULL, 0, NULL, }, 202 }; 203 204 /* 205 * Class 0x05. 206 * Memory controller. 207 */ 208 static const struct pci_class pci_subclass_memory[] = { 209 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 210 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 211 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 212 { NULL, 0, NULL, }, 213 }; 214 215 /* 216 * Class 0x06. 217 * Bridge device. 218 */ 219 220 /* PCI bridge programming interface */ 221 static const struct pci_class pci_interface_pcibridge[] = { 222 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 223 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 224 { NULL, 0, NULL, }, 225 }; 226 227 /* Semi-transparent PCI-to-PCI bridge programming interface */ 228 static const struct pci_class pci_interface_stpci[] = { 229 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 230 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 231 { NULL, 0, NULL, }, 232 }; 233 234 /* Advanced Switching programming interface */ 235 static const struct pci_class pci_interface_advsw[] = { 236 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 237 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 238 { NULL, 0, NULL, }, 239 }; 240 241 /* Subclasses */ 242 static const struct pci_class pci_subclass_bridge[] = { 243 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 244 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 245 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 246 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 247 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 248 pci_interface_pcibridge, }, 249 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 250 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 251 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 252 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 253 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 254 pci_interface_stpci, }, 255 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 256 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 257 pci_interface_advsw, }, 258 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 259 { NULL, 0, NULL, }, 260 }; 261 262 /* 263 * Class 0x07. 264 * Simple communications controller. 265 */ 266 267 /* Serial controller programming interface */ 268 static const struct pci_class pci_interface_serial[] = { 269 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 270 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 271 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 272 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 273 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 274 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 275 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 276 { NULL, 0, NULL, }, 277 }; 278 279 /* Parallel controller programming interface */ 280 static const struct pci_class pci_interface_parallel[] = { 281 { "", PCI_INTERFACE_PARALLEL, NULL,}, 282 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 283 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 284 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 285 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 286 { NULL, 0, NULL,}, 287 }; 288 289 /* Modem programming interface */ 290 static const struct pci_class pci_interface_modem[] = { 291 { "", PCI_INTERFACE_MODEM, NULL,}, 292 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 293 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 294 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 295 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 296 { NULL, 0, NULL,}, 297 }; 298 299 /* Subclasses */ 300 static const struct pci_class pci_subclass_communications[] = { 301 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 302 pci_interface_serial, }, 303 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 304 pci_interface_parallel, }, 305 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 306 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 307 pci_interface_modem, }, 308 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 309 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 310 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 311 { NULL, 0, NULL,}, 312 }; 313 314 /* 315 * Class 0x08. 316 * Base system peripheral. 317 */ 318 319 /* PIC programming interface */ 320 static const struct pci_class pci_interface_pic[] = { 321 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 322 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 323 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 324 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 325 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 326 { NULL, 0, NULL, }, 327 }; 328 329 /* DMA programming interface */ 330 static const struct pci_class pci_interface_dma[] = { 331 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 332 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 333 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 334 { NULL, 0, NULL, }, 335 }; 336 337 /* Timer programming interface */ 338 static const struct pci_class pci_interface_tmr[] = { 339 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 340 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 341 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 342 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 343 { NULL, 0, NULL, }, 344 }; 345 346 /* RTC programming interface */ 347 static const struct pci_class pci_interface_rtc[] = { 348 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 349 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 350 { NULL, 0, NULL, }, 351 }; 352 353 /* Subclasses */ 354 static const struct pci_class pci_subclass_system[] = { 355 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 356 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 357 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 358 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 359 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 360 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 361 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 362 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 363 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 364 { NULL, 0, NULL, }, 365 }; 366 367 /* 368 * Class 0x09. 369 * Input device. 370 */ 371 372 /* Gameport programming interface */ 373 static const struct pci_class pci_interface_game[] = { 374 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 375 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 376 { NULL, 0, NULL, }, 377 }; 378 379 /* Subclasses */ 380 static const struct pci_class pci_subclass_input[] = { 381 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 382 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 383 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 384 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 385 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 386 pci_interface_game, }, 387 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 388 { NULL, 0, NULL, }, 389 }; 390 391 /* 392 * Class 0x0a. 393 * Docking station. 394 */ 395 static const struct pci_class pci_subclass_dock[] = { 396 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 397 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 398 { NULL, 0, NULL, }, 399 }; 400 401 /* 402 * Class 0x0b. 403 * Processor. 404 */ 405 static const struct pci_class pci_subclass_processor[] = { 406 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 407 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 408 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 409 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 410 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 411 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 412 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 413 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 414 { NULL, 0, NULL, }, 415 }; 416 417 /* 418 * Class 0x0c. 419 * Serial bus controller. 420 */ 421 422 /* IEEE1394 programming interface */ 423 static const struct pci_class pci_interface_ieee1394[] = { 424 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 425 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 426 { NULL, 0, NULL,}, 427 }; 428 429 /* USB programming interface */ 430 static const struct pci_class pci_interface_usb[] = { 431 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 432 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 433 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 434 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 435 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 436 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 437 { NULL, 0, NULL, }, 438 }; 439 440 /* IPMI programming interface */ 441 static const struct pci_class pci_interface_ipmi[] = { 442 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL, }, 443 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL, }, 444 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL, }, 445 { NULL, 0, NULL, }, 446 }; 447 448 /* Subclasses */ 449 static const struct pci_class pci_subclass_serialbus[] = { 450 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 451 pci_interface_ieee1394, }, 452 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 453 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 454 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 455 pci_interface_usb, }, 456 /* XXX Fiber Channel/_FIBRECHANNEL */ 457 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 458 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 459 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 460 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 461 pci_interface_ipmi, }, 462 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 463 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 464 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 465 { NULL, 0, NULL, }, 466 }; 467 468 /* 469 * Class 0x0d. 470 * Wireless Controller. 471 */ 472 static const struct pci_class pci_subclass_wireless[] = { 473 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 474 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 475 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 476 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 477 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 478 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 479 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 480 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 481 { NULL, 0, NULL, }, 482 }; 483 484 /* 485 * Class 0x0e. 486 * Intelligent IO controller. 487 */ 488 489 /* Intelligent IO programming interface */ 490 static const struct pci_class pci_interface_i2o[] = { 491 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL, }, 492 { NULL, 0, NULL, }, 493 }; 494 495 /* Subclasses */ 496 static const struct pci_class pci_subclass_i2o[] = { 497 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 498 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 499 { NULL, 0, NULL, }, 500 }; 501 502 /* 503 * Class 0x0f. 504 * Satellite communication controller. 505 */ 506 static const struct pci_class pci_subclass_satcom[] = { 507 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 508 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 509 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 510 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 511 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 512 { NULL, 0, NULL, }, 513 }; 514 515 /* 516 * Class 0x10. 517 * Encryption/Decryption controller. 518 */ 519 static const struct pci_class pci_subclass_crypto[] = { 520 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 521 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 522 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 523 { NULL, 0, NULL, }, 524 }; 525 526 /* 527 * Class 0x11. 528 * Data aquuisition and signal processing controller. 529 */ 530 static const struct pci_class pci_subclass_dasp[] = { 531 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 532 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 533 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 534 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 535 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 536 { NULL, 0, NULL, }, 537 }; 538 539 /* List of classes */ 540 static const struct pci_class pci_classes[] = { 541 { "prehistoric", PCI_CLASS_PREHISTORIC, 542 pci_subclass_prehistoric, }, 543 { "mass storage", PCI_CLASS_MASS_STORAGE, 544 pci_subclass_mass_storage, }, 545 { "network", PCI_CLASS_NETWORK, 546 pci_subclass_network, }, 547 { "display", PCI_CLASS_DISPLAY, 548 pci_subclass_display, }, 549 { "multimedia", PCI_CLASS_MULTIMEDIA, 550 pci_subclass_multimedia, }, 551 { "memory", PCI_CLASS_MEMORY, 552 pci_subclass_memory, }, 553 { "bridge", PCI_CLASS_BRIDGE, 554 pci_subclass_bridge, }, 555 { "communications", PCI_CLASS_COMMUNICATIONS, 556 pci_subclass_communications, }, 557 { "system", PCI_CLASS_SYSTEM, 558 pci_subclass_system, }, 559 { "input", PCI_CLASS_INPUT, 560 pci_subclass_input, }, 561 { "dock", PCI_CLASS_DOCK, 562 pci_subclass_dock, }, 563 { "processor", PCI_CLASS_PROCESSOR, 564 pci_subclass_processor, }, 565 { "serial bus", PCI_CLASS_SERIALBUS, 566 pci_subclass_serialbus, }, 567 { "wireless", PCI_CLASS_WIRELESS, 568 pci_subclass_wireless, }, 569 { "I2O", PCI_CLASS_I2O, 570 pci_subclass_i2o, }, 571 { "satellite comm", PCI_CLASS_SATCOM, 572 pci_subclass_satcom, }, 573 { "crypto", PCI_CLASS_CRYPTO, 574 pci_subclass_crypto, }, 575 { "DASP", PCI_CLASS_DASP, 576 pci_subclass_dasp, }, 577 { "processing accelerators", PCI_CLASS_ACCEL, 578 NULL, }, 579 { "non-essential instrumentation", PCI_CLASS_INSTRUMENT, 580 NULL, }, 581 { "undefined", PCI_CLASS_UNDEFINED, 582 NULL, }, 583 { NULL, 0, 584 NULL, }, 585 }; 586 587 DEV_VERBOSE_DEFINE(pci); 588 589 /* 590 * Append a formatted string to dest without writing more than len 591 * characters (including the trailing NUL character). dest and len 592 * are updated for use in subsequent calls to snappendf(). 593 * 594 * Returns 0 on success, a negative value if vnsprintf() fails, or 595 * a positive value if the dest buffer would have overflowed. 596 */ 597 598 static int __printflike(3, 4) 599 snappendf(char **dest, size_t *len, const char * restrict fmt, ...) 600 { 601 va_list ap; 602 int count; 603 604 va_start(ap, fmt); 605 count = vsnprintf(*dest, *len, fmt, ap); 606 va_end(ap); 607 608 /* Let vsnprintf() errors bubble up to caller */ 609 if (count < 0 || *len == 0) 610 return count; 611 612 /* Handle overflow */ 613 if ((size_t)count >= *len) { 614 *dest += *len - 1; 615 *len = 1; 616 return 1; 617 } 618 619 /* Update dest & len to point at trailing NUL */ 620 *dest += count; 621 *len -= count; 622 623 return 0; 624 } 625 626 void 627 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 628 size_t l) 629 { 630 pci_class_t class; 631 pci_subclass_t subclass; 632 pci_interface_t interface; 633 pci_revision_t revision; 634 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 635 const struct pci_class *classp, *subclassp, *interfacep; 636 637 class = PCI_CLASS(class_reg); 638 subclass = PCI_SUBCLASS(class_reg); 639 interface = PCI_INTERFACE(class_reg); 640 revision = PCI_REVISION(class_reg); 641 642 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 643 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 644 PCI_PRODUCT(id_reg)); 645 646 classp = pci_classes; 647 while (classp->name != NULL) { 648 if (class == classp->val) 649 break; 650 classp++; 651 } 652 653 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 654 while (subclassp && subclassp->name != NULL) { 655 if (subclass == subclassp->val) 656 break; 657 subclassp++; 658 } 659 660 interfacep = (subclassp && subclassp->name != NULL) ? 661 subclassp->subclasses : NULL; 662 while (interfacep && interfacep->name != NULL) { 663 if (interface == interfacep->val) 664 break; 665 interfacep++; 666 } 667 668 (void)snappendf(&cp, &l, "%s %s", vendor, product); 669 if (showclass) { 670 (void)snappendf(&cp, &l, " ("); 671 if (classp->name == NULL) 672 (void)snappendf(&cp, &l, 673 "class 0x%02x, subclass 0x%02x", 674 class, subclass); 675 else { 676 if (subclassp == NULL || subclassp->name == NULL) 677 (void)snappendf(&cp, &l, 678 "%s, subclass 0x%02x", 679 classp->name, subclass); 680 else 681 (void)snappendf(&cp, &l, "%s %s", 682 subclassp->name, classp->name); 683 } 684 if ((interfacep == NULL) || (interfacep->name == NULL)) { 685 if (interface != 0) 686 (void)snappendf(&cp, &l, ", interface 0x%02x", 687 interface); 688 } else if (strncmp(interfacep->name, "", 1) != 0) 689 (void)snappendf(&cp, &l, ", %s", interfacep->name); 690 if (revision != 0) 691 (void)snappendf(&cp, &l, ", revision 0x%02x", revision); 692 (void)snappendf(&cp, &l, ")"); 693 } 694 } 695 696 #ifdef _KERNEL 697 void 698 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 699 const char *known, int addrev) 700 { 701 char devinfo[256]; 702 703 if (known) { 704 aprint_normal(": %s", known); 705 if (addrev) 706 aprint_normal(" (rev. 0x%02x)", 707 PCI_REVISION(pa->pa_class)); 708 aprint_normal("\n"); 709 } else { 710 pci_devinfo(pa->pa_id, pa->pa_class, 0, 711 devinfo, sizeof(devinfo)); 712 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 713 PCI_REVISION(pa->pa_class)); 714 } 715 if (naive) 716 aprint_naive(": %s\n", naive); 717 else 718 aprint_naive("\n"); 719 } 720 #endif 721 722 /* 723 * Print out most of the PCI configuration registers. Typically used 724 * in a device attach routine like this: 725 * 726 * #ifdef MYDEV_DEBUG 727 * printf("%s: ", device_xname(sc->sc_dev)); 728 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 729 * #endif 730 */ 731 732 #define i2o(i) ((i) * 4) 733 #define o2i(o) ((o) / 4) 734 #define onoff2(str, rval, bit, onstr, offstr) \ 735 /*CONSTCOND*/ \ 736 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 737 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 738 739 static void 740 pci_conf_print_common( 741 #ifdef _KERNEL 742 pci_chipset_tag_t pc, pcitag_t tag, 743 #endif 744 const pcireg_t *regs) 745 { 746 pci_class_t class; 747 pci_subclass_t subclass; 748 pci_interface_t interface; 749 pci_revision_t revision; 750 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 751 const struct pci_class *classp, *subclassp, *interfacep; 752 const char *name; 753 pcireg_t rval; 754 unsigned int num; 755 756 rval = regs[o2i(PCI_CLASS_REG)]; 757 class = PCI_CLASS(rval); 758 subclass = PCI_SUBCLASS(rval); 759 interface = PCI_INTERFACE(rval); 760 revision = PCI_REVISION(rval); 761 762 rval = regs[o2i(PCI_ID_REG)]; 763 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 764 if (name) 765 printf(" Vendor Name: %s (0x%04x)\n", name, 766 PCI_VENDOR(rval)); 767 else 768 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 769 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 770 PCI_PRODUCT(rval)); 771 if (name) 772 printf(" Device Name: %s (0x%04x)\n", name, 773 PCI_PRODUCT(rval)); 774 else 775 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 776 777 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 778 779 printf(" Command register: 0x%04x\n", rval & 0xffff); 780 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 781 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 782 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 783 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 784 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 785 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 786 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 787 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 788 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 789 onoff("Fast back-to-back transactions", rval, 790 PCI_COMMAND_BACKTOBACK_ENABLE); 791 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 792 793 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 794 onoff("Immediate Readiness", rval, PCI_STATUS_IMMD_READNESS); 795 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 796 "inactive"); 797 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 798 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 799 onoff("User Definable Features (UDF) support", rval, 800 PCI_STATUS_UDF_SUPPORT); 801 onoff("Fast back-to-back capable", rval, 802 PCI_STATUS_BACKTOBACK_SUPPORT); 803 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 804 805 printf(" DEVSEL timing: "); 806 switch (rval & PCI_STATUS_DEVSEL_MASK) { 807 case PCI_STATUS_DEVSEL_FAST: 808 printf("fast"); 809 break; 810 case PCI_STATUS_DEVSEL_MEDIUM: 811 printf("medium"); 812 break; 813 case PCI_STATUS_DEVSEL_SLOW: 814 printf("slow"); 815 break; 816 default: 817 printf("unknown/reserved"); /* XXX */ 818 break; 819 } 820 printf(" (0x%x)\n", PCIREG_SHIFTOUT(rval, PCI_STATUS_DEVSEL_MASK)); 821 822 onoff("Slave signaled Target Abort", rval, 823 PCI_STATUS_TARGET_TARGET_ABORT); 824 onoff("Master received Target Abort", rval, 825 PCI_STATUS_MASTER_TARGET_ABORT); 826 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 827 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 828 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 829 830 rval = regs[o2i(PCI_CLASS_REG)]; 831 for (classp = pci_classes; classp->name != NULL; classp++) { 832 if (class == classp->val) 833 break; 834 } 835 836 /* 837 * ECN: Change Root Complex Event Collector Class Code 838 * Old RCEC has subclass 0x06. It's the same as IOMMU. Read the type 839 * in PCIe extend capability to know whether it's RCEC or IOMMU. 840 */ 841 if ((class == PCI_CLASS_SYSTEM) 842 && (subclass == PCI_SUBCLASS_SYSTEM_IOMMU)) { 843 int pcie_capoff; 844 pcireg_t reg; 845 846 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 847 reg = regs[o2i(pcie_capoff + PCIE_XCAP)]; 848 if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_ROOT_EVNTC) 849 subclass = PCI_SUBCLASS_SYSTEM_RCEC; 850 } 851 } 852 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 853 while (subclassp && subclassp->name != NULL) { 854 if (subclass == subclassp->val) 855 break; 856 subclassp++; 857 } 858 859 interfacep = (subclassp && subclassp->name != NULL) ? 860 subclassp->subclasses : NULL; 861 while (interfacep && interfacep->name != NULL) { 862 if (interface == interfacep->val) 863 break; 864 interfacep++; 865 } 866 867 if (classp->name != NULL) 868 printf(" Class Name: %s (0x%02x)\n", classp->name, class); 869 else 870 printf(" Class ID: 0x%02x\n", class); 871 if (subclassp != NULL && subclassp->name != NULL) 872 printf(" Subclass Name: %s (0x%02x)\n", 873 subclassp->name, PCI_SUBCLASS(rval)); 874 else 875 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 876 if ((interfacep != NULL) && (interfacep->name != NULL) 877 && (strncmp(interfacep->name, "", 1) != 0)) 878 printf(" Interface Name: %s (0x%02x)\n", 879 interfacep->name, interface); 880 else 881 printf(" Interface: 0x%02x\n", interface); 882 printf(" Revision ID: 0x%02x\n", revision); 883 884 rval = regs[o2i(PCI_BHLC_REG)]; 885 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 886 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 887 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 888 PCI_HDRTYPE(rval)); 889 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 890 num = PCI_CACHELINE(rval); 891 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 892 } 893 894 static int 895 pci_conf_print_bar( 896 #ifdef _KERNEL 897 pci_chipset_tag_t pc, pcitag_t tag, 898 #endif 899 const pcireg_t *regs, int reg, const char *name) 900 { 901 int width; 902 pcireg_t rval, rval64h; 903 bool ioen, memen; 904 #ifdef _KERNEL 905 pcireg_t mask, mask64h = 0; 906 #endif 907 908 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 909 ioen = rval & PCI_COMMAND_IO_ENABLE; 910 memen = rval & PCI_COMMAND_MEM_ENABLE; 911 912 width = 4; 913 /* 914 * Section 6.2.5.1, `Address Maps', tells us that: 915 * 916 * 1) The builtin software should have already mapped the 917 * device in a reasonable way. 918 * 919 * 2) A device which wants 2^n bytes of memory will hardwire 920 * the bottom n bits of the address to 0. As recommended, 921 * we write all 1s and see what we get back. 922 */ 923 924 rval = regs[o2i(reg)]; 925 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 926 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 927 rval64h = regs[o2i(reg + 4)]; 928 width = 8; 929 } else 930 rval64h = 0; 931 932 #ifdef _KERNEL 933 if (rval != 0 && memen) { 934 int s; 935 936 /* 937 * The following sequence seems to make some devices 938 * (e.g. host bus bridges, which don't normally 939 * have their space mapped) very unhappy, to 940 * the point of crashing the system. 941 * 942 * Therefore, if the mapping register is zero to 943 * start out with, don't bother trying. 944 */ 945 s = splhigh(); 946 pci_conf_write(pc, tag, reg, 0xffffffff); 947 mask = pci_conf_read(pc, tag, reg); 948 pci_conf_write(pc, tag, reg, rval); 949 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 950 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 951 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 952 mask64h = pci_conf_read(pc, tag, reg + 4); 953 pci_conf_write(pc, tag, reg + 4, rval64h); 954 } 955 splx(s); 956 } else 957 mask = mask64h = 0; 958 #endif /* _KERNEL */ 959 960 printf(" Base address register at 0x%02x", reg); 961 if (name) 962 printf(" (%s)", name); 963 printf("\n "); 964 if (rval == 0) { 965 printf("not implemented\n"); 966 return width; 967 } 968 printf("type: "); 969 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 970 const char *type, *prefetch; 971 972 switch (PCI_MAPREG_MEM_TYPE(rval)) { 973 case PCI_MAPREG_MEM_TYPE_32BIT: 974 type = "32-bit"; 975 break; 976 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 977 type = "32-bit-1M"; 978 break; 979 case PCI_MAPREG_MEM_TYPE_64BIT: 980 type = "64-bit"; 981 break; 982 default: 983 type = "unknown (XXX)"; 984 break; 985 } 986 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 987 prefetch = ""; 988 else 989 prefetch = "non"; 990 printf("%s %sprefetchable memory\n", type, prefetch); 991 switch (PCI_MAPREG_MEM_TYPE(rval)) { 992 case PCI_MAPREG_MEM_TYPE_64BIT: 993 printf(" base: 0x%016llx", 994 PCI_MAPREG_MEM64_ADDR( 995 ((((long long) rval64h) << 32) | rval))); 996 if (!memen) 997 printf(", disabled"); 998 printf("\n"); 999 #ifdef _KERNEL 1000 printf(" size: 0x%016llx\n", 1001 PCI_MAPREG_MEM64_SIZE( 1002 ((((long long) mask64h) << 32) | mask))); 1003 #endif 1004 break; 1005 case PCI_MAPREG_MEM_TYPE_32BIT: 1006 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 1007 default: 1008 printf(" base: 0x%08x", 1009 PCI_MAPREG_MEM_ADDR(rval)); 1010 if (!memen) 1011 printf(", disabled"); 1012 printf("\n"); 1013 #ifdef _KERNEL 1014 printf(" size: 0x%08x\n", 1015 PCI_MAPREG_MEM_SIZE(mask)); 1016 #endif 1017 break; 1018 } 1019 } else { 1020 #ifdef _KERNEL 1021 if (ioen) 1022 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 1023 #endif 1024 printf("I/O\n"); 1025 printf(" base: 0x%08x", PCI_MAPREG_IO_ADDR(rval)); 1026 if (!ioen) 1027 printf(", disabled"); 1028 printf("\n"); 1029 #ifdef _KERNEL 1030 printf(" size: 0x%08x\n", PCI_MAPREG_IO_SIZE(mask)); 1031 #endif 1032 } 1033 1034 return width; 1035 } 1036 1037 static void 1038 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 1039 { 1040 int off, needaddr, neednl; 1041 1042 needaddr = 1; 1043 neednl = 0; 1044 for (off = first; off < pastlast; off += 4) { 1045 if ((off % 16) == 0 || needaddr) { 1046 printf(" 0x%02x:", off); 1047 needaddr = 0; 1048 } 1049 printf(" 0x%08x", regs[o2i(off)]); 1050 neednl = 1; 1051 if ((off % 16) == 12) { 1052 printf("\n"); 1053 neednl = 0; 1054 } 1055 } 1056 if (neednl) 1057 printf("\n"); 1058 } 1059 1060 static const char * 1061 pci_conf_print_agp_calcycle(uint8_t cal) 1062 { 1063 1064 switch (cal) { 1065 case 0x0: 1066 return "4ms"; 1067 case 0x1: 1068 return "16ms"; 1069 case 0x2: 1070 return "64ms"; 1071 case 0x3: 1072 return "256ms"; 1073 case 0x7: 1074 return "Calibration Cycle Not Needed"; 1075 default: 1076 return "(reserved)"; 1077 } 1078 } 1079 1080 static void 1081 pci_conf_print_agp_datarate(pcireg_t reg, bool isagp3) 1082 { 1083 if (isagp3) { 1084 /* AGP 3.0 */ 1085 if (reg & AGP_MODE_V3_RATE_4x) 1086 printf("x4"); 1087 if (reg & AGP_MODE_V3_RATE_8x) 1088 printf("x8"); 1089 } else { 1090 /* AGP 2.0 */ 1091 if (reg & AGP_MODE_V2_RATE_1x) 1092 printf("x1"); 1093 if (reg & AGP_MODE_V2_RATE_2x) 1094 printf("x2"); 1095 if (reg & AGP_MODE_V2_RATE_4x) 1096 printf("x4"); 1097 } 1098 printf("\n"); 1099 } 1100 1101 static void 1102 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 1103 { 1104 pcireg_t rval; 1105 bool isagp3; 1106 1107 printf("\n AGP Capabilities Register\n"); 1108 1109 rval = regs[o2i(capoff)]; 1110 printf(" Revision: %d.%d\n", 1111 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 1112 1113 rval = regs[o2i(capoff + PCI_AGP_STATUS)]; 1114 printf(" Status register: 0x%04x\n", rval); 1115 printf(" RQ: %u\n", 1116 PCIREG_SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1117 printf(" ARQSZ: %u\n", 1118 PCIREG_SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1119 printf(" CAL cycle: %s\n", 1120 pci_conf_print_agp_calcycle(PCIREG_SHIFTOUT(rval, AGP_MODE_CAL))); 1121 onoff("SBA", rval, AGP_MODE_SBA); 1122 onoff("htrans#", rval, AGP_MODE_HTRANS); 1123 onoff("Over 4G", rval, AGP_MODE_4G); 1124 onoff("Fast Write", rval, AGP_MODE_FW); 1125 onoff("AGP 3.0 Mode", rval, AGP_MODE_MODE_3); 1126 isagp3 = rval & AGP_MODE_MODE_3; 1127 printf(" Data Rate Support: "); 1128 pci_conf_print_agp_datarate(rval, isagp3); 1129 1130 rval = regs[o2i(capoff + PCI_AGP_COMMAND)]; 1131 printf(" Command register: 0x%08x\n", rval); 1132 printf(" PRQ: %u\n", 1133 PCIREG_SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1134 printf(" PARQSZ: %u\n", 1135 PCIREG_SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1136 printf(" PCAL cycle: %s\n", 1137 pci_conf_print_agp_calcycle(PCIREG_SHIFTOUT(rval, AGP_MODE_CAL))); 1138 onoff("SBA", rval, AGP_MODE_SBA); 1139 onoff("AGP", rval, AGP_MODE_AGP); 1140 onoff("Over 4G", rval, AGP_MODE_4G); 1141 onoff("Fast Write", rval, AGP_MODE_FW); 1142 if (isagp3) { 1143 printf(" Data Rate Enable: "); 1144 /* 1145 * The Data Rate Enable bits are used only on 3.0 and the 1146 * Command register has no AGP_MODE_MODE_3 bit, so pass the 1147 * flag to print correctly. 1148 */ 1149 pci_conf_print_agp_datarate(rval, isagp3); 1150 } 1151 } 1152 1153 static const char * 1154 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1155 { 1156 1157 switch ((caps >> 6) & 7) { 1158 case 0: return "self-powered"; 1159 case 1: return "55 mA"; 1160 case 2: return "100 mA"; 1161 case 3: return "160 mA"; 1162 case 4: return "220 mA"; 1163 case 5: return "270 mA"; 1164 case 6: return "320 mA"; 1165 case 7: 1166 default: return "375 mA"; 1167 } 1168 } 1169 1170 static const char * 1171 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1172 { 1173 static const char unk[] = "unknown"; 1174 static const char *pmrev[8] = { 1175 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1176 }; 1177 if (val > 7) 1178 return unk; 1179 return pmrev[val]; 1180 } 1181 1182 static void 1183 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1184 { 1185 uint16_t caps, pmcsr; 1186 1187 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1188 pmcsr = regs[o2i(capoff + PCI_PMCSR)]; 1189 1190 printf("\n PCI Power Management Capabilities Register\n"); 1191 1192 printf(" Capabilities register: 0x%04x\n", caps); 1193 printf(" Version: %s\n", 1194 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1195 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1196 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1197 printf(" 3.3V auxiliary current: %s\n", 1198 pci_conf_print_pcipm_cap_aux(caps)); 1199 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1200 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1201 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1202 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1203 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1204 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1205 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1206 1207 printf(" Control/status register: 0x%08x\n", pmcsr); 1208 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1209 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1210 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1211 printf(" PME# assertion: %sabled\n", 1212 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1213 printf(" Data Select: %d\n", 1214 PCIREG_SHIFTOUT(pmcsr, PCI_PMCSR_DATASEL_MASK)); 1215 printf(" Data Scale: %d\n", 1216 PCIREG_SHIFTOUT(pmcsr, PCI_PMCSR_DATASCL_MASK)); 1217 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1218 printf(" Bridge Support Extensions register: 0x%02x\n", 1219 (pmcsr >> 16) & 0xff); 1220 onoff("B2/B3 support", pmcsr, PCI_PMCSR_B2B3_SUPPORT); 1221 onoff("Bus Power/Clock Control Enable", pmcsr, PCI_PMCSR_BPCC_EN); 1222 printf(" Data register: 0x%02x\n", 1223 PCIREG_SHIFTOUT(pmcsr, PCI_PMCSR_DATA)); 1224 } 1225 1226 /* XXX pci_conf_print_vpd_cap */ 1227 /* XXX pci_conf_print_slotid_cap */ 1228 1229 static void 1230 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1231 { 1232 uint32_t ctl, mmc, mme; 1233 1234 regs += o2i(capoff); 1235 ctl = *regs++; 1236 mmc = PCIREG_SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1237 mme = PCIREG_SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1238 1239 printf("\n PCI Message Signaled Interrupt\n"); 1240 1241 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1242 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1243 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1244 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1245 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1246 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1247 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1248 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1249 onoff("Extended Message Data Capable", ctl, PCI_MSI_CTL_EXTMDATA_CAP); 1250 onoff("Extended Message Data Enable", ctl, PCI_MSI_CTL_EXTMDATA_EN); 1251 printf(" Message Address %sregister: 0x%08x\n", 1252 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1253 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1254 printf(" Message Address %sregister: 0x%08x\n", 1255 "(upper) ", *regs++); 1256 } 1257 printf(" Message Data register: "); 1258 if (ctl & PCI_MSI_CTL_EXTMDATA_CAP) 1259 printf("0x%08x\n", *regs); 1260 else 1261 printf("0x%04x\n", *regs & 0xffff); 1262 regs++; 1263 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1264 printf(" Vector Mask register: 0x%08x\n", *regs++); 1265 printf(" Vector Pending register: 0x%08x\n", *regs++); 1266 } 1267 } 1268 1269 /* XXX pci_conf_print_cpci_hostwap_cap */ 1270 1271 /* 1272 * For both command register and status register. 1273 * The argument "idx" is index number (0 to 7). 1274 */ 1275 static int 1276 pcix_split_trans(unsigned int idx) 1277 { 1278 static int table[8] = { 1279 1, 2, 3, 4, 8, 12, 16, 32 1280 }; 1281 1282 if (idx >= __arraycount(table)) 1283 return -1; 1284 return table[idx]; 1285 } 1286 1287 static void 1288 pci_conf_print_pcix_cap_2ndbusmode(int num) 1289 { 1290 const char *maxfreq, *maxperiod; 1291 1292 printf(" Mode: "); 1293 if (num <= 0x07) 1294 printf("PCI-X Mode 1\n"); 1295 else if (num <= 0x0b) 1296 printf("PCI-X 266 (Mode 2)\n"); 1297 else 1298 printf("PCI-X 533 (Mode 2)\n"); 1299 1300 printf(" Error protection: %s\n", (num <= 3) ? "parity" : "ECC"); 1301 switch (num & 0x03) { 1302 default: 1303 case 0: 1304 maxfreq = "N/A"; 1305 maxperiod = "N/A"; 1306 break; 1307 case 1: 1308 maxfreq = "66MHz"; 1309 maxperiod = "15ns"; 1310 break; 1311 case 2: 1312 maxfreq = "100MHz"; 1313 maxperiod = "10ns"; 1314 break; 1315 case 3: 1316 maxfreq = "133MHz"; 1317 maxperiod = "7.5ns"; 1318 break; 1319 } 1320 printf(" Max Clock Freq: %s\n", maxfreq); 1321 printf(" Min Clock Period: %s\n", maxperiod); 1322 } 1323 1324 static void 1325 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1326 { 1327 pcireg_t reg; 1328 int isbridge; 1329 int i; 1330 1331 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1332 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1333 printf("\n PCI-X %s Capabilities Register\n", 1334 isbridge ? "Bridge" : "Non-bridge"); 1335 1336 reg = regs[o2i(capoff)]; 1337 if (isbridge != 0) { 1338 printf(" Secondary status register: 0x%04x\n", 1339 (reg & 0xffff0000) >> 16); 1340 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1341 onoff("133MHz capable", reg, PCIX_STATUS_133); 1342 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1343 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1344 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1345 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1346 pci_conf_print_pcix_cap_2ndbusmode( 1347 PCIREG_SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF)); 1348 printf(" Version: 0x%x\n", 1349 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1350 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1351 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1352 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1353 } else { 1354 printf(" Command register: 0x%04x\n", 1355 (reg & 0xffff0000) >> 16); 1356 onoff("Data Parity Error Recovery", reg, 1357 PCIX_CMD_PERR_RECOVER); 1358 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1359 printf(" Maximum Burst Read Count: %u\n", 1360 PCIX_CMD_BYTECNT(reg)); 1361 printf(" Maximum Split Transactions: %d\n", 1362 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1363 >> PCIX_CMD_SPLTRANS_SHIFT)); 1364 } 1365 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1366 printf(" %sStatus register: 0x%08x\n", 1367 isbridge ? "Bridge " : "", reg); 1368 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1369 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1370 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1371 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1372 onoff("133MHz capable", reg, PCIX_STATUS_133); 1373 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1374 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1375 if (isbridge != 0) { 1376 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1377 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1378 } else { 1379 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1380 "bridge device", "simple device"); 1381 printf(" Designed max memory read byte count: %d\n", 1382 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1383 >> PCIX_STATUS_MAXB_SHIFT)); 1384 printf(" Designed max outstanding split transaction: %d\n", 1385 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1386 >> PCIX_STATUS_MAXST_SHIFT)); 1387 printf(" MAX cumulative Read Size: %u\n", 1388 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1389 onoff("Received split completion error", reg, 1390 PCIX_STATUS_SCERR); 1391 } 1392 onoff("266MHz capable", reg, PCIX_STATUS_266); 1393 onoff("533MHz capable", reg, PCIX_STATUS_533); 1394 1395 if (isbridge == 0) 1396 return; 1397 1398 /* Only for bridge */ 1399 for (i = 0; i < 2; i++) { 1400 reg = regs[o2i(capoff + PCIX_BRIDGE_UP_STCR + (4 * i))]; 1401 printf(" %s split transaction control register: 0x%08x\n", 1402 (i == 0) ? "Upstream" : "Downstream", reg); 1403 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1404 printf(" Commitment Limit: %d\n", 1405 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1406 } 1407 } 1408 1409 /* pci_conf_print_ht_slave_cap */ 1410 /* pci_conf_print_ht_host_cap */ 1411 /* pci_conf_print_ht_switch_cap */ 1412 /* pci_conf_print_ht_intr_cap */ 1413 /* pci_conf_print_ht_revid_cap */ 1414 /* pci_conf_print_ht_unitid_cap */ 1415 /* pci_conf_print_ht_extcnf_cap */ 1416 /* pci_conf_print_ht_addrmap_cap */ 1417 /* pci_conf_print_ht_msimap_cap */ 1418 1419 static void 1420 pci_conf_print_ht_msimap_cap(const pcireg_t *regs, int capoff) 1421 { 1422 pcireg_t val; 1423 uint32_t lo, hi; 1424 1425 /* 1426 * Print the rest of the command register bits. Others are 1427 * printed in pci_conf_print_ht_cap(). 1428 */ 1429 val = regs[o2i(capoff + PCI_HT_CMD)]; 1430 onoff("Enable", val, PCI_HT_MSI_ENABLED); 1431 onoff("Fixed", val, PCI_HT_MSI_FIXED); 1432 1433 lo = regs[o2i(capoff + PCI_HT_MSI_ADDR_LO)]; 1434 hi = regs[o2i(capoff + PCI_HT_MSI_ADDR_HI)]; 1435 printf(" Address Low register: 0x%08x\n", lo); 1436 printf(" Address high register: 0x%08x\n", hi); 1437 printf(" Address: 0x%016" PRIx64 "\n", 1438 (uint64_t)hi << 32 | (lo & PCI_HT_MSI_ADDR_LO_MASK)); 1439 } 1440 1441 /* pci_conf_print_ht_droute_cap */ 1442 /* pci_conf_print_ht_vcset_cap */ 1443 /* pci_conf_print_ht_retry_cap */ 1444 /* pci_conf_print_ht_x86enc_cap */ 1445 /* pci_conf_print_ht_gen3_cap */ 1446 /* pci_conf_print_ht_fle_cap */ 1447 /* pci_conf_print_ht_pm_cap */ 1448 /* pci_conf_print_ht_hnc_cap */ 1449 1450 static const struct ht_types { 1451 pcireg_t cap; 1452 const char *name; 1453 void (*printfunc)(const pcireg_t *, int); 1454 } ht_captab[] = { 1455 {PCI_HT_CAP_SLAVE, "Slave or Primary Interface", NULL }, 1456 {PCI_HT_CAP_HOST, "Host or Secondary Interface", NULL }, 1457 {PCI_HT_CAP_SWITCH, "Switch", NULL }, 1458 {PCI_HT_CAP_INTERRUPT, "Interrupt Discovery and Configuration", NULL}, 1459 {PCI_HT_CAP_REVID, "Revision ID", NULL }, 1460 {PCI_HT_CAP_UNITID_CLUMP, "UnitID Clumping", NULL }, 1461 {PCI_HT_CAP_EXTCNFSPACE, "Extended Configuration Space Access", NULL }, 1462 {PCI_HT_CAP_ADDRMAP, "Address Mapping", NULL }, 1463 {PCI_HT_CAP_MSIMAP, "MSI Mapping", pci_conf_print_ht_msimap_cap }, 1464 {PCI_HT_CAP_DIRECTROUTE, "Direct Route", NULL }, 1465 {PCI_HT_CAP_VCSET, "VCSet", NULL }, 1466 {PCI_HT_CAP_RETRYMODE, "Retry Mode", NULL }, 1467 {PCI_HT_CAP_X86ENCODE, "X86 Encoding", NULL }, 1468 {PCI_HT_CAP_GEN3, "Gen3", NULL }, 1469 {PCI_HT_CAP_FLE, "Function-Level Extension", NULL }, 1470 {PCI_HT_CAP_PM, "Power Management", NULL }, 1471 {PCI_HT_CAP_HIGHNODECNT, "High Node Count", NULL }, 1472 }; 1473 1474 static void 1475 pci_conf_print_ht_cap(const pcireg_t *regs, int capoff) 1476 { 1477 pcireg_t val, foundcap; 1478 unsigned int off; 1479 1480 val = regs[o2i(capoff + PCI_HT_CMD)]; 1481 1482 printf("\n HyperTransport Capability Register at 0x%02x\n", capoff); 1483 1484 printf(" Command register: 0x%04x\n", val >> 16); 1485 foundcap = PCI_HT_CAP(val); 1486 for (off = 0; off < __arraycount(ht_captab); off++) { 1487 if (ht_captab[off].cap == foundcap) 1488 break; 1489 } 1490 printf(" Capability Type: 0x%02x ", foundcap); 1491 if (off >= __arraycount(ht_captab)) { 1492 printf("(unknown)\n"); 1493 return; 1494 } 1495 printf("(%s)\n", ht_captab[off].name); 1496 if (ht_captab[off].printfunc != NULL) 1497 ht_captab[off].printfunc(regs, capoff); 1498 } 1499 1500 static void 1501 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1502 { 1503 uint16_t caps; 1504 1505 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1506 1507 printf("\n PCI Vendor Specific Capabilities Register\n"); 1508 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1509 } 1510 1511 static void 1512 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1513 { 1514 pcireg_t val; 1515 1516 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1517 1518 printf("\n Debugport Capability Register\n"); 1519 printf(" Debug base Register: 0x%04x\n", 1520 val >> PCI_DEBUG_BASER_SHIFT); 1521 printf(" port offset: 0x%04x\n", 1522 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1523 printf(" BAR number: %u\n", 1524 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1525 } 1526 1527 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1528 /* XXX pci_conf_print_hotplug_cap */ 1529 1530 static void 1531 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1532 { 1533 pcireg_t reg; 1534 1535 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1536 1537 printf("\n Subsystem ID Capability Register\n"); 1538 printf(" Subsystem ID: 0x%08x\n", reg); 1539 } 1540 1541 /* XXX pci_conf_print_agp8_cap */ 1542 static void 1543 pci_conf_print_secure_cap(const pcireg_t *regs, int capoff) 1544 { 1545 pcireg_t reg, reg2, val; 1546 bool havemisc1; 1547 1548 printf("\n Secure Capability Register\n"); 1549 reg = regs[o2i(capoff + PCI_SECURE_CAP)]; 1550 printf(" Capability Register: 0x%04x\n", reg >> 16); 1551 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_CAP_TYPE); 1552 printf(" Capability block type: "); 1553 /* I know IOMMU Only */ 1554 if (val == PCI_SECURE_CAP_TYPE_IOMMU) 1555 printf("IOMMU\n"); 1556 else { 1557 printf("0x%x(unknown)\n", val); 1558 return; 1559 } 1560 1561 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_CAP_REV); 1562 printf(" Capability revision: 0x%02x ", val); 1563 if (val == PCI_SECURE_CAP_REV_IOMMU) 1564 printf("(IOMMU)\n"); 1565 else { 1566 printf("(unknown)\n"); 1567 return; 1568 } 1569 onoff("IOTLB support", reg, PCI_SECURE_CAP_IOTLBSUP); 1570 onoff("HyperTransport tunnel translation support", reg, 1571 PCI_SECURE_CAP_HTTUNNEL); 1572 onoff("Not present table entries cached", reg, PCI_SECURE_CAP_NPCACHE); 1573 onoff("IOMMU Extended Feature Register support", reg, 1574 PCI_SECURE_CAP_EFRSUP); 1575 onoff("IOMMU Miscellaneous Information Register 1", reg, 1576 PCI_SECURE_CAP_EXT); 1577 havemisc1 = reg & PCI_SECURE_CAP_EXT; 1578 1579 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_BAL)]; 1580 printf(" Base Address Low Register: 0x%08x\n", reg); 1581 onoff("Enable", reg, PCI_SECURE_IOMMU_BAL_EN); 1582 reg2 = regs[o2i(capoff + PCI_SECURE_IOMMU_BAH)]; 1583 printf(" Base Address High Register: 0x%08x\n", reg2); 1584 printf(" Base Address: 0x%016" PRIx64 "\n", 1585 ((uint64_t)reg2 << 32) 1586 | (reg & (PCI_SECURE_IOMMU_BAL_H | PCI_SECURE_IOMMU_BAL_L))); 1587 1588 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_RANGE)]; 1589 printf(" IOMMU Range Register: 0x%08x\n", reg); 1590 printf(" HyperTransport UnitID: 0x%02x\n", 1591 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_UNITID)); 1592 onoff("Range valid", reg, PCI_SECURE_IOMMU_RANGE_RNGVALID); 1593 printf(" Device range bus number: 0x%02x\n", 1594 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_BUSNUM)); 1595 printf(" First device: 0x%04x\n", 1596 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_FIRSTDEV)); 1597 printf(" Last device: 0x%04x\n", 1598 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_LASTDEV)); 1599 1600 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC0)]; 1601 printf(" Miscellaneous Information Register 0: 0x%08x\n", reg); 1602 printf(" MSI Message number: 0x%02x\n", 1603 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MSINUM)); 1604 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_GVASIZE); 1605 printf(" Guest Virtual Address size: "); 1606 if (val == PCI_SECURE_IOMMU_MISC0_GVASIZE_48B) 1607 printf("48bits\n"); 1608 else 1609 printf("0x%x(unknown)\n", val); 1610 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_PASIZE); 1611 printf(" Physical Address size: %dbits\n", val); 1612 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_VASIZE); 1613 printf(" Virtual Address size: %dbits\n", val); 1614 onoff("ATS response address range reserved", reg, 1615 PCI_SECURE_IOMMU_MISC0_ATSRESV); 1616 printf(" Peripheral Page Request MSI Message number: 0x%02x\n", 1617 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MISNPPR)); 1618 1619 if (!havemisc1) 1620 return; 1621 1622 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC1)]; 1623 printf(" Miscellaneous Information Register 1: 0x%08x\n", reg); 1624 printf(" MSI Message number (GA): 0x%02x\n", 1625 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC1_MSINUM)); 1626 } 1627 1628 static void 1629 pci_print_pcie_L0s_latency(uint32_t val) 1630 { 1631 1632 switch (val) { 1633 case 0x0: 1634 printf("Less than 64ns\n"); 1635 break; 1636 case 0x1: 1637 case 0x2: 1638 case 0x3: 1639 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1640 break; 1641 case 0x4: 1642 printf("512ns to less than 1us\n"); 1643 break; 1644 case 0x5: 1645 printf("1us to less than 2us\n"); 1646 break; 1647 case 0x6: 1648 printf("2us - 4us\n"); 1649 break; 1650 case 0x7: 1651 printf("More than 4us\n"); 1652 break; 1653 } 1654 } 1655 1656 static void 1657 pci_print_pcie_L1_latency(uint32_t val) 1658 { 1659 1660 switch (val) { 1661 case 0x0: 1662 printf("Less than 1us\n"); 1663 break; 1664 case 0x6: 1665 printf("32us - 64us\n"); 1666 break; 1667 case 0x7: 1668 printf("More than 64us\n"); 1669 break; 1670 default: 1671 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1672 break; 1673 } 1674 } 1675 1676 static void 1677 pci_print_pcie_compl_timeout(uint32_t val) 1678 { 1679 1680 switch (val) { 1681 case 0x0: 1682 printf("50us to 50ms\n"); 1683 break; 1684 case 0x5: 1685 printf("16ms to 55ms\n"); 1686 break; 1687 case 0x6: 1688 printf("65ms to 210ms\n"); 1689 break; 1690 case 0x9: 1691 printf("260ms to 900ms\n"); 1692 break; 1693 case 0xa: 1694 printf("1s to 3.5s\n"); 1695 break; 1696 default: 1697 printf("unknown %u value\n", val); 1698 break; 1699 } 1700 } 1701 1702 static const char * const pcie_linkspeeds[] = {"2.5", "5.0", "8.0", "16.0"}; 1703 1704 /* 1705 * Print link speed. This function is used for the following register bits: 1706 * Maximum Link Speed in LCAP 1707 * Current Link Speed in LCSR 1708 * Target Link Speed in LCSR2 1709 * All of above bitfield's values start from 1. 1710 * For LCSR2, 0 is allowed for a device which supports 2.5GT/s only (and 1711 * this check also works for devices which compliant to versions of the base 1712 * specification prior to 3.0. 1713 */ 1714 static void 1715 pci_print_pcie_linkspeed(int regnum, pcireg_t val) 1716 { 1717 1718 if ((regnum == PCIE_LCSR2) && (val == 0)) 1719 printf("2.5GT/s\n"); 1720 else if ((val < 1) || (val > __arraycount(pcie_linkspeeds))) 1721 printf("unknown value (%u)\n", val); 1722 else 1723 printf("%sGT/s\n", pcie_linkspeeds[val - 1]); 1724 } 1725 1726 /* 1727 * Print link speed "vector". 1728 * This function is used for the following register bits: 1729 * Supported Link Speeds Vector in LCAP2 1730 * Lower SKP OS Generation Supported Speed Vector in LCAP2 1731 * Lower SKP OS Reception Supported Speed Vector in LCAP2 1732 * Enable Lower SKP OS Generation Vector in LCTL3 1733 * All of above bitfield's values start from 0. 1734 */ 1735 static void 1736 pci_print_pcie_linkspeedvector(pcireg_t val) 1737 { 1738 unsigned int i; 1739 1740 /* Start from 0 */ 1741 for (i = 0; i < 16; i++) 1742 if (((val >> i) & 0x01) != 0) { 1743 if (i >= __arraycount(pcie_linkspeeds)) 1744 printf(" unknown vector (0x%x)", 1 << i); 1745 else 1746 printf(" %sGT/s", pcie_linkspeeds[i]); 1747 } 1748 } 1749 1750 static void 1751 pci_print_pcie_link_deemphasis(pcireg_t val) 1752 { 1753 switch (val) { 1754 case 0: 1755 printf("-6dB"); 1756 break; 1757 case 1: 1758 printf("-3.5dB"); 1759 break; 1760 default: 1761 printf("(reserved value)"); 1762 } 1763 } 1764 1765 static void 1766 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1767 { 1768 pcireg_t reg; /* for each register */ 1769 pcireg_t val; /* for each bitfield */ 1770 bool check_slot = false; 1771 unsigned int pcie_devtype; 1772 bool check_upstreamport = false; 1773 unsigned int pciever; 1774 unsigned int i; 1775 1776 printf("\n PCI Express Capabilities Register\n"); 1777 /* Capability Register */ 1778 reg = regs[o2i(capoff)]; 1779 printf(" Capability register: 0x%04x\n", reg >> 16); 1780 pciever = (unsigned int)(PCIE_XCAP_VER(reg)); 1781 printf(" Capability version: %u\n", pciever); 1782 printf(" Device type: "); 1783 pcie_devtype = PCIE_XCAP_TYPE(reg); 1784 switch (pcie_devtype) { 1785 case PCIE_XCAP_TYPE_PCIE_DEV: /* 0x0 */ 1786 printf("PCI Express Endpoint device\n"); 1787 check_upstreamport = true; 1788 break; 1789 case PCIE_XCAP_TYPE_PCI_DEV: /* 0x1 */ 1790 printf("Legacy PCI Express Endpoint device\n"); 1791 check_upstreamport = true; 1792 break; 1793 case PCIE_XCAP_TYPE_ROOT: /* 0x4 */ 1794 printf("Root Port of PCI Express Root Complex\n"); 1795 check_slot = true; 1796 break; 1797 case PCIE_XCAP_TYPE_UP: /* 0x5 */ 1798 printf("Upstream Port of PCI Express Switch\n"); 1799 check_upstreamport = true; 1800 break; 1801 case PCIE_XCAP_TYPE_DOWN: /* 0x6 */ 1802 printf("Downstream Port of PCI Express Switch\n"); 1803 check_slot = true; 1804 break; 1805 case PCIE_XCAP_TYPE_PCIE2PCI: /* 0x7 */ 1806 printf("PCI Express to PCI/PCI-X Bridge\n"); 1807 check_upstreamport = true; 1808 break; 1809 case PCIE_XCAP_TYPE_PCI2PCIE: /* 0x8 */ 1810 printf("PCI/PCI-X to PCI Express Bridge\n"); 1811 /* Upstream port is not PCIe */ 1812 check_slot = true; 1813 break; 1814 case PCIE_XCAP_TYPE_ROOT_INTEP: /* 0x9 */ 1815 printf("Root Complex Integrated Endpoint\n"); 1816 break; 1817 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* 0xa */ 1818 printf("Root Complex Event Collector\n"); 1819 break; 1820 default: 1821 printf("unknown\n"); 1822 break; 1823 } 1824 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1825 printf(" Interrupt Message Number: 0x%02x\n", 1826 PCIREG_SHIFTOUT(reg, PCIE_XCAP_IRQ)); 1827 1828 /* Device Capability Register */ 1829 reg = regs[o2i(capoff + PCIE_DCAP)]; 1830 printf(" Device Capabilities Register: 0x%08x\n", reg); 1831 printf(" Max Payload Size Supported: %u bytes max\n", 1832 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1833 printf(" Phantom Functions Supported: "); 1834 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP_PHANTOM_FUNCS)) { 1835 case 0x0: 1836 printf("not available\n"); 1837 break; 1838 case 0x1: 1839 printf("MSB\n"); 1840 break; 1841 case 0x2: 1842 printf("two MSB\n"); 1843 break; 1844 case 0x3: 1845 printf("All three bits\n"); 1846 break; 1847 } 1848 printf(" Extended Tag Field Supported: %dbit\n", 1849 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1850 printf(" Endpoint L0 Acceptable Latency: "); 1851 pci_print_pcie_L0s_latency(PCIREG_SHIFTOUT(reg, PCIE_DCAP_L0S_LATENCY)); 1852 printf(" Endpoint L1 Acceptable Latency: "); 1853 pci_print_pcie_L1_latency(PCIREG_SHIFTOUT(reg, PCIE_DCAP_L1_LATENCY)); 1854 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1855 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1856 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1857 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1858 if (check_upstreamport) { 1859 printf(" Captured Slot Power Limit: "); 1860 pci_conf_print_pcie_power( 1861 PCIREG_SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_VAL), 1862 PCIREG_SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_SCALE)); 1863 } 1864 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1865 1866 /* Device Control Register */ 1867 reg = regs[o2i(capoff + PCIE_DCSR)]; 1868 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1869 onoff("Correctable Error Reporting Enable", reg, 1870 PCIE_DCSR_ENA_COR_ERR); 1871 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1872 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1873 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1874 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1875 printf(" Max Payload Size: %d byte\n", 1876 128 << PCIREG_SHIFTOUT(reg, PCIE_DCSR_MAX_PAYLOAD)); 1877 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1878 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1879 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1880 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1881 printf(" Max Read Request Size: %d byte\n", 1882 128 << PCIREG_SHIFTOUT(reg, PCIE_DCSR_MAX_READ_REQ)); 1883 if (pcie_devtype == PCIE_XCAP_TYPE_PCIE2PCI) 1884 onoff("Bridge Config Retry Enable", reg, 1885 PCIE_DCSR_BRDG_CFG_RETRY); 1886 1887 /* Device Status Register */ 1888 reg = regs[o2i(capoff + PCIE_DCSR)]; 1889 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1890 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1891 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1892 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1893 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1894 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1895 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1896 onoff("Emergency Power Reduction Detected", reg, PCIE_DCSR_EMGPWRREDD); 1897 1898 if (PCIE_HAS_LINKREGS(pcie_devtype)) { 1899 /* Link Capability Register */ 1900 reg = regs[o2i(capoff + PCIE_LCAP)]; 1901 printf(" Link Capabilities Register: 0x%08x\n", reg); 1902 printf(" Maximum Link Speed: "); 1903 pci_print_pcie_linkspeed(PCIE_LCAP, reg & PCIE_LCAP_MAX_SPEED); 1904 printf(" Maximum Link Width: x%u lanes\n", 1905 PCIREG_SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH)); 1906 printf(" Active State PM Support: "); 1907 switch (PCIREG_SHIFTOUT(reg, PCIE_LCAP_ASPM)) { 1908 case 0x0: 1909 printf("No ASPM support\n"); 1910 break; 1911 case 0x1: 1912 printf("L0s supported\n"); 1913 break; 1914 case 0x2: 1915 printf("L1 supported\n"); 1916 break; 1917 case 0x3: 1918 printf("L0s and L1 supported\n"); 1919 break; 1920 } 1921 printf(" L0 Exit Latency: "); 1922 pci_print_pcie_L0s_latency(PCIREG_SHIFTOUT(reg,PCIE_LCAP_L0S_EXIT)); 1923 printf(" L1 Exit Latency: "); 1924 pci_print_pcie_L1_latency(PCIREG_SHIFTOUT(reg, PCIE_LCAP_L1_EXIT)); 1925 printf(" Port Number: %u\n", 1926 PCIREG_SHIFTOUT(reg, PCIE_LCAP_PORT)); 1927 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1928 onoff("Surprise Down Error Report", reg, 1929 PCIE_LCAP_SURPRISE_DOWN); 1930 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1931 onoff("Link BW Notification Capable", reg, 1932 PCIE_LCAP_LINK_BW_NOTIFY); 1933 onoff("ASPM Optionally Compliance", reg, 1934 PCIE_LCAP_ASPM_COMPLIANCE); 1935 1936 /* Link Control Register */ 1937 reg = regs[o2i(capoff + PCIE_LCSR)]; 1938 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1939 printf(" Active State PM Control: "); 1940 switch (reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S)) { 1941 case 0: 1942 printf("disabled\n"); 1943 break; 1944 case 1: 1945 printf("L0s Entry Enabled\n"); 1946 break; 1947 case 2: 1948 printf("L1 Entry Enabled\n"); 1949 break; 1950 case 3: 1951 printf("L0s and L1 Entry Enabled\n"); 1952 break; 1953 } 1954 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1955 "128bytes", "64bytes"); 1956 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1957 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1958 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1959 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1960 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1961 onoff("Hardware Autonomous Width Disable", reg,PCIE_LCSR_HAWD); 1962 onoff("Link Bandwidth Management Interrupt Enable", reg, 1963 PCIE_LCSR_LBMIE); 1964 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1965 PCIE_LCSR_LABIE); 1966 printf(" DRS Signaling Control: "); 1967 switch (PCIREG_SHIFTOUT(reg, PCIE_LCSR_DRSSGNL)) { 1968 case 0: 1969 printf("not reported\n"); 1970 break; 1971 case 1: 1972 printf("Interrupt Enabled\n"); 1973 break; 1974 case 2: 1975 printf("DRS to FRS Signaling Enabled\n"); 1976 break; 1977 default: 1978 printf("reserved\n"); 1979 break; 1980 } 1981 1982 /* Link Status Register */ 1983 reg = regs[o2i(capoff + PCIE_LCSR)]; 1984 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1985 printf(" Negotiated Link Speed: "); 1986 pci_print_pcie_linkspeed(PCIE_LCSR, 1987 PCIREG_SHIFTOUT(reg, PCIE_LCSR_LINKSPEED)); 1988 printf(" Negotiated Link Width: x%u lanes\n", 1989 PCIREG_SHIFTOUT(reg, PCIE_LCSR_NLW)); 1990 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1991 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1992 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1993 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1994 onoff("Link Bandwidth Management Status", reg, 1995 PCIE_LCSR_LINK_BW_MGMT); 1996 onoff("Link Autonomous Bandwidth Status", reg, 1997 PCIE_LCSR_LINK_AUTO_BW); 1998 } 1999 2000 if (check_slot == true) { 2001 pcireg_t slcap; 2002 2003 /* Slot Capability Register */ 2004 slcap = reg = regs[o2i(capoff + PCIE_SLCAP)]; 2005 printf(" Slot Capability Register: 0x%08x\n", reg); 2006 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 2007 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 2008 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 2009 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 2010 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 2011 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 2012 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 2013 printf(" Slot Power Limit Value: "); 2014 pci_conf_print_pcie_power(PCIREG_SHIFTOUT(reg, PCIE_SLCAP_SPLV), 2015 PCIREG_SHIFTOUT(reg, PCIE_SLCAP_SPLS)); 2016 onoff("Electromechanical Interlock Present", reg, 2017 PCIE_SLCAP_EIP); 2018 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 2019 printf(" Physical Slot Number: %d\n", 2020 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 2021 2022 /* Slot Control Register */ 2023 reg = regs[o2i(capoff + PCIE_SLCSR)]; 2024 printf(" Slot Control Register: 0x%04x\n", reg & 0xffff); 2025 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 2026 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 2027 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 2028 onoff("Presence Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 2029 onoff("Command Completed Interrupt Enabled", reg, 2030 PCIE_SLCSR_CCE); 2031 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 2032 /* 2033 * For Attention Indicator Control and Power Indicator Control, 2034 * it's allowed to be a read only value 0 if corresponding 2035 * capability register bit is 0. 2036 */ 2037 if (slcap & PCIE_SLCAP_AIP) { 2038 printf(" Attention Indicator Control: "); 2039 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 2040 case 0x0: 2041 printf("reserved\n"); 2042 break; 2043 case PCIE_SLCSR_IND_ON: 2044 printf("on\n"); 2045 break; 2046 case PCIE_SLCSR_IND_BLINK: 2047 printf("blink\n"); 2048 break; 2049 case PCIE_SLCSR_IND_OFF: 2050 printf("off\n"); 2051 break; 2052 } 2053 } 2054 if (slcap & PCIE_SLCAP_PIP) { 2055 printf(" Power Indicator Control: "); 2056 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 2057 case 0x0: 2058 printf("reserved\n"); 2059 break; 2060 case PCIE_SLCSR_IND_ON: 2061 printf("on\n"); 2062 break; 2063 case PCIE_SLCSR_IND_BLINK: 2064 printf("blink\n"); 2065 break; 2066 case PCIE_SLCSR_IND_OFF: 2067 printf("off\n"); 2068 break; 2069 } 2070 } 2071 printf(" Power Controller Control: Power %s\n", 2072 reg & PCIE_SLCSR_PCC ? "off" : "on"); 2073 onoff("Electromechanical Interlock Control", 2074 reg, PCIE_SLCSR_EIC); 2075 onoff("Data Link Layer State Changed Enable", reg, 2076 PCIE_SLCSR_DLLSCE); 2077 onoff("Auto Slot Power Limit Disable", reg, 2078 PCIE_SLCSR_AUTOSPLDIS); 2079 2080 /* Slot Status Register */ 2081 printf(" Slot Status Register: 0x%04x\n", reg >> 16); 2082 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 2083 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 2084 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 2085 onoff("Presence Detect Changed", reg, PCIE_SLCSR_PDC); 2086 onoff("Command Completed", reg, PCIE_SLCSR_CC); 2087 onoff("MRL Open", reg, PCIE_SLCSR_MS); 2088 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 2089 onoff("Electromechanical Interlock engaged", reg, 2090 PCIE_SLCSR_EIS); 2091 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 2092 } 2093 2094 if (PCIE_HAS_ROOTREGS(pcie_devtype)) { 2095 /* Root Control Register */ 2096 reg = regs[o2i(capoff + PCIE_RCR)]; 2097 printf(" Root Control Register: 0x%04x\n", reg & 0xffff); 2098 onoff("SERR on Correctable Error Enable", reg, 2099 PCIE_RCR_SERR_CER); 2100 onoff("SERR on Non-Fatal Error Enable", reg, 2101 PCIE_RCR_SERR_NFER); 2102 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 2103 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 2104 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 2105 2106 /* Root Capability Register */ 2107 printf(" Root Capability Register: 0x%04x\n", 2108 reg >> 16); 2109 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV); 2110 2111 /* Root Status Register */ 2112 reg = regs[o2i(capoff + PCIE_RSR)]; 2113 printf(" Root Status Register: 0x%08x\n", reg); 2114 printf(" PME Requester ID: 0x%04x\n", 2115 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 2116 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 2117 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 2118 } 2119 2120 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2121 if (pciever < 2) 2122 return; 2123 2124 /* Device Capabilities 2 */ 2125 reg = regs[o2i(capoff + PCIE_DCAP2)]; 2126 printf(" Device Capabilities 2: 0x%08x\n", reg); 2127 printf(" Completion Timeout Ranges Supported: "); 2128 val = reg & PCIE_DCAP2_COMPT_RANGE; 2129 switch (val) { 2130 case 0: 2131 printf("not supported\n"); 2132 break; 2133 default: 2134 for (i = 0; i <= 3; i++) { 2135 if (((val >> i) & 0x01) != 0) 2136 printf("%c", 'A' + i); 2137 } 2138 printf("\n"); 2139 } 2140 onoff("Completion Timeout Disable Supported", reg, 2141 PCIE_DCAP2_COMPT_DIS); 2142 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 2143 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 2144 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 2145 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 2146 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 2147 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 2148 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 2149 printf(" TPH Completer Supported: "); 2150 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP2_TPH_COMP)) { 2151 case 0: 2152 printf("Not supported\n"); 2153 break; 2154 case 1: 2155 printf("TPH\n"); 2156 break; 2157 case 3: 2158 printf("TPH and Extended TPH\n"); 2159 break; 2160 default: 2161 printf("(reserved value)\n"); 2162 break; 2163 } 2164 printf(" LN System CLS: "); 2165 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) { 2166 case 0x0: 2167 printf("Not supported or not in effect\n"); 2168 break; 2169 case 0x1: 2170 printf("64byte cachelines in effect\n"); 2171 break; 2172 case 0x2: 2173 printf("128byte cachelines in effect\n"); 2174 break; 2175 case 0x3: 2176 printf("Reserved\n"); 2177 break; 2178 } 2179 onoff("10-bit Tag Completer Supported", reg, PCIE_DCAP2_TBT_COMP); 2180 onoff("10-bit Tag Requester Supported", reg, PCIE_DCAP2_TBT_REQ); 2181 printf(" OBFF Supported: "); 2182 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP2_OBFF)) { 2183 case 0x0: 2184 printf("Not supported\n"); 2185 break; 2186 case 0x1: 2187 printf("Message only\n"); 2188 break; 2189 case 0x2: 2190 printf("WAKE# only\n"); 2191 break; 2192 case 0x3: 2193 printf("Both\n"); 2194 break; 2195 } 2196 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 2197 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 2198 val = PCIREG_SHIFTOUT(reg, PCIE_DCAP2_MAX_EETLP); 2199 printf(" Max End-End TLP Prefixes: %u\n", (val == 0) ? 4 : val); 2200 printf(" Emergency Power Reduction Supported: "); 2201 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP2_EMGPWRRED)) { 2202 case 0x0: 2203 printf("Not supported\n"); 2204 break; 2205 case 0x1: 2206 printf("Device Specific mechanism\n"); 2207 break; 2208 case 0x2: 2209 printf("Form Factor spec or Device Specific mechanism\n"); 2210 break; 2211 case 0x3: 2212 printf("Reserved\n"); 2213 break; 2214 } 2215 onoff("Emergency Power Reduction Initialization Required", reg, 2216 PCIE_DCAP2_EMGPWRRED_INI); 2217 onoff("FRS Supported", reg, PCIE_DCAP2_FRS); 2218 2219 /* Device Control 2 */ 2220 reg = regs[o2i(capoff + PCIE_DCSR2)]; 2221 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 2222 printf(" Completion Timeout Value: "); 2223 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 2224 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 2225 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 2226 onoff("AtomicOp Requester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 2227 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 2228 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 2229 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 2230 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 2231 onoff("Emergency Power Reduction Request", reg, 2232 PCIE_DCSR2_EMGPWRRED_REQ); 2233 onoff("10-bit Tag Requester Enabled", reg, PCIE_DCSR2_TBT_REQ); 2234 printf(" OBFF: "); 2235 switch (PCIREG_SHIFTOUT(reg, PCIE_DCSR2_OBFF_EN)) { 2236 case 0x0: 2237 printf("Disabled\n"); 2238 break; 2239 case 0x1: 2240 printf("Enabled with Message Signaling Variation A\n"); 2241 break; 2242 case 0x2: 2243 printf("Enabled with Message Signaling Variation B\n"); 2244 break; 2245 case 0x3: 2246 printf("Enabled using WAKE# signaling\n"); 2247 break; 2248 } 2249 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 2250 2251 if (PCIE_HAS_LINKREGS(pcie_devtype)) { 2252 bool drs_supported = false; 2253 2254 /* Link Capability 2 */ 2255 reg = regs[o2i(capoff + PCIE_LCAP2)]; 2256 /* If the vector is 0, LCAP2 is not implemented */ 2257 if ((reg & PCIE_LCAP2_SUP_LNKSV) != 0) { 2258 printf(" Link Capabilities 2: 0x%08x\n", reg); 2259 printf(" Supported Link Speeds Vector:"); 2260 pci_print_pcie_linkspeedvector( 2261 PCIREG_SHIFTOUT(reg, PCIE_LCAP2_SUP_LNKSV)); 2262 printf("\n"); 2263 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 2264 printf(" " 2265 "Lower SKP OS Generation Supported Speed Vector:"); 2266 pci_print_pcie_linkspeedvector( 2267 PCIREG_SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_GENSUPPSV)); 2268 printf("\n"); 2269 printf(" " 2270 "Lower SKP OS Reception Supported Speed Vector:"); 2271 pci_print_pcie_linkspeedvector( 2272 PCIREG_SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV)); 2273 printf("\n"); 2274 onoff("Retimer Presence Detect Supported", reg, 2275 PCIE_LCAP2_RETIMERPD); 2276 onoff("DRS Supported", reg, PCIE_LCAP2_DRS); 2277 drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false; 2278 } 2279 2280 /* Link Control 2 */ 2281 reg = regs[o2i(capoff + PCIE_LCSR2)]; 2282 /* If the vector is 0, LCAP2 is not implemented */ 2283 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 2284 printf(" Target Link Speed: "); 2285 pci_print_pcie_linkspeed(PCIE_LCSR2, 2286 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_TGT_LSPEED)); 2287 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 2288 onoff("HW Autonomous Speed Disabled", reg, 2289 PCIE_LCSR2_HW_AS_DIS); 2290 printf(" Selectable De-emphasis: "); 2291 pci_print_pcie_link_deemphasis( 2292 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_SEL_DEEMP)); 2293 printf("\n"); 2294 printf(" Transmit Margin: %u\n", 2295 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_TX_MARGIN)); 2296 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 2297 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 2298 printf(" Compliance Present/De-emphasis: "); 2299 pci_print_pcie_link_deemphasis( 2300 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_COMP_DEEMP)); 2301 printf("\n"); 2302 2303 /* Link Status 2 */ 2304 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 2305 printf(" Current De-emphasis Level: "); 2306 pci_print_pcie_link_deemphasis( 2307 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_DEEMP_LVL)); 2308 printf("\n"); 2309 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 2310 onoff("Equalization Phase 1 Successful", reg, 2311 PCIE_LCSR2_EQP1_SUC); 2312 onoff("Equalization Phase 2 Successful", reg, 2313 PCIE_LCSR2_EQP2_SUC); 2314 onoff("Equalization Phase 3 Successful", reg, 2315 PCIE_LCSR2_EQP3_SUC); 2316 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 2317 onoff("Retimer Presence Detected", reg, PCIE_LCSR2_RETIMERPD); 2318 if (drs_supported) { 2319 printf(" Downstream Component Presence: "); 2320 switch (PCIREG_SHIFTOUT(reg, PCIE_LCSR2_DSCOMPN)) { 2321 case PCIE_DSCOMPN_DOWN_NOTDETERM: 2322 printf("Link Down - Presence Not" 2323 " Determined\n"); 2324 break; 2325 case PCIE_DSCOMPN_DOWN_NOTPRES: 2326 printf("Link Down - Component Not Present\n"); 2327 break; 2328 case PCIE_DSCOMPN_DOWN_PRES: 2329 printf("Link Down - Component Present\n"); 2330 break; 2331 case PCIE_DSCOMPN_UP_PRES: 2332 printf("Link Up - Component Present\n"); 2333 break; 2334 case PCIE_DSCOMPN_UP_PRES_DRS: 2335 printf("Link Up - Component Present and DRS" 2336 " received\n"); 2337 break; 2338 default: 2339 printf("reserved\n"); 2340 break; 2341 } 2342 onoff("DRS Message Received", reg, PCIE_LCSR2_DRSRCV); 2343 } 2344 } 2345 2346 /* Slot Capability 2 */ 2347 /* Slot Control 2 */ 2348 /* Slot Status 2 */ 2349 } 2350 2351 static void 2352 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 2353 { 2354 pcireg_t reg; 2355 2356 printf("\n MSI-X Capability Register\n"); 2357 2358 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2359 printf(" Message Control register: 0x%04x\n", 2360 (reg >> 16) & 0xff); 2361 printf(" Table Size: %d\n", PCI_MSIX_CTL_TBLSIZE(reg)); 2362 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 2363 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 2364 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 2365 printf(" Table offset register: 0x%08x\n", reg); 2366 printf(" Table offset: 0x%08x\n", 2367 (pcireg_t)(reg & PCI_MSIX_TBLOFFSET_MASK)); 2368 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_TBLBIR_MASK)); 2369 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 2370 printf(" Pending bit array register: 0x%08x\n", reg); 2371 printf(" Pending bit array offset: 0x%08x\n", 2372 (pcireg_t)(reg & PCI_MSIX_PBAOFFSET_MASK)); 2373 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_PBABIR_MASK)); 2374 } 2375 2376 static void 2377 pci_conf_print_sata_cap(const pcireg_t *regs, int capoff) 2378 { 2379 pcireg_t reg; 2380 2381 printf("\n Serial ATA Capability Register\n"); 2382 2383 reg = regs[o2i(capoff + PCI_SATA_REV)]; 2384 printf(" Revision register: 0x%04x\n", (reg >> 16) & 0xff); 2385 printf(" Revision: %u.%u\n", 2386 PCIREG_SHIFTOUT(reg, PCI_SATA_REV_MAJOR), 2387 PCIREG_SHIFTOUT(reg, PCI_SATA_REV_MINOR)); 2388 2389 reg = regs[o2i(capoff + PCI_SATA_BAR)]; 2390 2391 printf(" BAR Register: 0x%08x\n", reg); 2392 printf(" Register location: "); 2393 if ((reg & PCI_SATA_BAR_SPEC) == PCI_SATA_BAR_INCONF) 2394 printf("in config space\n"); 2395 else { 2396 printf("BAR %d\n", (int)PCI_SATA_BAR_NUM(reg)); 2397 printf(" BAR offset: 0x%08x\n", 2398 PCIREG_SHIFTOUT(reg, PCI_SATA_BAR_OFFSET) * 4); 2399 } 2400 } 2401 2402 static void 2403 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 2404 { 2405 pcireg_t reg; 2406 2407 printf("\n Advanced Features Capability Register\n"); 2408 2409 reg = regs[o2i(capoff + PCI_AFCAPR)]; 2410 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 2411 printf(" AF Structure Length: 0x%02x\n", 2412 PCIREG_SHIFTOUT(reg, PCI_AF_LENGTH)); 2413 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 2414 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 2415 reg = regs[o2i(capoff + PCI_AFCSR)]; 2416 printf(" AF Control register: 0x%02x\n", reg & 0xff); 2417 /* 2418 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 2419 * and it's always 0 on read 2420 */ 2421 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 2422 onoff("Transaction Pending", reg, PCI_AFSR_TP); 2423 } 2424 2425 static void 2426 pci_conf_print_ea_cap_prop(unsigned int prop) 2427 { 2428 2429 switch (prop) { 2430 case PCI_EA_PROP_MEM_NONPREF: 2431 printf("Memory Space, Non-Prefetchable\n"); 2432 break; 2433 case PCI_EA_PROP_MEM_PREF: 2434 printf("Memory Space, Prefetchable\n"); 2435 break; 2436 case PCI_EA_PROP_IO: 2437 printf("I/O Space\n"); 2438 break; 2439 case PCI_EA_PROP_VF_MEM_NONPREF: 2440 printf("Resorce for VF use, Memory Space, Non-Prefetchable\n"); 2441 break; 2442 case PCI_EA_PROP_VF_MEM_PREF: 2443 printf("Resorce for VF use, Memory Space, Prefetch\n"); 2444 break; 2445 case PCI_EA_PROP_BB_MEM_NONPREF: 2446 printf("Behind the Bridge, Memory Space, Non-Pref\n"); 2447 break; 2448 case PCI_EA_PROP_BB_MEM_PREF: 2449 printf("Behind the Bridge, Memory Space. Prefetchable\n"); 2450 break; 2451 case PCI_EA_PROP_BB_IO: 2452 printf("Behind Bridge, I/O Space\n"); 2453 break; 2454 case PCI_EA_PROP_MEM_UNAVAIL: 2455 printf("Memory Space Unavailable\n"); 2456 break; 2457 case PCI_EA_PROP_IO_UNAVAIL: 2458 printf("IO Space Unavailable\n"); 2459 break; 2460 case PCI_EA_PROP_UNAVAIL: 2461 printf("Entry Unavailable for use\n"); 2462 break; 2463 default: 2464 printf("Reserved\n"); 2465 break; 2466 } 2467 } 2468 2469 static void 2470 pci_conf_print_ea_cap(const pcireg_t *regs, int capoff) 2471 { 2472 pcireg_t reg, reg2; 2473 unsigned int entries, entoff, i; 2474 2475 printf("\n Enhanced Allocation Capability Register\n"); 2476 2477 reg = regs[o2i(capoff + PCI_EA_CAP1)]; 2478 printf(" EA Num Entries register: 0x%04x\n", reg >> 16); 2479 entries = PCIREG_SHIFTOUT(reg, PCI_EA_CAP1_NUMENTRIES); 2480 printf(" EA Num Entries: %u\n", entries); 2481 2482 /* Type 1 only */ 2483 if (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) == PCI_HDRTYPE_PPB) { 2484 reg = regs[o2i(capoff + PCI_EA_CAP2)]; 2485 printf(" EA Capability Second register: 0x%08x\n", reg); 2486 printf(" Fixed Secondary Bus Number: %hhu\n", 2487 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_EA_CAP2_SECONDARY)); 2488 printf(" Fixed Subordinate Bus Number: %hhu\n", 2489 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_EA_CAP2_SUBORDINATE)); 2490 entoff = capoff + 8; 2491 } else 2492 entoff = capoff + 4; 2493 2494 for (i = 0; i < entries; i++) { 2495 uint64_t base, offset; 2496 bool baseis64, offsetis64; 2497 unsigned int bei, entry_size; 2498 2499 printf(" Entry %u:\n", i); 2500 /* The first DW */ 2501 reg = regs[o2i(entoff)]; 2502 printf(" The first register: 0x%08x\n", reg); 2503 entry_size = PCIREG_SHIFTOUT(reg, PCI_EA_ES); 2504 printf(" Entry size: %u\n", entry_size); 2505 printf(" BAR Equivalent Indicator: "); 2506 bei = PCIREG_SHIFTOUT(reg, PCI_EA_BEI); 2507 switch (bei) { 2508 case PCI_EA_BEI_BAR0: 2509 case PCI_EA_BEI_BAR1: 2510 case PCI_EA_BEI_BAR2: 2511 case PCI_EA_BEI_BAR3: 2512 case PCI_EA_BEI_BAR4: 2513 case PCI_EA_BEI_BAR5: 2514 printf("BAR %u\n", bei - PCI_EA_BEI_BAR0); 2515 break; 2516 case PCI_EA_BEI_BEHIND: 2517 printf("Behind the function\n"); 2518 break; 2519 case PCI_EA_BEI_NOTIND: 2520 printf("Not Indicated\n"); 2521 break; 2522 case PCI_EA_BEI_EXPROM: 2523 printf("Expansion ROM\n"); 2524 break; 2525 case PCI_EA_BEI_VFBAR0: 2526 case PCI_EA_BEI_VFBAR1: 2527 case PCI_EA_BEI_VFBAR2: 2528 case PCI_EA_BEI_VFBAR3: 2529 case PCI_EA_BEI_VFBAR4: 2530 case PCI_EA_BEI_VFBAR5: 2531 printf("VF BAR %u\n", bei - PCI_EA_BEI_VFBAR0); 2532 break; 2533 case PCI_EA_BEI_RESERVED: 2534 default: 2535 printf("Reserved\n"); 2536 break; 2537 } 2538 2539 printf(" Primary Properties: "); 2540 pci_conf_print_ea_cap_prop(PCIREG_SHIFTOUT(reg, PCI_EA_PP)); 2541 printf(" Secondary Properties: "); 2542 pci_conf_print_ea_cap_prop(PCIREG_SHIFTOUT(reg, PCI_EA_SP)); 2543 onoff("Writable", reg, PCI_EA_W); 2544 onoff("Enable for this entry", reg, PCI_EA_E); 2545 2546 if (entry_size == 0) { 2547 entoff += 4; 2548 continue; 2549 } 2550 2551 /* Base addr */ 2552 reg = regs[o2i(entoff + 4)]; 2553 base = reg & PCI_EA_LOWMASK; 2554 baseis64 = reg & PCI_EA_BASEMAXOFFSET_64BIT; 2555 printf(" Base Address Register Low: 0x%08x\n", reg); 2556 if (baseis64) { 2557 /* 64bit */ 2558 reg2 = regs[o2i(entoff + 12)]; 2559 printf(" Base Address Register high: 0x%08x\n", 2560 reg2); 2561 base |= (uint64_t)reg2 << 32; 2562 } 2563 2564 /* Offset addr */ 2565 reg = regs[o2i(entoff + 8)]; 2566 offset = reg & PCI_EA_LOWMASK; 2567 offsetis64 = reg & PCI_EA_BASEMAXOFFSET_64BIT; 2568 printf(" Max Offset Register Low: 0x%08x\n", reg); 2569 if (offsetis64) { 2570 /* 64bit */ 2571 reg2 = regs[o2i(entoff + (baseis64 ? 16 : 12))]; 2572 printf(" Max Offset Register high: 0x%08x\n", 2573 reg2); 2574 offset |= (uint64_t)reg2 << 32; 2575 } 2576 2577 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 2578 "\n", base, base + offset); 2579 2580 entoff += 4 + (4 * entry_size); 2581 } 2582 } 2583 2584 /* XXX pci_conf_print_fpb_cap */ 2585 2586 static struct { 2587 pcireg_t cap; 2588 const char *name; 2589 void (*printfunc)(const pcireg_t *, int); 2590 } pci_captab[] = { 2591 { PCI_CAP_RESERVED0, "reserved", NULL }, 2592 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 2593 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 2594 { PCI_CAP_VPD, "VPD", NULL }, 2595 { PCI_CAP_SLOTID, "SlotID", NULL }, 2596 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 2597 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 2598 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 2599 { PCI_CAP_LDT, "HyperTransport", pci_conf_print_ht_cap }, 2600 { PCI_CAP_VENDSPEC, "Vendor-specific", 2601 pci_conf_print_vendspec_cap }, 2602 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 2603 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 2604 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 2605 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 2606 pci_conf_print_subsystem_cap }, 2607 { PCI_CAP_AGP8, "AGP 8x", NULL }, 2608 { PCI_CAP_SECURE, "Secure Device", pci_conf_print_secure_cap }, 2609 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 2610 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 2611 { PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap }, 2612 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap}, 2613 { PCI_CAP_EA, "Enhanced Allocation", pci_conf_print_ea_cap }, 2614 { PCI_CAP_FPB, "Flattening Portal Bridge", NULL } 2615 }; 2616 2617 static int 2618 pci_conf_find_cap(const pcireg_t *regs, unsigned int capid, int *offsetp) 2619 { 2620 pcireg_t rval; 2621 unsigned int capptr; 2622 int off; 2623 2624 if (!(regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)) 2625 return 0; 2626 2627 /* Determine the Capability List Pointer register to start with. */ 2628 switch (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)])) { 2629 case 0: /* standard device header */ 2630 case 1: /* PCI-PCI bridge header */ 2631 capptr = PCI_CAPLISTPTR_REG; 2632 break; 2633 case 2: /* PCI-CardBus Bridge header */ 2634 capptr = PCI_CARDBUS_CAPLISTPTR_REG; 2635 break; 2636 default: 2637 return 0; 2638 } 2639 2640 for (off = PCI_CAPLIST_PTR(regs[o2i(capptr)]); 2641 off != 0; off = PCI_CAPLIST_NEXT(rval)) { 2642 rval = regs[o2i(off)]; 2643 if (capid == PCI_CAPLIST_CAP(rval)) { 2644 if (offsetp != NULL) 2645 *offsetp = off; 2646 return 1; 2647 } 2648 } 2649 return 0; 2650 } 2651 2652 static void 2653 pci_conf_print_caplist( 2654 #ifdef _KERNEL 2655 pci_chipset_tag_t pc, pcitag_t tag, 2656 #endif 2657 const pcireg_t *regs, int capoff) 2658 { 2659 int off; 2660 pcireg_t foundcap; 2661 pcireg_t rval; 2662 bool foundtable[__arraycount(pci_captab)]; 2663 unsigned int i; 2664 2665 /* Clear table */ 2666 for (i = 0; i < __arraycount(pci_captab); i++) 2667 foundtable[i] = false; 2668 2669 /* Print capability register's offset and the type first */ 2670 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2671 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2672 rval = regs[o2i(off)]; 2673 printf(" Capability register at 0x%02x\n", off); 2674 2675 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 2676 foundcap = PCI_CAPLIST_CAP(rval); 2677 if (foundcap < __arraycount(pci_captab)) { 2678 printf("%s)\n", pci_captab[foundcap].name); 2679 /* Mark as found */ 2680 foundtable[foundcap] = true; 2681 } else 2682 printf("unknown)\n"); 2683 } 2684 2685 /* 2686 * And then, print the detail of each capability registers 2687 * in capability value's order. 2688 */ 2689 for (i = 0; i < __arraycount(pci_captab); i++) { 2690 if (foundtable[i] == false) 2691 continue; 2692 2693 /* 2694 * The type was found. Search capability list again and 2695 * print all capabilities that the capabiliy type is 2696 * the same. This is required because some capabilities 2697 * appear multiple times (e.g. HyperTransport capability). 2698 */ 2699 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2700 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2701 rval = regs[o2i(off)]; 2702 if ((PCI_CAPLIST_CAP(rval) == i) 2703 && (pci_captab[i].printfunc != NULL)) 2704 pci_captab[i].printfunc(regs, off); 2705 } 2706 } 2707 } 2708 2709 /* Extended Capability */ 2710 2711 static void 2712 pci_conf_print_aer_cap_uc(pcireg_t reg) 2713 { 2714 2715 onoff("Undefined", reg, PCI_AER_UC_UNDEFINED); 2716 onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR); 2717 onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR); 2718 onoff("Poisoned TLP Received", reg, PCI_AER_UC_POISONED_TLP); 2719 onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR); 2720 onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT); 2721 onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT); 2722 onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION); 2723 onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW); 2724 onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP); 2725 onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR); 2726 onoff("Unsupported Request Error", reg, 2727 PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR); 2728 onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION); 2729 onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR); 2730 onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP); 2731 onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED); 2732 onoff("TLP Prefix Blocked Error", reg, 2733 PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR); 2734 onoff("Poisoned TLP Egress Blocked", reg, 2735 PCI_AER_UC_POISONTLP_EGRESS_BLOCKED); 2736 } 2737 2738 static void 2739 pci_conf_print_aer_cap_cor(pcireg_t reg) 2740 { 2741 2742 onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR); 2743 onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP); 2744 onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP); 2745 onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER); 2746 onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT); 2747 onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR); 2748 onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR); 2749 onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW); 2750 } 2751 2752 static void 2753 pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log) 2754 { 2755 2756 printf(" First Error Pointer: 0x%04x\n", 2757 PCIREG_SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR)); 2758 onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE); 2759 onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE); 2760 onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE); 2761 onoff("ECRC Check Enable", reg, PCI_AER_ECRC_CHECK_ENABLE); 2762 onoff("Multiple Header Recording Capable", reg, 2763 PCI_AER_MULT_HDR_CAPABLE); 2764 onoff("Multiple Header Recording Enable", reg,PCI_AER_MULT_HDR_ENABLE); 2765 onoff("Completion Timeout Prefix/Header Log Capable", reg, 2766 PCI_AER_COMPTOUTPRFXHDRLOG_CAP); 2767 2768 /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */ 2769 if (!tlp_prefix_log) 2770 return; 2771 onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT); 2772 *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false; 2773 } 2774 2775 static void 2776 pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg) 2777 { 2778 2779 onoff("Correctable Error Reporting Enable", reg, 2780 PCI_AER_ROOTERR_COR_ENABLE); 2781 onoff("Non-Fatal Error Reporting Enable", reg, 2782 PCI_AER_ROOTERR_NF_ENABLE); 2783 onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE); 2784 } 2785 2786 static void 2787 pci_conf_print_aer_cap_rooterr_status(pcireg_t reg) 2788 { 2789 2790 onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR); 2791 onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR); 2792 onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR); 2793 onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg, 2794 PCI_AER_ROOTERR_MULTI_UC_ERR); 2795 onoff("First Uncorrectable Fatal", reg,PCI_AER_ROOTERR_FIRST_UC_FATAL); 2796 onoff("Non-Fatal Error Messages Received", reg,PCI_AER_ROOTERR_NF_ERR); 2797 onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR); 2798 printf(" Advanced Error Interrupt Message Number: 0x%02x\n", 2799 PCIREG_SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE)); 2800 } 2801 2802 static void 2803 pci_conf_print_aer_cap_errsrc_id(pcireg_t reg) 2804 { 2805 2806 printf(" Correctable Source ID: 0x%04x\n", 2807 PCIREG_SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR)); 2808 printf(" ERR_FATAL/NONFATAL Source ID: 0x%04x\n", 2809 PCIREG_SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC)); 2810 } 2811 2812 static void 2813 pci_conf_print_aer_cap(const pcireg_t *regs, int extcapoff) 2814 { 2815 pcireg_t reg; 2816 int pcie_capoff; 2817 int pcie_devtype = -1; 2818 bool tlp_prefix_log = false; 2819 2820 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 2821 reg = regs[o2i(pcie_capoff)]; 2822 pcie_devtype = PCIE_XCAP_TYPE(reg); 2823 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2824 if (PCIREG_SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) { 2825 reg = regs[o2i(pcie_capoff + PCIE_DCAP2)]; 2826 /* End-End TLP Prefix Supported */ 2827 if (reg & PCIE_DCAP2_EETLP_PREF) { 2828 tlp_prefix_log = true; 2829 } 2830 } 2831 } 2832 2833 printf("\n Advanced Error Reporting Register\n"); 2834 2835 reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)]; 2836 printf(" Uncorrectable Error Status register: 0x%08x\n", reg); 2837 pci_conf_print_aer_cap_uc(reg); 2838 reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)]; 2839 printf(" Uncorrectable Error Mask register: 0x%08x\n", reg); 2840 pci_conf_print_aer_cap_uc(reg); 2841 reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)]; 2842 printf(" Uncorrectable Error Severity register: 0x%08x\n", reg); 2843 pci_conf_print_aer_cap_uc(reg); 2844 2845 reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)]; 2846 printf(" Correctable Error Status register: 0x%08x\n", reg); 2847 pci_conf_print_aer_cap_cor(reg); 2848 reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)]; 2849 printf(" Correctable Error Mask register: 0x%08x\n", reg); 2850 pci_conf_print_aer_cap_cor(reg); 2851 2852 reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)]; 2853 printf(" Advanced Error Capabilities and Control register: 0x%08x\n", 2854 reg); 2855 pci_conf_print_aer_cap_control(reg, &tlp_prefix_log); 2856 reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)]; 2857 printf(" Header Log register:\n"); 2858 pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG, 2859 extcapoff + PCI_AER_ROOTERR_CMD); 2860 2861 switch (pcie_devtype) { 2862 case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */ 2863 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */ 2864 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)]; 2865 printf(" Root Error Command register: 0x%08x\n", reg); 2866 pci_conf_print_aer_cap_rooterr_cmd(reg); 2867 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)]; 2868 printf(" Root Error Status register: 0x%08x\n", reg); 2869 pci_conf_print_aer_cap_rooterr_status(reg); 2870 2871 reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)]; 2872 printf(" Error Source Identification register: 0x%08x\n", 2873 reg); 2874 pci_conf_print_aer_cap_errsrc_id(reg); 2875 break; 2876 } 2877 2878 if (tlp_prefix_log) { 2879 reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)]; 2880 printf(" TLP Prefix Log register: 0x%08x\n", reg); 2881 } 2882 } 2883 2884 /* 2885 * Helper function to print the arbitration phase register. 2886 * 2887 * phases: Number of phases in the arbitration tables. 2888 * arbsize: Number of bits in each phase. 2889 * indent: Add more two spaces if it's true. 2890 */ 2891 static void 2892 pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name, 2893 const int phases, int arbsize, bool indent) 2894 { 2895 pcireg_t reg; 2896 int num_per_reg = 32 / arbsize; 2897 int i, j; 2898 2899 printf("%s %s Arbitration Table:\n", indent ? " " : "", name); 2900 for (i = 0; i < phases; i += num_per_reg) { 2901 reg = regs[o2i(off + (sizeof(uint32_t) * (i / num_per_reg)))]; 2902 for (j = 0; j < num_per_reg; j++) { 2903 printf("%s Phase[%d]: 0x%x\n", indent ? " " : "", 2904 i + j, 2905 (uint32_t)(reg & __BITS(arbsize - 1, 0))); 2906 reg >>= arbsize; 2907 } 2908 } 2909 } 2910 2911 /* For VC, bit 4-7 are reserved. For Port, bit 6-7 are reserved */ 2912 static const int arb_phases[8] = {0, 32, 64, 128, 128, 256, 0, 0 }; 2913 2914 static void 2915 pci_conf_print_vc_cap(const pcireg_t *regs, int extcapoff) 2916 { 2917 pcireg_t reg, n; 2918 int arbtab, parbsize; 2919 pcireg_t arbsel; 2920 int i, count; 2921 2922 printf("\n Virtual Channel Register\n"); 2923 reg = regs[o2i(extcapoff + PCI_VC_CAP1)]; 2924 printf(" Port VC Capability register 1: 0x%08x\n", reg); 2925 count = PCIREG_SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT); 2926 printf(" Extended VC Count: %d\n", count); 2927 n = PCIREG_SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT); 2928 printf(" Low Priority Extended VC Count: %u\n", n); 2929 n = PCIREG_SHIFTOUT(reg, PCI_VC_CAP1_REFCLK); 2930 printf(" Reference Clock: %s\n", 2931 (n == PCI_VC_CAP1_REFCLK_100NS) ? "100ns" : "unknown"); 2932 parbsize = 1 << PCIREG_SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE); 2933 printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize); 2934 2935 reg = regs[o2i(extcapoff + PCI_VC_CAP2)]; 2936 printf(" Port VC Capability register 2: 0x%08x\n", reg); 2937 onoff("Hardware fixed arbitration scheme", 2938 reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME); 2939 onoff("WRR arbitration with 32 phases", 2940 reg, PCI_VC_CAP2_ARB_CAP_WRR_32); 2941 onoff("WRR arbitration with 64 phases", 2942 reg, PCI_VC_CAP2_ARB_CAP_WRR_64); 2943 onoff("WRR arbitration with 128 phases", 2944 reg, PCI_VC_CAP2_ARB_CAP_WRR_128); 2945 arbtab = PCIREG_SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET); 2946 printf(" VC Arbitration Table Offset: 0x%x\n", arbtab); 2947 2948 reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff; 2949 printf(" Port VC Control register: 0x%04x\n", reg); 2950 arbsel = PCIREG_SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT); 2951 printf(" VC Arbitration Select: 0x%x\n", arbsel); 2952 2953 reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16; 2954 printf(" Port VC Status register: 0x%04x\n", reg); 2955 onoff("VC Arbitration Table Status", 2956 reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE); 2957 2958 if ((arbtab != 0) && (arbsel != 0)) 2959 pci_conf_print_vc_cap_arbtab(regs, extcapoff + (arbtab * 16), 2960 "VC", arb_phases[arbsel], 4, false); 2961 2962 for (i = 0; i < count + 1; i++) { 2963 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))]; 2964 printf(" VC number %d\n", i); 2965 printf(" VC Resource Capability Register: 0x%08x\n", reg); 2966 onoff(" Non-configurable Hardware fixed arbitration scheme", 2967 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME); 2968 onoff(" WRR arbitration with 32 phases", 2969 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32); 2970 onoff(" WRR arbitration with 64 phases", 2971 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64); 2972 onoff(" WRR arbitration with 128 phases", 2973 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128); 2974 onoff(" Time-based WRR arbitration with 128 phases", 2975 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128); 2976 onoff(" WRR arbitration with 256 phases", 2977 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256); 2978 onoff(" Advanced Packet Switching", 2979 reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH); 2980 onoff(" Reject Snoop Transaction", 2981 reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS); 2982 n = PCIREG_SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1; 2983 printf(" Maximum Time Slots: %d\n", n); 2984 arbtab = PCIREG_SHIFTOUT(reg, 2985 PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET); 2986 printf(" Port Arbitration Table offset: 0x%02x\n", 2987 arbtab); 2988 2989 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))]; 2990 printf(" VC Resource Control Register: 0x%08x\n", reg); 2991 printf(" TC/VC Map: 0x%02x\n", 2992 PCIREG_SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP)); 2993 /* 2994 * The load Port Arbitration Table bit is used to update 2995 * the Port Arbitration logic and it's always 0 on read, so 2996 * we don't print it. 2997 */ 2998 arbsel = PCIREG_SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT); 2999 printf(" Port Arbitration Select: 0x%x\n", arbsel); 3000 n = PCIREG_SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID); 3001 printf(" VC ID: %d\n", n); 3002 onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE); 3003 3004 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16; 3005 printf(" VC Resource Status Register: 0x%08x\n", reg); 3006 onoff(" Port Arbitration Table Status", 3007 reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE); 3008 onoff(" VC Negotiation Pending", 3009 reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING); 3010 3011 if ((arbtab != 0) && (arbsel != 0)) 3012 pci_conf_print_vc_cap_arbtab(regs, 3013 extcapoff + (arbtab * 16), 3014 "Port", arb_phases[arbsel], parbsize, true); 3015 } 3016 } 3017 3018 /* 3019 * Print Power limit. This encoding is the same among the following registers: 3020 * - The Captured Slot Power Limit in the PCIe Device Capability Register. 3021 * - The Slot Power Limit in the PCIe Slot Capability Register. 3022 * - The Base Power in the Data register of Power Budgeting capability. 3023 */ 3024 static void 3025 pci_conf_print_pcie_power(uint8_t base, unsigned int scale) 3026 { 3027 unsigned int sdiv = 1; 3028 3029 if ((scale == 0) && (base > 0xef)) { 3030 const char *s; 3031 3032 switch (base) { 3033 case 0xf0: 3034 s = "239W < x <= 250W"; 3035 break; 3036 case 0xf1: 3037 s = "250W < x <= 275W"; 3038 break; 3039 case 0xf2: 3040 s = "275W < x <= 300W"; 3041 break; 3042 default: 3043 s = "reserved for greater than 300W"; 3044 break; 3045 } 3046 printf("%s\n", s); 3047 return; 3048 } 3049 3050 for (unsigned int i = scale; i > 0; i--) 3051 sdiv *= 10; 3052 3053 printf("%u", base / sdiv); 3054 3055 if (scale != 0) { 3056 printf(".%u", base % sdiv); 3057 } 3058 printf ("W\n"); 3059 return; 3060 } 3061 3062 static const char * 3063 pci_conf_print_pwrbdgt_type(uint8_t reg) 3064 { 3065 3066 switch (reg) { 3067 case 0x00: 3068 return "PME Aux"; 3069 case 0x01: 3070 return "Auxilary"; 3071 case 0x02: 3072 return "Idle"; 3073 case 0x03: 3074 return "Sustained"; 3075 case 0x04: 3076 return "Sustained (Emergency Power Reduction)"; 3077 case 0x05: 3078 return "Maximum (Emergency Power Reduction)"; 3079 case 0x07: 3080 return "Maximum"; 3081 default: 3082 return "Unknown"; 3083 } 3084 } 3085 3086 static const char * 3087 pci_conf_print_pwrbdgt_pwrrail(uint8_t reg) 3088 { 3089 3090 switch (reg) { 3091 case 0x00: 3092 return "Power(12V)"; 3093 case 0x01: 3094 return "Power(3.3V)"; 3095 case 0x02: 3096 return "Power(1.5V or 1.8V)"; 3097 case 0x07: 3098 return "Thermal"; 3099 default: 3100 return "Unknown"; 3101 } 3102 } 3103 3104 static void 3105 pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int extcapoff) 3106 { 3107 pcireg_t reg; 3108 3109 printf("\n Power Budgeting\n"); 3110 3111 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)]; 3112 printf(" Data Select register: 0x%08x\n", reg); 3113 3114 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)]; 3115 printf(" Data register: 0x%08x\n", reg); 3116 printf(" Base Power: "); 3117 pci_conf_print_pcie_power( 3118 PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_DATA_BASEPWR), 3119 PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE)); 3120 printf(" PM Sub State: 0x%hhx\n", 3121 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT)); 3122 printf(" PM State: D%u\n", 3123 PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT)); 3124 printf(" Type: %s\n", 3125 pci_conf_print_pwrbdgt_type( 3126 (uint8_t)(PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_TYPE)))); 3127 printf(" Power Rail: %s\n", 3128 pci_conf_print_pwrbdgt_pwrrail( 3129 (uint8_t)(PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL)))); 3130 3131 reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)]; 3132 printf(" Power Budget Capability register: 0x%08x\n", reg); 3133 onoff("System Allocated", 3134 reg, PCI_PWRBDGT_CAP_SYSALLOC); 3135 } 3136 3137 static const char * 3138 pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type) 3139 { 3140 3141 switch (type) { 3142 case 0x00: 3143 return "Configuration Space Element"; 3144 case 0x01: 3145 return "System Egress Port or internal sink (memory)"; 3146 case 0x02: 3147 return "Internal Root Complex Link"; 3148 default: 3149 return "Unknown"; 3150 } 3151 } 3152 3153 static void 3154 pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int extcapoff) 3155 { 3156 pcireg_t reg; 3157 unsigned char nent, linktype; 3158 int i; 3159 3160 printf("\n Root Complex Link Declaration\n"); 3161 3162 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)]; 3163 printf(" Element Self Description Register: 0x%08x\n", reg); 3164 printf(" Element Type: %s\n", 3165 pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg)); 3166 nent = PCIREG_SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT); 3167 printf(" Number of Link Entries: %hhu\n", nent); 3168 printf(" Component ID: %hhu\n", 3169 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID)); 3170 printf(" Port Number: %hhu\n", 3171 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM)); 3172 for (i = 0; i < nent; i++) { 3173 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))]; 3174 printf(" Link Entry %d:\n", i + 1); 3175 printf(" Link Description Register: 0x%08x\n", reg); 3176 onoff(" Link Valid", reg, PCI_RCLINK_DCL_LINKDESC_LVALID); 3177 linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE; 3178 onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, 3179 "Configuration Space", "Memory-Mapped Space"); 3180 onoff(" Associated RCRB Header", reg, 3181 PCI_RCLINK_DCL_LINKDESC_ARCRBH); 3182 printf(" Target Component ID: %hhu\n", 3183 (uint8_t)PCIREG_SHIFTOUT(reg, 3184 PCI_RCLINK_DCL_LINKDESC_TCOMPID)); 3185 printf(" Target Port Number: %hhu\n", 3186 (uint8_t)PCIREG_SHIFTOUT(reg, 3187 PCI_RCLINK_DCL_LINKDESC_TPNUM)); 3188 3189 if (linktype == 0) { 3190 /* Memory-Mapped Space */ 3191 reg = regs[o2i(extcapoff 3192 + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))]; 3193 printf(" Link Address Low Register: 0x%08x\n", 3194 reg); 3195 reg = regs[o2i(extcapoff 3196 + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))]; 3197 printf(" Link Address High Register: 0x%08x\n", 3198 reg); 3199 } else { 3200 unsigned int nb; 3201 pcireg_t lo, hi; 3202 3203 /* Configuration Space */ 3204 lo = regs[o2i(extcapoff 3205 + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))]; 3206 printf(" Configuration Space Low Register: " 3207 "0x%08x\n", lo); 3208 hi = regs[o2i(extcapoff 3209 + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))]; 3210 printf(" Configuration Space High Register: " 3211 "0x%08x\n", hi); 3212 nb = PCIREG_SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N); 3213 printf(" N: %u\n", nb); 3214 printf(" Func: %hhu\n", 3215 (uint8_t)PCIREG_SHIFTOUT(lo, 3216 PCI_RCLINK_DCL_LINKADDR_LT1_FUNC)); 3217 printf(" Dev: %hhu\n", 3218 (uint8_t)PCIREG_SHIFTOUT(lo, 3219 PCI_RCLINK_DCL_LINKADDR_LT1_DEV)); 3220 printf(" Bus: %hhu\n", 3221 (uint8_t)PCIREG_SHIFTOUT(lo, 3222 PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb))); 3223 lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i); 3224 printf(" Configuration Space Base Address: " 3225 "0x%016" PRIx64 "\n", ((uint64_t)hi << 32) + lo); 3226 } 3227 } 3228 } 3229 3230 /* XXX pci_conf_print_rclink_ctl_cap */ 3231 3232 static void 3233 pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int extcapoff) 3234 { 3235 pcireg_t reg; 3236 3237 printf("\n Root Complex Event Collector Association\n"); 3238 3239 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)]; 3240 printf(" Association Bitmap for Root Complex Integrated Devices:" 3241 " 0x%08x\n", reg); 3242 3243 if (PCI_EXTCAPLIST_VERSION(regs[o2i(extcapoff)]) >= 2) { 3244 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBUSNUM)]; 3245 printf(" RCEC Associated Bus Numbers register: 0x%08x\n", 3246 reg); 3247 printf(" RCEC Next Bus: %u\n", 3248 PCIREG_SHIFTOUT(reg, 3249 PCI_RCEC_ASSOCBUSNUM_RCECNEXT)); 3250 printf(" RCEC Last Bus: %u\n", 3251 PCIREG_SHIFTOUT(reg, 3252 PCI_RCEC_ASSOCBUSNUM_RCECLAST)); 3253 } 3254 } 3255 3256 /* XXX pci_conf_print_mfvc_cap */ 3257 /* XXX pci_conf_print_vc2_cap */ 3258 /* XXX pci_conf_print_rcrb_cap */ 3259 /* XXX pci_conf_print_vendor_cap */ 3260 /* XXX pci_conf_print_cac_cap */ 3261 3262 static void 3263 pci_conf_print_acs_cap(const pcireg_t *regs, int extcapoff) 3264 { 3265 pcireg_t reg, cap, ctl; 3266 unsigned int size, i; 3267 3268 printf("\n Access Control Services\n"); 3269 3270 reg = regs[o2i(extcapoff + PCI_ACS_CAP)]; 3271 cap = reg & 0xffff; 3272 ctl = reg >> 16; 3273 printf(" ACS Capability register: 0x%08x\n", cap); 3274 onoff("ACS Source Validation", cap, PCI_ACS_CAP_V); 3275 onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B); 3276 onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R); 3277 onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C); 3278 onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U); 3279 onoff("ACS Egress Control", cap, PCI_ACS_CAP_E); 3280 onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T); 3281 size = PCIREG_SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE); 3282 if (size == 0) 3283 size = 256; 3284 printf(" Egress Control Vector Size: %u\n", size); 3285 printf(" ACS Control register: 0x%08x\n", ctl); 3286 onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V); 3287 onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B); 3288 onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R); 3289 onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C); 3290 onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U); 3291 onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E); 3292 onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T); 3293 3294 /* 3295 * If the P2P Egress Control Capability bit is 0, ignore the Egress 3296 * Control vector. 3297 */ 3298 if ((cap & PCI_ACS_CAP_E) == 0) 3299 return; 3300 for (i = 0; i < size; i += 32) 3301 printf(" Egress Control Vector [%u..%u]: 0x%08x\n", i + 31, 3302 i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]); 3303 } 3304 3305 static void 3306 pci_conf_print_ari_cap(const pcireg_t *regs, int extcapoff) 3307 { 3308 pcireg_t reg, cap, ctl; 3309 3310 printf("\n Alternative Routing-ID Interpretation Register\n"); 3311 3312 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 3313 cap = reg & 0xffff; 3314 ctl = reg >> 16; 3315 printf(" Capability register: 0x%08x\n", cap); 3316 onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M); 3317 onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A); 3318 printf(" Next Function Number: %u\n", 3319 PCIREG_SHIFTOUT(reg, PCI_ARI_CAP_NXTFN)); 3320 printf(" Control register: 0x%08x\n", ctl); 3321 onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M); 3322 onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A); 3323 printf(" Function Group: %u\n", 3324 PCIREG_SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP)); 3325 } 3326 3327 static void 3328 pci_conf_print_ats_cap(const pcireg_t *regs, int extcapoff) 3329 { 3330 pcireg_t reg, cap, ctl; 3331 unsigned int num; 3332 3333 printf("\n Address Translation Services\n"); 3334 3335 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 3336 cap = reg & 0xffff; 3337 ctl = reg >> 16; 3338 printf(" Capability register: 0x%04x\n", cap); 3339 num = PCIREG_SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH); 3340 if (num == 0) 3341 num = 32; 3342 printf(" Invalidate Queue Depth: %u\n", num); 3343 onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ); 3344 onoff("Global Invalidate", reg, PCI_ATS_CAP_GLOBALINVL); 3345 onoff("Relaxed Ordering", reg, PCI_ATS_CAP_RELAXORD); 3346 3347 printf(" Control register: 0x%04x\n", ctl); 3348 printf(" Smallest Translation Unit: %u\n", 3349 PCIREG_SHIFTOUT(reg, PCI_ATS_CTL_STU)); 3350 onoff("Enable", reg, PCI_ATS_CTL_EN); 3351 } 3352 3353 static void 3354 pci_conf_print_sernum_cap(const pcireg_t *regs, int extcapoff) 3355 { 3356 pcireg_t lo, hi; 3357 3358 printf("\n Device Serial Number Register\n"); 3359 3360 lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)]; 3361 hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)]; 3362 printf(" Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 3363 hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff, 3364 lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff); 3365 } 3366 3367 static void 3368 pci_conf_print_sriov_cap(const pcireg_t *regs, int extcapoff) 3369 { 3370 char buf[sizeof("99999 MB")]; 3371 pcireg_t reg; 3372 pcireg_t total_vfs; 3373 int i; 3374 bool first; 3375 3376 printf("\n Single Root IO Virtualization Register\n"); 3377 3378 reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)]; 3379 printf(" Capabilities register: 0x%08x\n", reg); 3380 onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION); 3381 onoff("ARI Capable Hierarchy Preserved", reg, 3382 PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED); 3383 if (reg & PCI_SRIOV_CAP_VF_MIGRATION) { 3384 printf(" VF Migration Interrupt Message Number: 0x%03x\n", 3385 PCIREG_SHIFTOUT(reg, PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N)); 3386 } 3387 3388 reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff; 3389 printf(" Control register: 0x%04x\n", reg); 3390 onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE); 3391 onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT); 3392 onoff("VF Migration Interrupt Enable", reg, 3393 PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE); 3394 onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE); 3395 onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER); 3396 3397 reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16; 3398 printf(" Status register: 0x%04x\n", reg); 3399 onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION); 3400 3401 reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff; 3402 printf(" InitialVFs register: 0x%04x\n", reg); 3403 total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16; 3404 printf(" TotalVFs register: 0x%04x\n", reg); 3405 reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff; 3406 printf(" NumVFs register: 0x%04x\n", reg); 3407 3408 reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16; 3409 printf(" Function Dependency Link register: 0x%04x\n", reg); 3410 3411 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff; 3412 printf(" First VF Offset register: 0x%04x\n", reg); 3413 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16; 3414 printf(" VF Stride register: 0x%04x\n", reg); 3415 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_DID)] >> 16; 3416 printf(" Device ID: 0x%04x\n", reg); 3417 3418 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)]; 3419 printf(" Supported Page Sizes register: 0x%08x\n", reg); 3420 printf(" Supported Page Size:"); 3421 for (i = 0, first = true; i < 32; i++) { 3422 if (reg & __BIT(i)) { 3423 #ifdef _KERNEL 3424 format_bytes(buf, sizeof(buf), 1LL << (i + 12)); 3425 #else 3426 humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B", 3427 HN_AUTOSCALE, 0); 3428 #endif 3429 printf("%s %s", first ? "" : ",", buf); 3430 first = false; 3431 } 3432 } 3433 printf("\n"); 3434 3435 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)]; 3436 printf(" System Page Sizes register: 0x%08x\n", reg); 3437 printf(" Page Size: "); 3438 if (reg != 0) { 3439 int bitpos = ffs(reg) -1; 3440 3441 /* Assume only one bit is set. */ 3442 #ifdef _KERNEL 3443 format_bytes(buf, sizeof(buf), 1LL << (bitpos + 12)); 3444 #else 3445 humanize_number(buf, sizeof(buf), 1LL << (bitpos + 12), 3446 "B", HN_AUTOSCALE, 0); 3447 #endif 3448 printf("%s", buf); 3449 } else { 3450 printf("unknown"); 3451 } 3452 printf("\n"); 3453 3454 for (i = 0; i < 6; i++) { 3455 reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))]; 3456 printf(" VF BAR%d register: 0x%08x\n", i, reg); 3457 } 3458 3459 if (total_vfs > 0) { 3460 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)]; 3461 printf(" VF Migration State Array Offset register: 0x%08x\n", 3462 reg); 3463 printf(" VF Migration State Offset: 0x%08x\n", 3464 PCIREG_SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET)); 3465 i = PCIREG_SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR); 3466 printf(" VF Migration State BIR: "); 3467 if (i >= 0 && i <= 5) { 3468 printf("BAR%d", i); 3469 } else { 3470 printf("unknown BAR (%d)", i); 3471 } 3472 printf("\n"); 3473 } 3474 } 3475 3476 /* XXX pci_conf_print_mriov_cap */ 3477 3478 static void 3479 pci_conf_print_multicast_cap(const pcireg_t *regs, int extcapoff) 3480 { 3481 pcireg_t reg, cap, ctl; 3482 pcireg_t regl, regh; 3483 uint64_t addr; 3484 int n; 3485 3486 printf("\n Multicast\n"); 3487 3488 reg = regs[o2i(extcapoff + PCI_MCAST_CTL)]; 3489 cap = reg & 0xffff; 3490 ctl = reg >> 16; 3491 printf(" Capability Register: 0x%04x\n", cap); 3492 printf(" Max Group: %u\n", 3493 (pcireg_t)(reg & PCI_MCAST_CAP_MAXGRP) + 1); 3494 3495 /* Endpoint Only */ 3496 n = PCIREG_SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ); 3497 if (n > 0) 3498 printf(" Windw Size Requested: %d\n", 1 << (n - 1)); 3499 3500 onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN); 3501 3502 printf(" Control Register: 0x%04x\n", ctl); 3503 printf(" Num Group: %u\n", 3504 PCIREG_SHIFTOUT(reg, PCI_MCAST_CTL_NUMGRP) + 1); 3505 onoff("Enable", reg, PCI_MCAST_CTL_ENA); 3506 3507 regl = regs[o2i(extcapoff + PCI_MCAST_BARL)]; 3508 regh = regs[o2i(extcapoff + PCI_MCAST_BARH)]; 3509 printf(" Base Address Register 0: 0x%08x\n", regl); 3510 printf(" Base Address Register 1: 0x%08x\n", regh); 3511 printf(" Index Position: %u\n", 3512 (unsigned int)(regl & PCI_MCAST_BARL_INDPOS)); 3513 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_BARL_ADDR); 3514 printf(" Base Address: 0x%016" PRIx64 "\n", addr); 3515 3516 regl = regs[o2i(extcapoff + PCI_MCAST_RECVL)]; 3517 regh = regs[o2i(extcapoff + PCI_MCAST_RECVH)]; 3518 printf(" Receive Register 0: 0x%08x\n", regl); 3519 printf(" Receive Register 1: 0x%08x\n", regh); 3520 3521 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLL)]; 3522 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLH)]; 3523 printf(" Block All Register 0: 0x%08x\n", regl); 3524 printf(" Block All Register 1: 0x%08x\n", regh); 3525 3526 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSL)]; 3527 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSH)]; 3528 printf(" Block Untranslated Register 0: 0x%08x\n", regl); 3529 printf(" Block Untranslated Register 1: 0x%08x\n", regh); 3530 3531 regl = regs[o2i(extcapoff + PCI_MCAST_OVERLAYL)]; 3532 regh = regs[o2i(extcapoff + PCI_MCAST_OVERLAYH)]; 3533 printf(" Overlay BAR 0: 0x%08x\n", regl); 3534 printf(" Overlay BAR 1: 0x%08x\n", regh); 3535 3536 n = regl & PCI_MCAST_OVERLAYL_SIZE; 3537 printf(" Overlay Size: "); 3538 if (n >= 6) 3539 printf("%d\n", n); 3540 else 3541 printf("off\n"); 3542 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_OVERLAYL_ADDR); 3543 printf(" Overlay BAR: 0x%016" PRIx64 "\n", addr); 3544 } 3545 3546 static void 3547 pci_conf_print_page_req_cap(const pcireg_t *regs, int extcapoff) 3548 { 3549 pcireg_t reg, ctl, sta; 3550 3551 printf("\n Page Request\n"); 3552 3553 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)]; 3554 ctl = reg & 0xffff; 3555 sta = reg >> 16; 3556 printf(" Control Register: 0x%04x\n", ctl); 3557 onoff("Enable", reg, PCI_PAGE_REQ_CTL_E); 3558 onoff("Reset", reg, PCI_PAGE_REQ_CTL_R); 3559 3560 printf(" Status Register: 0x%04x\n", sta); 3561 onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF); 3562 onoff("Unexpected Page Request Group Index", reg, 3563 PCI_PAGE_REQ_STA_UPRGI); 3564 onoff("Stopped", reg, PCI_PAGE_REQ_STA_S); 3565 onoff("PRG Response PASID Required", reg, PCI_PAGE_REQ_STA_PASIDR); 3566 3567 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)]; 3568 printf(" Outstanding Page Request Capacity: %u\n", reg); 3569 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)]; 3570 printf(" Outstanding Page Request Allocation: %u\n", reg); 3571 } 3572 3573 /* XXX pci_conf_print_amd_cap */ 3574 3575 #define MEM_PBUFSIZE sizeof("999GB") 3576 3577 static void 3578 pci_conf_print_resizbar_cap(const pcireg_t *regs, int extcapoff) 3579 { 3580 pcireg_t cap, ctl; 3581 unsigned int bars, i, n; 3582 char pbuf[MEM_PBUFSIZE]; 3583 3584 printf("\n Resizable BAR\n"); 3585 3586 /* Get Number of Resizable BARs */ 3587 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(0))]; 3588 bars = PCIREG_SHIFTOUT(ctl, PCI_RESIZBAR_CTL_NUMBAR); 3589 printf(" Number of Resizable BARs: "); 3590 if (bars <= 6) 3591 printf("%u\n", bars); 3592 else { 3593 printf("incorrect (%u)\n", bars); 3594 return; 3595 } 3596 3597 for (n = 0; n < 6; n++) { 3598 cap = regs[o2i(extcapoff + PCI_RESIZBAR_CAP(n))]; 3599 printf(" Capability register(%u): 0x%08x\n", n, cap); 3600 if ((cap & PCI_RESIZBAR_CAP_SIZEMASK) == 0) 3601 continue; /* Not Used */ 3602 printf(" Acceptable BAR sizes:"); 3603 for (i = 4; i <= 23; i++) { 3604 if ((cap & (1 << i)) != 0) { 3605 humanize_number(pbuf, MEM_PBUFSIZE, 3606 (int64_t)1024 * 1024 << (i - 4), "B", 3607 #ifdef _KERNEL 3608 1); 3609 #else 3610 HN_AUTOSCALE, HN_NOSPACE); 3611 #endif 3612 printf(" %s", pbuf); 3613 } 3614 } 3615 printf("\n"); 3616 3617 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(n))]; 3618 printf(" Control register(%u): 0x%08x\n", n, ctl); 3619 printf(" BAR Index: %u\n", 3620 PCIREG_SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARIDX)); 3621 humanize_number(pbuf, MEM_PBUFSIZE, 3622 (int64_t)1024 * 1024 3623 << PCIREG_SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARSIZ), 3624 "B", 3625 #ifdef _KERNEL 3626 1); 3627 #else 3628 HN_AUTOSCALE, HN_NOSPACE); 3629 #endif 3630 printf(" BAR Size: %s\n", pbuf); 3631 } 3632 } 3633 3634 static void 3635 pci_conf_print_dpa_cap(const pcireg_t *regs, int extcapoff) 3636 { 3637 pcireg_t reg; 3638 unsigned int substmax, i; 3639 3640 printf("\n Dynamic Power Allocation\n"); 3641 3642 reg = regs[o2i(extcapoff + PCI_DPA_CAP)]; 3643 printf(" Capability register: 0x%08x\n", reg); 3644 substmax = PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_SUBSTMAX); 3645 printf(" Substate Max: %u\n", substmax); 3646 printf(" Transition Latency Unit: "); 3647 switch (PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_TLUINT)) { 3648 case 0: 3649 printf("1ms\n"); 3650 break; 3651 case 1: 3652 printf("10ms\n"); 3653 break; 3654 case 2: 3655 printf("100ms\n"); 3656 break; 3657 default: 3658 printf("reserved\n"); 3659 break; 3660 } 3661 printf(" Power Allocation Scale: "); 3662 switch (PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_PAS)) { 3663 case 0: 3664 printf("10.0x\n"); 3665 break; 3666 case 1: 3667 printf("1.0x\n"); 3668 break; 3669 case 2: 3670 printf("0.1x\n"); 3671 break; 3672 case 3: 3673 printf("0.01x\n"); 3674 break; 3675 } 3676 printf(" Transition Latency Value 0: %u\n", 3677 PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_XLCY0)); 3678 printf(" Transition Latency Value 1: %u\n", 3679 PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_XLCY1)); 3680 3681 reg = regs[o2i(extcapoff + PCI_DPA_LATIND)]; 3682 printf(" Latency Indicatior register: 0x%08x\n", reg); 3683 3684 reg = regs[o2i(extcapoff + PCI_DPA_CS)]; 3685 printf(" Status register: 0x%04x\n", reg & 0xffff); 3686 printf(" Substate Status: 0x%02x\n", 3687 PCIREG_SHIFTOUT(reg, PCI_DPA_CS_SUBSTSTAT)); 3688 onoff("Substate Control Enabled", reg, PCI_DPA_CS_SUBSTCTLEN); 3689 printf(" Control register: 0x%04x\n", reg >> 16); 3690 printf(" Substate Control: 0x%02x\n", 3691 PCIREG_SHIFTOUT(reg, PCI_DPA_CS_SUBSTCTL)); 3692 3693 for (i = 0; i <= substmax; i++) 3694 printf(" Substate Power Allocation register %d: 0x%02x\n", 3695 i, (regs[PCI_DPA_PWRALLOC + (i / 4)] >> (i % 4) & 0xff)); 3696 } 3697 3698 static const char * 3699 pci_conf_print_tph_req_cap_sttabloc(uint8_t val) 3700 { 3701 3702 switch (val) { 3703 case PCI_TPH_REQ_STTBLLOC_NONE: 3704 return "Not Present"; 3705 case PCI_TPH_REQ_STTBLLOC_TPHREQ: 3706 return "in the TPH Requester Capability Structure"; 3707 case PCI_TPH_REQ_STTBLLOC_MSIX: 3708 return "in the MSI-X Table"; 3709 default: 3710 return "Unknown"; 3711 } 3712 } 3713 3714 static void 3715 pci_conf_print_tph_req_cap(const pcireg_t *regs, int extcapoff) 3716 { 3717 pcireg_t reg; 3718 int size = 0, i, j; 3719 uint8_t sttbloc; 3720 3721 printf("\n TPH Requester Extended Capability\n"); 3722 3723 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)]; 3724 printf(" TPH Requester Capabililty register: 0x%08x\n", reg); 3725 onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST); 3726 onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC); 3727 onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC); 3728 onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ); 3729 sttbloc = PCIREG_SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC); 3730 printf(" ST Table Location: %s\n", 3731 pci_conf_print_tph_req_cap_sttabloc(sttbloc)); 3732 if (sttbloc == PCI_TPH_REQ_STTBLLOC_TPHREQ) { 3733 size = PCIREG_SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1; 3734 printf(" ST Table Size: %d\n", size); 3735 } 3736 3737 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CTL)]; 3738 printf(" TPH Requester Control register: 0x%08x\n", reg); 3739 printf(" ST Mode Select: "); 3740 switch (PCIREG_SHIFTOUT(reg, PCI_TPH_REQ_CTL_STSEL)) { 3741 case PCI_TPH_REQ_CTL_STSEL_NO: 3742 printf("No ST Mode\n"); 3743 break; 3744 case PCI_TPH_REQ_CTL_STSEL_IV: 3745 printf("Interrupt Vector Mode\n"); 3746 break; 3747 case PCI_TPH_REQ_CTL_STSEL_DS: 3748 printf("Device Specific Mode\n"); 3749 break; 3750 default: 3751 printf("(reserved value)\n"); 3752 break; 3753 } 3754 printf(" TPH Requester Enable: "); 3755 switch (PCIREG_SHIFTOUT(reg, PCI_TPH_REQ_CTL_TPHREQEN)) { 3756 case PCI_TPH_REQ_CTL_TPHREQEN_NO: /* 0x0 */ 3757 printf("Not permitted\n"); 3758 break; 3759 case PCI_TPH_REQ_CTL_TPHREQEN_TPH: 3760 printf("TPH and not Extended TPH\n"); 3761 break; 3762 case PCI_TPH_REQ_CTL_TPHREQEN_ETPH: 3763 printf("TPH and Extended TPH"); 3764 break; 3765 default: 3766 printf("(reserved value)\n"); 3767 break; 3768 } 3769 3770 if (sttbloc != PCI_TPH_REQ_STTBLLOC_TPHREQ) 3771 return; 3772 3773 for (i = 0; i < size ; i += 2) { 3774 reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)]; 3775 for (j = 0; j < 2 ; j++) { 3776 uint32_t entry = reg; 3777 3778 if (j != 0) 3779 entry >>= 16; 3780 entry &= 0xffff; 3781 printf(" TPH ST Table Entry (%d): 0x%04"PRIx32"\n", 3782 i + j, entry); 3783 } 3784 } 3785 } 3786 3787 static void 3788 pci_conf_print_ltr_cap(const pcireg_t *regs, int extcapoff) 3789 { 3790 pcireg_t reg; 3791 3792 printf("\n Latency Tolerance Reporting\n"); 3793 reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)]; 3794 printf(" Max Snoop Latency Register: 0x%04x\n", reg & 0xffff); 3795 printf(" Max Snoop Latency: %juns\n", 3796 (uintmax_t)(PCIREG_SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL) 3797 * PCI_LTR_SCALETONS(PCIREG_SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE)))); 3798 printf(" Max No-Snoop Latency Register: 0x%04x\n", reg >> 16); 3799 printf(" Max No-Snoop Latency: %juns\n", 3800 (uintmax_t)(PCIREG_SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL) 3801 * PCI_LTR_SCALETONS(PCIREG_SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE)))); 3802 } 3803 3804 static void 3805 pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int extcapoff) 3806 { 3807 int pcie_capoff; 3808 pcireg_t reg; 3809 int i, maxlinkwidth; 3810 3811 printf("\n Secondary PCI Express Register\n"); 3812 3813 reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)]; 3814 printf(" Link Control 3 register: 0x%08x\n", reg); 3815 onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ); 3816 onoff("Link Equalization Request Interrupt Enable", 3817 reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE); 3818 printf(" Enable Lower SKP OS Generation Vector:"); 3819 pci_print_pcie_linkspeedvector( 3820 PCIREG_SHIFTOUT(reg, PCI_SECPCIE_LCTL3_ELSKPOSGENV)); 3821 printf("\n"); 3822 3823 reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)]; 3824 printf(" Lane Error Status register: 0x%08x\n", reg); 3825 3826 /* Get Max Link Width */ 3827 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 3828 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 3829 maxlinkwidth = PCIREG_SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 3830 } else { 3831 printf("error: falied to get PCIe capablity\n"); 3832 return; 3833 } 3834 for (i = 0; i < maxlinkwidth; i++) { 3835 reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))]; 3836 if (i % 2 != 0) 3837 reg >>= 16; 3838 else 3839 reg &= 0xffff; 3840 printf(" Equalization Control Register (Link %d): 0x%04x\n", 3841 i, reg); 3842 printf(" Downstream Port Transmit Preset: 0x%x\n", 3843 PCIREG_SHIFTOUT(reg, 3844 PCI_SECPCIE_EQCTL_DP_XMIT_PRESET)); 3845 printf(" Downstream Port Receive Hint: 0x%x\n", 3846 PCIREG_SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT)); 3847 printf(" Upstream Port Transmit Preset: 0x%x\n", 3848 PCIREG_SHIFTOUT(reg, 3849 PCI_SECPCIE_EQCTL_UP_XMIT_PRESET)); 3850 printf(" Upstream Port Receive Hint: 0x%x\n", 3851 PCIREG_SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT)); 3852 } 3853 } 3854 3855 /* XXX pci_conf_print_pmux_cap */ 3856 3857 static void 3858 pci_conf_print_pasid_cap(const pcireg_t *regs, int extcapoff) 3859 { 3860 pcireg_t reg, cap, ctl; 3861 unsigned int num; 3862 3863 printf("\n Process Address Space ID\n"); 3864 3865 reg = regs[o2i(extcapoff + PCI_PASID_CAP)]; 3866 cap = reg & 0xffff; 3867 ctl = reg >> 16; 3868 printf(" PASID Capability Register: 0x%04x\n", cap); 3869 onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM); 3870 onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE); 3871 num = (1 << PCIREG_SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1; 3872 printf(" Max PASID Width: %u\n", num); 3873 3874 printf(" PASID Control Register: 0x%04x\n", ctl); 3875 onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN); 3876 onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN); 3877 onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN); 3878 } 3879 3880 static void 3881 pci_conf_print_lnr_cap(const pcireg_t *regs, int extcapoff) 3882 { 3883 pcireg_t reg, cap, ctl; 3884 unsigned int num; 3885 3886 printf("\n LN Requester\n"); 3887 3888 reg = regs[o2i(extcapoff + PCI_LNR_CAP)]; 3889 cap = reg & 0xffff; 3890 ctl = reg >> 16; 3891 printf(" LNR Capability register: 0x%04x\n", cap); 3892 onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64); 3893 onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128); 3894 num = 1 << PCIREG_SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX); 3895 printf(" LNR Registration MAX: %u\n", num); 3896 3897 printf(" LNR Control register: 0x%04x\n", ctl); 3898 onoff("LNR Enable", reg, PCI_LNR_CTL_EN); 3899 onoff("LNR CLS", reg, PCI_LNR_CTL_CLS); 3900 num = 1 << PCIREG_SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM); 3901 printf(" LNR Registration Limit: %u\n", num); 3902 } 3903 3904 static void 3905 pci_conf_print_dpc_pio(pcireg_t r) 3906 { 3907 onoff("Cfg Request received UR Completion", r,PCI_DPC_RPPIO_CFGUR_CPL); 3908 onoff("Cfg Request received CA Completion", r,PCI_DPC_RPPIO_CFGCA_CPL); 3909 onoff("Cfg Request Completion Timeout", r, PCI_DPC_RPPIO_CFG_CTO); 3910 onoff("I/O Request received UR Completion", r, PCI_DPC_RPPIO_IOUR_CPL); 3911 onoff("I/O Request received CA Completion", r, PCI_DPC_RPPIO_IOCA_CPL); 3912 onoff("I/O Request Completion Timeout", r, PCI_DPC_RPPIO_IO_CTO); 3913 onoff("Mem Request received UR Completion", r,PCI_DPC_RPPIO_MEMUR_CPL); 3914 onoff("Mem Request received CA Completion", r,PCI_DPC_RPPIO_MEMCA_CPL); 3915 onoff("Mem Request Completion Timeout", r, PCI_DPC_RPPIO_MEM_CTO); 3916 } 3917 3918 static void 3919 pci_conf_print_dpc_cap(const pcireg_t *regs, int extcapoff) 3920 { 3921 pcireg_t reg, cap, ctl, stat, errsrc; 3922 const char *trigstr; 3923 bool rpext; 3924 3925 printf("\n Downstream Port Containment\n"); 3926 3927 reg = regs[o2i(extcapoff + PCI_DPC_CCR)]; 3928 cap = reg & 0xffff; 3929 ctl = reg >> 16; 3930 rpext = (reg & PCI_DPCCAP_RPEXT) ? true : false; 3931 printf(" DPC Capability register: 0x%04x\n", cap); 3932 printf(" DPC Interrupt Message Number: %02x\n", 3933 (unsigned int)(cap & PCI_DPCCAP_IMSGN)); 3934 onoff("RP Extensions for DPC", reg, PCI_DPCCAP_RPEXT); 3935 onoff("Poisoned TLP Egress Blocking Supported", reg, 3936 PCI_DPCCAP_POISONTLPEB); 3937 onoff("DPC Software Triggering Supported", reg, PCI_DPCCAP_SWTRIG); 3938 printf(" RP PIO Log Size: %u\n", 3939 PCIREG_SHIFTOUT(reg, PCI_DPCCAP_RPPIOLOGSZ)); 3940 onoff("DL_Active ERR_COR Signaling Supported", reg, 3941 PCI_DPCCAP_DLACTECORS); 3942 printf(" DPC Control register: 0x%04x\n", ctl); 3943 switch (PCIREG_SHIFTOUT(reg, PCI_DPCCTL_TIRGEN)) { 3944 case 0: 3945 trigstr = "disabled"; 3946 break; 3947 case 1: 3948 trigstr = "enabled(ERR_FATAL)"; 3949 break; 3950 case 2: 3951 trigstr = "enabled(ERR_NONFATAL or ERR_FATAL)"; 3952 break; 3953 default: 3954 trigstr = "(reserverd)"; 3955 break; 3956 } 3957 printf(" DPC Trigger Enable: %s\n", trigstr); 3958 printf(" DPC Completion Control: %s Completion Status\n", 3959 (reg & PCI_DPCCTL_COMPCTL) 3960 ? "Unsupported Request(UR)" : "Completer Abort(CA)"); 3961 onoff("DPC Interrupt Enable", reg, PCI_DPCCTL_IE); 3962 onoff("DPC ERR_COR Enable", reg, PCI_DPCCTL_ERRCOREN); 3963 onoff("Poisoned TLP Egress Blocking Enable", reg, 3964 PCI_DPCCTL_POISONTLPEB); 3965 onoff("DPC Software Trigger", reg, PCI_DPCCTL_SWTRIG); 3966 onoff("DL_Active ERR_COR Enable", reg, PCI_DPCCTL_DLACTECOR); 3967 3968 reg = regs[o2i(extcapoff + PCI_DPC_STATESID)]; 3969 stat = reg & 0xffff; 3970 errsrc = reg >> 16; 3971 printf(" DPC Status register: 0x%04x\n", stat); 3972 onoff("DPC Trigger Status", reg, PCI_DPCSTAT_TSTAT); 3973 switch (PCIREG_SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) { 3974 case 0: 3975 trigstr = "an unmasked uncorrectable error"; 3976 break; 3977 case 1: 3978 trigstr = "receiving an ERR_NONFATAL"; 3979 break; 3980 case 2: 3981 trigstr = "receiving an ERR_FATAL"; 3982 break; 3983 case 3: 3984 trigstr = "DPC Trigger Reason Extension field"; 3985 break; 3986 } 3987 printf(" DPC Trigger Reason: Due to %s\n", trigstr); 3988 onoff("DPC Interrupt Status", reg, PCI_DPCSTAT_ISTAT); 3989 if (rpext) 3990 onoff("DPC RP Busy", reg, PCI_DPCSTAT_RPBUSY); 3991 switch (PCIREG_SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) { 3992 case 0: 3993 trigstr = "Due to RP PIO error"; 3994 break; 3995 case 1: 3996 trigstr = "Due to the DPC Software trigger bit"; 3997 break; 3998 default: 3999 trigstr = "(reserved)"; 4000 break; 4001 } 4002 printf(" DPC Trigger Reason Extension: %s\n", trigstr); 4003 if (rpext) 4004 printf(" RP PIO First Error Pointer: 0x%02x\n", 4005 PCIREG_SHIFTOUT(reg, PCI_DPCSTAT_RPPIOFEP)); 4006 printf(" DPC Error Source ID register: 0x%04x\n", errsrc); 4007 4008 if (!rpext) 4009 return; 4010 /* 4011 * All of the following registers are implemented by a device which has 4012 * RP Extensions for DPC 4013 */ 4014 4015 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_STAT)]; 4016 printf(" RP PIO Status Register: 0x%08x\n", reg); 4017 pci_conf_print_dpc_pio(reg); 4018 4019 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_MASK)]; 4020 printf(" RP PIO Mask Register: 0x%08x\n", reg); 4021 pci_conf_print_dpc_pio(reg); 4022 4023 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SEVE)]; 4024 printf(" RP PIO Severity Register: 0x%08x\n", reg); 4025 pci_conf_print_dpc_pio(reg); 4026 4027 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SYSERR)]; 4028 printf(" RP PIO SysError Register: 0x%08x\n", reg); 4029 pci_conf_print_dpc_pio(reg); 4030 4031 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_EXCPT)]; 4032 printf(" RP PIO Exception Register: 0x%08x\n", reg); 4033 pci_conf_print_dpc_pio(reg); 4034 4035 printf(" RP PIO Header Log Register: start from 0x%03x\n", 4036 extcapoff + PCI_DPC_RPPIO_HLOG); 4037 printf(" RP PIO ImpSpec Log Register: start from 0x%03x\n", 4038 extcapoff + PCI_DPC_RPPIO_IMPSLOG); 4039 printf(" RP PIO TLP Prefix Log Register: start from 0x%03x\n", 4040 extcapoff + PCI_DPC_RPPIO_TLPPLOG); 4041 } 4042 4043 4044 static int 4045 pci_conf_l1pm_cap_tposcale(unsigned char scale) 4046 { 4047 4048 /* Return scale in us */ 4049 switch (scale) { 4050 case 0x0: 4051 return 2; 4052 case 0x1: 4053 return 10; 4054 case 0x2: 4055 return 100; 4056 default: 4057 return -1; 4058 } 4059 } 4060 4061 static void 4062 pci_conf_print_l1pm_cap(const pcireg_t *regs, int extcapoff) 4063 { 4064 pcireg_t reg; 4065 int scale, val; 4066 int pcie_capoff; 4067 4068 printf("\n L1 PM Substates\n"); 4069 4070 reg = regs[o2i(extcapoff + PCI_L1PM_CAP)]; 4071 printf(" L1 PM Substates Capability register: 0x%08x\n", reg); 4072 onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12); 4073 onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11); 4074 onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12); 4075 onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11); 4076 onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM); 4077 /* The Link Activation Supported bit is only for Downstream Port */ 4078 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 4079 uint32_t t = regs[o2i(pcie_capoff)]; 4080 4081 if ((t == PCIE_XCAP_TYPE_ROOT) || (t == PCIE_XCAP_TYPE_DOWN)) 4082 onoff("Link Activation Supported", reg, 4083 PCI_L1PM_CAP_LA); 4084 } 4085 printf(" Port Common Mode Restore Time: %uus\n", 4086 PCIREG_SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT)); 4087 scale = pci_conf_l1pm_cap_tposcale( 4088 PCIREG_SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE)); 4089 val = PCIREG_SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL); 4090 printf(" Port T_POWER_ON: "); 4091 if (scale == -1) 4092 printf("unknown\n"); 4093 else 4094 printf("%dus\n", val * scale); 4095 4096 reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)]; 4097 printf(" L1 PM Substates Control register 1: 0x%08x\n", reg); 4098 onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN); 4099 onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN); 4100 onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN); 4101 onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN); 4102 onoff("Link Activation Interrupt Enable", reg, PCI_L1PM_CTL1_LAIE); 4103 onoff("Link Activation Control", reg, PCI_L1PM_CTL1_LA); 4104 printf(" Common Mode Restore Time: %uus\n", 4105 PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT)); 4106 scale = PCI_LTR_SCALETONS(PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE)); 4107 val = PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL); 4108 printf(" LTR L1.2 THRESHOLD: %dus\n", val * scale); 4109 4110 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 4111 printf(" L1 PM Substates Control register 2: 0x%08x\n", reg); 4112 scale = pci_conf_l1pm_cap_tposcale( 4113 PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE)); 4114 val = PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL); 4115 printf(" T_POWER_ON: "); 4116 if (scale == -1) 4117 printf("unknown\n"); 4118 else 4119 printf("%dus\n", val * scale); 4120 4121 if (PCI_EXTCAPLIST_VERSION(regs[o2i(extcapoff)]) >= 2) { 4122 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 4123 printf(" L1 PM Substates Status register: 0x%08x\n", reg); 4124 onoff("Link Activation Status", reg, PCI_L1PM_STAT_LA); 4125 } 4126 } 4127 4128 static void 4129 pci_conf_print_ptm_cap(const pcireg_t *regs, int extcapoff) 4130 { 4131 pcireg_t reg; 4132 uint32_t val; 4133 4134 printf("\n Precision Time Management\n"); 4135 4136 reg = regs[o2i(extcapoff + PCI_PTM_CAP)]; 4137 printf(" PTM Capability register: 0x%08x\n", reg); 4138 onoff("PTM Requester Capable", reg, PCI_PTM_CAP_REQ); 4139 onoff("PTM Responder Capable", reg, PCI_PTM_CAP_RESP); 4140 onoff("PTM Root Capable", reg, PCI_PTM_CAP_ROOT); 4141 printf(" Local Clock Granularity: "); 4142 val = PCIREG_SHIFTOUT(reg, PCI_PTM_CAP_LCLCLKGRNL); 4143 switch (val) { 4144 case 0: 4145 printf("Not implemented\n"); 4146 break; 4147 case 0xffff: 4148 printf("> 254ns\n"); 4149 break; 4150 default: 4151 printf("%uns\n", val); 4152 break; 4153 } 4154 4155 reg = regs[o2i(extcapoff + PCI_PTM_CTL)]; 4156 printf(" PTM Control register: 0x%08x\n", reg); 4157 onoff("PTM Enable", reg, PCI_PTM_CTL_EN); 4158 onoff("Root Select", reg, PCI_PTM_CTL_ROOTSEL); 4159 printf(" Effective Granularity: "); 4160 val = PCIREG_SHIFTOUT(reg, PCI_PTM_CTL_EFCTGRNL); 4161 switch (val) { 4162 case 0: 4163 printf("Unknown\n"); 4164 break; 4165 case 0xffff: 4166 printf("> 254ns\n"); 4167 break; 4168 default: 4169 printf("%uns\n", val); 4170 break; 4171 } 4172 } 4173 4174 /* XXX pci_conf_print_mpcie_cap */ 4175 /* XXX pci_conf_print_frsq_cap */ 4176 /* XXX pci_conf_print_rtr_cap */ 4177 /* XXX pci_conf_print_desigvndsp_cap */ 4178 /* XXX pci_conf_print_vf_resizbar_cap */ 4179 4180 static void 4181 pci_conf_print_dlf_cap(const pcireg_t *regs, int extcapoff) 4182 { 4183 pcireg_t reg; 4184 4185 printf("\n Data link Feature Register\n"); 4186 reg = regs[o2i(extcapoff + PCI_DLF_CAP)]; 4187 printf(" Capability register: 0x%08x\n", reg); 4188 onoff("Scaled Flow Control", reg, PCI_DLF_LFEAT_SCLFCTL); 4189 onoff("DLF Exchange enable", reg, PCI_DLF_CAP_XCHG); 4190 4191 reg = regs[o2i(extcapoff + PCI_DLF_STAT)]; 4192 printf(" Status register: 0x%08x\n", reg); 4193 onoff("Scaled Flow Control", reg, PCI_DLF_LFEAT_SCLFCTL); 4194 onoff("Remote DLF supported Valid", reg, PCI_DLF_STAT_RMTVALID); 4195 } 4196 4197 /* XXX pci_conf_print_hierarchyid_cap */ 4198 /* XXX pci_conf_print_npem_cap */ 4199 4200 #undef MS 4201 #undef SM 4202 #undef RW 4203 4204 static struct { 4205 pcireg_t cap; 4206 const char *name; 4207 void (*printfunc)(const pcireg_t *, int); 4208 } pci_extcaptab[] = { 4209 { 0, "reserved", 4210 NULL }, 4211 { PCI_EXTCAP_AER, "Advanced Error Reporting", 4212 pci_conf_print_aer_cap }, 4213 { PCI_EXTCAP_VC, "Virtual Channel", 4214 pci_conf_print_vc_cap }, 4215 { PCI_EXTCAP_SERNUM, "Device Serial Number", 4216 pci_conf_print_sernum_cap }, 4217 { PCI_EXTCAP_PWRBDGT, "Power Budgeting", 4218 pci_conf_print_pwrbdgt_cap }, 4219 { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration", 4220 pci_conf_print_rclink_dcl_cap }, 4221 { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control", 4222 NULL }, 4223 { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association", 4224 pci_conf_print_rcec_assoc_cap }, 4225 { PCI_EXTCAP_MFVC, "Multi-Function Virtual Channel", 4226 NULL }, 4227 { PCI_EXTCAP_VC2, "Virtual Channel", 4228 NULL }, 4229 { PCI_EXTCAP_RCRB, "RCRB Header", 4230 NULL }, 4231 { PCI_EXTCAP_VENDOR, "Vendor Unique", 4232 NULL }, 4233 { PCI_EXTCAP_CAC, "Configuration Access Correction", 4234 NULL }, 4235 { PCI_EXTCAP_ACS, "Access Control Services", 4236 pci_conf_print_acs_cap }, 4237 { PCI_EXTCAP_ARI, "Alternative Routing-ID Interpretation", 4238 pci_conf_print_ari_cap }, 4239 { PCI_EXTCAP_ATS, "Address Translation Services", 4240 pci_conf_print_ats_cap }, 4241 { PCI_EXTCAP_SRIOV, "Single Root IO Virtualization", 4242 pci_conf_print_sriov_cap }, 4243 { PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization", 4244 NULL }, 4245 { PCI_EXTCAP_MCAST, "Multicast", 4246 pci_conf_print_multicast_cap }, 4247 { PCI_EXTCAP_PAGE_REQ, "Page Request", 4248 pci_conf_print_page_req_cap }, 4249 { PCI_EXTCAP_AMD, "Reserved for AMD", 4250 NULL }, 4251 { PCI_EXTCAP_RESIZBAR, "Resizable BAR", 4252 pci_conf_print_resizbar_cap }, 4253 { PCI_EXTCAP_DPA, "Dynamic Power Allocation", 4254 pci_conf_print_dpa_cap }, 4255 { PCI_EXTCAP_TPH_REQ, "TPH Requester", 4256 pci_conf_print_tph_req_cap }, 4257 { PCI_EXTCAP_LTR, "Latency Tolerance Reporting", 4258 pci_conf_print_ltr_cap }, 4259 { PCI_EXTCAP_SEC_PCIE, "Secondary PCI Express", 4260 pci_conf_print_sec_pcie_cap }, 4261 { PCI_EXTCAP_PMUX, "Protocol Multiplexing", 4262 NULL }, 4263 { PCI_EXTCAP_PASID, "Process Address Space ID", 4264 pci_conf_print_pasid_cap }, 4265 { PCI_EXTCAP_LNR, "LN Requester", 4266 pci_conf_print_lnr_cap }, 4267 { PCI_EXTCAP_DPC, "Downstream Port Containment", 4268 pci_conf_print_dpc_cap }, 4269 { PCI_EXTCAP_L1PM, "L1 PM Substates", 4270 pci_conf_print_l1pm_cap }, 4271 { PCI_EXTCAP_PTM, "Precision Time Management", 4272 pci_conf_print_ptm_cap }, 4273 { PCI_EXTCAP_MPCIE, "M-PCIe", 4274 NULL }, 4275 { PCI_EXTCAP_FRSQ, "Function Reading Status Queueing", 4276 NULL }, 4277 { PCI_EXTCAP_RTR, "Readiness Time Reporting", 4278 NULL }, 4279 { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific", 4280 NULL }, 4281 { PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs", 4282 NULL }, 4283 { PCI_EXTCAP_DLF, "Data link Feature", pci_conf_print_dlf_cap }, 4284 { PCI_EXTCAP_PYSLAY_16GT, "Physical Layer 16.0 GT/s", NULL }, 4285 { 0x27, "unknown", NULL }, 4286 { PCI_EXTCAP_HIERARCHYID, "Hierarchy ID", 4287 NULL }, 4288 { PCI_EXTCAP_NPEM, "Native PCIe Enclosure Management", 4289 NULL }, 4290 }; 4291 4292 static int 4293 pci_conf_find_extcap(const pcireg_t *regs, unsigned int capid, int *offsetp) 4294 { 4295 int off; 4296 pcireg_t rval; 4297 4298 for (off = PCI_EXTCAPLIST_BASE; 4299 off != 0; 4300 off = PCI_EXTCAPLIST_NEXT(rval)) { 4301 rval = regs[o2i(off)]; 4302 if (capid == PCI_EXTCAPLIST_CAP(rval)) { 4303 if (offsetp != NULL) 4304 *offsetp = off; 4305 return 1; 4306 } 4307 } 4308 return 0; 4309 } 4310 4311 static void 4312 pci_conf_print_extcaplist( 4313 #ifdef _KERNEL 4314 pci_chipset_tag_t pc, pcitag_t tag, 4315 #endif 4316 const pcireg_t *regs) 4317 { 4318 int off; 4319 pcireg_t foundcap; 4320 pcireg_t rval; 4321 bool foundtable[__arraycount(pci_extcaptab)]; 4322 unsigned int i; 4323 4324 /* Check Extended capability structure */ 4325 off = PCI_EXTCAPLIST_BASE; 4326 rval = regs[o2i(off)]; 4327 if (rval == 0xffffffff || rval == 0) 4328 return; 4329 4330 /* Clear table */ 4331 for (i = 0; i < __arraycount(pci_extcaptab); i++) 4332 foundtable[i] = false; 4333 4334 /* Print extended capability register's offset and the type first */ 4335 for (;;) { 4336 printf(" Extended Capability Register at 0x%02x\n", off); 4337 4338 foundcap = PCI_EXTCAPLIST_CAP(rval); 4339 printf(" type: 0x%04x (", foundcap); 4340 if (foundcap < __arraycount(pci_extcaptab)) { 4341 printf("%s)\n", pci_extcaptab[foundcap].name); 4342 /* Mark as found */ 4343 foundtable[foundcap] = true; 4344 } else 4345 printf("unknown)\n"); 4346 printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval)); 4347 4348 off = PCI_EXTCAPLIST_NEXT(rval); 4349 if (off == 0) 4350 break; 4351 else if (off <= PCI_CONF_SIZE) { 4352 printf(" next pointer: 0x%03x (incorrect)\n", off); 4353 return; 4354 } 4355 rval = regs[o2i(off)]; 4356 } 4357 4358 /* 4359 * And then, print the detail of each capability registers 4360 * in capability value's order. 4361 */ 4362 for (i = 0; i < __arraycount(pci_extcaptab); i++) { 4363 if (foundtable[i] == false) 4364 continue; 4365 4366 /* 4367 * The type was found. Search capability list again and 4368 * print all capabilities that the capabiliy type is 4369 * the same. 4370 */ 4371 if (pci_conf_find_extcap(regs, i, &off) == 0) 4372 continue; 4373 rval = regs[o2i(off)]; 4374 if ((PCI_EXTCAPLIST_VERSION(rval) <= 0) 4375 || (pci_extcaptab[i].printfunc == NULL)) 4376 continue; 4377 4378 pci_extcaptab[i].printfunc(regs, off); 4379 4380 } 4381 } 4382 4383 /* Print the Secondary Status Register. */ 4384 static void 4385 pci_conf_print_ssr(pcireg_t rval) 4386 { 4387 pcireg_t devsel; 4388 4389 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 4390 onoff("66 MHz capable", rval, __BIT(5)); 4391 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 4392 onoff("Fast back-to-back capable", rval, __BIT(7)); 4393 onoff("Data parity error detected", rval, __BIT(8)); 4394 4395 printf(" DEVSEL timing: "); 4396 devsel = PCIREG_SHIFTOUT(rval, __BITS(10, 9)); 4397 switch (devsel) { 4398 case 0: 4399 printf("fast"); 4400 break; 4401 case 1: 4402 printf("medium"); 4403 break; 4404 case 2: 4405 printf("slow"); 4406 break; 4407 default: 4408 printf("unknown/reserved"); /* XXX */ 4409 break; 4410 } 4411 printf(" (0x%x)\n", devsel); 4412 4413 onoff("Signalled target abort", rval, __BIT(11)); 4414 onoff("Received target abort", rval, __BIT(12)); 4415 onoff("Received master abort", rval, __BIT(13)); 4416 onoff("Received system error", rval, __BIT(14)); 4417 onoff("Detected parity error", rval, __BIT(15)); 4418 } 4419 4420 static void 4421 pci_conf_print_type0( 4422 #ifdef _KERNEL 4423 pci_chipset_tag_t pc, pcitag_t tag, 4424 #endif 4425 const pcireg_t *regs) 4426 { 4427 int off, width; 4428 pcireg_t rval; 4429 const char *str; 4430 4431 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 4432 #ifdef _KERNEL 4433 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 4434 #else 4435 width = pci_conf_print_bar(regs, off, NULL); 4436 #endif 4437 } 4438 4439 printf(" Cardbus CIS Pointer: 0x%08x\n", 4440 regs[o2i(PCI_CARDBUS_CIS_REG)]); 4441 4442 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 4443 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4444 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4445 4446 rval = regs[o2i(PCI_MAPREG_ROM)]; 4447 printf(" Expansion ROM Base Address Register: 0x%08x\n", rval); 4448 printf(" base: 0x%08x\n", (uint32_t)PCI_MAPREG_ROM_ADDR(rval)); 4449 onoff("Expansion ROM Enable", rval, PCI_MAPREG_ROM_ENABLE); 4450 printf(" Validation Status: "); 4451 switch (PCIREG_SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_STAT)) { 4452 case PCI_MAPREG_ROM_VSTAT_NOTSUPP: 4453 str = "Validation not supported"; 4454 break; 4455 case PCI_MAPREG_ROM_VSTAT_INPROG: 4456 str = "Validation in Progress"; 4457 break; 4458 case PCI_MAPREG_ROM_VSTAT_VPASS: 4459 str = "Validation Pass. " 4460 "Valid contents, trust test was not performed"; 4461 break; 4462 case PCI_MAPREG_ROM_VSTAT_VPASSTRUST: 4463 str = "Validation Pass. Valid and trusted contents"; 4464 break; 4465 case PCI_MAPREG_ROM_VSTAT_VFAIL: 4466 str = "Validation Fail. Invalid contents"; 4467 break; 4468 case PCI_MAPREG_ROM_VSTAT_VFAILUNTRUST: 4469 str = "Validation Fail. Valid but untrusted contents"; 4470 break; 4471 case PCI_MAPREG_ROM_VSTAT_WPASS: 4472 str = "Warning Pass. Validation passed with warning. " 4473 "Valid contents, trust test was not performed"; 4474 break; 4475 case PCI_MAPREG_ROM_VSTAT_WPASSTRUST: 4476 str = "Warning Pass. Validation passed with warning. " 4477 "Valid and trusted contents"; 4478 break; 4479 } 4480 printf("%s\n", str); 4481 printf(" Validation Details: 0x%x\n", 4482 PCIREG_SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_DETAIL)); 4483 4484 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4485 printf(" Capability list pointer: 0x%02x\n", 4486 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4487 else 4488 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4489 4490 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 4491 4492 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4493 printf(" Maximum Latency: 0x%02x\n", PCI_MAX_LAT(rval)); 4494 printf(" Minimum Grant: 0x%02x\n", PCI_MIN_GNT(rval)); 4495 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 4496 switch (PCI_INTERRUPT_PIN(rval)) { 4497 case PCI_INTERRUPT_PIN_NONE: 4498 printf("(none)"); 4499 break; 4500 case PCI_INTERRUPT_PIN_A: 4501 printf("(pin A)"); 4502 break; 4503 case PCI_INTERRUPT_PIN_B: 4504 printf("(pin B)"); 4505 break; 4506 case PCI_INTERRUPT_PIN_C: 4507 printf("(pin C)"); 4508 break; 4509 case PCI_INTERRUPT_PIN_D: 4510 printf("(pin D)"); 4511 break; 4512 default: 4513 printf("(? ? ?)"); 4514 break; 4515 } 4516 printf("\n"); 4517 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 4518 } 4519 4520 static void 4521 pci_conf_print_type1( 4522 #ifdef _KERNEL 4523 pci_chipset_tag_t pc, pcitag_t tag, 4524 #endif 4525 const pcireg_t *regs) 4526 { 4527 int off, width; 4528 pcireg_t rval, csreg; 4529 uint32_t base, limit; 4530 uint32_t base_h, limit_h; 4531 uint64_t pbase, plimit; 4532 int use_upper; 4533 4534 /* 4535 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 4536 * Bridge chip documentation, and may not be correct with 4537 * respect to various standards. (XXX) 4538 */ 4539 4540 for (off = 0x10; off < 0x18; off += width) { 4541 #ifdef _KERNEL 4542 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 4543 #else 4544 width = pci_conf_print_bar(regs, off, NULL); 4545 #endif 4546 } 4547 4548 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4549 printf(" Primary bus number: 0x%02x\n", 4550 PCI_BRIDGE_BUS_NUM_PRIMARY(rval)); 4551 printf(" Secondary bus number: 0x%02x\n", 4552 PCI_BRIDGE_BUS_NUM_SECONDARY(rval)); 4553 printf(" Subordinate bus number: 0x%02x\n", 4554 PCI_BRIDGE_BUS_NUM_SUBORDINATE(rval)); 4555 printf(" Secondary bus latency timer: 0x%02x\n", 4556 PCI_BRIDGE_BUS_SEC_LATTIMER_VAL(rval)); 4557 4558 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 4559 pci_conf_print_ssr(PCIREG_SHIFTOUT(rval, __BITS(31, 16))); 4560 4561 /* I/O region */ 4562 printf(" I/O region:\n"); 4563 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 4564 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 4565 if (PCI_BRIDGE_IO_32BITS(rval)) 4566 use_upper = 1; 4567 else 4568 use_upper = 0; 4569 onoff("32bit I/O", rval, use_upper); 4570 base = PCI_BRIDGE_STATIO_IOBASE_ADDR(rval); 4571 limit = PCI_BRIDGE_STATIO_IOLIMIT_ADDR(rval); 4572 4573 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 4574 base_h = PCIREG_SHIFTOUT(rval, PCI_BRIDGE_IOHIGH_BASE); 4575 limit_h = PCIREG_SHIFTOUT(rval, PCI_BRIDGE_IOHIGH_LIMIT); 4576 printf(" base upper 16 bits register: 0x%04x\n", base_h); 4577 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 4578 4579 if (use_upper == 1) { 4580 base |= base_h << 16; 4581 limit |= limit_h << 16; 4582 } 4583 if (base < limit) { 4584 if (use_upper == 1) 4585 printf(" range: 0x%08x-0x%08x\n", base, limit); 4586 else 4587 printf(" range: 0x%04x-0x%04x\n", base, limit); 4588 } else 4589 printf(" range: not set\n"); 4590 4591 /* Non-prefetchable memory region */ 4592 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 4593 printf(" Memory region:\n"); 4594 printf(" base register: 0x%04hx\n", 4595 (uint16_t)PCIREG_SHIFTOUT(rval, PCI_BRIDGE_MEMORY_BASE)); 4596 printf(" limit register: 0x%04hx\n", 4597 (uint16_t)PCIREG_SHIFTOUT(rval, PCI_BRIDGE_MEMORY_LIMIT)); 4598 base = PCI_BRIDGE_MEMORY_BASE_ADDR(rval); 4599 limit = PCI_BRIDGE_MEMORY_LIMIT_ADDR(rval); 4600 if (base < limit) 4601 printf(" range: 0x%08x-0x%08x\n", base, limit); 4602 else 4603 printf(" range: not set\n"); 4604 4605 /* Prefetchable memory region */ 4606 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 4607 printf(" Prefetchable memory region:\n"); 4608 printf(" base register: 0x%04x\n", 4609 (rval >> 0) & 0xffff); 4610 printf(" limit register: 0x%04x\n", 4611 (rval >> 16) & 0xffff); 4612 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASEUP32_REG)]; 4613 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMITUP32_REG)]; 4614 printf(" base upper 32 bits register: 0x%08x\n", 4615 base_h); 4616 printf(" limit upper 32 bits register: 0x%08x\n", 4617 limit_h); 4618 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 4619 use_upper = 1; 4620 else 4621 use_upper = 0; 4622 onoff("64bit memory address", rval, use_upper); 4623 pbase = PCI_BRIDGE_PREFETCHMEM_BASE_ADDR(rval); 4624 plimit = PCI_BRIDGE_PREFETCHMEM_LIMIT_ADDR(rval); 4625 if (use_upper == 1) { 4626 pbase |= (uint64_t)base_h << 32; 4627 plimit |= (uint64_t)limit_h << 32; 4628 } 4629 if (pbase < plimit) { 4630 if (use_upper == 1) 4631 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 4632 "\n", pbase, plimit); 4633 else 4634 printf(" range: 0x%08x-0x%08x\n", 4635 (uint32_t)pbase, (uint32_t)plimit); 4636 } else 4637 printf(" range: not set\n"); 4638 4639 csreg = regs[o2i(PCI_COMMAND_STATUS_REG)]; 4640 if (csreg & PCI_STATUS_CAPLIST_SUPPORT) 4641 printf(" Capability list pointer: 0x%02x\n", 4642 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4643 else 4644 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4645 4646 printf(" Expansion ROM Base Address: 0x%08x\n", 4647 regs[o2i(PCI_BRIDGE_EXPROMADDR_REG)]); 4648 4649 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4650 printf(" Interrupt line: 0x%02x\n", 4651 (rval >> 0) & 0xff); 4652 printf(" Interrupt pin: 0x%02x ", 4653 (rval >> 8) & 0xff); 4654 switch ((rval >> 8) & 0xff) { 4655 case PCI_INTERRUPT_PIN_NONE: 4656 printf("(none)"); 4657 break; 4658 case PCI_INTERRUPT_PIN_A: 4659 printf("(pin A)"); 4660 break; 4661 case PCI_INTERRUPT_PIN_B: 4662 printf("(pin B)"); 4663 break; 4664 case PCI_INTERRUPT_PIN_C: 4665 printf("(pin C)"); 4666 break; 4667 case PCI_INTERRUPT_PIN_D: 4668 printf("(pin D)"); 4669 break; 4670 default: 4671 printf("(? ? ?)"); 4672 break; 4673 } 4674 printf("\n"); 4675 rval = regs[o2i(PCI_BRIDGE_CONTROL_REG)]; 4676 printf(" Bridge control register: 0x%04hx\n", 4677 (uint16_t)PCIREG_SHIFTOUT(rval, PCI_BRIDGE_CONTROL)); 4678 onoff("Parity error response", rval, PCI_BRIDGE_CONTROL_PERE); 4679 onoff("Secondary SERR forwarding", rval, PCI_BRIDGE_CONTROL_SERR); 4680 onoff("ISA enable", rval, PCI_BRIDGE_CONTROL_ISA); 4681 onoff("VGA enable", rval, PCI_BRIDGE_CONTROL_VGA); 4682 /* 4683 * VGA 16bit decode bit has meaning if the VGA enable bit or the 4684 * VGA Palette Snoop Enable bit is set. 4685 */ 4686 if (((rval & PCI_BRIDGE_CONTROL_VGA) != 0) 4687 || ((csreg & PCI_COMMAND_PALETTE_ENABLE) != 0)) 4688 onoff("VGA 16bit enable", rval, PCI_BRIDGE_CONTROL_VGA16); 4689 onoff("Master abort reporting", rval, PCI_BRIDGE_CONTROL_MABRT); 4690 onoff("Secondary bus reset", rval, PCI_BRIDGE_CONTROL_SECBR); 4691 onoff("Fast back-to-back enable", rval, PCI_BRIDGE_CONTROL_SECFASTB2B); 4692 onoff("Primary Discard Timer", rval, 4693 PCI_BRIDGE_CONTROL_PRI_DISC_TIMER); 4694 onoff("Secondary Discard Timer", 4695 rval, PCI_BRIDGE_CONTROL_SEC_DISC_TIMER); 4696 onoff("Discard Timer Status", rval, 4697 PCI_BRIDGE_CONTROL_DISC_TIMER_STAT); 4698 onoff("Discard Timer SERR# Enable", rval, 4699 PCI_BRIDGE_CONTROL_DISC_TIMER_SERR); 4700 } 4701 4702 static void 4703 pci_conf_print_type2( 4704 #ifdef _KERNEL 4705 pci_chipset_tag_t pc, pcitag_t tag, 4706 #endif 4707 const pcireg_t *regs) 4708 { 4709 pcireg_t rval; 4710 4711 /* 4712 * XXX these need to be printed in more detail, need to be 4713 * XXX checked against specs/docs, etc. 4714 * 4715 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 4716 * controller chip documentation, and may not be correct with 4717 * respect to various standards. (XXX) 4718 */ 4719 4720 #ifdef _KERNEL 4721 pci_conf_print_bar(pc, tag, regs, 0x10, 4722 "CardBus socket/ExCA registers"); 4723 #else 4724 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 4725 #endif 4726 4727 /* Capability list pointer and secondary status register */ 4728 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 4729 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4730 printf(" Capability list pointer: 0x%02x\n", 4731 PCI_CAPLIST_PTR(rval)); 4732 else 4733 printf(" Reserved @ 0x14: 0x%04x\n", 4734 PCIREG_SHIFTOUT(rval, __BITS(15, 0))); 4735 pci_conf_print_ssr(PCIREG_SHIFTOUT(rval, __BITS(31, 16))); 4736 4737 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4738 printf(" PCI bus number: 0x%02x\n", 4739 (rval >> 0) & 0xff); 4740 printf(" CardBus bus number: 0x%02x\n", 4741 (rval >> 8) & 0xff); 4742 printf(" Subordinate bus number: 0x%02x\n", 4743 (rval >> 16) & 0xff); 4744 printf(" CardBus latency timer: 0x%02x\n", 4745 (rval >> 24) & 0xff); 4746 4747 /* XXX Print more prettily */ 4748 printf(" CardBus memory region 0:\n"); 4749 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 4750 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 4751 printf(" CardBus memory region 1:\n"); 4752 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 4753 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 4754 printf(" CardBus I/O region 0:\n"); 4755 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 4756 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 4757 printf(" CardBus I/O region 1:\n"); 4758 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 4759 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 4760 4761 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4762 printf(" Interrupt line: 0x%02x\n", 4763 (rval >> 0) & 0xff); 4764 printf(" Interrupt pin: 0x%02x ", 4765 (rval >> 8) & 0xff); 4766 switch ((rval >> 8) & 0xff) { 4767 case PCI_INTERRUPT_PIN_NONE: 4768 printf("(none)"); 4769 break; 4770 case PCI_INTERRUPT_PIN_A: 4771 printf("(pin A)"); 4772 break; 4773 case PCI_INTERRUPT_PIN_B: 4774 printf("(pin B)"); 4775 break; 4776 case PCI_INTERRUPT_PIN_C: 4777 printf("(pin C)"); 4778 break; 4779 case PCI_INTERRUPT_PIN_D: 4780 printf("(pin D)"); 4781 break; 4782 default: 4783 printf("(? ? ?)"); 4784 break; 4785 } 4786 printf("\n"); 4787 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> 16) & 0xffff; 4788 printf(" Bridge control register: 0x%04x\n", rval); 4789 onoff("Parity error response", rval, __BIT(0)); 4790 onoff("SERR# enable", rval, __BIT(1)); 4791 onoff("ISA enable", rval, __BIT(2)); 4792 onoff("VGA enable", rval, __BIT(3)); 4793 onoff("Master abort mode", rval, __BIT(5)); 4794 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 4795 onoff("Functional interrupts routed by ExCA registers", rval, 4796 __BIT(7)); 4797 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 4798 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 4799 onoff("Write posting enable", rval, __BIT(10)); 4800 4801 rval = regs[o2i(0x40)]; 4802 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4803 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4804 4805 #ifdef _KERNEL 4806 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers"); 4807 #else 4808 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 4809 #endif 4810 } 4811 4812 void 4813 pci_conf_print( 4814 #ifdef _KERNEL 4815 pci_chipset_tag_t pc, pcitag_t tag, 4816 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 4817 #else 4818 int pcifd, u_int bus, u_int dev, u_int func 4819 #endif 4820 ) 4821 { 4822 pcireg_t *regs; 4823 int off, capoff, endoff, hdrtype; 4824 const char *type_name; 4825 #ifdef _KERNEL 4826 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *); 4827 #else 4828 void (*type_printfn)(const pcireg_t *); 4829 #endif 4830 4831 regs = MALLOC(PCI_EXTCONF_SIZE); 4832 4833 printf("PCI configuration registers:\n"); 4834 4835 for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) { 4836 #ifdef _KERNEL 4837 regs[o2i(off)] = pci_conf_read(pc, tag, off); 4838 #else 4839 if (pcibus_conf_read(pcifd, bus, dev, func, off, 4840 ®s[o2i(off)]) == -1) 4841 regs[o2i(off)] = 0; 4842 #endif 4843 } 4844 4845 /* common header */ 4846 printf(" Common header:\n"); 4847 pci_conf_print_regs(regs, 0, 16); 4848 4849 printf("\n"); 4850 #ifdef _KERNEL 4851 pci_conf_print_common(pc, tag, regs); 4852 #else 4853 pci_conf_print_common(regs); 4854 #endif 4855 printf("\n"); 4856 4857 /* type-dependent header */ 4858 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 4859 switch (hdrtype) { /* XXX make a table, eventually */ 4860 case 0: 4861 /* Standard device header */ 4862 type_name = "\"normal\" device"; 4863 type_printfn = &pci_conf_print_type0; 4864 capoff = PCI_CAPLISTPTR_REG; 4865 endoff = 64; 4866 break; 4867 case 1: 4868 /* PCI-PCI bridge header */ 4869 type_name = "PCI-PCI bridge"; 4870 type_printfn = &pci_conf_print_type1; 4871 capoff = PCI_CAPLISTPTR_REG; 4872 endoff = 64; 4873 break; 4874 case 2: 4875 /* PCI-CardBus bridge header */ 4876 type_name = "PCI-CardBus bridge"; 4877 type_printfn = &pci_conf_print_type2; 4878 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 4879 endoff = 72; 4880 break; 4881 default: 4882 type_name = NULL; 4883 type_printfn = 0; 4884 capoff = -1; 4885 endoff = 64; 4886 break; 4887 } 4888 printf(" Type %d ", hdrtype); 4889 if (type_name != NULL) 4890 printf("(%s) ", type_name); 4891 printf("header:\n"); 4892 pci_conf_print_regs(regs, 16, endoff); 4893 printf("\n"); 4894 if (type_printfn) { 4895 #ifdef _KERNEL 4896 (*type_printfn)(pc, tag, regs); 4897 #else 4898 (*type_printfn)(regs); 4899 #endif 4900 } else 4901 printf(" Don't know how to pretty-print type %d header.\n", 4902 hdrtype); 4903 printf("\n"); 4904 4905 /* capability list, if present */ 4906 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4907 && (capoff > 0)) { 4908 #ifdef _KERNEL 4909 pci_conf_print_caplist(pc, tag, regs, capoff); 4910 #else 4911 pci_conf_print_caplist(regs, capoff); 4912 #endif 4913 printf("\n"); 4914 } 4915 4916 /* device-dependent header */ 4917 printf(" Device-dependent header:\n"); 4918 pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE); 4919 #ifdef _KERNEL 4920 printf("\n"); 4921 if (printfn) 4922 (*printfn)(pc, tag, regs); 4923 else 4924 printf(" Don't know how to pretty-print device-dependent header.\n"); 4925 #endif /* _KERNEL */ 4926 4927 if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff || 4928 regs[o2i(PCI_EXTCAPLIST_BASE)] == 0) 4929 goto out; 4930 4931 printf("\n"); 4932 #ifdef _KERNEL 4933 pci_conf_print_extcaplist(pc, tag, regs); 4934 #else 4935 pci_conf_print_extcaplist(regs); 4936 #endif 4937 printf("\n"); 4938 4939 /* Extended Configuration Space, if present */ 4940 printf(" Extended Configuration Space:\n"); 4941 pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE); 4942 4943 out: 4944 FREE(regs, PCI_EXTCONF_SIZE); 4945 } 4946