1 /* $NetBSD: pci_subr.c,v 1.31 1998/12/21 20:56:06 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 */ 38 39 #include "opt_pciverbose.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 45 #include <machine/intr.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #ifdef PCIVERBOSE 50 #include <dev/pci/pcidevs.h> 51 #endif 52 53 static void pci_conf_print_common __P((pci_chipset_tag_t, pcitag_t, 54 const pcireg_t *regs)); 55 static void pci_conf_print_bar __P((pci_chipset_tag_t, pcitag_t, 56 const pcireg_t *regs, int, const char *)); 57 static void pci_conf_print_regs __P((const pcireg_t *regs, int first, 58 int pastlast)); 59 static void pci_conf_print_type0 __P((pci_chipset_tag_t, pcitag_t, 60 const pcireg_t *regs)); 61 static void pci_conf_print_type1 __P((pci_chipset_tag_t, pcitag_t, 62 const pcireg_t *regs)); 63 static void pci_conf_print_type2 __P((pci_chipset_tag_t, pcitag_t, 64 const pcireg_t *regs)); 65 66 /* 67 * Descriptions of known PCI classes and subclasses. 68 * 69 * Subclasses are described in the same way as classes, but have a 70 * NULL subclass pointer. 71 */ 72 struct pci_class { 73 char *name; 74 int val; /* as wide as pci_{,sub}class_t */ 75 struct pci_class *subclasses; 76 }; 77 78 struct pci_class pci_subclass_prehistoric[] = { 79 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, }, 80 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, }, 81 { 0 } 82 }; 83 84 struct pci_class pci_subclass_mass_storage[] = { 85 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, }, 86 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, }, 87 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, }, 88 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, }, 89 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, }, 90 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, }, 91 { 0 }, 92 }; 93 94 struct pci_class pci_subclass_network[] = { 95 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, }, 96 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, }, 97 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, }, 98 { "ATM", PCI_SUBCLASS_NETWORK_ATM, }, 99 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, }, 100 { 0 }, 101 }; 102 103 struct pci_class pci_subclass_display[] = { 104 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, }, 105 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, }, 106 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, }, 107 { 0 }, 108 }; 109 110 struct pci_class pci_subclass_multimedia[] = { 111 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, }, 112 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, }, 113 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, }, 114 { 0 }, 115 }; 116 117 struct pci_class pci_subclass_memory[] = { 118 { "RAM", PCI_SUBCLASS_MEMORY_RAM, }, 119 { "flash", PCI_SUBCLASS_MEMORY_FLASH, }, 120 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, }, 121 { 0 }, 122 }; 123 124 struct pci_class pci_subclass_bridge[] = { 125 { "host", PCI_SUBCLASS_BRIDGE_HOST, }, 126 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, }, 127 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, }, 128 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, }, 129 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, }, 130 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, }, 131 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, }, 132 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, }, 133 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, }, 134 { 0 }, 135 }; 136 137 struct pci_class pci_subclass_communications[] = { 138 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, }, 139 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, }, 140 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, }, 141 { 0 }, 142 }; 143 144 struct pci_class pci_subclass_system[] = { 145 { "8259 PIC", PCI_SUBCLASS_SYSTEM_PIC, }, 146 { "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, }, 147 { "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, }, 148 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, }, 149 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, }, 150 { 0 }, 151 }; 152 153 struct pci_class pci_subclass_input[] = { 154 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, }, 155 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, }, 156 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, }, 157 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, }, 158 { 0 }, 159 }; 160 161 struct pci_class pci_subclass_dock[] = { 162 { "generic", PCI_SUBCLASS_DOCK_GENERIC, }, 163 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, }, 164 { 0 }, 165 }; 166 167 struct pci_class pci_subclass_processor[] = { 168 { "386", PCI_SUBCLASS_PROCESSOR_386, }, 169 { "486", PCI_SUBCLASS_PROCESSOR_486, }, 170 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, }, 171 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, }, 172 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, }, 173 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, }, 174 { 0 }, 175 }; 176 177 struct pci_class pci_subclass_serialbus[] = { 178 { "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, }, 179 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, }, 180 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, }, 181 { "USB", PCI_SUBCLASS_SERIALBUS_USB, }, 182 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, }, 183 { 0 }, 184 }; 185 186 struct pci_class pci_class[] = { 187 { "prehistoric", PCI_CLASS_PREHISTORIC, 188 pci_subclass_prehistoric, }, 189 { "mass storage", PCI_CLASS_MASS_STORAGE, 190 pci_subclass_mass_storage, }, 191 { "network", PCI_CLASS_NETWORK, 192 pci_subclass_network, }, 193 { "display", PCI_CLASS_DISPLAY, 194 pci_subclass_display, }, 195 { "multimedia", PCI_CLASS_MULTIMEDIA, 196 pci_subclass_multimedia, }, 197 { "memory", PCI_CLASS_MEMORY, 198 pci_subclass_memory, }, 199 { "bridge", PCI_CLASS_BRIDGE, 200 pci_subclass_bridge, }, 201 { "communications", PCI_CLASS_COMMUNICATIONS, 202 pci_subclass_communications, }, 203 { "system", PCI_CLASS_SYSTEM, 204 pci_subclass_system, }, 205 { "input", PCI_CLASS_INPUT, 206 pci_subclass_input, }, 207 { "dock", PCI_CLASS_DOCK, 208 pci_subclass_dock, }, 209 { "processor", PCI_CLASS_PROCESSOR, 210 pci_subclass_processor, }, 211 { "serial bus", PCI_CLASS_SERIALBUS, 212 pci_subclass_serialbus, }, 213 { "undefined", PCI_CLASS_UNDEFINED, 214 0, }, 215 { 0 }, 216 }; 217 218 #ifdef PCIVERBOSE 219 /* 220 * Descriptions of of known vendors and devices ("products"). 221 */ 222 struct pci_knowndev { 223 pci_vendor_id_t vendor; 224 pci_product_id_t product; 225 int flags; 226 char *vendorname, *productname; 227 }; 228 #define PCI_KNOWNDEV_NOPROD 0x01 /* match on vendor only */ 229 230 #include <dev/pci/pcidevs_data.h> 231 #endif /* PCIVERBOSE */ 232 233 char * 234 pci_findvendor(id_reg) 235 pcireg_t id_reg; 236 { 237 #ifdef PCIVERBOSE 238 pci_vendor_id_t vendor = PCI_VENDOR(id_reg); 239 struct pci_knowndev *kdp; 240 241 kdp = pci_knowndevs; 242 while (kdp->vendorname != NULL) { /* all have vendor name */ 243 if (kdp->vendor == vendor) 244 break; 245 kdp++; 246 } 247 return (kdp->vendorname); 248 #else 249 return (NULL); 250 #endif 251 } 252 253 void 254 pci_devinfo(id_reg, class_reg, showclass, cp) 255 pcireg_t id_reg, class_reg; 256 int showclass; 257 char *cp; 258 { 259 pci_vendor_id_t vendor; 260 pci_product_id_t product; 261 pci_class_t class; 262 pci_subclass_t subclass; 263 pci_interface_t interface; 264 pci_revision_t revision; 265 char *vendor_namep, *product_namep; 266 struct pci_class *classp, *subclassp; 267 #ifdef PCIVERBOSE 268 struct pci_knowndev *kdp; 269 const char *unmatched = "unknown "; 270 #else 271 const char *unmatched = ""; 272 #endif 273 274 vendor = PCI_VENDOR(id_reg); 275 product = PCI_PRODUCT(id_reg); 276 277 class = PCI_CLASS(class_reg); 278 subclass = PCI_SUBCLASS(class_reg); 279 interface = PCI_INTERFACE(class_reg); 280 revision = PCI_REVISION(class_reg); 281 282 #ifdef PCIVERBOSE 283 kdp = pci_knowndevs; 284 while (kdp->vendorname != NULL) { /* all have vendor name */ 285 if (kdp->vendor == vendor && (kdp->product == product || 286 (kdp->flags & PCI_KNOWNDEV_NOPROD) != 0)) 287 break; 288 kdp++; 289 } 290 if (kdp->vendorname == NULL) 291 vendor_namep = product_namep = NULL; 292 else { 293 vendor_namep = kdp->vendorname; 294 product_namep = (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0 ? 295 kdp->productname : NULL; 296 } 297 #else /* PCIVERBOSE */ 298 vendor_namep = product_namep = NULL; 299 #endif /* PCIVERBOSE */ 300 301 classp = pci_class; 302 while (classp->name != NULL) { 303 if (class == classp->val) 304 break; 305 classp++; 306 } 307 308 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 309 while (subclassp && subclassp->name != NULL) { 310 if (subclass == subclassp->val) 311 break; 312 subclassp++; 313 } 314 315 if (vendor_namep == NULL) 316 cp += sprintf(cp, "%svendor 0x%04x product 0x%04x", 317 unmatched, vendor, product); 318 else if (product_namep != NULL) 319 cp += sprintf(cp, "%s %s", vendor_namep, product_namep); 320 else 321 cp += sprintf(cp, "%s product 0x%04x", 322 vendor_namep, product); 323 if (showclass) { 324 cp += sprintf(cp, " ("); 325 if (classp->name == NULL) 326 cp += sprintf(cp, "class 0x%02x, subclass 0x%02x", 327 class, subclass); 328 else { 329 if (subclassp == NULL || subclassp->name == NULL) 330 cp += sprintf(cp, 331 "%s subclass 0x%02x", 332 classp->name, subclass); 333 else 334 cp += sprintf(cp, "%s %s", 335 subclassp->name, classp->name); 336 } 337 if (interface != 0) 338 cp += sprintf(cp, ", interface 0x%02x", interface); 339 if (revision != 0) 340 cp += sprintf(cp, ", revision 0x%02x", revision); 341 cp += sprintf(cp, ")"); 342 } 343 } 344 345 /* 346 * Print out most of the PCI configuration registers. Typically used 347 * in a device attach routine like this: 348 * 349 * #ifdef MYDEV_DEBUG 350 * printf("%s: ", sc->sc_dev.dv_xname); 351 * pci_conf_print(pa->pa_pc, pa->pa_tag); 352 * #endif 353 */ 354 355 #define i2o(i) ((i) * 4) 356 #define o2i(o) ((o) / 4) 357 #define onoff(str, bit) \ 358 printf(" %s: %s\n", (str), (rval & (bit)) ? "on" : "off"); 359 360 static void 361 pci_conf_print_common(pc, tag, regs) 362 pci_chipset_tag_t pc; 363 pcitag_t tag; 364 const pcireg_t *regs; 365 { 366 #ifdef PCIVERBOSE 367 struct pci_knowndev *kdp; 368 #endif 369 struct pci_class *classp, *subclassp; 370 pcireg_t rval; 371 372 rval = regs[o2i(PCI_ID_REG)]; 373 #ifndef PCIVERBOSE 374 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 375 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 376 #else 377 for (kdp = pci_knowndevs; kdp->vendorname != NULL; kdp++) { 378 if (kdp->vendor == PCI_VENDOR(rval) && 379 (kdp->product == PCI_PRODUCT(rval) || 380 (kdp->flags & PCI_KNOWNDEV_NOPROD) != 0)) { 381 break; 382 } 383 } 384 if (kdp->vendorname != NULL) 385 printf(" Vendor Name: %s (0x%04x)\n", kdp->vendorname, 386 PCI_VENDOR(rval)); 387 else 388 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 389 if (kdp->productname != NULL && (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0) 390 printf(" Device Name: %s (0x%04x)\n", kdp->productname, 391 PCI_PRODUCT(rval)); 392 else 393 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 394 #endif /* PCIVERBOSE */ 395 396 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 397 398 printf(" Command register: 0x%04x\n", rval & 0xffff); 399 onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE); 400 onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE); 401 onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE); 402 onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE); 403 onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE); 404 onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE); 405 onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE); 406 onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE); 407 onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE); 408 onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE); 409 410 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 411 onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT); 412 onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT); 413 onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT); 414 onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR); 415 416 printf(" DEVSEL timing: "); 417 switch (rval & PCI_STATUS_DEVSEL_MASK) { 418 case PCI_STATUS_DEVSEL_FAST: 419 printf("fast"); 420 break; 421 case PCI_STATUS_DEVSEL_MEDIUM: 422 printf("medium"); 423 break; 424 case PCI_STATUS_DEVSEL_SLOW: 425 printf("slow"); 426 break; 427 default: 428 printf("unknown/reserved"); /* XXX */ 429 break; 430 } 431 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 432 433 onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT); 434 onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT); 435 onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT); 436 onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR); 437 onoff("Parity error detected", PCI_STATUS_PARITY_DETECT); 438 439 rval = regs[o2i(PCI_CLASS_REG)]; 440 for (classp = pci_class; classp->name != NULL; classp++) { 441 if (PCI_CLASS(rval) == classp->val) 442 break; 443 } 444 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 445 while (subclassp && subclassp->name != NULL) { 446 if (PCI_SUBCLASS(rval) == subclassp->val) 447 break; 448 subclassp++; 449 } 450 if (classp->name != NULL) { 451 printf(" Class Name: %s (0x%02x)\n", classp->name, 452 PCI_CLASS(rval)); 453 if (subclassp != NULL && subclassp->name != NULL) 454 printf(" Subclass Name: %s (0x%02x)\n", 455 subclassp->name, PCI_SUBCLASS(rval)); 456 else 457 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 458 } else { 459 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 460 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 461 } 462 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 463 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 464 465 rval = regs[o2i(PCI_BHLC_REG)]; 466 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 467 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 468 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 469 PCI_HDRTYPE(rval)); 470 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 471 printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval)); 472 } 473 474 static void 475 pci_conf_print_bar(pc, tag, regs, reg, name) 476 pci_chipset_tag_t pc; 477 pcitag_t tag; 478 const pcireg_t *regs; 479 int reg; 480 const char *name; 481 { 482 int s; 483 pcireg_t mask, rval; 484 485 /* 486 * Section 6.2.5.1, `Address Maps', tells us that: 487 * 488 * 1) The builtin software should have already mapped the 489 * device in a reasonable way. 490 * 491 * 2) A device which wants 2^n bytes of memory will hardwire 492 * the bottom n bits of the address to 0. As recommended, 493 * we write all 1s and see what we get back. 494 */ 495 rval = regs[o2i(reg)]; 496 if (rval != 0) { 497 /* 498 * The following sequence seems to make some devices 499 * (e.g. host bus bridges, which don't normally 500 * have their space mapped) very unhappy, to 501 * the point of crashing the system. 502 * 503 * Therefore, if the mapping register is zero to 504 * start out with, don't bother trying. 505 */ 506 s = splhigh(); 507 pci_conf_write(pc, tag, reg, 0xffffffff); 508 mask = pci_conf_read(pc, tag, reg); 509 pci_conf_write(pc, tag, reg, rval); 510 splx(s); 511 } else 512 mask = 0; 513 514 printf(" Base address register at 0x%02x", reg); 515 if (name) 516 printf(" (%s)", name); 517 printf("\n "); 518 if (rval == 0) { 519 printf("not implemented(?)\n"); 520 return; 521 } 522 printf("type: "); 523 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 524 const char *type, *cache; 525 526 switch (PCI_MAPREG_MEM_TYPE(rval)) { 527 case PCI_MAPREG_MEM_TYPE_32BIT: 528 type = "32-bit"; 529 break; 530 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 531 type = "32-bit-1M"; 532 break; 533 case PCI_MAPREG_MEM_TYPE_64BIT: 534 type = "64-bit"; 535 break; 536 default: 537 type = "unknown (XXX)"; 538 break; 539 } 540 if (PCI_MAPREG_MEM_CACHEABLE(rval)) 541 cache = ""; 542 else 543 cache = "non"; 544 printf("%s %scacheable memory\n", type, cache); 545 printf(" base: 0x%08x, size: 0x%08x\n", 546 PCI_MAPREG_MEM_ADDR(rval), 547 PCI_MAPREG_MEM_SIZE(mask)); 548 } else { 549 printf("i/o\n"); 550 printf(" base: 0x%08x, size: 0x%08x\n", 551 PCI_MAPREG_IO_ADDR(rval), 552 PCI_MAPREG_IO_SIZE(mask)); 553 } 554 } 555 556 static void 557 pci_conf_print_regs(regs, first, pastlast) 558 const pcireg_t *regs; 559 int first, pastlast; 560 { 561 int off, needaddr, neednl; 562 563 needaddr = 1; 564 neednl = 0; 565 for (off = first; off < pastlast; off += 4) { 566 if ((off % 16) == 0 || needaddr) { 567 printf(" 0x%02x:", off); 568 needaddr = 0; 569 } 570 printf(" 0x%08x", regs[o2i(off)]); 571 neednl = 1; 572 if ((off % 16) == 12) { 573 printf("\n"); 574 neednl = 0; 575 } 576 } 577 if (neednl) 578 printf("\n"); 579 } 580 581 static void 582 pci_conf_print_type0(pc, tag, regs) 583 pci_chipset_tag_t pc; 584 pcitag_t tag; 585 const pcireg_t *regs; 586 { 587 int off; 588 pcireg_t rval; 589 590 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += 4) 591 pci_conf_print_bar(pc, tag, regs, off, NULL); 592 593 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 594 595 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 596 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 597 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 598 599 /* XXX */ 600 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 601 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 602 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 603 604 rval = regs[o2i(PCI_INTERRUPT_REG)]; 605 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 606 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 607 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 608 switch (PCI_INTERRUPT_PIN(rval)) { 609 case PCI_INTERRUPT_PIN_NONE: 610 printf("(none)"); 611 break; 612 case PCI_INTERRUPT_PIN_A: 613 printf("(pin A)"); 614 break; 615 case PCI_INTERRUPT_PIN_B: 616 printf("(pin B)"); 617 break; 618 case PCI_INTERRUPT_PIN_C: 619 printf("(pin C)"); 620 break; 621 case PCI_INTERRUPT_PIN_D: 622 printf("(pin D)"); 623 break; 624 default: 625 printf("(???)"); 626 break; 627 } 628 printf("\n"); 629 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 630 } 631 632 static void 633 pci_conf_print_type1(pc, tag, regs) 634 pci_chipset_tag_t pc; 635 pcitag_t tag; 636 const pcireg_t *regs; 637 { 638 int off; 639 pcireg_t rval; 640 641 /* 642 * XXX these need to be printed in more detail, need to be 643 * XXX checked against specs/docs, etc. 644 * 645 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 646 * Bridge chip documentation, and may not be correct with 647 * respect to various standards. (XXX) 648 */ 649 650 for (off = 0x10; off < 0x18; off += 4) 651 pci_conf_print_bar(pc, tag, regs, off, NULL); 652 653 printf(" Primary bus number: 0x%02x\n", 654 (regs[o2i(0x18)] >> 0) & 0xff); 655 printf(" Secondary bus number: 0x%02x\n", 656 (regs[o2i(0x18)] >> 8) & 0xff); 657 printf(" Subordinate bus number: 0x%02x\n", 658 (regs[o2i(0x18)] >> 16) & 0xff); 659 printf(" Secondary bus latency timer: 0x%02x\n", 660 (regs[o2i(0x18)] >> 24) & 0xff); 661 662 rval = (regs[o2i(0x1c)] >> 16) & 0xffff; 663 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 664 onoff("66 MHz capable", 0x0020); 665 onoff("User Definable Features (UDF) support", 0x0040); 666 onoff("Fast back-to-back capable", 0x0080); 667 onoff("Data parity error detected", 0x0100); 668 669 printf(" DEVSEL timing: "); 670 switch (rval & 0x0600) { 671 case 0x0000: 672 printf("fast"); 673 break; 674 case 0x0200: 675 printf("medium"); 676 break; 677 case 0x0400: 678 printf("slow"); 679 break; 680 default: 681 printf("unknown/reserved"); /* XXX */ 682 break; 683 } 684 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 685 686 onoff("Signaled Target Abort", 0x0800); 687 onoff("Received Target Abort", 0x1000); 688 onoff("Received Master Abort", 0x2000); 689 onoff("System Error", 0x4000); 690 onoff("Parity Error", 0x8000); 691 692 /* XXX Print more prettily */ 693 printf(" I/O region:\n"); 694 printf(" base register: 0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff); 695 printf(" limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff); 696 printf(" base upper 16 bits register: 0x%04x\n", 697 (regs[o2i(0x30)] >> 0) & 0xffff); 698 printf(" limit upper 16 bits register: 0x%04x\n", 699 (regs[o2i(0x30)] >> 16) & 0xffff); 700 701 /* XXX Print more prettily */ 702 printf(" Memory region:\n"); 703 printf(" base register: 0x%04x\n", 704 (regs[o2i(0x20)] >> 0) & 0xffff); 705 printf(" limit register: 0x%04x\n", 706 (regs[o2i(0x20)] >> 16) & 0xffff); 707 708 /* XXX Print more prettily */ 709 printf(" Prefetchable memory region:\n"); 710 printf(" base register: 0x%04x\n", 711 (regs[o2i(0x24)] >> 0) & 0xffff); 712 printf(" limit register: 0x%04x\n", 713 (regs[o2i(0x24)] >> 16) & 0xffff); 714 printf(" base upper 32 bits register: 0x%08x\n", regs[o2i(0x28)]); 715 printf(" limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]); 716 717 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 718 /* XXX */ 719 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 720 721 printf(" Interrupt line: 0x%02x\n", 722 (regs[o2i(0x3c)] >> 0) & 0xff); 723 printf(" Interrupt pin: 0x%02x ", 724 (regs[o2i(0x3c)] >> 8) & 0xff); 725 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 726 case PCI_INTERRUPT_PIN_NONE: 727 printf("(none)"); 728 break; 729 case PCI_INTERRUPT_PIN_A: 730 printf("(pin A)"); 731 break; 732 case PCI_INTERRUPT_PIN_B: 733 printf("(pin B)"); 734 break; 735 case PCI_INTERRUPT_PIN_C: 736 printf("(pin C)"); 737 break; 738 case PCI_INTERRUPT_PIN_D: 739 printf("(pin D)"); 740 break; 741 default: 742 printf("(???)"); 743 break; 744 } 745 printf("\n"); 746 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 747 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 748 onoff("Parity error response", 0x0001); 749 onoff("Secondary SERR forwarding", 0x0002); 750 onoff("ISA enable", 0x0004); 751 onoff("VGA enable", 0x0008); 752 onoff("Master abort reporting", 0x0020); 753 onoff("Secondary bus reset", 0x0040); 754 onoff("Fast back-to-back capable", 0x0080); 755 } 756 757 static void 758 pci_conf_print_type2(pc, tag, regs) 759 pci_chipset_tag_t pc; 760 pcitag_t tag; 761 const pcireg_t *regs; 762 { 763 pcireg_t rval; 764 765 /* 766 * XXX these need to be printed in more detail, need to be 767 * XXX checked against specs/docs, etc. 768 * 769 * This layout was cribbed from the TI PCI1130 PCI-to-CardBus 770 * controller chip documentation, and may not be correct with 771 * respect to various standards. (XXX) 772 */ 773 774 pci_conf_print_bar(pc, tag, regs, 0x10, 775 "CardBus socket/ExCA registers"); 776 777 printf(" Reserved @ 0x14: 0x%04x\n", 778 (regs[o2i(0x14)] >> 0) & 0xffff); 779 rval = (regs[o2i(0x14)] >> 16) & 0xffff; 780 printf(" Secondary status register: 0x%04x\n", rval); 781 onoff("66 MHz capable", 0x0020); 782 onoff("User Definable Features (UDF) support", 0x0040); 783 onoff("Fast back-to-back capable", 0x0080); 784 onoff("Data parity error detection", 0x0100); 785 786 printf(" DEVSEL timing: "); 787 switch (rval & 0x0600) { 788 case 0x0000: 789 printf("fast"); 790 break; 791 case 0x0200: 792 printf("medium"); 793 break; 794 case 0x0400: 795 printf("slow"); 796 break; 797 default: 798 printf("unknown/reserved"); /* XXX */ 799 break; 800 } 801 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 802 onoff("PCI target aborts terminate CardBus bus master transactions", 803 0x0800); 804 onoff("CardBus target aborts terminate PCI bus master transactions", 805 0x1000); 806 onoff("Bus initiator aborts terminate initiator transactions", 807 0x2000); 808 onoff("System error", 0x4000); 809 onoff("Parity error", 0x8000); 810 811 printf(" PCI bus number: 0x%02x\n", 812 (regs[o2i(0x18)] >> 0) & 0xff); 813 printf(" CardBus bus number: 0x%02x\n", 814 (regs[o2i(0x18)] >> 8) & 0xff); 815 printf(" Subordinate bus number: 0x%02x\n", 816 (regs[o2i(0x18)] >> 16) & 0xff); 817 printf(" CardBus latency timer: 0x%02x\n", 818 (regs[o2i(0x18)] >> 24) & 0xff); 819 820 /* XXX Print more prettily */ 821 printf(" CardBus memory region 0:\n"); 822 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 823 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 824 printf(" CardBus memory region 1:\n"); 825 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 826 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 827 printf(" CardBus I/O region 0:\n"); 828 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 829 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 830 printf(" CardBus I/O region 1:\n"); 831 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 832 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 833 834 printf(" Interrupt line: 0x%02x\n", 835 (regs[o2i(0x3c)] >> 0) & 0xff); 836 printf(" Interrupt pin: 0x%02x ", 837 (regs[o2i(0x3c)] >> 8) & 0xff); 838 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 839 case PCI_INTERRUPT_PIN_NONE: 840 printf("(none)"); 841 break; 842 case PCI_INTERRUPT_PIN_A: 843 printf("(pin A)"); 844 break; 845 case PCI_INTERRUPT_PIN_B: 846 printf("(pin B)"); 847 break; 848 case PCI_INTERRUPT_PIN_C: 849 printf("(pin C)"); 850 break; 851 case PCI_INTERRUPT_PIN_D: 852 printf("(pin D)"); 853 break; 854 default: 855 printf("(???)"); 856 break; 857 } 858 printf("\n"); 859 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 860 printf(" Bridge control register: 0x%04x\n", rval); 861 onoff("Parity error response", 0x0001); 862 onoff("CardBus SERR forwarding", 0x0002); 863 onoff("ISA enable", 0x0004); 864 onoff("VGA enable", 0x0008); 865 onoff("CardBus master abort reporting", 0x0020); 866 onoff("CardBus reset", 0x0040); 867 onoff("Functional interrupts routed by ExCA registers", 0x0080); 868 onoff("Memory window 0 prefetchable", 0x0100); 869 onoff("Memory window 1 prefetchable", 0x0200); 870 onoff("Write posting enable", 0x0400); 871 872 rval = regs[o2i(0x40)]; 873 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 874 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 875 876 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers"); 877 } 878 879 void 880 pci_conf_print(pc, tag, printfn) 881 pci_chipset_tag_t pc; 882 pcitag_t tag; 883 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *); 884 { 885 pcireg_t regs[o2i(256)]; 886 int off, endoff, hdrtype; 887 const char *typename; 888 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *); 889 890 printf("PCI configuration registers:\n"); 891 892 for (off = 0; off < 256; off += 4) 893 regs[o2i(off)] = pci_conf_read(pc, tag, off); 894 895 /* common header */ 896 printf(" Common header:\n"); 897 pci_conf_print_regs(regs, 0, 16); 898 899 printf("\n"); 900 pci_conf_print_common(pc, tag, regs); 901 printf("\n"); 902 903 /* type-dependent header */ 904 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 905 switch (hdrtype) { /* XXX make a table, eventually */ 906 case 0: 907 /* Standard device header */ 908 typename = "\"normal\" device"; 909 typeprintfn = &pci_conf_print_type0; 910 endoff = 64; 911 break; 912 case 1: 913 /* PCI-PCI bridge header */ 914 typename = "PCI-PCI bridge"; 915 typeprintfn = &pci_conf_print_type1; 916 endoff = 64; 917 break; 918 case 2: 919 /* PCI-CardBus bridge header */ 920 typename = "PCI-CardBus bridge"; 921 typeprintfn = &pci_conf_print_type2; 922 endoff = 72; 923 break; 924 default: 925 typename = NULL; 926 typeprintfn = 0; 927 endoff = 64; 928 break; 929 } 930 printf(" Type %d ", hdrtype); 931 if (typename != NULL) 932 printf("(%s) ", typename); 933 printf("header:\n"); 934 pci_conf_print_regs(regs, 16, endoff); 935 printf("\n"); 936 if (typeprintfn) 937 (*typeprintfn)(pc, tag, regs); 938 else 939 printf(" Don't know how to pretty-print type %d header.\n", 940 hdrtype); 941 printf("\n"); 942 943 /* device-dependent header */ 944 printf(" Device-dependent header:\n"); 945 pci_conf_print_regs(regs, endoff, 256); 946 printf("\n"); 947 if (printfn) 948 (*printfn)(pc, tag, regs); 949 else 950 printf(" Don't know how to pretty-print device-dependent header.\n"); 951 printf("\n"); 952 } 953