1 /* $NetBSD: pci_subr.c,v 1.53 2002/09/21 19:14:14 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.53 2002/09/21 19:14:14 drochner Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 52 #ifdef _KERNEL 53 #include <machine/intr.h> 54 #else 55 #include <pci.h> 56 #include <stdio.h> 57 #endif 58 59 #include <dev/pci/pcireg.h> 60 #ifdef _KERNEL 61 #include <dev/pci/pcivar.h> 62 #endif 63 #ifdef PCIVERBOSE 64 #include <dev/pci/pcidevs.h> 65 #endif 66 67 /* 68 * Descriptions of known PCI classes and subclasses. 69 * 70 * Subclasses are described in the same way as classes, but have a 71 * NULL subclass pointer. 72 */ 73 struct pci_class { 74 const char *name; 75 int val; /* as wide as pci_{,sub}class_t */ 76 const struct pci_class *subclasses; 77 }; 78 79 const struct pci_class pci_subclass_prehistoric[] = { 80 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, }, 81 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, }, 82 { 0 } 83 }; 84 85 const struct pci_class pci_subclass_mass_storage[] = { 86 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, }, 87 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, }, 88 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, }, 89 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, }, 90 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, }, 91 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, }, 92 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, }, 93 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, }, 94 { 0 }, 95 }; 96 97 const struct pci_class pci_subclass_network[] = { 98 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, }, 99 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, }, 100 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, }, 101 { "ATM", PCI_SUBCLASS_NETWORK_ATM, }, 102 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, }, 103 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, }, 104 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, }, 105 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, }, 106 { 0 }, 107 }; 108 109 const struct pci_class pci_subclass_display[] = { 110 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, }, 111 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, }, 112 { "3D", PCI_SUBCLASS_DISPLAY_3D, }, 113 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, }, 114 { 0 }, 115 }; 116 117 const struct pci_class pci_subclass_multimedia[] = { 118 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, }, 119 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, }, 120 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, }, 121 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, }, 122 { 0 }, 123 }; 124 125 const struct pci_class pci_subclass_memory[] = { 126 { "RAM", PCI_SUBCLASS_MEMORY_RAM, }, 127 { "flash", PCI_SUBCLASS_MEMORY_FLASH, }, 128 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, }, 129 { 0 }, 130 }; 131 132 const struct pci_class pci_subclass_bridge[] = { 133 { "host", PCI_SUBCLASS_BRIDGE_HOST, }, 134 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, }, 135 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, }, 136 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, }, 137 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, }, 138 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, }, 139 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, }, 140 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, }, 141 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, }, 142 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, }, 143 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, }, 144 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, }, 145 { 0 }, 146 }; 147 148 const struct pci_class pci_subclass_communications[] = { 149 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, }, 150 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, }, 151 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, }, 152 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, }, 153 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, }, 154 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, }, 155 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, }, 156 { 0 }, 157 }; 158 159 const struct pci_class pci_subclass_system[] = { 160 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, }, 161 { "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, }, 162 { "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, }, 163 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, }, 164 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_RTC, }, 165 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, }, 166 { 0 }, 167 }; 168 169 const struct pci_class pci_subclass_input[] = { 170 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, }, 171 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, }, 172 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, }, 173 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, }, 174 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, }, 175 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, }, 176 { 0 }, 177 }; 178 179 const struct pci_class pci_subclass_dock[] = { 180 { "generic", PCI_SUBCLASS_DOCK_GENERIC, }, 181 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, }, 182 { 0 }, 183 }; 184 185 const struct pci_class pci_subclass_processor[] = { 186 { "386", PCI_SUBCLASS_PROCESSOR_386, }, 187 { "486", PCI_SUBCLASS_PROCESSOR_486, }, 188 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, }, 189 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, }, 190 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, }, 191 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, }, 192 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, }, 193 { 0 }, 194 }; 195 196 const struct pci_class pci_subclass_serialbus[] = { 197 { "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, }, 198 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, }, 199 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, }, 200 { "USB", PCI_SUBCLASS_SERIALBUS_USB, }, 201 /* XXX Fiber Channel/_FIBRECHANNEL */ 202 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, }, 203 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, }, 204 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, }, 205 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, }, 206 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, }, 207 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, }, 208 { 0 }, 209 }; 210 211 const struct pci_class pci_subclass_wireless[] = { 212 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, }, 213 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, }, 214 { "RF", PCI_SUBCLASS_WIRELESS_RF, }, 215 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, }, 216 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, }, 217 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, }, 218 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, }, 219 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, }, 220 { 0 }, 221 }; 222 223 const struct pci_class pci_subclass_i2o[] = { 224 { "standard", PCI_SUBCLASS_I2O_STANDARD, }, 225 { 0 }, 226 }; 227 228 const struct pci_class pci_subclass_satcom[] = { 229 { "TV", PCI_SUBCLASS_SATCOM_TV, }, 230 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, }, 231 { "voice", PCI_SUBCLASS_SATCOM_VOICE, }, 232 { "data", PCI_SUBCLASS_SATCOM_DATA, }, 233 { 0 }, 234 }; 235 236 const struct pci_class pci_subclass_crypto[] = { 237 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, }, 238 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, }, 239 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, }, 240 { 0 }, 241 }; 242 243 const struct pci_class pci_subclass_dasp[] = { 244 { "DPIO", PCI_SUBCLASS_DASP_DPIO, }, 245 { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, }, 246 { "synchronization", PCI_SUBCLASS_DASP_SYNC, }, 247 { "management", PCI_SUBCLASS_DASP_MGMT, }, 248 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, }, 249 { 0 }, 250 }; 251 252 const struct pci_class pci_class[] = { 253 { "prehistoric", PCI_CLASS_PREHISTORIC, 254 pci_subclass_prehistoric, }, 255 { "mass storage", PCI_CLASS_MASS_STORAGE, 256 pci_subclass_mass_storage, }, 257 { "network", PCI_CLASS_NETWORK, 258 pci_subclass_network, }, 259 { "display", PCI_CLASS_DISPLAY, 260 pci_subclass_display, }, 261 { "multimedia", PCI_CLASS_MULTIMEDIA, 262 pci_subclass_multimedia, }, 263 { "memory", PCI_CLASS_MEMORY, 264 pci_subclass_memory, }, 265 { "bridge", PCI_CLASS_BRIDGE, 266 pci_subclass_bridge, }, 267 { "communications", PCI_CLASS_COMMUNICATIONS, 268 pci_subclass_communications, }, 269 { "system", PCI_CLASS_SYSTEM, 270 pci_subclass_system, }, 271 { "input", PCI_CLASS_INPUT, 272 pci_subclass_input, }, 273 { "dock", PCI_CLASS_DOCK, 274 pci_subclass_dock, }, 275 { "processor", PCI_CLASS_PROCESSOR, 276 pci_subclass_processor, }, 277 { "serial bus", PCI_CLASS_SERIALBUS, 278 pci_subclass_serialbus, }, 279 { "wireless", PCI_CLASS_WIRELESS, 280 pci_subclass_wireless, }, 281 { "I2O", PCI_CLASS_I2O, 282 pci_subclass_i2o, }, 283 { "satellite comm", PCI_CLASS_SATCOM, 284 pci_subclass_satcom, }, 285 { "crypto", PCI_CLASS_CRYPTO, 286 pci_subclass_crypto, }, 287 { "DASP", PCI_CLASS_DASP, 288 pci_subclass_dasp, }, 289 { "undefined", PCI_CLASS_UNDEFINED, 290 0, }, 291 { 0 }, 292 }; 293 294 #ifdef PCIVERBOSE 295 /* 296 * Descriptions of of known vendors and devices ("products"). 297 */ 298 struct pci_knowndev { 299 pci_vendor_id_t vendor; 300 pci_product_id_t product; 301 int flags; 302 char *vendorname, *productname; 303 }; 304 #define PCI_KNOWNDEV_NOPROD 0x01 /* match on vendor only */ 305 306 #include <dev/pci/pcidevs_data.h> 307 #endif /* PCIVERBOSE */ 308 309 char * 310 pci_findvendor(pcireg_t id_reg) 311 { 312 #ifdef PCIVERBOSE 313 pci_vendor_id_t vendor = PCI_VENDOR(id_reg); 314 const struct pci_knowndev *kdp; 315 316 kdp = pci_knowndevs; 317 while (kdp->vendorname != NULL) { /* all have vendor name */ 318 if (kdp->vendor == vendor) 319 break; 320 kdp++; 321 } 322 return (kdp->vendorname); 323 #else 324 return (NULL); 325 #endif 326 } 327 328 void 329 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp) 330 { 331 pci_vendor_id_t vendor; 332 pci_product_id_t product; 333 pci_class_t class; 334 pci_subclass_t subclass; 335 pci_interface_t interface; 336 pci_revision_t revision; 337 char *vendor_namep, *product_namep; 338 const struct pci_class *classp, *subclassp; 339 #ifdef PCIVERBOSE 340 const struct pci_knowndev *kdp; 341 const char *unmatched = "unknown "; 342 #else 343 const char *unmatched = ""; 344 #endif 345 346 vendor = PCI_VENDOR(id_reg); 347 product = PCI_PRODUCT(id_reg); 348 349 class = PCI_CLASS(class_reg); 350 subclass = PCI_SUBCLASS(class_reg); 351 interface = PCI_INTERFACE(class_reg); 352 revision = PCI_REVISION(class_reg); 353 354 #ifdef PCIVERBOSE 355 kdp = pci_knowndevs; 356 while (kdp->vendorname != NULL) { /* all have vendor name */ 357 if (kdp->vendor == vendor && (kdp->product == product || 358 (kdp->flags & PCI_KNOWNDEV_NOPROD) != 0)) 359 break; 360 kdp++; 361 } 362 if (kdp->vendorname == NULL) 363 vendor_namep = product_namep = NULL; 364 else { 365 vendor_namep = kdp->vendorname; 366 product_namep = (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0 ? 367 kdp->productname : NULL; 368 } 369 #else /* PCIVERBOSE */ 370 vendor_namep = product_namep = NULL; 371 #endif /* PCIVERBOSE */ 372 373 classp = pci_class; 374 while (classp->name != NULL) { 375 if (class == classp->val) 376 break; 377 classp++; 378 } 379 380 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 381 while (subclassp && subclassp->name != NULL) { 382 if (subclass == subclassp->val) 383 break; 384 subclassp++; 385 } 386 387 if (vendor_namep == NULL) 388 cp += sprintf(cp, "%svendor 0x%04x product 0x%04x", 389 unmatched, vendor, product); 390 else if (product_namep != NULL) 391 cp += sprintf(cp, "%s %s", vendor_namep, product_namep); 392 else 393 cp += sprintf(cp, "%s product 0x%04x", 394 vendor_namep, product); 395 if (showclass) { 396 cp += sprintf(cp, " ("); 397 if (classp->name == NULL) 398 cp += sprintf(cp, "class 0x%02x, subclass 0x%02x", 399 class, subclass); 400 else { 401 if (subclassp == NULL || subclassp->name == NULL) 402 cp += sprintf(cp, 403 "%s subclass 0x%02x", 404 classp->name, subclass); 405 else 406 cp += sprintf(cp, "%s %s", 407 subclassp->name, classp->name); 408 } 409 if (interface != 0) 410 cp += sprintf(cp, ", interface 0x%02x", interface); 411 if (revision != 0) 412 cp += sprintf(cp, ", revision 0x%02x", revision); 413 cp += sprintf(cp, ")"); 414 } 415 } 416 417 /* 418 * Print out most of the PCI configuration registers. Typically used 419 * in a device attach routine like this: 420 * 421 * #ifdef MYDEV_DEBUG 422 * printf("%s: ", sc->sc_dev.dv_xname); 423 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 424 * #endif 425 */ 426 427 #define i2o(i) ((i) * 4) 428 #define o2i(o) ((o) / 4) 429 #define onoff(str, bit) \ 430 printf(" %s: %s\n", (str), (rval & (bit)) ? "on" : "off"); 431 432 static void 433 pci_conf_print_common( 434 #ifdef _KERNEL 435 pci_chipset_tag_t pc, pcitag_t tag, 436 #endif 437 const pcireg_t *regs) 438 { 439 #ifdef PCIVERBOSE 440 const struct pci_knowndev *kdp; 441 #endif 442 const struct pci_class *classp, *subclassp; 443 pcireg_t rval; 444 445 rval = regs[o2i(PCI_ID_REG)]; 446 #ifndef PCIVERBOSE 447 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 448 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 449 #else 450 for (kdp = pci_knowndevs; kdp->vendorname != NULL; kdp++) { 451 if (kdp->vendor == PCI_VENDOR(rval) && 452 (kdp->product == PCI_PRODUCT(rval) || 453 (kdp->flags & PCI_KNOWNDEV_NOPROD) != 0)) { 454 break; 455 } 456 } 457 if (kdp->vendorname != NULL) 458 printf(" Vendor Name: %s (0x%04x)\n", kdp->vendorname, 459 PCI_VENDOR(rval)); 460 else 461 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 462 if (kdp->productname != NULL && (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0) 463 printf(" Device Name: %s (0x%04x)\n", kdp->productname, 464 PCI_PRODUCT(rval)); 465 else 466 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 467 #endif /* PCIVERBOSE */ 468 469 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 470 471 printf(" Command register: 0x%04x\n", rval & 0xffff); 472 onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE); 473 onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE); 474 onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE); 475 onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE); 476 onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE); 477 onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE); 478 onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE); 479 onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE); 480 onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE); 481 onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE); 482 483 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 484 onoff("Capability List support", PCI_STATUS_CAPLIST_SUPPORT); 485 onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT); 486 onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT); 487 onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT); 488 onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR); 489 490 printf(" DEVSEL timing: "); 491 switch (rval & PCI_STATUS_DEVSEL_MASK) { 492 case PCI_STATUS_DEVSEL_FAST: 493 printf("fast"); 494 break; 495 case PCI_STATUS_DEVSEL_MEDIUM: 496 printf("medium"); 497 break; 498 case PCI_STATUS_DEVSEL_SLOW: 499 printf("slow"); 500 break; 501 default: 502 printf("unknown/reserved"); /* XXX */ 503 break; 504 } 505 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 506 507 onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT); 508 onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT); 509 onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT); 510 onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR); 511 onoff("Parity error detected", PCI_STATUS_PARITY_DETECT); 512 513 rval = regs[o2i(PCI_CLASS_REG)]; 514 for (classp = pci_class; classp->name != NULL; classp++) { 515 if (PCI_CLASS(rval) == classp->val) 516 break; 517 } 518 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 519 while (subclassp && subclassp->name != NULL) { 520 if (PCI_SUBCLASS(rval) == subclassp->val) 521 break; 522 subclassp++; 523 } 524 if (classp->name != NULL) { 525 printf(" Class Name: %s (0x%02x)\n", classp->name, 526 PCI_CLASS(rval)); 527 if (subclassp != NULL && subclassp->name != NULL) 528 printf(" Subclass Name: %s (0x%02x)\n", 529 subclassp->name, PCI_SUBCLASS(rval)); 530 else 531 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 532 } else { 533 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 534 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 535 } 536 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 537 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 538 539 rval = regs[o2i(PCI_BHLC_REG)]; 540 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 541 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 542 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 543 PCI_HDRTYPE(rval)); 544 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 545 printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval)); 546 } 547 548 static int 549 pci_conf_print_bar( 550 #ifdef _KERNEL 551 pci_chipset_tag_t pc, pcitag_t tag, 552 #endif 553 const pcireg_t *regs, int reg, const char *name 554 #ifdef _KERNEL 555 , int sizebar 556 #endif 557 ) 558 { 559 int width; 560 pcireg_t rval, rval64h; 561 #ifdef _KERNEL 562 int s; 563 pcireg_t mask, mask64h; 564 #endif 565 566 width = 4; 567 568 /* 569 * Section 6.2.5.1, `Address Maps', tells us that: 570 * 571 * 1) The builtin software should have already mapped the 572 * device in a reasonable way. 573 * 574 * 2) A device which wants 2^n bytes of memory will hardwire 575 * the bottom n bits of the address to 0. As recommended, 576 * we write all 1s and see what we get back. 577 */ 578 579 rval = regs[o2i(reg)]; 580 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 581 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 582 rval64h = regs[o2i(reg + 4)]; 583 width = 8; 584 } else 585 rval64h = 0; 586 587 #ifdef _KERNEL 588 /* XXX don't size unknown memory type? */ 589 if (rval != 0 && sizebar) { 590 /* 591 * The following sequence seems to make some devices 592 * (e.g. host bus bridges, which don't normally 593 * have their space mapped) very unhappy, to 594 * the point of crashing the system. 595 * 596 * Therefore, if the mapping register is zero to 597 * start out with, don't bother trying. 598 */ 599 s = splhigh(); 600 pci_conf_write(pc, tag, reg, 0xffffffff); 601 mask = pci_conf_read(pc, tag, reg); 602 pci_conf_write(pc, tag, reg, rval); 603 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 604 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 605 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 606 mask64h = pci_conf_read(pc, tag, reg + 4); 607 pci_conf_write(pc, tag, reg + 4, rval64h); 608 } 609 splx(s); 610 } else 611 mask = 0; 612 #endif /* _KERNEL */ 613 614 printf(" Base address register at 0x%02x", reg); 615 if (name) 616 printf(" (%s)", name); 617 printf("\n "); 618 if (rval == 0) { 619 printf("not implemented(?)\n"); 620 return width; 621 } 622 printf("type: "); 623 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 624 const char *type, *prefetch; 625 626 switch (PCI_MAPREG_MEM_TYPE(rval)) { 627 case PCI_MAPREG_MEM_TYPE_32BIT: 628 type = "32-bit"; 629 break; 630 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 631 type = "32-bit-1M"; 632 break; 633 case PCI_MAPREG_MEM_TYPE_64BIT: 634 type = "64-bit"; 635 break; 636 default: 637 type = "unknown (XXX)"; 638 break; 639 } 640 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 641 prefetch = ""; 642 else 643 prefetch = "non"; 644 printf("%s %sprefetchable memory\n", type, prefetch); 645 switch (PCI_MAPREG_MEM_TYPE(rval)) { 646 case PCI_MAPREG_MEM_TYPE_64BIT: 647 printf(" base: 0x%016llx, ", 648 PCI_MAPREG_MEM64_ADDR( 649 ((((long long) rval64h) << 32) | rval))); 650 #ifdef _KERNEL 651 if (sizebar) 652 printf("size: 0x%016llx", 653 PCI_MAPREG_MEM64_SIZE( 654 ((((long long) mask64h) << 32) | mask))); 655 else 656 #endif /* _KERNEL */ 657 printf("not sized"); 658 printf("\n"); 659 break; 660 case PCI_MAPREG_MEM_TYPE_32BIT: 661 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 662 default: 663 printf(" base: 0x%08x, ", 664 PCI_MAPREG_MEM_ADDR(rval)); 665 #ifdef _KERNEL 666 if (sizebar) 667 printf("size: 0x%08x", 668 PCI_MAPREG_MEM_SIZE(mask)); 669 else 670 #endif /* _KERNEL */ 671 printf("not sized"); 672 printf("\n"); 673 break; 674 } 675 } else { 676 #ifdef _KERNEL 677 if (sizebar) 678 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 679 #endif /* _KERNEL */ 680 printf("i/o\n"); 681 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 682 #ifdef _KERNEL 683 if (sizebar) 684 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 685 else 686 #endif /* _KERNEL */ 687 printf("not sized"); 688 printf("\n"); 689 } 690 691 return width; 692 } 693 694 static void 695 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 696 { 697 int off, needaddr, neednl; 698 699 needaddr = 1; 700 neednl = 0; 701 for (off = first; off < pastlast; off += 4) { 702 if ((off % 16) == 0 || needaddr) { 703 printf(" 0x%02x:", off); 704 needaddr = 0; 705 } 706 printf(" 0x%08x", regs[o2i(off)]); 707 neednl = 1; 708 if ((off % 16) == 12) { 709 printf("\n"); 710 neednl = 0; 711 } 712 } 713 if (neednl) 714 printf("\n"); 715 } 716 717 static void 718 pci_conf_print_type0( 719 #ifdef _KERNEL 720 pci_chipset_tag_t pc, pcitag_t tag, 721 #endif 722 const pcireg_t *regs 723 #ifdef _KERNEL 724 , int sizebars 725 #endif 726 ) 727 { 728 int off, width; 729 pcireg_t rval; 730 731 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 732 #ifdef _KERNEL 733 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 734 #else 735 width = pci_conf_print_bar(regs, off, NULL); 736 #endif 737 } 738 739 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 740 741 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 742 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 743 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 744 745 /* XXX */ 746 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 747 748 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 749 printf(" Capability list pointer: 0x%02x\n", 750 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 751 else 752 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 753 754 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 755 756 rval = regs[o2i(PCI_INTERRUPT_REG)]; 757 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 758 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 759 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 760 switch (PCI_INTERRUPT_PIN(rval)) { 761 case PCI_INTERRUPT_PIN_NONE: 762 printf("(none)"); 763 break; 764 case PCI_INTERRUPT_PIN_A: 765 printf("(pin A)"); 766 break; 767 case PCI_INTERRUPT_PIN_B: 768 printf("(pin B)"); 769 break; 770 case PCI_INTERRUPT_PIN_C: 771 printf("(pin C)"); 772 break; 773 case PCI_INTERRUPT_PIN_D: 774 printf("(pin D)"); 775 break; 776 default: 777 printf("(? ? ?)"); 778 break; 779 } 780 printf("\n"); 781 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 782 } 783 784 static void 785 pci_conf_print_caplist( 786 #ifdef _KERNEL 787 pci_chipset_tag_t pc, pcitag_t tag, 788 #endif 789 const pcireg_t *regs, int capoff) 790 { 791 int off; 792 pcireg_t rval; 793 794 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 795 off != 0; 796 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 797 rval = regs[o2i(off)]; 798 printf(" Capability register at 0x%02x\n", off); 799 800 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 801 switch (PCI_CAPLIST_CAP(rval)) { 802 case PCI_CAP_RESERVED0: 803 printf("reserved"); 804 break; 805 case PCI_CAP_PWRMGMT: 806 printf("Power Management, rev. %d.0", 807 (rval >> 0) & 0x07); /* XXX not clear */ 808 break; 809 case PCI_CAP_AGP: 810 printf("AGP, rev. %d.%d", 811 (rval >> 24) & 0x0f, 812 (rval >> 20) & 0x0f); 813 break; 814 case PCI_CAP_VPD: 815 printf("VPD"); 816 break; 817 case PCI_CAP_SLOTID: 818 printf("SlotID"); 819 break; 820 case PCI_CAP_MSI: 821 printf("MSI"); 822 break; 823 case PCI_CAP_CPCI_HOTSWAP: 824 printf("CompactPCI Hot-swapping"); 825 break; 826 case PCI_CAP_PCIX: 827 printf("PCI-X"); 828 break; 829 case PCI_CAP_LDT: 830 printf("LDT"); 831 break; 832 case PCI_CAP_VENDSPEC: 833 printf("Vendor-specific"); 834 break; 835 case PCI_CAP_DEBUGPORT: 836 printf("Debug Port"); 837 break; 838 case PCI_CAP_CPCI_RSRCCTL: 839 printf("CompactPCI Resource Control"); 840 break; 841 case PCI_CAP_HOTPLUG: 842 printf("Hot-Plug"); 843 break; 844 case PCI_CAP_AGP8: 845 printf("AGP 8x"); 846 break; 847 case PCI_CAP_SECURE: 848 printf("Secure Device"); 849 break; 850 case PCI_CAP_PCIEXPRESS: 851 printf("PCI Express"); 852 break; 853 case PCI_CAP_MSIX: 854 printf("MSI-X"); 855 break; 856 default: 857 printf("unknown"); 858 } 859 printf(")\n"); 860 } 861 } 862 863 static void 864 pci_conf_print_type1( 865 #ifdef _KERNEL 866 pci_chipset_tag_t pc, pcitag_t tag, 867 #endif 868 const pcireg_t *regs 869 #ifdef _KERNEL 870 , int sizebars 871 #endif 872 ) 873 { 874 int off, width; 875 pcireg_t rval; 876 877 /* 878 * XXX these need to be printed in more detail, need to be 879 * XXX checked against specs/docs, etc. 880 * 881 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 882 * Bridge chip documentation, and may not be correct with 883 * respect to various standards. (XXX) 884 */ 885 886 for (off = 0x10; off < 0x18; off += width) { 887 #ifdef _KERNEL 888 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 889 #else 890 width = pci_conf_print_bar(regs, off, NULL); 891 #endif 892 } 893 894 printf(" Primary bus number: 0x%02x\n", 895 (regs[o2i(0x18)] >> 0) & 0xff); 896 printf(" Secondary bus number: 0x%02x\n", 897 (regs[o2i(0x18)] >> 8) & 0xff); 898 printf(" Subordinate bus number: 0x%02x\n", 899 (regs[o2i(0x18)] >> 16) & 0xff); 900 printf(" Secondary bus latency timer: 0x%02x\n", 901 (regs[o2i(0x18)] >> 24) & 0xff); 902 903 rval = (regs[o2i(0x1c)] >> 16) & 0xffff; 904 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 905 onoff("66 MHz capable", 0x0020); 906 onoff("User Definable Features (UDF) support", 0x0040); 907 onoff("Fast back-to-back capable", 0x0080); 908 onoff("Data parity error detected", 0x0100); 909 910 printf(" DEVSEL timing: "); 911 switch (rval & 0x0600) { 912 case 0x0000: 913 printf("fast"); 914 break; 915 case 0x0200: 916 printf("medium"); 917 break; 918 case 0x0400: 919 printf("slow"); 920 break; 921 default: 922 printf("unknown/reserved"); /* XXX */ 923 break; 924 } 925 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 926 927 onoff("Signaled Target Abort", 0x0800); 928 onoff("Received Target Abort", 0x1000); 929 onoff("Received Master Abort", 0x2000); 930 onoff("System Error", 0x4000); 931 onoff("Parity Error", 0x8000); 932 933 /* XXX Print more prettily */ 934 printf(" I/O region:\n"); 935 printf(" base register: 0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff); 936 printf(" limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff); 937 printf(" base upper 16 bits register: 0x%04x\n", 938 (regs[o2i(0x30)] >> 0) & 0xffff); 939 printf(" limit upper 16 bits register: 0x%04x\n", 940 (regs[o2i(0x30)] >> 16) & 0xffff); 941 942 /* XXX Print more prettily */ 943 printf(" Memory region:\n"); 944 printf(" base register: 0x%04x\n", 945 (regs[o2i(0x20)] >> 0) & 0xffff); 946 printf(" limit register: 0x%04x\n", 947 (regs[o2i(0x20)] >> 16) & 0xffff); 948 949 /* XXX Print more prettily */ 950 printf(" Prefetchable memory region:\n"); 951 printf(" base register: 0x%04x\n", 952 (regs[o2i(0x24)] >> 0) & 0xffff); 953 printf(" limit register: 0x%04x\n", 954 (regs[o2i(0x24)] >> 16) & 0xffff); 955 printf(" base upper 32 bits register: 0x%08x\n", regs[o2i(0x28)]); 956 printf(" limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]); 957 958 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 959 printf(" Capability list pointer: 0x%02x\n", 960 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 961 else 962 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 963 964 /* XXX */ 965 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 966 967 printf(" Interrupt line: 0x%02x\n", 968 (regs[o2i(0x3c)] >> 0) & 0xff); 969 printf(" Interrupt pin: 0x%02x ", 970 (regs[o2i(0x3c)] >> 8) & 0xff); 971 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 972 case PCI_INTERRUPT_PIN_NONE: 973 printf("(none)"); 974 break; 975 case PCI_INTERRUPT_PIN_A: 976 printf("(pin A)"); 977 break; 978 case PCI_INTERRUPT_PIN_B: 979 printf("(pin B)"); 980 break; 981 case PCI_INTERRUPT_PIN_C: 982 printf("(pin C)"); 983 break; 984 case PCI_INTERRUPT_PIN_D: 985 printf("(pin D)"); 986 break; 987 default: 988 printf("(? ? ?)"); 989 break; 990 } 991 printf("\n"); 992 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 993 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 994 onoff("Parity error response", 0x0001); 995 onoff("Secondary SERR forwarding", 0x0002); 996 onoff("ISA enable", 0x0004); 997 onoff("VGA enable", 0x0008); 998 onoff("Master abort reporting", 0x0020); 999 onoff("Secondary bus reset", 0x0040); 1000 onoff("Fast back-to-back capable", 0x0080); 1001 } 1002 1003 static void 1004 pci_conf_print_type2( 1005 #ifdef _KERNEL 1006 pci_chipset_tag_t pc, pcitag_t tag, 1007 #endif 1008 const pcireg_t *regs 1009 #ifdef _KERNEL 1010 , int sizebars 1011 #endif 1012 ) 1013 { 1014 pcireg_t rval; 1015 1016 /* 1017 * XXX these need to be printed in more detail, need to be 1018 * XXX checked against specs/docs, etc. 1019 * 1020 * This layout was cribbed from the TI PCI1130 PCI-to-CardBus 1021 * controller chip documentation, and may not be correct with 1022 * respect to various standards. (XXX) 1023 */ 1024 1025 #ifdef _KERNEL 1026 pci_conf_print_bar(pc, tag, regs, 0x10, 1027 "CardBus socket/ExCA registers", sizebars); 1028 #else 1029 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 1030 #endif 1031 1032 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1033 printf(" Capability list pointer: 0x%02x\n", 1034 PCI_CAPLIST_PTR(regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)])); 1035 else 1036 printf(" Reserved @ 0x14: 0x%04x\n", 1037 (regs[o2i(0x14)] >> 0) & 0xffff); 1038 rval = (regs[o2i(0x14)] >> 16) & 0xffff; 1039 printf(" Secondary status register: 0x%04x\n", rval); 1040 onoff("66 MHz capable", 0x0020); 1041 onoff("User Definable Features (UDF) support", 0x0040); 1042 onoff("Fast back-to-back capable", 0x0080); 1043 onoff("Data parity error detection", 0x0100); 1044 1045 printf(" DEVSEL timing: "); 1046 switch (rval & 0x0600) { 1047 case 0x0000: 1048 printf("fast"); 1049 break; 1050 case 0x0200: 1051 printf("medium"); 1052 break; 1053 case 0x0400: 1054 printf("slow"); 1055 break; 1056 default: 1057 printf("unknown/reserved"); /* XXX */ 1058 break; 1059 } 1060 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 1061 onoff("PCI target aborts terminate CardBus bus master transactions", 1062 0x0800); 1063 onoff("CardBus target aborts terminate PCI bus master transactions", 1064 0x1000); 1065 onoff("Bus initiator aborts terminate initiator transactions", 1066 0x2000); 1067 onoff("System error", 0x4000); 1068 onoff("Parity error", 0x8000); 1069 1070 printf(" PCI bus number: 0x%02x\n", 1071 (regs[o2i(0x18)] >> 0) & 0xff); 1072 printf(" CardBus bus number: 0x%02x\n", 1073 (regs[o2i(0x18)] >> 8) & 0xff); 1074 printf(" Subordinate bus number: 0x%02x\n", 1075 (regs[o2i(0x18)] >> 16) & 0xff); 1076 printf(" CardBus latency timer: 0x%02x\n", 1077 (regs[o2i(0x18)] >> 24) & 0xff); 1078 1079 /* XXX Print more prettily */ 1080 printf(" CardBus memory region 0:\n"); 1081 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 1082 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 1083 printf(" CardBus memory region 1:\n"); 1084 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 1085 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 1086 printf(" CardBus I/O region 0:\n"); 1087 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 1088 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 1089 printf(" CardBus I/O region 1:\n"); 1090 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 1091 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 1092 1093 printf(" Interrupt line: 0x%02x\n", 1094 (regs[o2i(0x3c)] >> 0) & 0xff); 1095 printf(" Interrupt pin: 0x%02x ", 1096 (regs[o2i(0x3c)] >> 8) & 0xff); 1097 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1098 case PCI_INTERRUPT_PIN_NONE: 1099 printf("(none)"); 1100 break; 1101 case PCI_INTERRUPT_PIN_A: 1102 printf("(pin A)"); 1103 break; 1104 case PCI_INTERRUPT_PIN_B: 1105 printf("(pin B)"); 1106 break; 1107 case PCI_INTERRUPT_PIN_C: 1108 printf("(pin C)"); 1109 break; 1110 case PCI_INTERRUPT_PIN_D: 1111 printf("(pin D)"); 1112 break; 1113 default: 1114 printf("(? ? ?)"); 1115 break; 1116 } 1117 printf("\n"); 1118 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1119 printf(" Bridge control register: 0x%04x\n", rval); 1120 onoff("Parity error response", 0x0001); 1121 onoff("CardBus SERR forwarding", 0x0002); 1122 onoff("ISA enable", 0x0004); 1123 onoff("VGA enable", 0x0008); 1124 onoff("CardBus master abort reporting", 0x0020); 1125 onoff("CardBus reset", 0x0040); 1126 onoff("Functional interrupts routed by ExCA registers", 0x0080); 1127 onoff("Memory window 0 prefetchable", 0x0100); 1128 onoff("Memory window 1 prefetchable", 0x0200); 1129 onoff("Write posting enable", 0x0400); 1130 1131 rval = regs[o2i(0x40)]; 1132 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 1133 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 1134 1135 #ifdef _KERNEL 1136 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 1137 sizebars); 1138 #else 1139 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 1140 #endif 1141 } 1142 1143 void 1144 pci_conf_print( 1145 #ifdef _KERNEL 1146 pci_chipset_tag_t pc, pcitag_t tag, 1147 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 1148 #else 1149 int pcifd, u_int bus, u_int dev, u_int func 1150 #endif 1151 ) 1152 { 1153 pcireg_t regs[o2i(256)]; 1154 int off, capoff, endoff, hdrtype; 1155 const char *typename; 1156 #ifdef _KERNEL 1157 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, int); 1158 int sizebars; 1159 #else 1160 void (*typeprintfn)(const pcireg_t *); 1161 #endif 1162 1163 printf("PCI configuration registers:\n"); 1164 1165 for (off = 0; off < 256; off += 4) { 1166 #ifdef _KERNEL 1167 regs[o2i(off)] = pci_conf_read(pc, tag, off); 1168 #else 1169 if (pcibus_conf_read(pcifd, bus, dev, func, off, 1170 ®s[o2i(off)]) == -1) 1171 regs[o2i(off)] = 0; 1172 #endif 1173 } 1174 1175 #ifdef _KERNEL 1176 sizebars = 1; 1177 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 1178 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 1179 sizebars = 0; 1180 #endif 1181 1182 /* common header */ 1183 printf(" Common header:\n"); 1184 pci_conf_print_regs(regs, 0, 16); 1185 1186 printf("\n"); 1187 #ifdef _KERNEL 1188 pci_conf_print_common(pc, tag, regs); 1189 #else 1190 pci_conf_print_common(regs); 1191 #endif 1192 printf("\n"); 1193 1194 /* type-dependent header */ 1195 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 1196 switch (hdrtype) { /* XXX make a table, eventually */ 1197 case 0: 1198 /* Standard device header */ 1199 typename = "\"normal\" device"; 1200 typeprintfn = &pci_conf_print_type0; 1201 capoff = PCI_CAPLISTPTR_REG; 1202 endoff = 64; 1203 break; 1204 case 1: 1205 /* PCI-PCI bridge header */ 1206 typename = "PCI-PCI bridge"; 1207 typeprintfn = &pci_conf_print_type1; 1208 capoff = PCI_CAPLISTPTR_REG; 1209 endoff = 64; 1210 break; 1211 case 2: 1212 /* PCI-CardBus bridge header */ 1213 typename = "PCI-CardBus bridge"; 1214 typeprintfn = &pci_conf_print_type2; 1215 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 1216 endoff = 72; 1217 break; 1218 default: 1219 typename = NULL; 1220 typeprintfn = 0; 1221 capoff = -1; 1222 endoff = 64; 1223 break; 1224 } 1225 printf(" Type %d ", hdrtype); 1226 if (typename != NULL) 1227 printf("(%s) ", typename); 1228 printf("header:\n"); 1229 pci_conf_print_regs(regs, 16, endoff); 1230 printf("\n"); 1231 if (typeprintfn) { 1232 #ifdef _KERNEL 1233 (*typeprintfn)(pc, tag, regs, sizebars); 1234 #else 1235 (*typeprintfn)(regs); 1236 #endif 1237 } else 1238 printf(" Don't know how to pretty-print type %d header.\n", 1239 hdrtype); 1240 printf("\n"); 1241 1242 /* papability list, if present */ 1243 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1244 && (capoff > 0)) { 1245 #ifdef _KERNEL 1246 pci_conf_print_caplist(pc, tag, regs, capoff); 1247 #else 1248 pci_conf_print_caplist(regs, capoff); 1249 #endif 1250 printf("\n"); 1251 } 1252 1253 /* device-dependent header */ 1254 printf(" Device-dependent header:\n"); 1255 pci_conf_print_regs(regs, endoff, 256); 1256 printf("\n"); 1257 #ifdef _KERNEL 1258 if (printfn) 1259 (*printfn)(pc, tag, regs); 1260 else 1261 printf(" Don't know how to pretty-print device-dependent header.\n"); 1262 printf("\n"); 1263 #endif /* _KERNEL */ 1264 } 1265