1 /* $NetBSD: pci_subr.c,v 1.93 2012/09/23 01:10:10 chs Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.93 2012/09/23 01:10:10 chs Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdbool.h> 58 #include <stdio.h> 59 #endif 60 61 #include <dev/pci/pcireg.h> 62 #ifdef _KERNEL 63 #include <dev/pci/pcivar.h> 64 #endif 65 66 /* 67 * Descriptions of known PCI classes and subclasses. 68 * 69 * Subclasses are described in the same way as classes, but have a 70 * NULL subclass pointer. 71 */ 72 struct pci_class { 73 const char *name; 74 u_int val; /* as wide as pci_{,sub}class_t */ 75 const struct pci_class *subclasses; 76 }; 77 78 static const struct pci_class pci_subclass_prehistoric[] = { 79 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 80 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 81 { NULL, 0, NULL, }, 82 }; 83 84 static const struct pci_class pci_subclass_mass_storage[] = { 85 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 86 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 87 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 88 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 89 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 90 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, NULL, }, 91 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, NULL, }, 92 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 93 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 94 { NULL, 0, NULL, }, 95 }; 96 97 static const struct pci_class pci_subclass_network[] = { 98 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 99 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 100 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 101 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 102 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 103 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 104 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 105 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 106 { NULL, 0, NULL, }, 107 }; 108 109 static const struct pci_class pci_subclass_display[] = { 110 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, NULL, }, 111 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 112 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 113 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 114 { NULL, 0, NULL, }, 115 }; 116 117 static const struct pci_class pci_subclass_multimedia[] = { 118 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 119 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 120 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 121 { "HD audio", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 122 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 123 { NULL, 0, NULL, }, 124 }; 125 126 static const struct pci_class pci_subclass_memory[] = { 127 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 128 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 129 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 130 { NULL, 0, NULL, }, 131 }; 132 133 static const struct pci_class pci_subclass_bridge[] = { 134 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 135 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 136 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 137 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 138 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, NULL, }, 139 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 140 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 141 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 142 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 143 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, NULL, }, 144 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 145 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 146 { NULL, 0, NULL, }, 147 }; 148 149 static const struct pci_class pci_subclass_communications[] = { 150 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, NULL, }, 151 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, NULL, }, 152 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL, }, 153 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, NULL, }, 154 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL, }, 155 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL, }, 156 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL, }, 157 { NULL, 0, NULL, }, 158 }; 159 160 static const struct pci_class pci_subclass_system[] = { 161 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, NULL, }, 162 { "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, NULL, }, 163 { "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, NULL, }, 164 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, NULL, }, 165 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 166 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 167 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 168 { NULL, 0, NULL, }, 169 }; 170 171 static const struct pci_class pci_subclass_input[] = { 172 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 173 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 174 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 175 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 176 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, NULL, }, 177 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 178 { NULL, 0, NULL, }, 179 }; 180 181 static const struct pci_class pci_subclass_dock[] = { 182 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 183 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 184 { NULL, 0, NULL, }, 185 }; 186 187 static const struct pci_class pci_subclass_processor[] = { 188 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 189 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 190 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 191 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 192 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 193 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 194 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 195 { NULL, 0, NULL, }, 196 }; 197 198 static const struct pci_class pci_subclass_serialbus[] = { 199 { "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, NULL, }, 200 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 201 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 202 { "USB", PCI_SUBCLASS_SERIALBUS_USB, NULL, }, 203 /* XXX Fiber Channel/_FIBRECHANNEL */ 204 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 205 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 206 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 207 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, NULL, }, 208 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 209 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 210 { NULL, 0, NULL, }, 211 }; 212 213 static const struct pci_class pci_subclass_wireless[] = { 214 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 215 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 216 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 217 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 218 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 219 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 220 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 221 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 222 { NULL, 0, NULL, }, 223 }; 224 225 static const struct pci_class pci_subclass_i2o[] = { 226 { "standard", PCI_SUBCLASS_I2O_STANDARD, NULL, }, 227 { NULL, 0, NULL, }, 228 }; 229 230 static const struct pci_class pci_subclass_satcom[] = { 231 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 232 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 233 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 234 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 235 { NULL, 0, NULL, }, 236 }; 237 238 static const struct pci_class pci_subclass_crypto[] = { 239 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 240 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 241 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 242 { NULL, 0, NULL, }, 243 }; 244 245 static const struct pci_class pci_subclass_dasp[] = { 246 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 247 { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 248 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 249 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 250 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 251 { NULL, 0, NULL, }, 252 }; 253 254 static const struct pci_class pci_class[] = { 255 { "prehistoric", PCI_CLASS_PREHISTORIC, 256 pci_subclass_prehistoric, }, 257 { "mass storage", PCI_CLASS_MASS_STORAGE, 258 pci_subclass_mass_storage, }, 259 { "network", PCI_CLASS_NETWORK, 260 pci_subclass_network, }, 261 { "display", PCI_CLASS_DISPLAY, 262 pci_subclass_display, }, 263 { "multimedia", PCI_CLASS_MULTIMEDIA, 264 pci_subclass_multimedia, }, 265 { "memory", PCI_CLASS_MEMORY, 266 pci_subclass_memory, }, 267 { "bridge", PCI_CLASS_BRIDGE, 268 pci_subclass_bridge, }, 269 { "communications", PCI_CLASS_COMMUNICATIONS, 270 pci_subclass_communications, }, 271 { "system", PCI_CLASS_SYSTEM, 272 pci_subclass_system, }, 273 { "input", PCI_CLASS_INPUT, 274 pci_subclass_input, }, 275 { "dock", PCI_CLASS_DOCK, 276 pci_subclass_dock, }, 277 { "processor", PCI_CLASS_PROCESSOR, 278 pci_subclass_processor, }, 279 { "serial bus", PCI_CLASS_SERIALBUS, 280 pci_subclass_serialbus, }, 281 { "wireless", PCI_CLASS_WIRELESS, 282 pci_subclass_wireless, }, 283 { "I2O", PCI_CLASS_I2O, 284 pci_subclass_i2o, }, 285 { "satellite comm", PCI_CLASS_SATCOM, 286 pci_subclass_satcom, }, 287 { "crypto", PCI_CLASS_CRYPTO, 288 pci_subclass_crypto, }, 289 { "DASP", PCI_CLASS_DASP, 290 pci_subclass_dasp, }, 291 { "undefined", PCI_CLASS_UNDEFINED, 292 NULL, }, 293 { NULL, 0, 294 NULL, }, 295 }; 296 297 void pci_load_verbose(void); 298 299 #if defined(_KERNEL) 300 /* 301 * In kernel, these routines are provided and linked via the 302 * pciverbose module. 303 */ 304 const char *pci_findvendor_stub(pcireg_t); 305 const char *pci_findproduct_stub(pcireg_t); 306 307 const char *(*pci_findvendor)(pcireg_t) = pci_findvendor_stub; 308 const char *(*pci_findproduct)(pcireg_t) = pci_findproduct_stub; 309 const char *pci_unmatched = ""; 310 #else 311 /* 312 * For userland we just set the vectors here. 313 */ 314 const char *(*pci_findvendor)(pcireg_t id_reg) = pci_findvendor_real; 315 const char *(*pci_findproduct)(pcireg_t id_reg) = pci_findproduct_real; 316 const char *pci_unmatched = "unmatched "; 317 #endif 318 319 int pciverbose_loaded = 0; 320 321 #if defined(_KERNEL) 322 /* 323 * Routine to load the pciverbose kernel module as needed 324 */ 325 void pci_load_verbose(void) 326 { 327 if (pciverbose_loaded == 0) 328 module_autoload("pciverbose", MODULE_CLASS_MISC); 329 } 330 331 const char *pci_findvendor_stub(pcireg_t id_reg) 332 { 333 pci_load_verbose(); 334 if (pciverbose_loaded) 335 return pci_findvendor(id_reg); 336 else 337 return NULL; 338 } 339 340 const char *pci_findproduct_stub(pcireg_t id_reg) 341 { 342 pci_load_verbose(); 343 if (pciverbose_loaded) 344 return pci_findproduct(id_reg); 345 else 346 return NULL; 347 } 348 #endif 349 350 void 351 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 352 size_t l) 353 { 354 pci_vendor_id_t vendor; 355 pci_product_id_t product; 356 pci_class_t class; 357 pci_subclass_t subclass; 358 pci_interface_t interface; 359 pci_revision_t revision; 360 const char *unmatched = pci_unmatched; 361 const char *vendor_namep, *product_namep; 362 const struct pci_class *classp, *subclassp; 363 char *ep; 364 365 ep = cp + l; 366 367 vendor = PCI_VENDOR(id_reg); 368 product = PCI_PRODUCT(id_reg); 369 370 class = PCI_CLASS(class_reg); 371 subclass = PCI_SUBCLASS(class_reg); 372 interface = PCI_INTERFACE(class_reg); 373 revision = PCI_REVISION(class_reg); 374 375 vendor_namep = pci_findvendor(id_reg); 376 product_namep = pci_findproduct(id_reg); 377 378 classp = pci_class; 379 while (classp->name != NULL) { 380 if (class == classp->val) 381 break; 382 classp++; 383 } 384 385 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 386 while (subclassp && subclassp->name != NULL) { 387 if (subclass == subclassp->val) 388 break; 389 subclassp++; 390 } 391 392 if (vendor_namep == NULL) 393 cp += snprintf(cp, ep - cp, "%svendor 0x%04x product 0x%04x", 394 unmatched, vendor, product); 395 else if (product_namep != NULL) 396 cp += snprintf(cp, ep - cp, "%s %s", vendor_namep, 397 product_namep); 398 else 399 cp += snprintf(cp, ep - cp, "%s product 0x%04x", 400 vendor_namep, product); 401 if (showclass) { 402 cp += snprintf(cp, ep - cp, " ("); 403 if (classp->name == NULL) 404 cp += snprintf(cp, ep - cp, 405 "class 0x%02x, subclass 0x%02x", class, subclass); 406 else { 407 if (subclassp == NULL || subclassp->name == NULL) 408 cp += snprintf(cp, ep - cp, 409 "%s, subclass 0x%02x", 410 classp->name, subclass); 411 else 412 cp += snprintf(cp, ep - cp, "%s %s", 413 subclassp->name, classp->name); 414 } 415 if (interface != 0) 416 cp += snprintf(cp, ep - cp, ", interface 0x%02x", 417 interface); 418 if (revision != 0) 419 cp += snprintf(cp, ep - cp, ", revision 0x%02x", 420 revision); 421 cp += snprintf(cp, ep - cp, ")"); 422 } 423 } 424 425 #ifdef _KERNEL 426 void 427 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 428 const char *known, int addrev) 429 { 430 char devinfo[256]; 431 432 if (known) { 433 aprint_normal(": %s", known); 434 if (addrev) 435 aprint_normal(" (rev. 0x%02x)", 436 PCI_REVISION(pa->pa_class)); 437 aprint_normal("\n"); 438 } else { 439 pci_devinfo(pa->pa_id, pa->pa_class, 0, 440 devinfo, sizeof(devinfo)); 441 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 442 PCI_REVISION(pa->pa_class)); 443 } 444 if (naive) 445 aprint_naive(": %s\n", naive); 446 else 447 aprint_naive("\n"); 448 } 449 #endif 450 451 /* 452 * Print out most of the PCI configuration registers. Typically used 453 * in a device attach routine like this: 454 * 455 * #ifdef MYDEV_DEBUG 456 * printf("%s: ", device_xname(&sc->sc_dev)); 457 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 458 * #endif 459 */ 460 461 #define i2o(i) ((i) * 4) 462 #define o2i(o) ((o) / 4) 463 #define onoff2(str, bit, onstr, offstr) \ 464 printf(" %s: %s\n", (str), (rval & (bit)) ? onstr : offstr); 465 #define onoff(str, bit) onoff2(str, bit, "on", "off") 466 467 static void 468 pci_conf_print_common( 469 #ifdef _KERNEL 470 pci_chipset_tag_t pc, pcitag_t tag, 471 #endif 472 const pcireg_t *regs) 473 { 474 const char *name; 475 const struct pci_class *classp, *subclassp; 476 pcireg_t rval; 477 478 rval = regs[o2i(PCI_ID_REG)]; 479 name = pci_findvendor(rval); 480 if (name) 481 printf(" Vendor Name: %s (0x%04x)\n", name, 482 PCI_VENDOR(rval)); 483 else 484 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 485 name = pci_findproduct(rval); 486 if (name) 487 printf(" Device Name: %s (0x%04x)\n", name, 488 PCI_PRODUCT(rval)); 489 else 490 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 491 492 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 493 494 printf(" Command register: 0x%04x\n", rval & 0xffff); 495 onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE); 496 onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE); 497 onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE); 498 onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE); 499 onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE); 500 onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE); 501 onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE); 502 onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE); 503 onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE); 504 onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE); 505 onoff("Interrupt disable", PCI_COMMAND_INTERRUPT_DISABLE); 506 507 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 508 onoff2("Interrupt status", PCI_STATUS_INT_STATUS, "active", "inactive"); 509 onoff("Capability List support", PCI_STATUS_CAPLIST_SUPPORT); 510 onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT); 511 onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT); 512 onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT); 513 onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR); 514 515 printf(" DEVSEL timing: "); 516 switch (rval & PCI_STATUS_DEVSEL_MASK) { 517 case PCI_STATUS_DEVSEL_FAST: 518 printf("fast"); 519 break; 520 case PCI_STATUS_DEVSEL_MEDIUM: 521 printf("medium"); 522 break; 523 case PCI_STATUS_DEVSEL_SLOW: 524 printf("slow"); 525 break; 526 default: 527 printf("unknown/reserved"); /* XXX */ 528 break; 529 } 530 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 531 532 onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT); 533 onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT); 534 onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT); 535 onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR); 536 onoff("Parity error detected", PCI_STATUS_PARITY_DETECT); 537 538 rval = regs[o2i(PCI_CLASS_REG)]; 539 for (classp = pci_class; classp->name != NULL; classp++) { 540 if (PCI_CLASS(rval) == classp->val) 541 break; 542 } 543 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 544 while (subclassp && subclassp->name != NULL) { 545 if (PCI_SUBCLASS(rval) == subclassp->val) 546 break; 547 subclassp++; 548 } 549 if (classp->name != NULL) { 550 printf(" Class Name: %s (0x%02x)\n", classp->name, 551 PCI_CLASS(rval)); 552 if (subclassp != NULL && subclassp->name != NULL) 553 printf(" Subclass Name: %s (0x%02x)\n", 554 subclassp->name, PCI_SUBCLASS(rval)); 555 else 556 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 557 } else { 558 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 559 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 560 } 561 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 562 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 563 564 rval = regs[o2i(PCI_BHLC_REG)]; 565 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 566 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 567 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 568 PCI_HDRTYPE(rval)); 569 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 570 printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval)); 571 } 572 573 static int 574 pci_conf_print_bar( 575 #ifdef _KERNEL 576 pci_chipset_tag_t pc, pcitag_t tag, 577 #endif 578 const pcireg_t *regs, int reg, const char *name 579 #ifdef _KERNEL 580 , int sizebar 581 #endif 582 ) 583 { 584 int width; 585 pcireg_t rval, rval64h; 586 #ifdef _KERNEL 587 int s; 588 pcireg_t mask, mask64h; 589 #endif 590 591 width = 4; 592 593 /* 594 * Section 6.2.5.1, `Address Maps', tells us that: 595 * 596 * 1) The builtin software should have already mapped the 597 * device in a reasonable way. 598 * 599 * 2) A device which wants 2^n bytes of memory will hardwire 600 * the bottom n bits of the address to 0. As recommended, 601 * we write all 1s and see what we get back. 602 */ 603 604 rval = regs[o2i(reg)]; 605 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 606 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 607 rval64h = regs[o2i(reg + 4)]; 608 width = 8; 609 } else 610 rval64h = 0; 611 612 #ifdef _KERNEL 613 /* XXX don't size unknown memory type? */ 614 if (rval != 0 && sizebar) { 615 /* 616 * The following sequence seems to make some devices 617 * (e.g. host bus bridges, which don't normally 618 * have their space mapped) very unhappy, to 619 * the point of crashing the system. 620 * 621 * Therefore, if the mapping register is zero to 622 * start out with, don't bother trying. 623 */ 624 s = splhigh(); 625 pci_conf_write(pc, tag, reg, 0xffffffff); 626 mask = pci_conf_read(pc, tag, reg); 627 pci_conf_write(pc, tag, reg, rval); 628 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 629 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 630 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 631 mask64h = pci_conf_read(pc, tag, reg + 4); 632 pci_conf_write(pc, tag, reg + 4, rval64h); 633 } else 634 mask64h = 0; 635 splx(s); 636 } else 637 mask = mask64h = 0; 638 #endif /* _KERNEL */ 639 640 printf(" Base address register at 0x%02x", reg); 641 if (name) 642 printf(" (%s)", name); 643 printf("\n "); 644 if (rval == 0) { 645 printf("not implemented(?)\n"); 646 return width; 647 } 648 printf("type: "); 649 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 650 const char *type, *prefetch; 651 652 switch (PCI_MAPREG_MEM_TYPE(rval)) { 653 case PCI_MAPREG_MEM_TYPE_32BIT: 654 type = "32-bit"; 655 break; 656 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 657 type = "32-bit-1M"; 658 break; 659 case PCI_MAPREG_MEM_TYPE_64BIT: 660 type = "64-bit"; 661 break; 662 default: 663 type = "unknown (XXX)"; 664 break; 665 } 666 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 667 prefetch = ""; 668 else 669 prefetch = "non"; 670 printf("%s %sprefetchable memory\n", type, prefetch); 671 switch (PCI_MAPREG_MEM_TYPE(rval)) { 672 case PCI_MAPREG_MEM_TYPE_64BIT: 673 printf(" base: 0x%016llx, ", 674 PCI_MAPREG_MEM64_ADDR( 675 ((((long long) rval64h) << 32) | rval))); 676 #ifdef _KERNEL 677 if (sizebar) 678 printf("size: 0x%016llx", 679 PCI_MAPREG_MEM64_SIZE( 680 ((((long long) mask64h) << 32) | mask))); 681 else 682 #endif /* _KERNEL */ 683 printf("not sized"); 684 printf("\n"); 685 break; 686 case PCI_MAPREG_MEM_TYPE_32BIT: 687 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 688 default: 689 printf(" base: 0x%08x, ", 690 PCI_MAPREG_MEM_ADDR(rval)); 691 #ifdef _KERNEL 692 if (sizebar) 693 printf("size: 0x%08x", 694 PCI_MAPREG_MEM_SIZE(mask)); 695 else 696 #endif /* _KERNEL */ 697 printf("not sized"); 698 printf("\n"); 699 break; 700 } 701 } else { 702 #ifdef _KERNEL 703 if (sizebar) 704 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 705 #endif /* _KERNEL */ 706 printf("i/o\n"); 707 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 708 #ifdef _KERNEL 709 if (sizebar) 710 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 711 else 712 #endif /* _KERNEL */ 713 printf("not sized"); 714 printf("\n"); 715 } 716 717 return width; 718 } 719 720 static void 721 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 722 { 723 int off, needaddr, neednl; 724 725 needaddr = 1; 726 neednl = 0; 727 for (off = first; off < pastlast; off += 4) { 728 if ((off % 16) == 0 || needaddr) { 729 printf(" 0x%02x:", off); 730 needaddr = 0; 731 } 732 printf(" 0x%08x", regs[o2i(off)]); 733 neednl = 1; 734 if ((off % 16) == 12) { 735 printf("\n"); 736 neednl = 0; 737 } 738 } 739 if (neednl) 740 printf("\n"); 741 } 742 743 static void 744 pci_conf_print_type0( 745 #ifdef _KERNEL 746 pci_chipset_tag_t pc, pcitag_t tag, 747 #endif 748 const pcireg_t *regs 749 #ifdef _KERNEL 750 , int sizebars 751 #endif 752 ) 753 { 754 int off, width; 755 pcireg_t rval; 756 757 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 758 #ifdef _KERNEL 759 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 760 #else 761 width = pci_conf_print_bar(regs, off, NULL); 762 #endif 763 } 764 765 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 766 767 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 768 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 769 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 770 771 /* XXX */ 772 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 773 774 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 775 printf(" Capability list pointer: 0x%02x\n", 776 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 777 else 778 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 779 780 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 781 782 rval = regs[o2i(PCI_INTERRUPT_REG)]; 783 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 784 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 785 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 786 switch (PCI_INTERRUPT_PIN(rval)) { 787 case PCI_INTERRUPT_PIN_NONE: 788 printf("(none)"); 789 break; 790 case PCI_INTERRUPT_PIN_A: 791 printf("(pin A)"); 792 break; 793 case PCI_INTERRUPT_PIN_B: 794 printf("(pin B)"); 795 break; 796 case PCI_INTERRUPT_PIN_C: 797 printf("(pin C)"); 798 break; 799 case PCI_INTERRUPT_PIN_D: 800 printf("(pin D)"); 801 break; 802 default: 803 printf("(? ? ?)"); 804 break; 805 } 806 printf("\n"); 807 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 808 } 809 810 static void 811 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 812 { 813 bool check_slot = false; 814 static const char * const linkspeeds[] = {"2.5", "5.0", "8.0"}; 815 816 printf("\n PCI Express Capabilities Register\n"); 817 printf(" Capability version: %x\n", 818 (unsigned int)((regs[o2i(capoff)] & 0x000f0000) >> 16)); 819 printf(" Device type: "); 820 switch ((regs[o2i(capoff)] & 0x00f00000) >> 20) { 821 case 0x0: 822 printf("PCI Express Endpoint device\n"); 823 break; 824 case 0x1: 825 printf("Legacy PCI Express Endpoint device\n"); 826 break; 827 case 0x4: 828 printf("Root Port of PCI Express Root Complex\n"); 829 check_slot = true; 830 break; 831 case 0x5: 832 printf("Upstream Port of PCI Express Switch\n"); 833 break; 834 case 0x6: 835 printf("Downstream Port of PCI Express Switch\n"); 836 check_slot = true; 837 break; 838 case 0x7: 839 printf("PCI Express to PCI/PCI-X Bridge\n"); 840 break; 841 case 0x8: 842 printf("PCI/PCI-X to PCI Express Bridge\n"); 843 break; 844 default: 845 printf("unknown\n"); 846 break; 847 } 848 if (check_slot && (regs[o2i(capoff)] & 0x01000000) != 0) 849 printf(" Slot implemented\n"); 850 printf(" Interrupt Message Number: %x\n", 851 (unsigned int)((regs[o2i(capoff)] & 0x4e000000) >> 27)); 852 printf(" Link Capabilities Register: 0x%08x\n", 853 regs[o2i(capoff + 0x0c)]); 854 printf(" Maximum Link Speed: "); 855 if ((regs[o2i(capoff + 0x0c)] & 0x000f) < 1 || 856 (regs[o2i(capoff + 0x0c)] & 0x000f) > 3) { 857 printf("unknown %u value\n", 858 (regs[o2i(capoff + 0x0c)] & 0x000f)); 859 } else { 860 printf("%sGb/s\n", linkspeeds[(regs[o2i(capoff + 0x0c)] & 0x000f) - 1]); 861 } 862 printf(" Maximum Link Width: x%u lanes\n", 863 (regs[o2i(capoff + 0x0c)] & 0x03f0) >> 4); 864 printf(" Port Number: %u\n", regs[o2i(capoff + 0x0c)] >> 24); 865 printf(" Link Status Register: 0x%04x\n", 866 regs[o2i(capoff + 0x10)] >> 16); 867 printf(" Negotiated Link Speed: "); 868 if (((regs[o2i(capoff + 0x10)] >> 16) & 0x000f) < 1 || 869 ((regs[o2i(capoff + 0x10)] >> 16) & 0x000f) > 3) { 870 printf("unknown %u value\n", 871 (regs[o2i(capoff + 0x10)] >> 16) & 0x000f); 872 } else { 873 printf("%sGb/s\n", linkspeeds[((regs[o2i(capoff + 0x10)] >> 16) & 0x000f) - 1]); 874 } 875 printf(" Negotiated Link Width: x%u lanes\n", 876 (regs[o2i(capoff + 0x10)] >> 20) & 0x003f); 877 if ((regs[o2i(capoff + 0x18)] & 0x07ff) != 0) { 878 printf(" Slot Control Register:\n"); 879 if ((regs[o2i(capoff + 0x18)] & 0x0001) != 0) 880 printf(" Attention Button Pressed Enabled\n"); 881 if ((regs[o2i(capoff + 0x18)] & 0x0002) != 0) 882 printf(" Power Fault Detected Enabled\n"); 883 if ((regs[o2i(capoff + 0x18)] & 0x0004) != 0) 884 printf(" MRL Sensor Changed Enabled\n"); 885 if ((regs[o2i(capoff + 0x18)] & 0x0008) != 0) 886 printf(" Presense Detected Changed Enabled\n"); 887 if ((regs[o2i(capoff + 0x18)] & 0x0010) != 0) 888 printf(" Command Completed Interrupt Enabled\n"); 889 if ((regs[o2i(capoff + 0x18)] & 0x0020) != 0) 890 printf(" Hot-Plug Interrupt Enabled\n"); 891 printf(" Attention Indicator Control: "); 892 switch ((regs[o2i(capoff + 0x18)] & 0x00c0) >> 6) { 893 case 0x0: 894 printf("reserved\n"); 895 break; 896 case 0x1: 897 printf("on\n"); 898 break; 899 case 0x2: 900 printf("blink\n"); 901 break; 902 case 0x3: 903 printf("off\n"); 904 break; 905 } 906 printf(" Power Indicator Control: "); 907 switch ((regs[o2i(capoff + 0x18)] & 0x0300) >> 8) { 908 case 0x0: 909 printf("reserved\n"); 910 break; 911 case 0x1: 912 printf("on\n"); 913 break; 914 case 0x2: 915 printf("blink\n"); 916 break; 917 case 0x3: 918 printf("off\n"); 919 break; 920 } 921 printf(" Power Controller Control: "); 922 if ((regs[o2i(capoff + 0x18)] & 0x0400) != 0) 923 printf("off\n"); 924 else 925 printf("on\n"); 926 } 927 } 928 929 static const char * 930 pci_conf_print_pcipm_cap_aux(uint16_t caps) 931 { 932 switch ((caps >> 6) & 7) { 933 case 0: return "self-powered"; 934 case 1: return "55 mA"; 935 case 2: return "100 mA"; 936 case 3: return "160 mA"; 937 case 4: return "220 mA"; 938 case 5: return "270 mA"; 939 case 6: return "320 mA"; 940 case 7: 941 default: return "375 mA"; 942 } 943 } 944 945 static const char * 946 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 947 { 948 static const char unk[] = "unknown"; 949 static const char *pmrev[8] = { 950 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 951 }; 952 if (val > 7) 953 return unk; 954 return pmrev[val]; 955 } 956 957 static void 958 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 959 { 960 uint16_t caps, pmcsr; 961 962 caps = regs[o2i(capoff)] >> 16; 963 pmcsr = regs[o2i(capoff + 0x04)] & 0xffff; 964 965 printf("\n PCI Power Management Capabilities Register\n"); 966 967 printf(" Capabilities register: 0x%04x\n", caps); 968 printf(" Version: %s\n", 969 pci_conf_print_pcipm_cap_pmrev(caps & 0x3)); 970 printf(" PME# clock: %s\n", caps & 0x4 ? "on" : "off"); 971 printf(" Device specific initialization: %s\n", 972 caps & 0x20 ? "on" : "off"); 973 printf(" 3.3V auxiliary current: %s\n", 974 pci_conf_print_pcipm_cap_aux(caps)); 975 printf(" D1 power management state support: %s\n", 976 (caps >> 9) & 1 ? "on" : "off"); 977 printf(" D2 power management state support: %s\n", 978 (caps >> 10) & 1 ? "on" : "off"); 979 printf(" PME# support: 0x%02x\n", caps >> 11); 980 981 printf(" Control/status register: 0x%04x\n", pmcsr); 982 printf(" Power state: D%d\n", pmcsr & 3); 983 printf(" PCI Express reserved: %s\n", 984 (pmcsr >> 2) & 1 ? "on" : "off"); 985 printf(" No soft reset: %s\n", (pmcsr >> 3) & 1 ? "on" : "off"); 986 printf(" PME# assertion %sabled\n", 987 (pmcsr >> 8) & 1 ? "en" : "dis"); 988 printf(" PME# status: %s\n", (pmcsr >> 15) ? "on" : "off"); 989 } 990 991 static void 992 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 993 { 994 uint32_t ctl, mmc, mme; 995 996 regs += o2i(capoff); 997 ctl = *regs++; 998 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 999 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1000 1001 printf("\n PCI Message Signaled Interrupt\n"); 1002 1003 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1004 printf(" MSI Enabled: %s\n", 1005 ctl & PCI_MSI_CTL_MSI_ENABLE ? "yes" : "no"); 1006 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1007 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1008 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1009 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1010 printf(" 64 Bit Address Capable: %s\n", 1011 ctl & PCI_MSI_CTL_64BIT_ADDR ? "yes" : "no"); 1012 printf(" Per-Vector Masking Capable: %s\n", 1013 ctl & PCI_MSI_CTL_PERVEC_MASK ? "yes" : "no"); 1014 printf(" Message Address %sregister: 0x%08x\n", 1015 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1016 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1017 printf(" Message Address %sregister: 0x%08x\n", 1018 "(upper) ", *regs++); 1019 } 1020 printf(" Message Data register: 0x%08x\n", *regs++); 1021 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1022 printf(" Vector Mask register: 0x%08x\n", *regs++); 1023 printf(" Vector Pending register: 0x%08x\n", *regs++); 1024 } 1025 } 1026 static void 1027 pci_conf_print_caplist( 1028 #ifdef _KERNEL 1029 pci_chipset_tag_t pc, pcitag_t tag, 1030 #endif 1031 const pcireg_t *regs, int capoff) 1032 { 1033 int off; 1034 pcireg_t rval; 1035 int pcie_off = -1, pcipm_off = -1, msi_off = -1; 1036 1037 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 1038 off != 0; 1039 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 1040 rval = regs[o2i(off)]; 1041 printf(" Capability register at 0x%02x\n", off); 1042 1043 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 1044 switch (PCI_CAPLIST_CAP(rval)) { 1045 case PCI_CAP_RESERVED0: 1046 printf("reserved"); 1047 break; 1048 case PCI_CAP_PWRMGMT: 1049 printf("Power Management, rev. %s", 1050 pci_conf_print_pcipm_cap_pmrev((rval >> 0) & 0x07)); 1051 pcipm_off = off; 1052 break; 1053 case PCI_CAP_AGP: 1054 printf("AGP, rev. %d.%d", 1055 PCI_CAP_AGP_MAJOR(rval), 1056 PCI_CAP_AGP_MINOR(rval)); 1057 break; 1058 case PCI_CAP_VPD: 1059 printf("VPD"); 1060 break; 1061 case PCI_CAP_SLOTID: 1062 printf("SlotID"); 1063 break; 1064 case PCI_CAP_MSI: 1065 printf("MSI"); 1066 msi_off = off; 1067 break; 1068 case PCI_CAP_CPCI_HOTSWAP: 1069 printf("CompactPCI Hot-swapping"); 1070 break; 1071 case PCI_CAP_PCIX: 1072 printf("PCI-X"); 1073 break; 1074 case PCI_CAP_LDT: 1075 printf("LDT"); 1076 break; 1077 case PCI_CAP_VENDSPEC: 1078 printf("Vendor-specific"); 1079 break; 1080 case PCI_CAP_DEBUGPORT: 1081 printf("Debug Port"); 1082 break; 1083 case PCI_CAP_CPCI_RSRCCTL: 1084 printf("CompactPCI Resource Control"); 1085 break; 1086 case PCI_CAP_HOTPLUG: 1087 printf("Hot-Plug"); 1088 break; 1089 case PCI_CAP_AGP8: 1090 printf("AGP 8x"); 1091 break; 1092 case PCI_CAP_SECURE: 1093 printf("Secure Device"); 1094 break; 1095 case PCI_CAP_PCIEXPRESS: 1096 printf("PCI Express"); 1097 pcie_off = off; 1098 break; 1099 case PCI_CAP_MSIX: 1100 printf("MSI-X"); 1101 break; 1102 case PCI_CAP_SATA: 1103 printf("SATA"); 1104 break; 1105 case PCI_CAP_PCIAF: 1106 printf("Advanced Features"); 1107 break; 1108 default: 1109 printf("unknown"); 1110 } 1111 printf(")\n"); 1112 } 1113 if (msi_off != -1) 1114 pci_conf_print_msi_cap(regs, msi_off); 1115 if (pcipm_off != -1) 1116 pci_conf_print_pcipm_cap(regs, pcipm_off); 1117 if (pcie_off != -1) 1118 pci_conf_print_pcie_cap(regs, pcie_off); 1119 } 1120 1121 /* Print the Secondary Status Register. */ 1122 static void 1123 pci_conf_print_ssr(pcireg_t rval) 1124 { 1125 pcireg_t devsel; 1126 1127 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 1128 onoff("66 MHz capable", __BIT(5)); 1129 onoff("User Definable Features (UDF) support", __BIT(6)); 1130 onoff("Fast back-to-back capable", __BIT(7)); 1131 onoff("Data parity error detected", __BIT(8)); 1132 1133 printf(" DEVSEL timing: "); 1134 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 1135 switch (devsel) { 1136 case 0: 1137 printf("fast"); 1138 break; 1139 case 1: 1140 printf("medium"); 1141 break; 1142 case 2: 1143 printf("slow"); 1144 break; 1145 default: 1146 printf("unknown/reserved"); /* XXX */ 1147 break; 1148 } 1149 printf(" (0x%x)\n", devsel); 1150 1151 onoff("Signalled target abort", __BIT(11)); 1152 onoff("Received target abort", __BIT(12)); 1153 onoff("Received master abort", __BIT(13)); 1154 onoff("Received system error", __BIT(14)); 1155 onoff("Detected parity error", __BIT(15)); 1156 } 1157 1158 static void 1159 pci_conf_print_type1( 1160 #ifdef _KERNEL 1161 pci_chipset_tag_t pc, pcitag_t tag, 1162 #endif 1163 const pcireg_t *regs 1164 #ifdef _KERNEL 1165 , int sizebars 1166 #endif 1167 ) 1168 { 1169 int off, width; 1170 pcireg_t rval; 1171 1172 /* 1173 * XXX these need to be printed in more detail, need to be 1174 * XXX checked against specs/docs, etc. 1175 * 1176 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 1177 * Bridge chip documentation, and may not be correct with 1178 * respect to various standards. (XXX) 1179 */ 1180 1181 for (off = 0x10; off < 0x18; off += width) { 1182 #ifdef _KERNEL 1183 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 1184 #else 1185 width = pci_conf_print_bar(regs, off, NULL); 1186 #endif 1187 } 1188 1189 printf(" Primary bus number: 0x%02x\n", 1190 (regs[o2i(0x18)] >> 0) & 0xff); 1191 printf(" Secondary bus number: 0x%02x\n", 1192 (regs[o2i(0x18)] >> 8) & 0xff); 1193 printf(" Subordinate bus number: 0x%02x\n", 1194 (regs[o2i(0x18)] >> 16) & 0xff); 1195 printf(" Secondary bus latency timer: 0x%02x\n", 1196 (regs[o2i(0x18)] >> 24) & 0xff); 1197 1198 pci_conf_print_ssr(__SHIFTOUT(regs[o2i(0x1c)], __BITS(31, 16))); 1199 1200 /* XXX Print more prettily */ 1201 printf(" I/O region:\n"); 1202 printf(" base register: 0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff); 1203 printf(" limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff); 1204 printf(" base upper 16 bits register: 0x%04x\n", 1205 (regs[o2i(0x30)] >> 0) & 0xffff); 1206 printf(" limit upper 16 bits register: 0x%04x\n", 1207 (regs[o2i(0x30)] >> 16) & 0xffff); 1208 1209 /* XXX Print more prettily */ 1210 printf(" Memory region:\n"); 1211 printf(" base register: 0x%04x\n", 1212 (regs[o2i(0x20)] >> 0) & 0xffff); 1213 printf(" limit register: 0x%04x\n", 1214 (regs[o2i(0x20)] >> 16) & 0xffff); 1215 1216 /* XXX Print more prettily */ 1217 printf(" Prefetchable memory region:\n"); 1218 printf(" base register: 0x%04x\n", 1219 (regs[o2i(0x24)] >> 0) & 0xffff); 1220 printf(" limit register: 0x%04x\n", 1221 (regs[o2i(0x24)] >> 16) & 0xffff); 1222 printf(" base upper 32 bits register: 0x%08x\n", regs[o2i(0x28)]); 1223 printf(" limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]); 1224 1225 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1226 printf(" Capability list pointer: 0x%02x\n", 1227 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 1228 else 1229 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 1230 1231 /* XXX */ 1232 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 1233 1234 printf(" Interrupt line: 0x%02x\n", 1235 (regs[o2i(0x3c)] >> 0) & 0xff); 1236 printf(" Interrupt pin: 0x%02x ", 1237 (regs[o2i(0x3c)] >> 8) & 0xff); 1238 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1239 case PCI_INTERRUPT_PIN_NONE: 1240 printf("(none)"); 1241 break; 1242 case PCI_INTERRUPT_PIN_A: 1243 printf("(pin A)"); 1244 break; 1245 case PCI_INTERRUPT_PIN_B: 1246 printf("(pin B)"); 1247 break; 1248 case PCI_INTERRUPT_PIN_C: 1249 printf("(pin C)"); 1250 break; 1251 case PCI_INTERRUPT_PIN_D: 1252 printf("(pin D)"); 1253 break; 1254 default: 1255 printf("(? ? ?)"); 1256 break; 1257 } 1258 printf("\n"); 1259 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1260 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 1261 onoff("Parity error response", 0x0001); 1262 onoff("Secondary SERR forwarding", 0x0002); 1263 onoff("ISA enable", 0x0004); 1264 onoff("VGA enable", 0x0008); 1265 onoff("Master abort reporting", 0x0020); 1266 onoff("Secondary bus reset", 0x0040); 1267 onoff("Fast back-to-back capable", 0x0080); 1268 } 1269 1270 static void 1271 pci_conf_print_type2( 1272 #ifdef _KERNEL 1273 pci_chipset_tag_t pc, pcitag_t tag, 1274 #endif 1275 const pcireg_t *regs 1276 #ifdef _KERNEL 1277 , int sizebars 1278 #endif 1279 ) 1280 { 1281 pcireg_t rval; 1282 1283 /* 1284 * XXX these need to be printed in more detail, need to be 1285 * XXX checked against specs/docs, etc. 1286 * 1287 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 1288 * controller chip documentation, and may not be correct with 1289 * respect to various standards. (XXX) 1290 */ 1291 1292 #ifdef _KERNEL 1293 pci_conf_print_bar(pc, tag, regs, 0x10, 1294 "CardBus socket/ExCA registers", sizebars); 1295 #else 1296 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 1297 #endif 1298 1299 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1300 printf(" Capability list pointer: 0x%02x\n", 1301 PCI_CAPLIST_PTR(regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)])); 1302 else 1303 printf(" Reserved @ 0x14: 0x%04" PRIxMAX "\n", 1304 __SHIFTOUT(regs[o2i(0x14)], __BITS(15, 0))); 1305 pci_conf_print_ssr(__SHIFTOUT(regs[o2i(0x14)], __BITS(31, 16))); 1306 1307 printf(" PCI bus number: 0x%02x\n", 1308 (regs[o2i(0x18)] >> 0) & 0xff); 1309 printf(" CardBus bus number: 0x%02x\n", 1310 (regs[o2i(0x18)] >> 8) & 0xff); 1311 printf(" Subordinate bus number: 0x%02x\n", 1312 (regs[o2i(0x18)] >> 16) & 0xff); 1313 printf(" CardBus latency timer: 0x%02x\n", 1314 (regs[o2i(0x18)] >> 24) & 0xff); 1315 1316 /* XXX Print more prettily */ 1317 printf(" CardBus memory region 0:\n"); 1318 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 1319 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 1320 printf(" CardBus memory region 1:\n"); 1321 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 1322 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 1323 printf(" CardBus I/O region 0:\n"); 1324 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 1325 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 1326 printf(" CardBus I/O region 1:\n"); 1327 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 1328 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 1329 1330 printf(" Interrupt line: 0x%02x\n", 1331 (regs[o2i(0x3c)] >> 0) & 0xff); 1332 printf(" Interrupt pin: 0x%02x ", 1333 (regs[o2i(0x3c)] >> 8) & 0xff); 1334 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1335 case PCI_INTERRUPT_PIN_NONE: 1336 printf("(none)"); 1337 break; 1338 case PCI_INTERRUPT_PIN_A: 1339 printf("(pin A)"); 1340 break; 1341 case PCI_INTERRUPT_PIN_B: 1342 printf("(pin B)"); 1343 break; 1344 case PCI_INTERRUPT_PIN_C: 1345 printf("(pin C)"); 1346 break; 1347 case PCI_INTERRUPT_PIN_D: 1348 printf("(pin D)"); 1349 break; 1350 default: 1351 printf("(? ? ?)"); 1352 break; 1353 } 1354 printf("\n"); 1355 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1356 printf(" Bridge control register: 0x%04x\n", rval); 1357 onoff("Parity error response", __BIT(0)); 1358 onoff("SERR# enable", __BIT(1)); 1359 onoff("ISA enable", __BIT(2)); 1360 onoff("VGA enable", __BIT(3)); 1361 onoff("Master abort mode", __BIT(5)); 1362 onoff("Secondary (CardBus) bus reset", __BIT(6)); 1363 onoff("Functional interrupts routed by ExCA registers", __BIT(7)); 1364 onoff("Memory window 0 prefetchable", __BIT(8)); 1365 onoff("Memory window 1 prefetchable", __BIT(9)); 1366 onoff("Write posting enable", __BIT(10)); 1367 1368 rval = regs[o2i(0x40)]; 1369 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 1370 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 1371 1372 #ifdef _KERNEL 1373 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 1374 sizebars); 1375 #else 1376 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 1377 #endif 1378 } 1379 1380 void 1381 pci_conf_print( 1382 #ifdef _KERNEL 1383 pci_chipset_tag_t pc, pcitag_t tag, 1384 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 1385 #else 1386 int pcifd, u_int bus, u_int dev, u_int func 1387 #endif 1388 ) 1389 { 1390 pcireg_t regs[o2i(256)]; 1391 int off, capoff, endoff, hdrtype; 1392 const char *typename; 1393 #ifdef _KERNEL 1394 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, int); 1395 int sizebars; 1396 #else 1397 void (*typeprintfn)(const pcireg_t *); 1398 #endif 1399 1400 printf("PCI configuration registers:\n"); 1401 1402 for (off = 0; off < 256; off += 4) { 1403 #ifdef _KERNEL 1404 regs[o2i(off)] = pci_conf_read(pc, tag, off); 1405 #else 1406 if (pcibus_conf_read(pcifd, bus, dev, func, off, 1407 ®s[o2i(off)]) == -1) 1408 regs[o2i(off)] = 0; 1409 #endif 1410 } 1411 1412 #ifdef _KERNEL 1413 sizebars = 1; 1414 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 1415 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 1416 sizebars = 0; 1417 #endif 1418 1419 /* common header */ 1420 printf(" Common header:\n"); 1421 pci_conf_print_regs(regs, 0, 16); 1422 1423 printf("\n"); 1424 #ifdef _KERNEL 1425 pci_conf_print_common(pc, tag, regs); 1426 #else 1427 pci_conf_print_common(regs); 1428 #endif 1429 printf("\n"); 1430 1431 /* type-dependent header */ 1432 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 1433 switch (hdrtype) { /* XXX make a table, eventually */ 1434 case 0: 1435 /* Standard device header */ 1436 typename = "\"normal\" device"; 1437 typeprintfn = &pci_conf_print_type0; 1438 capoff = PCI_CAPLISTPTR_REG; 1439 endoff = 64; 1440 break; 1441 case 1: 1442 /* PCI-PCI bridge header */ 1443 typename = "PCI-PCI bridge"; 1444 typeprintfn = &pci_conf_print_type1; 1445 capoff = PCI_CAPLISTPTR_REG; 1446 endoff = 64; 1447 break; 1448 case 2: 1449 /* PCI-CardBus bridge header */ 1450 typename = "PCI-CardBus bridge"; 1451 typeprintfn = &pci_conf_print_type2; 1452 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 1453 endoff = 72; 1454 break; 1455 default: 1456 typename = NULL; 1457 typeprintfn = 0; 1458 capoff = -1; 1459 endoff = 64; 1460 break; 1461 } 1462 printf(" Type %d ", hdrtype); 1463 if (typename != NULL) 1464 printf("(%s) ", typename); 1465 printf("header:\n"); 1466 pci_conf_print_regs(regs, 16, endoff); 1467 printf("\n"); 1468 if (typeprintfn) { 1469 #ifdef _KERNEL 1470 (*typeprintfn)(pc, tag, regs, sizebars); 1471 #else 1472 (*typeprintfn)(regs); 1473 #endif 1474 } else 1475 printf(" Don't know how to pretty-print type %d header.\n", 1476 hdrtype); 1477 printf("\n"); 1478 1479 /* capability list, if present */ 1480 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1481 && (capoff > 0)) { 1482 #ifdef _KERNEL 1483 pci_conf_print_caplist(pc, tag, regs, capoff); 1484 #else 1485 pci_conf_print_caplist(regs, capoff); 1486 #endif 1487 printf("\n"); 1488 } 1489 1490 /* device-dependent header */ 1491 printf(" Device-dependent header:\n"); 1492 pci_conf_print_regs(regs, endoff, 256); 1493 printf("\n"); 1494 #ifdef _KERNEL 1495 if (printfn) 1496 (*printfn)(pc, tag, regs); 1497 else 1498 printf(" Don't know how to pretty-print device-dependent header.\n"); 1499 printf("\n"); 1500 #endif /* _KERNEL */ 1501 } 1502