1 /* $NetBSD: pci_map.c,v 1.23 2008/04/28 20:23:55 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum; by William R. Studenmund; by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * PCI device mapping. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: pci_map.c,v 1.23 2008/04/28 20:23:55 martin Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pcivar.h> 45 46 static int 47 pci_io_find(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type, 48 bus_addr_t *basep, bus_size_t *sizep, int *flagsp) 49 { 50 pcireg_t address, mask; 51 int s; 52 53 if (reg < PCI_MAPREG_START || 54 #if 0 55 /* 56 * Can't do this check; some devices have mapping registers 57 * way out in left field. 58 */ 59 reg >= PCI_MAPREG_END || 60 #endif 61 (reg & 3)) 62 panic("pci_io_find: bad request"); 63 64 /* 65 * Section 6.2.5.1, `Address Maps', tells us that: 66 * 67 * 1) The builtin software should have already mapped the device in a 68 * reasonable way. 69 * 70 * 2) A device which wants 2^n bytes of memory will hardwire the bottom 71 * n bits of the address to 0. As recommended, we write all 1s and see 72 * what we get back. 73 */ 74 s = splhigh(); 75 address = pci_conf_read(pc, tag, reg); 76 pci_conf_write(pc, tag, reg, 0xffffffff); 77 mask = pci_conf_read(pc, tag, reg); 78 pci_conf_write(pc, tag, reg, address); 79 splx(s); 80 81 if (PCI_MAPREG_TYPE(address) != PCI_MAPREG_TYPE_IO) { 82 aprint_debug("pci_io_find: expected type i/o, found mem\n"); 83 return (1); 84 } 85 86 if (PCI_MAPREG_IO_SIZE(mask) == 0) { 87 aprint_debug("pci_io_find: void region\n"); 88 return (1); 89 } 90 91 if (basep != 0) 92 *basep = PCI_MAPREG_IO_ADDR(address); 93 if (sizep != 0) 94 *sizep = PCI_MAPREG_IO_SIZE(mask); 95 if (flagsp != 0) 96 *flagsp = 0; 97 98 return (0); 99 } 100 101 static int 102 pci_mem_find(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type, 103 bus_addr_t *basep, bus_size_t *sizep, int *flagsp) 104 { 105 pcireg_t address, mask, address1 = 0, mask1 = 0xffffffff; 106 u_int64_t waddress, wmask; 107 int s, is64bit, isrom; 108 109 is64bit = (PCI_MAPREG_MEM_TYPE(type) == PCI_MAPREG_MEM_TYPE_64BIT); 110 isrom = (reg == PCI_MAPREG_ROM); 111 112 if ((!isrom) && (reg < PCI_MAPREG_START || 113 #if 0 114 /* 115 * Can't do this check; some devices have mapping registers 116 * way out in left field. 117 */ 118 reg >= PCI_MAPREG_END || 119 #endif 120 (reg & 3))) 121 panic("pci_mem_find: bad request"); 122 123 if (is64bit && (reg + 4) >= PCI_MAPREG_END) 124 panic("pci_mem_find: bad 64-bit request"); 125 126 /* 127 * Section 6.2.5.1, `Address Maps', tells us that: 128 * 129 * 1) The builtin software should have already mapped the device in a 130 * reasonable way. 131 * 132 * 2) A device which wants 2^n bytes of memory will hardwire the bottom 133 * n bits of the address to 0. As recommended, we write all 1s and see 134 * what we get back. 135 */ 136 s = splhigh(); 137 address = pci_conf_read(pc, tag, reg); 138 pci_conf_write(pc, tag, reg, 0xffffffff); 139 mask = pci_conf_read(pc, tag, reg); 140 pci_conf_write(pc, tag, reg, address); 141 if (is64bit) { 142 address1 = pci_conf_read(pc, tag, reg + 4); 143 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 144 mask1 = pci_conf_read(pc, tag, reg + 4); 145 pci_conf_write(pc, tag, reg + 4, address1); 146 } 147 splx(s); 148 149 if (!isrom) { 150 /* 151 * roms should have an enable bit instead of a memory 152 * type decoder bit. For normal BARs, make sure that 153 * the address decoder type matches what we asked for. 154 */ 155 if (PCI_MAPREG_TYPE(address) != PCI_MAPREG_TYPE_MEM) { 156 printf("pci_mem_find: expected type mem, found i/o\n"); 157 return (1); 158 } 159 /* XXX Allow 64bit bars for 32bit requests.*/ 160 if (PCI_MAPREG_MEM_TYPE(address) != 161 PCI_MAPREG_MEM_TYPE(type) && 162 PCI_MAPREG_MEM_TYPE(address) != 163 PCI_MAPREG_MEM_TYPE_64BIT) { 164 printf("pci_mem_find: " 165 "expected mem type %08x, found %08x\n", 166 PCI_MAPREG_MEM_TYPE(type), 167 PCI_MAPREG_MEM_TYPE(address)); 168 return (1); 169 } 170 } 171 172 waddress = (u_int64_t)address1 << 32UL | address; 173 wmask = (u_int64_t)mask1 << 32UL | mask; 174 175 if ((is64bit && PCI_MAPREG_MEM64_SIZE(wmask) == 0) || 176 (!is64bit && PCI_MAPREG_MEM_SIZE(mask) == 0)) { 177 aprint_debug("pci_mem_find: void region\n"); 178 return (1); 179 } 180 181 switch (PCI_MAPREG_MEM_TYPE(address)) { 182 case PCI_MAPREG_MEM_TYPE_32BIT: 183 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 184 break; 185 case PCI_MAPREG_MEM_TYPE_64BIT: 186 /* 187 * Handle the case of a 64-bit memory register on a 188 * platform with 32-bit addressing. Make sure that 189 * the address assigned and the device's memory size 190 * fit in 32 bits. We implicitly assume that if 191 * bus_addr_t is 64-bit, then so is bus_size_t. 192 */ 193 if (sizeof(u_int64_t) > sizeof(bus_addr_t) && 194 (address1 != 0 || mask1 != 0xffffffff)) { 195 printf("pci_mem_find: 64-bit memory map which is " 196 "inaccessible on a 32-bit platform\n"); 197 return (1); 198 } 199 break; 200 default: 201 printf("pci_mem_find: reserved mapping register type\n"); 202 return (1); 203 } 204 205 if (sizeof(u_int64_t) > sizeof(bus_addr_t)) { 206 if (basep != 0) 207 *basep = PCI_MAPREG_MEM_ADDR(address); 208 if (sizep != 0) 209 *sizep = PCI_MAPREG_MEM_SIZE(mask); 210 } else { 211 if (basep != 0) 212 *basep = PCI_MAPREG_MEM64_ADDR(waddress); 213 if (sizep != 0) 214 *sizep = PCI_MAPREG_MEM64_SIZE(wmask); 215 } 216 if (flagsp != 0) 217 *flagsp = (isrom || PCI_MAPREG_MEM_PREFETCHABLE(address)) ? 218 BUS_SPACE_MAP_PREFETCHABLE : 0; 219 220 return (0); 221 } 222 223 #define _PCI_MAPREG_TYPEBITS(reg) \ 224 (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO ? \ 225 reg & PCI_MAPREG_TYPE_MASK : \ 226 reg & (PCI_MAPREG_TYPE_MASK|PCI_MAPREG_MEM_TYPE_MASK)) 227 228 pcireg_t 229 pci_mapreg_type(pci_chipset_tag_t pc, pcitag_t tag, int reg) 230 { 231 232 return (_PCI_MAPREG_TYPEBITS(pci_conf_read(pc, tag, reg))); 233 } 234 235 int 236 pci_mapreg_probe(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t *typep) 237 { 238 pcireg_t address, mask; 239 int s; 240 241 s = splhigh(); 242 address = pci_conf_read(pc, tag, reg); 243 pci_conf_write(pc, tag, reg, 0xffffffff); 244 mask = pci_conf_read(pc, tag, reg); 245 pci_conf_write(pc, tag, reg, address); 246 splx(s); 247 248 if (mask == 0) /* unimplemented mapping register */ 249 return (0); 250 251 if (typep) 252 *typep = _PCI_MAPREG_TYPEBITS(address); 253 return (1); 254 } 255 256 int 257 pci_mapreg_info(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type, 258 bus_addr_t *basep, bus_size_t *sizep, int *flagsp) 259 { 260 261 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) 262 return (pci_io_find(pc, tag, reg, type, basep, sizep, 263 flagsp)); 264 else 265 return (pci_mem_find(pc, tag, reg, type, basep, sizep, 266 flagsp)); 267 } 268 269 int 270 pci_mapreg_map(struct pci_attach_args *pa, int reg, pcireg_t type, 271 int busflags, bus_space_tag_t *tagp, bus_space_handle_t *handlep, 272 bus_addr_t *basep, bus_size_t *sizep) 273 { 274 bus_space_tag_t tag; 275 bus_space_handle_t handle; 276 bus_addr_t base; 277 bus_size_t size; 278 int flags; 279 280 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) { 281 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) 282 return (1); 283 if (pci_io_find(pa->pa_pc, pa->pa_tag, reg, type, &base, 284 &size, &flags)) 285 return (1); 286 tag = pa->pa_iot; 287 } else { 288 if ((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) == 0) 289 return (1); 290 if (pci_mem_find(pa->pa_pc, pa->pa_tag, reg, type, &base, 291 &size, &flags)) 292 return (1); 293 tag = pa->pa_memt; 294 } 295 296 if (reg == PCI_MAPREG_ROM) { 297 pcireg_t mask; 298 int s; 299 /* we have to enable the ROM address decoder... */ 300 s = splhigh(); 301 mask = pci_conf_read(pa->pa_pc, pa->pa_tag, reg); 302 mask |= PCI_MAPREG_ROM_ENABLE; 303 pci_conf_write(pa->pa_pc, pa->pa_tag, reg, mask); 304 splx(s); 305 } 306 307 if (bus_space_map(tag, base, size, busflags | flags, &handle)) 308 return (1); 309 310 if (tagp != 0) 311 *tagp = tag; 312 if (handlep != 0) 313 *handlep = handle; 314 if (basep != 0) 315 *basep = base; 316 if (sizep != 0) 317 *sizep = size; 318 319 return (0); 320 } 321 322 int 323 pci_find_rom(struct pci_attach_args *pa, bus_space_tag_t bst, 324 bus_space_handle_t bsh, int type, bus_space_handle_t *romh, bus_size_t *sz) 325 { 326 bus_size_t romsz, offset = 0, imagesz; 327 uint16_t ptr; 328 int done = 0; 329 330 if (pci_mem_find(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 331 PCI_MAPREG_TYPE_ROM, NULL, &romsz, NULL)) 332 return 1; 333 334 /* 335 * no upper bound check; i cannot imagine a 4GB ROM, but 336 * it appears the spec would allow it! 337 */ 338 if (romsz < 1024) 339 return 1; 340 341 while (offset < romsz && !done){ 342 struct pci_rom_header hdr; 343 struct pci_rom rom; 344 345 hdr.romh_magic = bus_space_read_2(bst, bsh, 346 offset + offsetof (struct pci_rom_header, romh_magic)); 347 hdr.romh_data_ptr = bus_space_read_2(bst, bsh, 348 offset + offsetof (struct pci_rom_header, romh_data_ptr)); 349 350 /* no warning: quite possibly ROM is simply not populated */ 351 if (hdr.romh_magic != PCI_ROM_HEADER_MAGIC) 352 return 1; 353 354 ptr = offset + hdr.romh_data_ptr; 355 356 if (ptr > romsz) { 357 printf("pci_find_rom: rom data ptr out of range\n"); 358 return 1; 359 } 360 361 rom.rom_signature = bus_space_read_4(bst, bsh, ptr); 362 rom.rom_vendor = bus_space_read_2(bst, bsh, ptr + 363 offsetof(struct pci_rom, rom_vendor)); 364 rom.rom_product = bus_space_read_2(bst, bsh, ptr + 365 offsetof(struct pci_rom, rom_product)); 366 rom.rom_class = bus_space_read_1(bst, bsh, 367 ptr + offsetof (struct pci_rom, rom_class)); 368 rom.rom_subclass = bus_space_read_1(bst, bsh, 369 ptr + offsetof (struct pci_rom, rom_subclass)); 370 rom.rom_interface = bus_space_read_1(bst, bsh, 371 ptr + offsetof (struct pci_rom, rom_interface)); 372 rom.rom_len = bus_space_read_2(bst, bsh, 373 ptr + offsetof (struct pci_rom, rom_len)); 374 rom.rom_code_type = bus_space_read_1(bst, bsh, 375 ptr + offsetof (struct pci_rom, rom_code_type)); 376 rom.rom_indicator = bus_space_read_1(bst, bsh, 377 ptr + offsetof (struct pci_rom, rom_indicator)); 378 379 if (rom.rom_signature != PCI_ROM_SIGNATURE) { 380 printf("pci_find_rom: bad rom data signature\n"); 381 return 1; 382 } 383 384 imagesz = rom.rom_len * 512; 385 386 if ((rom.rom_vendor == PCI_VENDOR(pa->pa_id)) && 387 (rom.rom_product == PCI_PRODUCT(pa->pa_id)) && 388 (rom.rom_class == PCI_CLASS(pa->pa_class)) && 389 (rom.rom_subclass == PCI_SUBCLASS(pa->pa_class)) && 390 (rom.rom_interface == PCI_INTERFACE(pa->pa_class)) && 391 (rom.rom_code_type == type)) { 392 *sz = imagesz; 393 bus_space_subregion(bst, bsh, offset, imagesz, romh); 394 return 0; 395 } 396 397 /* last image check */ 398 if (rom.rom_indicator & PCI_ROM_INDICATOR_LAST) 399 return 1; 400 401 /* offset by size */ 402 offset += imagesz; 403 } 404 return 1; 405 } 406