1 /* $NetBSD: pci_map.c,v 1.22 2007/12/01 06:05:18 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum; by William R. Studenmund; by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * PCI device mapping. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: pci_map.c,v 1.22 2007/12/01 06:05:18 jmcneill Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 53 static int 54 pci_io_find(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type, 55 bus_addr_t *basep, bus_size_t *sizep, int *flagsp) 56 { 57 pcireg_t address, mask; 58 int s; 59 60 if (reg < PCI_MAPREG_START || 61 #if 0 62 /* 63 * Can't do this check; some devices have mapping registers 64 * way out in left field. 65 */ 66 reg >= PCI_MAPREG_END || 67 #endif 68 (reg & 3)) 69 panic("pci_io_find: bad request"); 70 71 /* 72 * Section 6.2.5.1, `Address Maps', tells us that: 73 * 74 * 1) The builtin software should have already mapped the device in a 75 * reasonable way. 76 * 77 * 2) A device which wants 2^n bytes of memory will hardwire the bottom 78 * n bits of the address to 0. As recommended, we write all 1s and see 79 * what we get back. 80 */ 81 s = splhigh(); 82 address = pci_conf_read(pc, tag, reg); 83 pci_conf_write(pc, tag, reg, 0xffffffff); 84 mask = pci_conf_read(pc, tag, reg); 85 pci_conf_write(pc, tag, reg, address); 86 splx(s); 87 88 if (PCI_MAPREG_TYPE(address) != PCI_MAPREG_TYPE_IO) { 89 aprint_debug("pci_io_find: expected type i/o, found mem\n"); 90 return (1); 91 } 92 93 if (PCI_MAPREG_IO_SIZE(mask) == 0) { 94 aprint_debug("pci_io_find: void region\n"); 95 return (1); 96 } 97 98 if (basep != 0) 99 *basep = PCI_MAPREG_IO_ADDR(address); 100 if (sizep != 0) 101 *sizep = PCI_MAPREG_IO_SIZE(mask); 102 if (flagsp != 0) 103 *flagsp = 0; 104 105 return (0); 106 } 107 108 static int 109 pci_mem_find(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type, 110 bus_addr_t *basep, bus_size_t *sizep, int *flagsp) 111 { 112 pcireg_t address, mask, address1 = 0, mask1 = 0xffffffff; 113 u_int64_t waddress, wmask; 114 int s, is64bit, isrom; 115 116 is64bit = (PCI_MAPREG_MEM_TYPE(type) == PCI_MAPREG_MEM_TYPE_64BIT); 117 isrom = (reg == PCI_MAPREG_ROM); 118 119 if ((!isrom) && (reg < PCI_MAPREG_START || 120 #if 0 121 /* 122 * Can't do this check; some devices have mapping registers 123 * way out in left field. 124 */ 125 reg >= PCI_MAPREG_END || 126 #endif 127 (reg & 3))) 128 panic("pci_mem_find: bad request"); 129 130 if (is64bit && (reg + 4) >= PCI_MAPREG_END) 131 panic("pci_mem_find: bad 64-bit request"); 132 133 /* 134 * Section 6.2.5.1, `Address Maps', tells us that: 135 * 136 * 1) The builtin software should have already mapped the device in a 137 * reasonable way. 138 * 139 * 2) A device which wants 2^n bytes of memory will hardwire the bottom 140 * n bits of the address to 0. As recommended, we write all 1s and see 141 * what we get back. 142 */ 143 s = splhigh(); 144 address = pci_conf_read(pc, tag, reg); 145 pci_conf_write(pc, tag, reg, 0xffffffff); 146 mask = pci_conf_read(pc, tag, reg); 147 pci_conf_write(pc, tag, reg, address); 148 if (is64bit) { 149 address1 = pci_conf_read(pc, tag, reg + 4); 150 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 151 mask1 = pci_conf_read(pc, tag, reg + 4); 152 pci_conf_write(pc, tag, reg + 4, address1); 153 } 154 splx(s); 155 156 if (!isrom) { 157 /* 158 * roms should have an enable bit instead of a memory 159 * type decoder bit. For normal BARs, make sure that 160 * the address decoder type matches what we asked for. 161 */ 162 if (PCI_MAPREG_TYPE(address) != PCI_MAPREG_TYPE_MEM) { 163 printf("pci_mem_find: expected type mem, found i/o\n"); 164 return (1); 165 } 166 /* XXX Allow 64bit bars for 32bit requests.*/ 167 if (PCI_MAPREG_MEM_TYPE(address) != 168 PCI_MAPREG_MEM_TYPE(type) && 169 PCI_MAPREG_MEM_TYPE(address) != 170 PCI_MAPREG_MEM_TYPE_64BIT) { 171 printf("pci_mem_find: " 172 "expected mem type %08x, found %08x\n", 173 PCI_MAPREG_MEM_TYPE(type), 174 PCI_MAPREG_MEM_TYPE(address)); 175 return (1); 176 } 177 } 178 179 waddress = (u_int64_t)address1 << 32UL | address; 180 wmask = (u_int64_t)mask1 << 32UL | mask; 181 182 if ((is64bit && PCI_MAPREG_MEM64_SIZE(wmask) == 0) || 183 (!is64bit && PCI_MAPREG_MEM_SIZE(mask) == 0)) { 184 aprint_debug("pci_mem_find: void region\n"); 185 return (1); 186 } 187 188 switch (PCI_MAPREG_MEM_TYPE(address)) { 189 case PCI_MAPREG_MEM_TYPE_32BIT: 190 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 191 break; 192 case PCI_MAPREG_MEM_TYPE_64BIT: 193 /* 194 * Handle the case of a 64-bit memory register on a 195 * platform with 32-bit addressing. Make sure that 196 * the address assigned and the device's memory size 197 * fit in 32 bits. We implicitly assume that if 198 * bus_addr_t is 64-bit, then so is bus_size_t. 199 */ 200 if (sizeof(u_int64_t) > sizeof(bus_addr_t) && 201 (address1 != 0 || mask1 != 0xffffffff)) { 202 printf("pci_mem_find: 64-bit memory map which is " 203 "inaccessible on a 32-bit platform\n"); 204 return (1); 205 } 206 break; 207 default: 208 printf("pci_mem_find: reserved mapping register type\n"); 209 return (1); 210 } 211 212 if (sizeof(u_int64_t) > sizeof(bus_addr_t)) { 213 if (basep != 0) 214 *basep = PCI_MAPREG_MEM_ADDR(address); 215 if (sizep != 0) 216 *sizep = PCI_MAPREG_MEM_SIZE(mask); 217 } else { 218 if (basep != 0) 219 *basep = PCI_MAPREG_MEM64_ADDR(waddress); 220 if (sizep != 0) 221 *sizep = PCI_MAPREG_MEM64_SIZE(wmask); 222 } 223 if (flagsp != 0) 224 *flagsp = (isrom || PCI_MAPREG_MEM_PREFETCHABLE(address)) ? 225 BUS_SPACE_MAP_PREFETCHABLE : 0; 226 227 return (0); 228 } 229 230 #define _PCI_MAPREG_TYPEBITS(reg) \ 231 (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO ? \ 232 reg & PCI_MAPREG_TYPE_MASK : \ 233 reg & (PCI_MAPREG_TYPE_MASK|PCI_MAPREG_MEM_TYPE_MASK)) 234 235 pcireg_t 236 pci_mapreg_type(pci_chipset_tag_t pc, pcitag_t tag, int reg) 237 { 238 239 return (_PCI_MAPREG_TYPEBITS(pci_conf_read(pc, tag, reg))); 240 } 241 242 int 243 pci_mapreg_probe(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t *typep) 244 { 245 pcireg_t address, mask; 246 int s; 247 248 s = splhigh(); 249 address = pci_conf_read(pc, tag, reg); 250 pci_conf_write(pc, tag, reg, 0xffffffff); 251 mask = pci_conf_read(pc, tag, reg); 252 pci_conf_write(pc, tag, reg, address); 253 splx(s); 254 255 if (mask == 0) /* unimplemented mapping register */ 256 return (0); 257 258 if (typep) 259 *typep = _PCI_MAPREG_TYPEBITS(address); 260 return (1); 261 } 262 263 int 264 pci_mapreg_info(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type, 265 bus_addr_t *basep, bus_size_t *sizep, int *flagsp) 266 { 267 268 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) 269 return (pci_io_find(pc, tag, reg, type, basep, sizep, 270 flagsp)); 271 else 272 return (pci_mem_find(pc, tag, reg, type, basep, sizep, 273 flagsp)); 274 } 275 276 int 277 pci_mapreg_map(struct pci_attach_args *pa, int reg, pcireg_t type, 278 int busflags, bus_space_tag_t *tagp, bus_space_handle_t *handlep, 279 bus_addr_t *basep, bus_size_t *sizep) 280 { 281 bus_space_tag_t tag; 282 bus_space_handle_t handle; 283 bus_addr_t base; 284 bus_size_t size; 285 int flags; 286 287 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) { 288 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) 289 return (1); 290 if (pci_io_find(pa->pa_pc, pa->pa_tag, reg, type, &base, 291 &size, &flags)) 292 return (1); 293 tag = pa->pa_iot; 294 } else { 295 if ((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) == 0) 296 return (1); 297 if (pci_mem_find(pa->pa_pc, pa->pa_tag, reg, type, &base, 298 &size, &flags)) 299 return (1); 300 tag = pa->pa_memt; 301 } 302 303 if (reg == PCI_MAPREG_ROM) { 304 pcireg_t mask; 305 int s; 306 /* we have to enable the ROM address decoder... */ 307 s = splhigh(); 308 mask = pci_conf_read(pa->pa_pc, pa->pa_tag, reg); 309 mask |= PCI_MAPREG_ROM_ENABLE; 310 pci_conf_write(pa->pa_pc, pa->pa_tag, reg, mask); 311 splx(s); 312 } 313 314 if (bus_space_map(tag, base, size, busflags | flags, &handle)) 315 return (1); 316 317 if (tagp != 0) 318 *tagp = tag; 319 if (handlep != 0) 320 *handlep = handle; 321 if (basep != 0) 322 *basep = base; 323 if (sizep != 0) 324 *sizep = size; 325 326 return (0); 327 } 328 329 int 330 pci_find_rom(struct pci_attach_args *pa, bus_space_tag_t bst, 331 bus_space_handle_t bsh, int type, bus_space_handle_t *romh, bus_size_t *sz) 332 { 333 bus_size_t romsz, offset = 0, imagesz; 334 uint16_t ptr; 335 int done = 0; 336 337 if (pci_mem_find(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 338 PCI_MAPREG_TYPE_ROM, NULL, &romsz, NULL)) 339 return 1; 340 341 /* 342 * no upper bound check; i cannot imagine a 4GB ROM, but 343 * it appears the spec would allow it! 344 */ 345 if (romsz < 1024) 346 return 1; 347 348 while (offset < romsz && !done){ 349 struct pci_rom_header hdr; 350 struct pci_rom rom; 351 352 hdr.romh_magic = bus_space_read_2(bst, bsh, 353 offset + offsetof (struct pci_rom_header, romh_magic)); 354 hdr.romh_data_ptr = bus_space_read_2(bst, bsh, 355 offset + offsetof (struct pci_rom_header, romh_data_ptr)); 356 357 /* no warning: quite possibly ROM is simply not populated */ 358 if (hdr.romh_magic != PCI_ROM_HEADER_MAGIC) 359 return 1; 360 361 ptr = offset + hdr.romh_data_ptr; 362 363 if (ptr > romsz) { 364 printf("pci_find_rom: rom data ptr out of range\n"); 365 return 1; 366 } 367 368 rom.rom_signature = bus_space_read_4(bst, bsh, ptr); 369 rom.rom_vendor = bus_space_read_2(bst, bsh, ptr + 370 offsetof(struct pci_rom, rom_vendor)); 371 rom.rom_product = bus_space_read_2(bst, bsh, ptr + 372 offsetof(struct pci_rom, rom_product)); 373 rom.rom_class = bus_space_read_1(bst, bsh, 374 ptr + offsetof (struct pci_rom, rom_class)); 375 rom.rom_subclass = bus_space_read_1(bst, bsh, 376 ptr + offsetof (struct pci_rom, rom_subclass)); 377 rom.rom_interface = bus_space_read_1(bst, bsh, 378 ptr + offsetof (struct pci_rom, rom_interface)); 379 rom.rom_len = bus_space_read_2(bst, bsh, 380 ptr + offsetof (struct pci_rom, rom_len)); 381 rom.rom_code_type = bus_space_read_1(bst, bsh, 382 ptr + offsetof (struct pci_rom, rom_code_type)); 383 rom.rom_indicator = bus_space_read_1(bst, bsh, 384 ptr + offsetof (struct pci_rom, rom_indicator)); 385 386 if (rom.rom_signature != PCI_ROM_SIGNATURE) { 387 printf("pci_find_rom: bad rom data signature\n"); 388 return 1; 389 } 390 391 imagesz = rom.rom_len * 512; 392 393 if ((rom.rom_vendor == PCI_VENDOR(pa->pa_id)) && 394 (rom.rom_product == PCI_PRODUCT(pa->pa_id)) && 395 (rom.rom_class == PCI_CLASS(pa->pa_class)) && 396 (rom.rom_subclass == PCI_SUBCLASS(pa->pa_class)) && 397 (rom.rom_interface == PCI_INTERFACE(pa->pa_class)) && 398 (rom.rom_code_type == type)) { 399 *sz = imagesz; 400 bus_space_subregion(bst, bsh, offset, imagesz, romh); 401 return 0; 402 } 403 404 /* last image check */ 405 if (rom.rom_indicator & PCI_ROM_INDICATOR_LAST) 406 return 1; 407 408 /* offset by size */ 409 offset += imagesz; 410 } 411 return 1; 412 } 413