1 /* $NetBSD: pci_map.c,v 1.40 2020/05/05 16:58:11 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum; by William R. Studenmund; by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * PCI device mapping. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: pci_map.c,v 1.40 2020/05/05 16:58:11 bouyer Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pcivar.h> 45 46 bool pci_mapreg_map_enable_decode = true; 47 48 static int 49 pci_io_find(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type, 50 bus_addr_t *basep, bus_size_t *sizep, int *flagsp) 51 { 52 pcireg_t address, mask, csr; 53 int s; 54 55 if (reg < PCI_MAPREG_START || 56 #if 0 57 /* 58 * Can't do this check; some devices have mapping registers 59 * way out in left field. 60 */ 61 reg >= PCI_MAPREG_END || 62 #endif 63 (reg & 3)) 64 panic("pci_io_find: bad request"); 65 66 /* 67 * Section 6.2.5.1, `Address Maps', tells us that: 68 * 69 * 1) The builtin software should have already mapped the device in a 70 * reasonable way. 71 * 72 * 2) A device which wants 2^n bytes of memory will hardwire the bottom 73 * n bits of the address to 0. As recommended, we write all 1s and see 74 * what we get back. 75 */ 76 s = splhigh(); 77 address = pci_conf_read(pc, tag, reg); 78 /* 79 * Disable decoding via the command register before writing to the 80 * BAR register. Changing the decoding address to all-one is 81 * not a valid address and could have side effects. 82 */ 83 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 84 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 85 csr & ~PCI_COMMAND_IO_ENABLE) ; 86 pci_conf_write(pc, tag, reg, 0xffffffff); 87 mask = pci_conf_read(pc, tag, reg); 88 pci_conf_write(pc, tag, reg, address); 89 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 90 splx(s); 91 92 if (PCI_MAPREG_TYPE(address) != PCI_MAPREG_TYPE_IO) { 93 aprint_debug("pci_io_find: expected type i/o, found mem\n"); 94 return 1; 95 } 96 97 if (PCI_MAPREG_IO_SIZE(mask) == 0) { 98 aprint_debug("pci_io_find: void region\n"); 99 return 1; 100 } 101 102 if (basep != NULL) 103 *basep = PCI_MAPREG_IO_ADDR(address); 104 if (sizep != NULL) 105 *sizep = PCI_MAPREG_IO_SIZE(mask); 106 if (flagsp != NULL) 107 *flagsp = 0; 108 109 return 0; 110 } 111 112 static int 113 pci_mem_find(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type, 114 bus_addr_t *basep, bus_size_t *sizep, int *flagsp) 115 { 116 pcireg_t address, mask, address1 = 0, mask1 = 0xffffffff; 117 uint64_t waddress, wmask; 118 int s, is64bit, isrom; 119 pcireg_t csr; 120 121 is64bit = (PCI_MAPREG_MEM_TYPE(type) == PCI_MAPREG_MEM_TYPE_64BIT); 122 isrom = (reg == PCI_MAPREG_ROM); 123 124 if ((!isrom) && (reg < PCI_MAPREG_START || 125 #if 0 126 /* 127 * Can't do this check; some devices have mapping registers 128 * way out in left field. 129 */ 130 reg >= PCI_MAPREG_END || 131 #endif 132 (reg & 3))) 133 panic("pci_mem_find: bad request"); 134 135 if (is64bit && (reg + 4) >= PCI_MAPREG_END) 136 panic("pci_mem_find: bad 64-bit request"); 137 138 /* 139 * Section 6.2.5.1, `Address Maps', tells us that: 140 * 141 * 1) The builtin software should have already mapped the device in a 142 * reasonable way. 143 * 144 * 2) A device which wants 2^n bytes of memory will hardwire the bottom 145 * n bits of the address to 0. As recommended, we write all 1s and see 146 * what we get back. Only probe the upper BAR of a mem64 BAR if bit 31 147 * is readonly. 148 */ 149 s = splhigh(); 150 address = pci_conf_read(pc, tag, reg); 151 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 152 /* 153 * Disable decoding via the command register before writing to the 154 * BAR register. Changing the decoding address to all-one is 155 * not a valid address and could have side effects. 156 */ 157 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 158 csr & ~PCI_COMMAND_MEM_ENABLE) ; 159 pci_conf_write(pc, tag, reg, 0xffffffff); 160 mask = pci_conf_read(pc, tag, reg); 161 pci_conf_write(pc, tag, reg, address); 162 if (is64bit) { 163 address1 = pci_conf_read(pc, tag, reg + 4); 164 if ((mask & 0x80000000) == 0) { 165 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 166 mask1 = pci_conf_read(pc, tag, reg + 4); 167 pci_conf_write(pc, tag, reg + 4, address1); 168 } 169 } 170 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 171 splx(s); 172 173 if (!isrom) { 174 /* 175 * roms should have an enable bit instead of a memory 176 * type decoder bit. For normal BARs, make sure that 177 * the address decoder type matches what we asked for. 178 */ 179 if (PCI_MAPREG_TYPE(address) != PCI_MAPREG_TYPE_MEM) { 180 printf("pci_mem_find: expected type mem, found i/o\n"); 181 return 1; 182 } 183 /* XXX Allow 64bit bars for 32bit requests.*/ 184 if (PCI_MAPREG_MEM_TYPE(address) != 185 PCI_MAPREG_MEM_TYPE(type) && 186 PCI_MAPREG_MEM_TYPE(address) != 187 PCI_MAPREG_MEM_TYPE_64BIT) { 188 printf("pci_mem_find: " 189 "expected mem type %08x, found %08x\n", 190 PCI_MAPREG_MEM_TYPE(type), 191 PCI_MAPREG_MEM_TYPE(address)); 192 return 1; 193 } 194 } 195 196 waddress = (uint64_t)address1 << 32UL | address; 197 wmask = (uint64_t)mask1 << 32UL | mask; 198 199 if ((is64bit && PCI_MAPREG_MEM64_SIZE(wmask) == 0) || 200 (!is64bit && PCI_MAPREG_MEM_SIZE(mask) == 0)) { 201 aprint_debug("pci_mem_find: void region\n"); 202 return 1; 203 } 204 205 switch (PCI_MAPREG_MEM_TYPE(address)) { 206 case PCI_MAPREG_MEM_TYPE_32BIT: 207 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 208 break; 209 case PCI_MAPREG_MEM_TYPE_64BIT: 210 /* 211 * Handle the case of a 64-bit memory register on a 212 * platform with 32-bit addressing. Make sure that 213 * the address assigned and the device's memory size 214 * fit in 32 bits. We implicitly assume that if 215 * bus_addr_t is 64-bit, then so is bus_size_t. 216 */ 217 if (sizeof(uint64_t) > sizeof(bus_addr_t) && 218 (address1 != 0 || mask1 != 0xffffffff)) { 219 printf("pci_mem_find: 64-bit memory map which is " 220 "inaccessible on a 32-bit platform\n"); 221 return 1; 222 } 223 break; 224 default: 225 printf("pci_mem_find: reserved mapping register type\n"); 226 return 1; 227 } 228 229 if (sizeof(uint64_t) > sizeof(bus_addr_t)) { 230 if (basep != NULL) 231 *basep = PCI_MAPREG_MEM_ADDR(address); 232 if (sizep != NULL) 233 *sizep = PCI_MAPREG_MEM_SIZE(mask); 234 } else { 235 if (basep != NULL) 236 *basep = PCI_MAPREG_MEM64_ADDR(waddress); 237 if (sizep != NULL) 238 *sizep = PCI_MAPREG_MEM64_SIZE(wmask); 239 } 240 if (flagsp != NULL) 241 *flagsp = (isrom || PCI_MAPREG_MEM_PREFETCHABLE(address)) ? 242 BUS_SPACE_MAP_PREFETCHABLE : 0; 243 244 return 0; 245 } 246 247 #define _PCI_MAPREG_TYPEBITS(reg) \ 248 (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO ? \ 249 reg & PCI_MAPREG_TYPE_MASK : \ 250 reg & (PCI_MAPREG_TYPE_MASK|PCI_MAPREG_MEM_TYPE_MASK)) 251 252 pcireg_t 253 pci_mapreg_type(pci_chipset_tag_t pc, pcitag_t tag, int reg) 254 { 255 256 return _PCI_MAPREG_TYPEBITS(pci_conf_read(pc, tag, reg)); 257 } 258 259 int 260 pci_mapreg_probe(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t *typep) 261 { 262 pcireg_t address, mask, csr; 263 int s; 264 265 s = splhigh(); 266 address = pci_conf_read(pc, tag, reg); 267 /* 268 * Disable decoding via the command register before writing to the 269 * BAR register. Changing the decoding address to all-one is 270 * not a valid address and could have side effects. 271 */ 272 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 273 if (PCI_MAPREG_TYPE(address) == PCI_MAPREG_TYPE_IO) { 274 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 275 csr & ~PCI_COMMAND_IO_ENABLE); 276 } else { 277 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 278 csr & ~PCI_COMMAND_MEM_ENABLE); 279 } 280 pci_conf_write(pc, tag, reg, 0xffffffff); 281 mask = pci_conf_read(pc, tag, reg); 282 pci_conf_write(pc, tag, reg, address); 283 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 284 splx(s); 285 286 if (mask == 0) /* unimplemented mapping register */ 287 return 0; 288 289 if (typep != NULL) 290 *typep = _PCI_MAPREG_TYPEBITS(address); 291 return 1; 292 } 293 294 int 295 pci_mapreg_info(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type, 296 bus_addr_t *basep, bus_size_t *sizep, int *flagsp) 297 { 298 299 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) 300 return pci_io_find(pc, tag, reg, type, basep, sizep, 301 flagsp); 302 else 303 return pci_mem_find(pc, tag, reg, type, basep, sizep, 304 flagsp); 305 } 306 307 int 308 pci_mapreg_map(const struct pci_attach_args *pa, int reg, pcireg_t type, 309 int busflags, bus_space_tag_t *tagp, bus_space_handle_t *handlep, 310 bus_addr_t *basep, bus_size_t *sizep) 311 { 312 return pci_mapreg_submap(pa, reg, type, busflags, 0, 0, tagp, 313 handlep, basep, sizep); 314 } 315 316 int 317 pci_mapreg_submap(const struct pci_attach_args *pa, int reg, pcireg_t type, 318 int busflags, bus_size_t reqsize, bus_size_t offset, bus_space_tag_t *tagp, 319 bus_space_handle_t *handlep, bus_addr_t *basep, bus_size_t *sizep) 320 { 321 bus_space_tag_t tag; 322 bus_space_handle_t handle; 323 bus_addr_t base; 324 bus_size_t realmaxsize; 325 pcireg_t csr; 326 int flags, s; 327 328 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) { 329 if ((pa->pa_flags & PCI_FLAGS_IO_OKAY) == 0) 330 return 1; 331 if (pci_io_find(pa->pa_pc, pa->pa_tag, reg, type, &base, 332 &realmaxsize, &flags)) 333 return 1; 334 tag = pa->pa_iot; 335 } else { 336 if ((pa->pa_flags & PCI_FLAGS_MEM_OKAY) == 0) 337 return 1; 338 if (pci_mem_find(pa->pa_pc, pa->pa_tag, reg, type, &base, 339 &realmaxsize, &flags)) 340 return 1; 341 tag = pa->pa_memt; 342 } 343 344 if (reg == PCI_MAPREG_ROM) { 345 pcireg_t mask; 346 /* we have to enable the ROM address decoder... */ 347 s = splhigh(); 348 mask = pci_conf_read(pa->pa_pc, pa->pa_tag, reg); 349 mask |= PCI_MAPREG_ROM_ENABLE; 350 pci_conf_write(pa->pa_pc, pa->pa_tag, reg, mask); 351 splx(s); 352 } 353 354 /* If we're called with maxsize/offset of 0, behave like 355 * pci_mapreg_map. 356 */ 357 358 reqsize = (reqsize != 0) ? reqsize : realmaxsize; 359 base += offset; 360 361 if (realmaxsize < (offset + reqsize)) 362 return 1; 363 364 if (bus_space_map(tag, base, reqsize, busflags, &handle)) 365 return 1; 366 367 if (pci_mapreg_map_enable_decode) { 368 s = splhigh(); 369 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 370 csr |= (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) ? 371 PCI_COMMAND_IO_ENABLE : PCI_COMMAND_MEM_ENABLE; 372 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr); 373 splx(s); 374 } 375 376 if (tagp != NULL) 377 *tagp = tag; 378 if (handlep != NULL) 379 *handlep = handle; 380 if (basep != NULL) 381 *basep = base; 382 if (sizep != NULL) 383 *sizep = reqsize; 384 385 return 0; 386 } 387 388 int 389 pci_find_rom(const struct pci_attach_args *pa, bus_space_tag_t bst, 390 bus_space_handle_t bsh, bus_size_t sz, int type, 391 bus_space_handle_t *romh, bus_size_t *romsz) 392 { 393 bus_size_t offset = 0, imagesz; 394 uint16_t ptr; 395 int done = 0; 396 397 /* 398 * no upper bound check; i cannot imagine a 4GB ROM, but 399 * it appears the spec would allow it! 400 */ 401 if (sz < 1024) 402 return 1; 403 404 while (offset < sz && !done){ 405 struct pci_rom_header hdr; 406 struct pci_rom rom; 407 408 hdr.romh_magic = bus_space_read_2(bst, bsh, 409 offset + offsetof (struct pci_rom_header, romh_magic)); 410 hdr.romh_data_ptr = bus_space_read_2(bst, bsh, 411 offset + offsetof (struct pci_rom_header, romh_data_ptr)); 412 413 /* no warning: quite possibly ROM is simply not populated */ 414 if (hdr.romh_magic != PCI_ROM_HEADER_MAGIC) 415 return 1; 416 417 ptr = offset + hdr.romh_data_ptr; 418 419 if (ptr > sz) { 420 printf("pci_find_rom: rom data ptr out of range\n"); 421 return 1; 422 } 423 424 rom.rom_signature = bus_space_read_4(bst, bsh, ptr); 425 rom.rom_vendor = bus_space_read_2(bst, bsh, ptr + 426 offsetof(struct pci_rom, rom_vendor)); 427 rom.rom_product = bus_space_read_2(bst, bsh, ptr + 428 offsetof(struct pci_rom, rom_product)); 429 rom.rom_class = bus_space_read_1(bst, bsh, 430 ptr + offsetof (struct pci_rom, rom_class)); 431 rom.rom_subclass = bus_space_read_1(bst, bsh, 432 ptr + offsetof (struct pci_rom, rom_subclass)); 433 rom.rom_interface = bus_space_read_1(bst, bsh, 434 ptr + offsetof (struct pci_rom, rom_interface)); 435 rom.rom_len = bus_space_read_2(bst, bsh, 436 ptr + offsetof (struct pci_rom, rom_len)); 437 rom.rom_code_type = bus_space_read_1(bst, bsh, 438 ptr + offsetof (struct pci_rom, rom_code_type)); 439 rom.rom_indicator = bus_space_read_1(bst, bsh, 440 ptr + offsetof (struct pci_rom, rom_indicator)); 441 442 if (rom.rom_signature != PCI_ROM_SIGNATURE) { 443 printf("pci_find_rom: bad rom data signature\n"); 444 return 1; 445 } 446 447 imagesz = rom.rom_len * 512; 448 449 if ((rom.rom_vendor == PCI_VENDOR(pa->pa_id)) && 450 (rom.rom_product == PCI_PRODUCT(pa->pa_id)) && 451 (rom.rom_class == PCI_CLASS(pa->pa_class)) && 452 (rom.rom_subclass == PCI_SUBCLASS(pa->pa_class)) && 453 (rom.rom_interface == PCI_INTERFACE(pa->pa_class)) && 454 (rom.rom_code_type == type)) { 455 *romsz = imagesz; 456 bus_space_subregion(bst, bsh, offset, imagesz, romh); 457 return 0; 458 } 459 460 /* last image check */ 461 if (rom.rom_indicator & PCI_ROM_INDICATOR_LAST) 462 return 1; 463 464 /* offset by size */ 465 offset += imagesz; 466 } 467 return 1; 468 } 469