1 /* $NetBSD: pci.c,v 1.118 2008/06/12 22:44:47 cegger Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.118 2008/06/12 22:44:47 cegger Exp $"); 40 41 #include "opt_pci.h" 42 43 #include <sys/param.h> 44 #include <sys/malloc.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcidevs.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <net/if.h> 55 56 #include "locators.h" 57 58 static bool pci_child_register(device_t); 59 60 #ifdef PCI_CONFIG_DUMP 61 int pci_config_dump = 1; 62 #else 63 int pci_config_dump = 0; 64 #endif 65 66 int pciprint(void *, const char *); 67 68 #ifdef PCI_MACHDEP_ENUMERATE_BUS 69 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 70 #else 71 int pci_enumerate_bus(struct pci_softc *, const int *, 72 int (*)(struct pci_attach_args *), struct pci_attach_args *); 73 #endif 74 75 /* 76 * Important note about PCI-ISA bridges: 77 * 78 * Callbacks are used to configure these devices so that ISA/EISA bridges 79 * can attach their child busses after PCI configuration is done. 80 * 81 * This works because: 82 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 83 * (2) any ISA/EISA bridges must be attached to primary PCI 84 * busses (i.e. bus zero). 85 * 86 * That boils down to: there can only be one of these outstanding 87 * at a time, it is cleared when configuring PCI bus 0 before any 88 * subdevices have been found, and it is run after all subdevices 89 * of PCI bus 0 have been found. 90 * 91 * This is needed because there are some (legacy) PCI devices which 92 * can show up as ISA/EISA devices as well (the prime example of which 93 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 94 * and the bridge is seen before the video board is, the board can show 95 * up as an ISA device, and that can (bogusly) complicate the PCI device's 96 * attach code, or make the PCI device not be properly attached at all. 97 * 98 * We use the generic config_defer() facility to achieve this. 99 */ 100 101 int 102 pcirescan(device_t self, const char *ifattr, const int *locators) 103 { 104 struct pci_softc *sc = device_private(self); 105 106 KASSERT(ifattr && !strcmp(ifattr, "pci")); 107 KASSERT(locators); 108 109 pci_enumerate_bus(sc, locators, NULL, NULL); 110 return 0; 111 } 112 113 int 114 pcimatch(device_t parent, cfdata_t cf, void *aux) 115 { 116 struct pcibus_attach_args *pba = aux; 117 118 /* Check the locators */ 119 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 120 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 121 return (0); 122 123 /* sanity */ 124 if (pba->pba_bus < 0 || pba->pba_bus > 255) 125 return (0); 126 127 /* 128 * XXX check other (hardware?) indicators 129 */ 130 131 return (1); 132 } 133 134 void 135 pciattach(device_t parent, device_t self, void *aux) 136 { 137 struct pcibus_attach_args *pba = aux; 138 struct pci_softc *sc = device_private(self); 139 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 140 const char *sep = ""; 141 static const int wildcard[PCICF_NLOCS] = { 142 PCICF_DEV_DEFAULT, PCICF_FUNCTION_DEFAULT 143 }; 144 145 sc->sc_dev = self; 146 147 pci_attach_hook(parent, self, pba); 148 149 aprint_naive("\n"); 150 aprint_normal("\n"); 151 152 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_ENABLED); 153 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_ENABLED); 154 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 155 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 156 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 157 158 if (io_enabled == 0 && mem_enabled == 0) { 159 aprint_error_dev(self, "no spaces enabled!\n"); 160 goto fail; 161 } 162 163 #define PRINT(str) \ 164 do { \ 165 aprint_verbose("%s%s", sep, str); \ 166 sep = ", "; \ 167 } while (/*CONSTCOND*/0) 168 169 aprint_verbose_dev(self, ""); 170 171 if (io_enabled) 172 PRINT("i/o space"); 173 if (mem_enabled) 174 PRINT("memory space"); 175 aprint_verbose(" enabled"); 176 177 if (mrl_enabled || mrm_enabled || mwi_enabled) { 178 if (mrl_enabled) 179 PRINT("rd/line"); 180 if (mrm_enabled) 181 PRINT("rd/mult"); 182 if (mwi_enabled) 183 PRINT("wr/inv"); 184 aprint_verbose(" ok"); 185 } 186 187 aprint_verbose("\n"); 188 189 #undef PRINT 190 191 sc->sc_iot = pba->pba_iot; 192 sc->sc_memt = pba->pba_memt; 193 sc->sc_dmat = pba->pba_dmat; 194 sc->sc_dmat64 = pba->pba_dmat64; 195 sc->sc_pc = pba->pba_pc; 196 sc->sc_bus = pba->pba_bus; 197 sc->sc_bridgetag = pba->pba_bridgetag; 198 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 199 sc->sc_intrswiz = pba->pba_intrswiz; 200 sc->sc_intrtag = pba->pba_intrtag; 201 sc->sc_flags = pba->pba_flags; 202 203 device_pmf_driver_set_child_register(sc->sc_dev, pci_child_register); 204 205 pcirescan(sc->sc_dev, "pci", wildcard); 206 207 fail: 208 if (!pmf_device_register(self, NULL, NULL)) 209 aprint_error_dev(self, "couldn't establish power handler\n"); 210 } 211 212 int 213 pcidetach(device_t self, int flags) 214 { 215 int rc; 216 217 if ((rc = config_detach_children(self, flags)) != 0) 218 return rc; 219 pmf_device_deregister(self); 220 return 0; 221 } 222 223 int 224 pciprint(void *aux, const char *pnp) 225 { 226 struct pci_attach_args *pa = aux; 227 char devinfo[256]; 228 const struct pci_quirkdata *qd; 229 230 if (pnp) { 231 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 232 aprint_normal("%s at %s", devinfo, pnp); 233 } 234 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 235 if (pci_config_dump) { 236 printf(": "); 237 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 238 if (!pnp) 239 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 240 printf("%s at %s", devinfo, pnp ? pnp : "?"); 241 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 242 #ifdef __i386__ 243 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 244 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 245 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 246 #else 247 printf("intrswiz %#lx, intrpin %#lx", 248 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 249 #endif 250 printf(", i/o %s, mem %s,", 251 pa->pa_flags & PCI_FLAGS_IO_ENABLED ? "on" : "off", 252 pa->pa_flags & PCI_FLAGS_MEM_ENABLED ? "on" : "off"); 253 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 254 PCI_PRODUCT(pa->pa_id)); 255 if (qd == NULL) { 256 printf(" no quirks"); 257 } else { 258 bitmask_snprintf(qd->quirks, 259 "\002\001multifn\002singlefn\003skipfunc0" 260 "\004skipfunc1\005skipfunc2\006skipfunc3" 261 "\007skipfunc4\010skipfunc5\011skipfunc6" 262 "\012skipfunc7", 263 devinfo, sizeof (devinfo)); 264 printf(" quirks %s", devinfo); 265 } 266 printf(")"); 267 } 268 return (UNCONF); 269 } 270 271 int 272 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 273 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 274 { 275 pci_chipset_tag_t pc = sc->sc_pc; 276 struct pci_attach_args pa; 277 pcireg_t id, csr, class, intr, bhlcr; 278 int ret, pin, bus, device, function; 279 int locs[PCICF_NLOCS]; 280 device_t subdev; 281 282 pci_decompose_tag(pc, tag, &bus, &device, &function); 283 284 /* a driver already attached? */ 285 if (sc->PCI_SC_DEVICESC(device, function).c_dev != NULL && !match) 286 return (0); 287 288 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 289 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 290 return (0); 291 292 id = pci_conf_read(pc, tag, PCI_ID_REG); 293 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 294 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 295 296 /* Invalid vendor ID value? */ 297 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 298 return (0); 299 /* XXX Not invalid, but we've done this ~forever. */ 300 if (PCI_VENDOR(id) == 0) 301 return (0); 302 303 pa.pa_iot = sc->sc_iot; 304 pa.pa_memt = sc->sc_memt; 305 pa.pa_dmat = sc->sc_dmat; 306 pa.pa_dmat64 = sc->sc_dmat64; 307 pa.pa_pc = pc; 308 pa.pa_bus = bus; 309 pa.pa_device = device; 310 pa.pa_function = function; 311 pa.pa_tag = tag; 312 pa.pa_id = id; 313 pa.pa_class = class; 314 315 /* 316 * Set up memory, I/O enable, and PCI command flags 317 * as appropriate. 318 */ 319 pa.pa_flags = sc->sc_flags; 320 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) 321 pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED; 322 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) 323 pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED; 324 325 /* 326 * If the cache line size is not configured, then 327 * clear the MRL/MRM/MWI command-ok flags. 328 */ 329 if (PCI_CACHELINE(bhlcr) == 0) 330 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 331 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 332 333 if (sc->sc_bridgetag == NULL) { 334 pa.pa_intrswiz = 0; 335 pa.pa_intrtag = tag; 336 } else { 337 pa.pa_intrswiz = sc->sc_intrswiz + device; 338 pa.pa_intrtag = sc->sc_intrtag; 339 } 340 341 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 342 343 pin = PCI_INTERRUPT_PIN(intr); 344 pa.pa_rawintrpin = pin; 345 if (pin == PCI_INTERRUPT_PIN_NONE) { 346 /* no interrupt */ 347 pa.pa_intrpin = 0; 348 } else { 349 /* 350 * swizzle it based on the number of busses we're 351 * behind and our device number. 352 */ 353 pa.pa_intrpin = /* XXX */ 354 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 355 } 356 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 357 358 if (match != NULL) { 359 ret = (*match)(&pa); 360 if (ret != 0 && pap != NULL) 361 *pap = pa; 362 } else { 363 struct pci_child *c; 364 locs[PCICF_DEV] = device; 365 locs[PCICF_FUNCTION] = function; 366 367 subdev = config_found_sm_loc(sc->sc_dev, "pci", locs, &pa, 368 pciprint, config_stdsubmatch); 369 370 c = &sc->PCI_SC_DEVICESC(device, function); 371 c->c_dev = subdev; 372 pci_conf_capture(pc, tag, &c->c_conf); 373 if (pci_get_powerstate(pc, tag, &c->c_powerstate) == 0) 374 c->c_psok = true; 375 else 376 c->c_psok = false; 377 ret = (subdev != NULL); 378 } 379 380 return (ret); 381 } 382 383 void 384 pcidevdetached(device_t self, device_t child) 385 { 386 struct pci_softc *sc = device_private(self); 387 int d, f; 388 pcitag_t tag; 389 struct pci_child *c; 390 391 d = device_locator(child, PCICF_DEV); 392 f = device_locator(child, PCICF_FUNCTION); 393 394 c = &sc->PCI_SC_DEVICESC(d, f); 395 396 KASSERT(c->c_dev == child); 397 398 tag = pci_make_tag(sc->sc_pc, sc->sc_bus, d, f); 399 if (c->c_psok) 400 pci_set_powerstate(sc->sc_pc, tag, c->c_powerstate); 401 pci_conf_restore(sc->sc_pc, tag, &c->c_conf); 402 c->c_dev = NULL; 403 } 404 405 CFATTACH_DECL2_NEW(pci, sizeof(struct pci_softc), 406 pcimatch, pciattach, pcidetach, NULL, pcirescan, pcidevdetached); 407 408 int 409 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 410 int *offset, pcireg_t *value) 411 { 412 pcireg_t reg; 413 unsigned int ofs; 414 415 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 416 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 417 return (0); 418 419 /* Determine the Capability List Pointer register to start with. */ 420 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 421 switch (PCI_HDRTYPE_TYPE(reg)) { 422 case 0: /* standard device header */ 423 case 1: /* PCI-PCI bridge header */ 424 ofs = PCI_CAPLISTPTR_REG; 425 break; 426 case 2: /* PCI-CardBus Bridge header */ 427 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 428 break; 429 default: 430 return (0); 431 } 432 433 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 434 while (ofs != 0) { 435 #ifdef DIAGNOSTIC 436 if ((ofs & 3) || (ofs < 0x40)) 437 panic("pci_get_capability"); 438 #endif 439 reg = pci_conf_read(pc, tag, ofs); 440 if (PCI_CAPLIST_CAP(reg) == capid) { 441 if (offset) 442 *offset = ofs; 443 if (value) 444 *value = reg; 445 return (1); 446 } 447 ofs = PCI_CAPLIST_NEXT(reg); 448 } 449 450 return (0); 451 } 452 453 int 454 pci_find_device(struct pci_attach_args *pa, 455 int (*match)(struct pci_attach_args *)) 456 { 457 extern struct cfdriver pci_cd; 458 device_t pcidev; 459 int i; 460 static const int wildcard[2] = { 461 PCICF_DEV_DEFAULT, 462 PCICF_FUNCTION_DEFAULT 463 }; 464 465 for (i = 0; i < pci_cd.cd_ndevs; i++) { 466 pcidev = device_lookup(&pci_cd, i); 467 if (pcidev != NULL && 468 pci_enumerate_bus(device_private(pcidev), wildcard, 469 match, pa) != 0) 470 return (1); 471 } 472 return (0); 473 } 474 475 #ifndef PCI_MACHDEP_ENUMERATE_BUS 476 /* 477 * Generic PCI bus enumeration routine. Used unless machine-dependent 478 * code needs to provide something else. 479 */ 480 int 481 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 482 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 483 { 484 pci_chipset_tag_t pc = sc->sc_pc; 485 int device, function, nfunctions, ret; 486 const struct pci_quirkdata *qd; 487 pcireg_t id, bhlcr; 488 pcitag_t tag; 489 #ifdef __PCI_BUS_DEVORDER 490 char devs[32]; 491 int i; 492 #endif 493 494 #ifdef __PCI_BUS_DEVORDER 495 pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs); 496 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) 497 #else 498 for (device = 0; device < sc->sc_maxndevs; device++) 499 #endif 500 { 501 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 502 (locators[PCICF_DEV] != device)) 503 continue; 504 505 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 506 507 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 508 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 509 continue; 510 511 id = pci_conf_read(pc, tag, PCI_ID_REG); 512 513 /* Invalid vendor ID value? */ 514 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 515 continue; 516 /* XXX Not invalid, but we've done this ~forever. */ 517 if (PCI_VENDOR(id) == 0) 518 continue; 519 520 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 521 522 if (qd != NULL && 523 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 524 nfunctions = 8; 525 else if (qd != NULL && 526 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 527 nfunctions = 1; 528 else 529 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 530 531 for (function = 0; function < nfunctions; function++) { 532 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 533 && (locators[PCICF_FUNCTION] != function)) 534 continue; 535 536 if (qd != NULL && 537 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 538 continue; 539 tag = pci_make_tag(pc, sc->sc_bus, device, function); 540 ret = pci_probe_device(sc, tag, match, pap); 541 if (match != NULL && ret != 0) 542 return (ret); 543 } 544 } 545 return (0); 546 } 547 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 548 549 550 /* 551 * Vital Product Data (PCI 2.2) 552 */ 553 554 int 555 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 556 pcireg_t *data) 557 { 558 uint32_t reg; 559 int ofs, i, j; 560 561 KASSERT(data != NULL); 562 KASSERT((offset + count) < 0x7fff); 563 564 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 565 return (1); 566 567 for (i = 0; i < count; offset += sizeof(*data), i++) { 568 reg &= 0x0000ffff; 569 reg &= ~PCI_VPD_OPFLAG; 570 reg |= PCI_VPD_ADDRESS(offset); 571 pci_conf_write(pc, tag, ofs, reg); 572 573 /* 574 * PCI 2.2 does not specify how long we should poll 575 * for completion nor whether the operation can fail. 576 */ 577 j = 0; 578 do { 579 if (j++ == 20) 580 return (1); 581 delay(4); 582 reg = pci_conf_read(pc, tag, ofs); 583 } while ((reg & PCI_VPD_OPFLAG) == 0); 584 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 585 } 586 587 return (0); 588 } 589 590 int 591 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 592 pcireg_t *data) 593 { 594 pcireg_t reg; 595 int ofs, i, j; 596 597 KASSERT(data != NULL); 598 KASSERT((offset + count) < 0x7fff); 599 600 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 601 return (1); 602 603 for (i = 0; i < count; offset += sizeof(*data), i++) { 604 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 605 606 reg &= 0x0000ffff; 607 reg |= PCI_VPD_OPFLAG; 608 reg |= PCI_VPD_ADDRESS(offset); 609 pci_conf_write(pc, tag, ofs, reg); 610 611 /* 612 * PCI 2.2 does not specify how long we should poll 613 * for completion nor whether the operation can fail. 614 */ 615 j = 0; 616 do { 617 if (j++ == 20) 618 return (1); 619 delay(1); 620 reg = pci_conf_read(pc, tag, ofs); 621 } while (reg & PCI_VPD_OPFLAG); 622 } 623 624 return (0); 625 } 626 627 int 628 pci_dma64_available(struct pci_attach_args *pa) 629 { 630 #ifdef _PCI_HAVE_DMA64 631 if (BUS_DMA_TAG_VALID(pa->pa_dmat64) && 632 ((uint64_t)physmem << PAGE_SHIFT) > 0xffffffffULL) 633 return 1; 634 #endif 635 return 0; 636 } 637 638 void 639 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 640 struct pci_conf_state *pcs) 641 { 642 int off; 643 644 for (off = 0; off < 16; off++) 645 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 646 647 return; 648 } 649 650 void 651 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 652 struct pci_conf_state *pcs) 653 { 654 int off; 655 pcireg_t val; 656 657 for (off = 15; off >= 0; off--) { 658 val = pci_conf_read(pc, tag, (off * 4)); 659 if (val != pcs->reg[off]) 660 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 661 } 662 663 return; 664 } 665 666 /* 667 * Power Management Capability (Rev 2.2) 668 */ 669 static int 670 pci_get_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state, 671 int offset) 672 { 673 pcireg_t value, now; 674 675 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 676 now = value & PCI_PMCSR_STATE_MASK; 677 switch (now) { 678 case PCI_PMCSR_STATE_D0: 679 case PCI_PMCSR_STATE_D1: 680 case PCI_PMCSR_STATE_D2: 681 case PCI_PMCSR_STATE_D3: 682 *state = now; 683 return 0; 684 default: 685 return EINVAL; 686 } 687 } 688 689 int 690 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state) 691 { 692 int offset; 693 pcireg_t value; 694 695 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 696 return EOPNOTSUPP; 697 698 return pci_get_powerstate_int(pc, tag, state, offset); 699 } 700 701 static int 702 pci_set_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state, 703 int offset, pcireg_t cap_reg) 704 { 705 pcireg_t value, cap, now; 706 707 cap = cap_reg >> PCI_PMCR_SHIFT; 708 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 709 now = value & PCI_PMCSR_STATE_MASK; 710 value &= ~PCI_PMCSR_STATE_MASK; 711 712 if (now == state) 713 return 0; 714 switch (state) { 715 case PCI_PMCSR_STATE_D0: 716 break; 717 case PCI_PMCSR_STATE_D1: 718 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) { 719 printf("invalid transition from %d to D1\n", (int)now); 720 return EINVAL; 721 } 722 if (!(cap & PCI_PMCR_D1SUPP)) { 723 printf("D1 not supported\n"); 724 return EOPNOTSUPP; 725 } 726 break; 727 case PCI_PMCSR_STATE_D2: 728 if (now == PCI_PMCSR_STATE_D3) { 729 printf("invalid transition from %d to D2\n", (int)now); 730 return EINVAL; 731 } 732 if (!(cap & PCI_PMCR_D2SUPP)) { 733 printf("D2 not supported\n"); 734 return EOPNOTSUPP; 735 } 736 break; 737 case PCI_PMCSR_STATE_D3: 738 break; 739 default: 740 return EINVAL; 741 } 742 value |= state; 743 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 744 /* delay according to pcipm1.2, ch. 5.6.1 */ 745 if (state == PCI_PMCSR_STATE_D3 || now == PCI_PMCSR_STATE_D3) 746 DELAY(10000); 747 else if (state == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D2) 748 DELAY(200); 749 750 return 0; 751 } 752 753 int 754 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state) 755 { 756 int offset; 757 pcireg_t value; 758 759 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) { 760 printf("pci_set_powerstate not supported\n"); 761 return EOPNOTSUPP; 762 } 763 764 return pci_set_powerstate_int(pc, tag, state, offset, value); 765 } 766 767 int 768 pci_activate(pci_chipset_tag_t pc, pcitag_t tag, device_t dev, 769 int (*wakefun)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t)) 770 { 771 pcireg_t pmode; 772 int error; 773 774 if ((error = pci_get_powerstate(pc, tag, &pmode))) 775 return error; 776 777 switch (pmode) { 778 case PCI_PMCSR_STATE_D0: 779 break; 780 case PCI_PMCSR_STATE_D3: 781 if (wakefun == NULL) { 782 /* 783 * The card has lost all configuration data in 784 * this state, so punt. 785 */ 786 aprint_error_dev(dev, 787 "unable to wake up from power state D3\n"); 788 return EOPNOTSUPP; 789 } 790 /*FALLTHROUGH*/ 791 default: 792 if (wakefun) { 793 error = (*wakefun)(pc, tag, dev, pmode); 794 if (error) 795 return error; 796 } 797 aprint_normal_dev(dev, "waking up from power state D%d\n", 798 pmode); 799 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 800 return error; 801 } 802 return 0; 803 } 804 805 int 806 pci_activate_null(pci_chipset_tag_t pc, pcitag_t tag, 807 device_t dev, pcireg_t state) 808 { 809 return 0; 810 } 811 812 /* I have disabled this code for now. --dyoung 813 * 814 * Insofar as I understand what the PCI retry timeout is [1], 815 * I see no justification for any driver to disable when it 816 * attaches/resumes a device. 817 * 818 * A PCI bus bridge may tell a bus master to retry its transaction 819 * at a later time if the resources to complete the transaction 820 * are not immediately available. Taking a guess, PCI bus masters 821 * that implement a PCI retry timeout register count down from the 822 * retry timeout to 0 while it retries a delayed PCI transaction. 823 * When it reaches 0, it stops retrying. A PCI master is *never* 824 * supposed to stop retrying a delayed transaction, though. 825 * 826 * Incidentally, I initially suspected that writing 0 to the register 827 * would not disable *retries*, but would disable the timeout. 828 * That is, any device whose retry timeout was set to 0 would 829 * *never* timeout. However, I found out, by using PCI debug 830 * facilities on the AMD Elan SC520, that if I write 0 to the retry 831 * timeout register on an ath(4) MiniPCI card, the card really does 832 * not retry transactions. 833 * 834 * Some uses of this register have mentioned "interference" with 835 * a CPU's "C3 sleep state." It seems to me that if a bus master 836 * is properly put to sleep, it will neither initiate new transactions, 837 * nor retry delayed transactions, so disabling retries should not 838 * be necessary. 839 * 840 * [1] The timeout does not appear to be documented in any PCI 841 * standard, and we have no documentation of it for the devices by 842 * Atheros, and others, that supposedly implement it. 843 */ 844 void 845 pci_disable_retry(pci_chipset_tag_t pc, pcitag_t tag) 846 { 847 #if 0 848 pcireg_t retry; 849 850 /* 851 * Disable retry timeout to keep PCI Tx retries from 852 * interfering with ACPI C3 CPU state. 853 */ 854 retry = pci_conf_read(pc, tag, PCI_RETRY_TIMEOUT_REG); 855 retry &= ~PCI_RETRY_TIMEOUT_REG_MASK; 856 pci_conf_write(pc, tag, PCI_RETRY_TIMEOUT_REG, retry); 857 #endif 858 } 859 860 struct pci_child_power { 861 struct pci_conf_state p_pciconf; 862 pci_chipset_tag_t p_pc; 863 pcitag_t p_tag; 864 bool p_has_pm; 865 int p_pm_offset; 866 pcireg_t p_pm_cap; 867 pcireg_t p_class; 868 }; 869 870 static bool 871 pci_child_suspend(device_t dv PMF_FN_ARGS) 872 { 873 struct pci_child_power *priv = device_pmf_bus_private(dv); 874 pcireg_t ocsr, csr; 875 876 pci_conf_capture(priv->p_pc, priv->p_tag, &priv->p_pciconf); 877 878 if (!priv->p_has_pm) 879 return true; /* ??? hopefully handled by ACPI */ 880 if (PCI_CLASS(priv->p_class) == PCI_CLASS_DISPLAY) 881 return true; /* XXX */ 882 883 /* disable decoding and busmastering, see pcipm1.2 ch. 8.2.1 */ 884 ocsr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 885 csr = ocsr & ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE 886 | PCI_COMMAND_MASTER_ENABLE); 887 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 888 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 889 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) { 890 pci_conf_write(priv->p_pc, priv->p_tag, 891 PCI_COMMAND_STATUS_REG, ocsr); 892 aprint_error_dev(dv, "unsupported state, continuing.\n"); 893 return false; 894 } 895 return true; 896 } 897 898 static bool 899 pci_child_resume(device_t dv PMF_FN_ARGS) 900 { 901 struct pci_child_power *priv = device_pmf_bus_private(dv); 902 903 if (priv->p_has_pm && 904 pci_set_powerstate_int(priv->p_pc, priv->p_tag, 905 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) { 906 aprint_error_dev(dv, "unsupported state, continuing.\n"); 907 return false; 908 } 909 910 pci_conf_restore(priv->p_pc, priv->p_tag, &priv->p_pciconf); 911 912 return true; 913 } 914 915 static bool 916 pci_child_shutdown(device_t dv, int how) 917 { 918 struct pci_child_power *priv = device_pmf_bus_private(dv); 919 pcireg_t csr; 920 921 /* disable busmastering */ 922 csr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 923 csr &= ~PCI_COMMAND_MASTER_ENABLE; 924 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 925 return true; 926 } 927 928 static void 929 pci_child_deregister(device_t dv) 930 { 931 struct pci_child_power *priv = device_pmf_bus_private(dv); 932 933 free(priv, M_DEVBUF); 934 } 935 936 static bool 937 pci_child_register(device_t child) 938 { 939 device_t self = device_parent(child); 940 struct pci_softc *sc = device_private(self); 941 struct pci_child_power *priv; 942 int device, function, off; 943 pcireg_t reg; 944 945 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK); 946 947 device = device_locator(child, PCICF_DEV); 948 function = device_locator(child, PCICF_FUNCTION); 949 950 priv->p_pc = sc->sc_pc; 951 priv->p_tag = pci_make_tag(priv->p_pc, sc->sc_bus, device, 952 function); 953 priv->p_class = pci_conf_read(priv->p_pc, priv->p_tag, PCI_CLASS_REG); 954 955 if (pci_get_capability(priv->p_pc, priv->p_tag, 956 PCI_CAP_PWRMGMT, &off, ®)) { 957 priv->p_has_pm = true; 958 priv->p_pm_offset = off; 959 priv->p_pm_cap = reg; 960 } else { 961 priv->p_has_pm = false; 962 priv->p_pm_offset = -1; 963 } 964 965 device_pmf_bus_register(child, priv, pci_child_suspend, 966 pci_child_resume, pci_child_shutdown, pci_child_deregister); 967 968 return true; 969 } 970