1 /* $NetBSD: pci.c,v 1.93 2005/06/28 00:28:42 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.93 2005/06/28 00:28:42 thorpej Exp $"); 40 41 #include "opt_pci.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcidevs.h> 50 51 #include <uvm/uvm_extern.h> 52 53 #include "locators.h" 54 55 #ifdef PCI_CONFIG_DUMP 56 int pci_config_dump = 1; 57 #else 58 int pci_config_dump = 0; 59 #endif 60 61 int pciprint(void *, const char *); 62 int pcisubmatch(struct device *, struct cfdata *, 63 const locdesc_t *, void *); 64 65 #ifdef PCI_MACHDEP_ENUMERATE_BUS 66 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 67 #else 68 int pci_enumerate_bus(struct pci_softc *, const int *, 69 int (*)(struct pci_attach_args *), struct pci_attach_args *); 70 #endif 71 72 /* 73 * Important note about PCI-ISA bridges: 74 * 75 * Callbacks are used to configure these devices so that ISA/EISA bridges 76 * can attach their child busses after PCI configuration is done. 77 * 78 * This works because: 79 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 80 * (2) any ISA/EISA bridges must be attached to primary PCI 81 * busses (i.e. bus zero). 82 * 83 * That boils down to: there can only be one of these outstanding 84 * at a time, it is cleared when configuring PCI bus 0 before any 85 * subdevices have been found, and it is run after all subdevices 86 * of PCI bus 0 have been found. 87 * 88 * This is needed because there are some (legacy) PCI devices which 89 * can show up as ISA/EISA devices as well (the prime example of which 90 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 91 * and the bridge is seen before the video board is, the board can show 92 * up as an ISA device, and that can (bogusly) complicate the PCI device's 93 * attach code, or make the PCI device not be properly attached at all. 94 * 95 * We use the generic config_defer() facility to achieve this. 96 */ 97 98 static int 99 pcirescan(struct device *sc, const char *ifattr, const int *locators) 100 { 101 102 KASSERT(ifattr && !strcmp(ifattr, "pci")); 103 KASSERT(locators); 104 105 pci_enumerate_bus((struct pci_softc *)sc, locators, NULL, NULL); 106 return (0); 107 } 108 109 static int 110 pcimatch(struct device *parent, struct cfdata *cf, void *aux) 111 { 112 struct pcibus_attach_args *pba = aux; 113 114 /* Check the locators */ 115 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 116 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 117 return (0); 118 119 /* sanity */ 120 if (pba->pba_bus < 0 || pba->pba_bus > 255) 121 return (0); 122 123 /* 124 * XXX check other (hardware?) indicators 125 */ 126 127 return (1); 128 } 129 130 static void 131 pciattach(struct device *parent, struct device *self, void *aux) 132 { 133 struct pcibus_attach_args *pba = aux; 134 struct pci_softc *sc = (struct pci_softc *)self; 135 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 136 const char *sep = ""; 137 static const int wildcard[2] = { PCICF_DEV_DEFAULT, 138 PCICF_FUNCTION_DEFAULT }; 139 140 pci_attach_hook(parent, self, pba); 141 142 aprint_naive("\n"); 143 aprint_normal("\n"); 144 145 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_ENABLED); 146 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_ENABLED); 147 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 148 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 149 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 150 151 if (io_enabled == 0 && mem_enabled == 0) { 152 aprint_error("%s: no spaces enabled!\n", self->dv_xname); 153 return; 154 } 155 156 #define PRINT(str) \ 157 do { \ 158 aprint_normal("%s%s", sep, str); \ 159 sep = ", "; \ 160 } while (/*CONSTCOND*/0) 161 162 aprint_normal("%s: ", self->dv_xname); 163 164 if (io_enabled) 165 PRINT("i/o space"); 166 if (mem_enabled) 167 PRINT("memory space"); 168 aprint_normal(" enabled"); 169 170 if (mrl_enabled || mrm_enabled || mwi_enabled) { 171 if (mrl_enabled) 172 PRINT("rd/line"); 173 if (mrm_enabled) 174 PRINT("rd/mult"); 175 if (mwi_enabled) 176 PRINT("wr/inv"); 177 aprint_normal(" ok"); 178 } 179 180 aprint_normal("\n"); 181 182 #undef PRINT 183 184 sc->sc_iot = pba->pba_iot; 185 sc->sc_memt = pba->pba_memt; 186 sc->sc_dmat = pba->pba_dmat; 187 sc->sc_dmat64 = pba->pba_dmat64; 188 sc->sc_pc = pba->pba_pc; 189 sc->sc_bus = pba->pba_bus; 190 sc->sc_bridgetag = pba->pba_bridgetag; 191 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 192 sc->sc_intrswiz = pba->pba_intrswiz; 193 sc->sc_intrtag = pba->pba_intrtag; 194 sc->sc_flags = pba->pba_flags; 195 pcirescan(&sc->sc_dev, "pci", wildcard); 196 } 197 198 int 199 pciprint(void *aux, const char *pnp) 200 { 201 struct pci_attach_args *pa = aux; 202 char devinfo[256]; 203 const struct pci_quirkdata *qd; 204 205 if (pnp) { 206 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 207 aprint_normal("%s at %s", devinfo, pnp); 208 } 209 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 210 if (pci_config_dump) { 211 printf(": "); 212 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 213 if (!pnp) 214 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 215 printf("%s at %s", devinfo, pnp ? pnp : "?"); 216 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 217 #ifdef __i386__ 218 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 219 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 220 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 221 #else 222 printf("intrswiz %#lx, intrpin %#lx", 223 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 224 #endif 225 printf(", i/o %s, mem %s,", 226 pa->pa_flags & PCI_FLAGS_IO_ENABLED ? "on" : "off", 227 pa->pa_flags & PCI_FLAGS_MEM_ENABLED ? "on" : "off"); 228 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 229 PCI_PRODUCT(pa->pa_id)); 230 if (qd == NULL) { 231 printf(" no quirks"); 232 } else { 233 bitmask_snprintf(qd->quirks, 234 "\002\001multifn\002singlefn\003skipfunc0" 235 "\004skipfunc1\005skipfunc2\006skipfunc3" 236 "\007skipfunc4\010skipfunc5\011skipfunc6" 237 "\012skipfunc7", 238 devinfo, sizeof (devinfo)); 239 printf(" quirks %s", devinfo); 240 } 241 printf(")"); 242 } 243 return (UNCONF); 244 } 245 246 int 247 pcisubmatch(struct device *parent, struct cfdata *cf, 248 const locdesc_t *ldesc, void *aux) 249 { 250 251 if (cf->cf_loc[PCICF_DEV] != PCICF_DEV_DEFAULT && 252 cf->cf_loc[PCICF_DEV] != ldesc->locs[PCICF_DEV]) 253 return (0); 254 if (cf->cf_loc[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT && 255 cf->cf_loc[PCICF_FUNCTION] != ldesc->locs[PCICF_FUNCTION]) 256 return (0); 257 return (config_match(parent, cf, aux)); 258 } 259 260 int 261 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 262 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 263 { 264 pci_chipset_tag_t pc = sc->sc_pc; 265 struct pci_attach_args pa; 266 pcireg_t id, csr, class, intr, bhlcr; 267 int ret, pin, bus, device, function; 268 int help[3]; 269 locdesc_t *ldp = (void *)&help; /* XXX XXX */ 270 struct device *subdev; 271 272 pci_decompose_tag(pc, tag, &bus, &device, &function); 273 274 /* a driver already attached? */ 275 if (sc->PCI_SC_DEVICESC(device, function) && !match) 276 return (0); 277 278 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 279 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 280 return (0); 281 282 id = pci_conf_read(pc, tag, PCI_ID_REG); 283 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 284 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 285 286 /* Invalid vendor ID value? */ 287 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 288 return (0); 289 /* XXX Not invalid, but we've done this ~forever. */ 290 if (PCI_VENDOR(id) == 0) 291 return (0); 292 293 pa.pa_iot = sc->sc_iot; 294 pa.pa_memt = sc->sc_memt; 295 pa.pa_dmat = sc->sc_dmat; 296 pa.pa_dmat64 = sc->sc_dmat64; 297 pa.pa_pc = pc; 298 pa.pa_bus = bus; 299 pa.pa_device = device; 300 pa.pa_function = function; 301 pa.pa_tag = tag; 302 pa.pa_id = id; 303 pa.pa_class = class; 304 305 /* 306 * Set up memory, I/O enable, and PCI command flags 307 * as appropriate. 308 */ 309 pa.pa_flags = sc->sc_flags; 310 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) 311 pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED; 312 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) 313 pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED; 314 315 /* 316 * If the cache line size is not configured, then 317 * clear the MRL/MRM/MWI command-ok flags. 318 */ 319 if (PCI_CACHELINE(bhlcr) == 0) 320 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 321 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 322 323 if (sc->sc_bridgetag == NULL) { 324 pa.pa_intrswiz = 0; 325 pa.pa_intrtag = tag; 326 } else { 327 pa.pa_intrswiz = sc->sc_intrswiz + device; 328 pa.pa_intrtag = sc->sc_intrtag; 329 } 330 331 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 332 333 pin = PCI_INTERRUPT_PIN(intr); 334 pa.pa_rawintrpin = pin; 335 if (pin == PCI_INTERRUPT_PIN_NONE) { 336 /* no interrupt */ 337 pa.pa_intrpin = 0; 338 } else { 339 /* 340 * swizzle it based on the number of busses we're 341 * behind and our device number. 342 */ 343 pa.pa_intrpin = /* XXX */ 344 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 345 } 346 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 347 348 if (match != NULL) { 349 ret = (*match)(&pa); 350 if (ret != 0 && pap != NULL) 351 *pap = pa; 352 } else { 353 ldp->len = 2; 354 ldp->locs[PCICF_DEV] = device; 355 ldp->locs[PCICF_FUNCTION] = function; 356 357 subdev = config_found_sm_loc(&sc->sc_dev, "pci", ldp, &pa, 358 pciprint, pcisubmatch); 359 sc->PCI_SC_DEVICESC(device, function) = subdev; 360 ret = (subdev != NULL); 361 } 362 363 return (ret); 364 } 365 366 static void 367 pcidevdetached(struct device *sc, struct device *dev) 368 { 369 struct pci_softc *psc = (struct pci_softc *)sc; 370 int d, f; 371 372 KASSERT(dev->dv_locators); 373 d = dev->dv_locators[PCICF_DEV]; 374 f = dev->dv_locators[PCICF_FUNCTION]; 375 376 KASSERT(psc->PCI_SC_DEVICESC(d, f) == dev); 377 378 psc->PCI_SC_DEVICESC(d, f) = 0; 379 } 380 381 int 382 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 383 int *offset, pcireg_t *value) 384 { 385 pcireg_t reg; 386 unsigned int ofs; 387 388 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 389 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 390 return (0); 391 392 /* Determine the Capability List Pointer register to start with. */ 393 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 394 switch (PCI_HDRTYPE_TYPE(reg)) { 395 case 0: /* standard device header */ 396 ofs = PCI_CAPLISTPTR_REG; 397 break; 398 case 2: /* PCI-CardBus Bridge header */ 399 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 400 break; 401 default: 402 return (0); 403 } 404 405 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 406 while (ofs != 0) { 407 #ifdef DIAGNOSTIC 408 if ((ofs & 3) || (ofs < 0x40)) 409 panic("pci_get_capability"); 410 #endif 411 reg = pci_conf_read(pc, tag, ofs); 412 if (PCI_CAPLIST_CAP(reg) == capid) { 413 if (offset) 414 *offset = ofs; 415 if (value) 416 *value = reg; 417 return (1); 418 } 419 ofs = PCI_CAPLIST_NEXT(reg); 420 } 421 422 return (0); 423 } 424 425 int 426 pci_find_device(struct pci_attach_args *pa, 427 int (*match)(struct pci_attach_args *)) 428 { 429 extern struct cfdriver pci_cd; 430 struct device *pcidev; 431 int i; 432 static const int wildcard[2] = { 433 PCICF_DEV_DEFAULT, 434 PCICF_FUNCTION_DEFAULT 435 }; 436 437 for (i = 0; i < pci_cd.cd_ndevs; i++) { 438 pcidev = pci_cd.cd_devs[i]; 439 if (pcidev != NULL && 440 pci_enumerate_bus((struct pci_softc *)pcidev, wildcard, 441 match, pa) != 0) 442 return (1); 443 } 444 return (0); 445 } 446 447 #ifndef PCI_MACHDEP_ENUMERATE_BUS 448 /* 449 * Generic PCI bus enumeration routine. Used unless machine-dependent 450 * code needs to provide something else. 451 */ 452 int 453 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 454 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 455 { 456 pci_chipset_tag_t pc = sc->sc_pc; 457 int device, function, nfunctions, ret; 458 const struct pci_quirkdata *qd; 459 pcireg_t id, bhlcr; 460 pcitag_t tag; 461 #ifdef __PCI_BUS_DEVORDER 462 char devs[32]; 463 int i; 464 #endif 465 466 #ifdef __PCI_BUS_DEVORDER 467 pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs); 468 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) 469 #else 470 for (device = 0; device < sc->sc_maxndevs; device++) 471 #endif 472 { 473 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 474 (locators[PCICF_DEV] != device)) 475 continue; 476 477 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 478 479 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 480 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 481 continue; 482 483 id = pci_conf_read(pc, tag, PCI_ID_REG); 484 485 /* Invalid vendor ID value? */ 486 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 487 continue; 488 /* XXX Not invalid, but we've done this ~forever. */ 489 if (PCI_VENDOR(id) == 0) 490 continue; 491 492 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 493 494 if (qd != NULL && 495 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 496 nfunctions = 8; 497 else if (qd != NULL && 498 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 499 nfunctions = 1; 500 else 501 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 502 503 for (function = 0; function < nfunctions; function++) { 504 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 505 && (locators[PCICF_FUNCTION] != function)) 506 continue; 507 508 if (qd != NULL && 509 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 510 continue; 511 tag = pci_make_tag(pc, sc->sc_bus, device, function); 512 ret = pci_probe_device(sc, tag, match, pap); 513 if (match != NULL && ret != 0) 514 return (ret); 515 } 516 } 517 return (0); 518 } 519 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 520 521 /* 522 * Power Management Capability (Rev 2.2) 523 */ 524 525 int 526 pci_powerstate(pci_chipset_tag_t pc, pcitag_t tag, const int *newstate, 527 int *oldstate) 528 { 529 int offset; 530 pcireg_t value, cap, now; 531 532 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 533 return EOPNOTSUPP; 534 535 cap = value >> 16; 536 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 537 now = value & PCI_PMCSR_STATE_MASK; 538 value &= ~PCI_PMCSR_STATE_MASK; 539 if (oldstate) { 540 switch (now) { 541 case PCI_PMCSR_STATE_D0: 542 *oldstate = PCI_PWR_D0; 543 break; 544 case PCI_PMCSR_STATE_D1: 545 *oldstate = PCI_PWR_D1; 546 break; 547 case PCI_PMCSR_STATE_D2: 548 *oldstate = PCI_PWR_D2; 549 break; 550 case PCI_PMCSR_STATE_D3: 551 *oldstate = PCI_PWR_D3; 552 break; 553 default: 554 return EINVAL; 555 } 556 } 557 if (newstate == NULL) 558 return 0; 559 switch (*newstate) { 560 case PCI_PWR_D0: 561 if (now == PCI_PMCSR_STATE_D0) 562 return 0; 563 value |= PCI_PMCSR_STATE_D0; 564 break; 565 case PCI_PWR_D1: 566 if (now == PCI_PMCSR_STATE_D1) 567 return 0; 568 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) 569 return EINVAL; 570 if (!(cap & PCI_PMCR_D1SUPP)) 571 return EOPNOTSUPP; 572 value |= PCI_PMCSR_STATE_D1; 573 break; 574 case PCI_PWR_D2: 575 if (now == PCI_PMCSR_STATE_D2) 576 return 0; 577 if (now == PCI_PMCSR_STATE_D3) 578 return EINVAL; 579 if (!(cap & PCI_PMCR_D2SUPP)) 580 return EOPNOTSUPP; 581 value |= PCI_PMCSR_STATE_D2; 582 break; 583 case PCI_PWR_D3: 584 if (now == PCI_PMCSR_STATE_D3) 585 return 0; 586 value |= PCI_PMCSR_STATE_D3; 587 break; 588 default: 589 return EINVAL; 590 } 591 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 592 DELAY(1000); 593 594 return 0; 595 } 596 597 /* 598 * Vital Product Data (PCI 2.2) 599 */ 600 601 int 602 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 603 pcireg_t *data) 604 { 605 uint32_t reg; 606 int ofs, i, j; 607 608 KASSERT(data != NULL); 609 KASSERT((offset + count) < 0x7fff); 610 611 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 612 return (1); 613 614 for (i = 0; i < count; offset += sizeof(*data), i++) { 615 reg &= 0x0000ffff; 616 reg &= ~PCI_VPD_OPFLAG; 617 reg |= PCI_VPD_ADDRESS(offset); 618 pci_conf_write(pc, tag, ofs, reg); 619 620 /* 621 * PCI 2.2 does not specify how long we should poll 622 * for completion nor whether the operation can fail. 623 */ 624 j = 0; 625 do { 626 if (j++ == 20) 627 return (1); 628 delay(4); 629 reg = pci_conf_read(pc, tag, ofs); 630 } while ((reg & PCI_VPD_OPFLAG) == 0); 631 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 632 } 633 634 return (0); 635 } 636 637 int 638 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 639 pcireg_t *data) 640 { 641 pcireg_t reg; 642 int ofs, i, j; 643 644 KASSERT(data != NULL); 645 KASSERT((offset + count) < 0x7fff); 646 647 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 648 return (1); 649 650 for (i = 0; i < count; offset += sizeof(*data), i++) { 651 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 652 653 reg &= 0x0000ffff; 654 reg |= PCI_VPD_OPFLAG; 655 reg |= PCI_VPD_ADDRESS(offset); 656 pci_conf_write(pc, tag, ofs, reg); 657 658 /* 659 * PCI 2.2 does not specify how long we should poll 660 * for completion nor whether the operation can fail. 661 */ 662 j = 0; 663 do { 664 if (j++ == 20) 665 return (1); 666 delay(1); 667 reg = pci_conf_read(pc, tag, ofs); 668 } while (reg & PCI_VPD_OPFLAG); 669 } 670 671 return (0); 672 } 673 674 int 675 pci_dma64_available(struct pci_attach_args *pa) 676 { 677 #ifdef _PCI_HAVE_DMA64 678 if (BUS_DMA_TAG_VALID(pa->pa_dmat64) && 679 ((uint64_t)physmem << PAGE_SHIFT) > 0xffffffffULL) 680 return 1; 681 #endif 682 return 0; 683 } 684 685 void 686 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 687 struct pci_conf_state *pcs) 688 { 689 int off; 690 691 for (off = 0; off < 16; off++) 692 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 693 694 return; 695 } 696 697 void 698 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 699 struct pci_conf_state *pcs) 700 { 701 int off; 702 703 for (off = 0; off < 16; off++) 704 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 705 706 return; 707 } 708 709 CFATTACH_DECL2(pci, sizeof(struct pci_softc), 710 pcimatch, pciattach, NULL, NULL, pcirescan, pcidevdetached); 711