xref: /netbsd-src/sys/dev/pci/pci.c (revision 81b108b45f75f89f1e3ffad9fb6f074e771c0935)
1 /*	$NetBSD: pci.c,v 1.21 1996/08/27 21:59:51 cgd Exp $	*/
2 
3 /*
4  * Copyright (c) 1995, 1996 Christopher G. Demetriou.  All rights reserved.
5  * Copyright (c) 1994 Charles Hannum.  All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. All advertising materials mentioning features or use of this software
16  *    must display the following acknowledgement:
17  *	This product includes software developed by Charles Hannum.
18  * 4. The name of the author may not be used to endorse or promote products
19  *    derived from this software without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 /*
34  * PCI bus autoconfiguration.
35  */
36 
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/device.h>
40 
41 #include <dev/pci/pcireg.h>
42 #include <dev/pci/pcivar.h>
43 
44 int pcimatch __P((struct device *, void *, void *));
45 void pciattach __P((struct device *, struct device *, void *));
46 
47 struct cfattach pci_ca = {
48 	sizeof(struct device), pcimatch, pciattach
49 };
50 
51 struct cfdriver pci_cd = {
52 	NULL, "pci", DV_DULL
53 };
54 
55 int	pciprint __P((void *, const char *));
56 int	pcisubmatch __P((struct device *, void *, void *));
57 
58 int
59 pcimatch(parent, match, aux)
60 	struct device *parent;
61 	void *match, *aux;
62 {
63 	struct cfdata *cf = match;
64 	struct pcibus_attach_args *pba = aux;
65 
66 	if (strcmp(pba->pba_busname, cf->cf_driver->cd_name))
67 		return (0);
68 
69 	/* Check the locators */
70 	if (cf->pcibuscf_bus != PCIBUS_UNK_BUS &&
71 	    cf->pcibuscf_bus != pba->pba_bus)
72 		return (0);
73 
74 	/* sanity */
75 	if (pba->pba_bus < 0 || pba->pba_bus > 255)
76 		return (0);
77 
78 	/*
79 	 * XXX check other (hardware?) indicators
80 	 */
81 
82 	return 1;
83 }
84 
85 void
86 pciattach(parent, self, aux)
87 	struct device *parent, *self;
88 	void *aux;
89 {
90 	struct pcibus_attach_args *pba = aux;
91 	bus_chipset_tag_t bc;
92 	pci_chipset_tag_t pc;
93 	int bus, device, maxndevs, function, nfunctions;
94 
95 	pci_attach_hook(parent, self, pba);
96 	printf("\n");
97 
98 	bc = pba->pba_bc;
99 	pc = pba->pba_pc;
100 	bus = pba->pba_bus;
101 	maxndevs = pci_bus_maxdevs(pc, bus);
102 
103 	for (device = 0; device < maxndevs; device++) {
104 		pcitag_t tag;
105 		pcireg_t id, class, intr, bhlcr;
106 		struct pci_attach_args pa;
107 		int pin;
108 
109 		tag = pci_make_tag(pc, bus, device, 0);
110 		id = pci_conf_read(pc, tag, PCI_ID_REG);
111 		if (id == 0 || id == 0xffffffff)
112 			continue;
113 
114 		bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG);
115 		nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1;
116 
117 		for (function = 0; function < nfunctions; function++) {
118 			tag = pci_make_tag(pc, bus, device, function);
119 			id = pci_conf_read(pc, tag, PCI_ID_REG);
120 			if (id == 0 || id == 0xffffffff)
121 				continue;
122 			class = pci_conf_read(pc, tag, PCI_CLASS_REG);
123 			intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
124 
125 			pa.pa_bc = bc;
126 			pa.pa_pc = pc;
127 			pa.pa_device = device;
128 			pa.pa_function = function;
129 			pa.pa_tag = tag;
130 			pa.pa_id = id;
131 			pa.pa_class = class;
132 
133 			if (bus == 0) {
134 				pa.pa_intrswiz = 0;
135 				pa.pa_intrtag = tag;
136 			} else {
137 				pa.pa_intrswiz = pba->pba_intrswiz + device;
138 				pa.pa_intrtag = pba->pba_intrtag;
139 			}
140 			pin = PCI_INTERRUPT_PIN(intr);
141 			if (pin == PCI_INTERRUPT_PIN_NONE) {
142 				/* no interrupt */
143 				pa.pa_intrpin = 0;
144 			} else {
145 				/*
146 				 * swizzle it based on the number of
147 				 * busses we're behind and our device
148 				 * number.
149 				 */
150 				pa.pa_intrpin =			/* XXX */
151 				    ((pin + pa.pa_intrswiz - 1) % 4) + 1;
152 			}
153 			pa.pa_intrline = PCI_INTERRUPT_LINE(intr);
154 
155 			config_found_sm(self, &pa, pciprint, pcisubmatch);
156 		}
157 	}
158 }
159 
160 int
161 pciprint(aux, pnp)
162 	void *aux;
163 	const char *pnp;
164 {
165 	register struct pci_attach_args *pa = aux;
166 	char devinfo[256];
167 
168 	if (pnp) {
169 		pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo);
170 		printf("%s at %s", devinfo, pnp);
171 	}
172 	printf(" dev %d function %d", pa->pa_device, pa->pa_function);
173 	return (UNCONF);
174 }
175 
176 int
177 pcisubmatch(parent, match, aux)
178 	struct device *parent;
179 	void *match, *aux;
180 {
181 	struct cfdata *cf = match;
182 	struct pci_attach_args *pa = aux;
183 
184 	if (cf->pcicf_dev != PCI_UNK_DEV &&
185 	    cf->pcicf_dev != pa->pa_device)
186 		return 0;
187 	if (cf->pcicf_function != PCI_UNK_FUNCTION &&
188 	    cf->pcicf_function != pa->pa_function)
189 		return 0;
190 	return ((*cf->cf_attach->ca_match)(parent, match, aux));
191 }
192 
193 int
194 pci_io_find(pc, pcitag, reg, iobasep, iosizep)
195 	pci_chipset_tag_t pc;
196 	pcitag_t pcitag;
197 	int reg;
198 	bus_io_addr_t *iobasep;
199 	bus_io_size_t *iosizep;
200 {
201 	pcireg_t addrdata, sizedata;
202 	int s;
203 
204 	if (reg < PCI_MAPREG_START || reg >= PCI_MAPREG_END || (reg & 3))
205 		panic("pci_io_find: bad request");
206 
207 	/* XXX?
208 	 * Section 6.2.5.1, `Address Maps', tells us that:
209 	 *
210 	 * 1) The builtin software should have already mapped the device in a
211 	 * reasonable way.
212 	 *
213 	 * 2) A device which wants 2^n bytes of memory will hardwire the bottom
214 	 * n bits of the address to 0.  As recommended, we write all 1s and see
215 	 * what we get back.
216 	 */
217 	addrdata = pci_conf_read(pc, pcitag, reg);
218 
219 	s = splhigh();
220 	pci_conf_write(pc, pcitag, reg, 0xffffffff);
221 	sizedata = pci_conf_read(pc, pcitag, reg);
222 	pci_conf_write(pc, pcitag, reg, addrdata);
223 	splx(s);
224 
225 	if (PCI_MAPREG_TYPE(addrdata) != PCI_MAPREG_TYPE_IO)
226 		panic("pci_io_find: not an I/O region");
227 
228 	if (iobasep != NULL)
229 		*iobasep = PCI_MAPREG_IO_ADDR(addrdata);
230 	if (iosizep != NULL)
231 		*iosizep = PCI_MAPREG_IO_SIZE(sizedata);
232 
233 	return (0);
234 }
235 
236 int
237 pci_mem_find(pc, pcitag, reg, membasep, memsizep, cacheablep)
238 	pci_chipset_tag_t pc;
239 	pcitag_t pcitag;
240 	int reg;
241 	bus_mem_addr_t *membasep;
242 	bus_mem_size_t *memsizep;
243 	int *cacheablep;
244 {
245 	pcireg_t addrdata, sizedata;
246 	int s;
247 
248 	if (reg < PCI_MAPREG_START || reg >= PCI_MAPREG_END || (reg & 3))
249 		panic("pci_find_mem: bad request");
250 
251 	/*
252 	 * Section 6.2.5.1, `Address Maps', tells us that:
253 	 *
254 	 * 1) The builtin software should have already mapped the device in a
255 	 * reasonable way.
256 	 *
257 	 * 2) A device which wants 2^n bytes of memory will hardwire the bottom
258 	 * n bits of the address to 0.  As recommended, we write all 1s and see
259 	 * what we get back.
260 	 */
261 	addrdata = pci_conf_read(pc, pcitag, reg);
262 
263 	s = splhigh();
264 	pci_conf_write(pc, pcitag, reg, 0xffffffff);
265 	sizedata = pci_conf_read(pc, pcitag, reg);
266 	pci_conf_write(pc, pcitag, reg, addrdata);
267 	splx(s);
268 
269 	if (PCI_MAPREG_TYPE(addrdata) == PCI_MAPREG_TYPE_IO)
270 		panic("pci_find_mem: I/O region");
271 
272 	switch (PCI_MAPREG_MEM_TYPE(addrdata)) {
273 	case PCI_MAPREG_MEM_TYPE_32BIT:
274 	case PCI_MAPREG_MEM_TYPE_32BIT_1M:
275 		break;
276 	case PCI_MAPREG_MEM_TYPE_64BIT:
277 /* XXX */	printf("pci_find_mem: 64-bit region\n");
278 /* XXX */	return (1);
279 	default:
280 		printf("pci_find_mem: reserved region type\n");
281 		return (1);
282 	}
283 
284 	if (membasep != NULL)
285 		*membasep = PCI_MAPREG_MEM_ADDR(addrdata);	/* PCI addr */
286 	if (memsizep != NULL)
287 		*memsizep = PCI_MAPREG_MEM_SIZE(sizedata);
288 	if (cacheablep != NULL)
289 		*cacheablep = PCI_MAPREG_MEM_CACHEABLE(addrdata);
290 
291 	return 0;
292 }
293