1 /* $NetBSD: pci.c,v 1.49 2000/06/28 16:08:48 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include "opt_pci.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcidevs.h> 47 48 #ifdef PCI_CONFIG_DUMP 49 int pci_config_dump = 1; 50 #else 51 int pci_config_dump = 0; 52 #endif 53 54 int pcimatch __P((struct device *, struct cfdata *, void *)); 55 void pciattach __P((struct device *, struct device *, void *)); 56 57 struct pci_softc { 58 struct device sc_dev; 59 bus_space_tag_t sc_iot, sc_memt; 60 bus_dma_tag_t sc_dmat; 61 pci_chipset_tag_t sc_pc; 62 int sc_bus, sc_maxndevs; 63 u_int sc_intrswiz; 64 pcitag_t sc_intrtag; 65 int sc_flags; 66 #ifdef __PCI_OFW_BINDING 67 int sc_node; 68 #endif 69 }; 70 71 struct cfattach pci_ca = { 72 sizeof(struct pci_softc), pcimatch, pciattach 73 }; 74 75 #ifdef __PCI_OFW_BINDING 76 void pci_ofw_probe_bus __P((struct device *)); 77 #else 78 void pci_probe_bus __P((struct device *)); 79 #endif 80 int pciprint __P((void *, const char *)); 81 int pcisubmatch __P((struct device *, struct cfdata *, void *)); 82 83 /* 84 * Important note about PCI-ISA bridges: 85 * 86 * Callbacks are used to configure these devices so that ISA/EISA bridges 87 * can attach their child busses after PCI configuration is done. 88 * 89 * This works because: 90 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 91 * (2) any ISA/EISA bridges must be attached to primary PCI 92 * busses (i.e. bus zero). 93 * 94 * That boils down to: there can only be one of these outstanding 95 * at a time, it is cleared when configuring PCI bus 0 before any 96 * subdevices have been found, and it is run after all subdevices 97 * of PCI bus 0 have been found. 98 * 99 * This is needed because there are some (legacy) PCI devices which 100 * can show up as ISA/EISA devices as well (the prime example of which 101 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 102 * and the bridge is seen before the video board is, the board can show 103 * up as an ISA device, and that can (bogusly) complicate the PCI device's 104 * attach code, or make the PCI device not be properly attached at all. 105 * 106 * We use the generic config_defer() facility to achieve this. 107 */ 108 109 int 110 pcimatch(parent, cf, aux) 111 struct device *parent; 112 struct cfdata *cf; 113 void *aux; 114 { 115 struct pcibus_attach_args *pba = aux; 116 117 if (strcmp(pba->pba_busname, cf->cf_driver->cd_name)) 118 return (0); 119 120 /* Check the locators */ 121 if (cf->pcibuscf_bus != PCIBUS_UNK_BUS && 122 cf->pcibuscf_bus != pba->pba_bus) 123 return (0); 124 125 /* sanity */ 126 if (pba->pba_bus < 0 || pba->pba_bus > 255) 127 return (0); 128 129 /* 130 * XXX check other (hardware?) indicators 131 */ 132 133 return 1; 134 } 135 136 #ifdef __PCI_OFW_BINDING 137 void 138 pci_ofw_probe_bus(self) 139 struct device *self; 140 { 141 struct pci_softc *sc = (struct pci_softc *)self; 142 int node; 143 144 for (node = OF_child(sc->sc_node); node; node = OF_peer(node)) { 145 146 } 147 } 148 #else 149 void 150 pci_probe_bus(self) 151 struct device *self; 152 { 153 struct pci_softc *sc = (struct pci_softc *)self; 154 bus_space_tag_t iot, memt; 155 pci_chipset_tag_t pc; 156 const struct pci_quirkdata *qd; 157 int bus, device, maxndevs, function, nfunctions; 158 159 iot = sc->sc_iot; 160 memt = sc->sc_memt; 161 pc = sc->sc_pc; 162 bus = sc->sc_bus; 163 maxndevs = sc->sc_maxndevs; 164 165 for (device = 0; device < maxndevs; device++) { 166 pcitag_t tag; 167 pcireg_t id, class, intr, bhlcr, csr; 168 struct pci_attach_args pa; 169 int pin; 170 171 tag = pci_make_tag(pc, bus, device, 0); 172 id = pci_conf_read(pc, tag, PCI_ID_REG); 173 174 /* Invalid vendor ID value? */ 175 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 176 continue; 177 /* XXX Not invalid, but we've done this ~forever. */ 178 if (PCI_VENDOR(id) == 0) 179 continue; 180 181 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 182 183 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 184 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 185 (qd != NULL && 186 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 187 nfunctions = 8; 188 else 189 nfunctions = 1; 190 191 for (function = 0; function < nfunctions; function++) { 192 tag = pci_make_tag(pc, bus, device, function); 193 id = pci_conf_read(pc, tag, PCI_ID_REG); 194 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 195 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 196 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 197 198 /* Invalid vendor ID value? */ 199 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 200 continue; 201 /* XXX Not invalid, but we've done this ~forever. */ 202 if (PCI_VENDOR(id) == 0) 203 continue; 204 205 pa.pa_iot = iot; 206 pa.pa_memt = memt; 207 pa.pa_dmat = sc->sc_dmat; 208 pa.pa_pc = pc; 209 pa.pa_device = device; 210 pa.pa_function = function; 211 pa.pa_tag = tag; 212 pa.pa_id = id; 213 pa.pa_class = class; 214 215 /* 216 * Set up memory, I/O enable, and PCI command flags 217 * as appropriate. 218 */ 219 pa.pa_flags = sc->sc_flags; 220 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) 221 pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED; 222 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) 223 pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED; 224 225 if (bus == 0) { 226 pa.pa_intrswiz = 0; 227 pa.pa_intrtag = tag; 228 } else { 229 pa.pa_intrswiz = sc->sc_intrswiz + device; 230 pa.pa_intrtag = sc->sc_intrtag; 231 } 232 pin = PCI_INTERRUPT_PIN(intr); 233 if (pin == PCI_INTERRUPT_PIN_NONE) { 234 /* no interrupt */ 235 pa.pa_intrpin = 0; 236 } else { 237 /* 238 * swizzle it based on the number of 239 * busses we're behind and our device 240 * number. 241 */ 242 pa.pa_intrpin = /* XXX */ 243 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 244 } 245 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 246 247 config_found_sm(self, &pa, pciprint, pcisubmatch); 248 } 249 } 250 } 251 #endif 252 253 void 254 pciattach(parent, self, aux) 255 struct device *parent, *self; 256 void *aux; 257 { 258 struct pcibus_attach_args *pba = aux; 259 struct pci_softc *sc = (struct pci_softc *)self; 260 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 261 const char *sep = ""; 262 263 pci_attach_hook(parent, self, pba); 264 printf("\n"); 265 266 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_ENABLED); 267 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_ENABLED); 268 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 269 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 270 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 271 272 if (io_enabled == 0 && mem_enabled == 0) { 273 printf("%s: no spaces enabled!\n", self->dv_xname); 274 return; 275 } 276 277 #define PRINT(s) do { printf("%s%s", sep, s); sep = ", "; } while (0) 278 279 printf("%s: ", self->dv_xname); 280 281 if (io_enabled) 282 PRINT("i/o space"); 283 if (mem_enabled) 284 PRINT("memory space"); 285 printf(" enabled"); 286 287 if (mrl_enabled || mrm_enabled || mwi_enabled) { 288 if (mrl_enabled) 289 PRINT("rd/line"); 290 if (mrm_enabled) 291 PRINT("rd/mult"); 292 if (mwi_enabled) 293 PRINT("wr/inv"); 294 printf(" ok"); 295 } 296 297 printf("\n"); 298 299 #undef PRINT 300 301 sc->sc_iot = pba->pba_iot; 302 sc->sc_memt = pba->pba_memt; 303 sc->sc_dmat = pba->pba_dmat; 304 sc->sc_pc = pba->pba_pc; 305 sc->sc_bus = pba->pba_bus; 306 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 307 sc->sc_intrswiz = pba->pba_intrswiz; 308 sc->sc_intrtag = pba->pba_intrtag; 309 sc->sc_flags = pba->pba_flags; 310 #ifdef __PCI_OFW_BINDING 311 sc->sc_node = pba->pba_node; 312 313 pci_ofw_probe_bus(self); 314 #else 315 pci_probe_bus(self); 316 #endif 317 } 318 319 int 320 pciprint(aux, pnp) 321 void *aux; 322 const char *pnp; 323 { 324 struct pci_attach_args *pa = aux; 325 char devinfo[256]; 326 const struct pci_quirkdata *qd; 327 328 if (pnp) { 329 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo); 330 printf("%s at %s", devinfo, pnp); 331 } 332 printf(" dev %d function %d", pa->pa_device, pa->pa_function); 333 if (pci_config_dump) { 334 printf(": "); 335 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 336 if (!pnp) 337 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo); 338 printf("%s at %s", devinfo, pnp ? pnp : "?"); 339 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 340 #ifdef __i386__ 341 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 342 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 343 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 344 #else 345 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 346 (long)pa->pa_tag, (long)pa->pa_intrtag, (long)pa->pa_intrswiz, 347 (long)pa->pa_intrpin); 348 #endif 349 printf(", i/o %s, mem %s,", 350 pa->pa_flags & PCI_FLAGS_IO_ENABLED ? "on" : "off", 351 pa->pa_flags & PCI_FLAGS_MEM_ENABLED ? "on" : "off"); 352 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 353 PCI_PRODUCT(pa->pa_id)); 354 if (qd == NULL) { 355 printf(" no quirks"); 356 } else { 357 bitmask_snprintf(qd->quirks, 358 "\20\1multifn", devinfo, sizeof (devinfo)); 359 printf(" quirks %s", devinfo); 360 } 361 printf(")"); 362 } 363 return (UNCONF); 364 } 365 366 int 367 pcisubmatch(parent, cf, aux) 368 struct device *parent; 369 struct cfdata *cf; 370 void *aux; 371 { 372 struct pci_attach_args *pa = aux; 373 374 if (cf->pcicf_dev != PCI_UNK_DEV && 375 cf->pcicf_dev != pa->pa_device) 376 return 0; 377 if (cf->pcicf_function != PCI_UNK_FUNCTION && 378 cf->pcicf_function != pa->pa_function) 379 return 0; 380 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 381 } 382 383 int 384 pci_get_capability(pc, tag, capid, offset, value) 385 pci_chipset_tag_t pc; 386 pcitag_t tag; 387 int capid; 388 int *offset; 389 pcireg_t *value; 390 { 391 pcireg_t reg; 392 unsigned int ofs; 393 394 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 395 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 396 return (0); 397 398 /* Determine the Capability List Pointer register to start with. */ 399 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 400 switch (PCI_HDRTYPE_TYPE(reg)) { 401 case 0: /* standard device header */ 402 ofs = PCI_CAPLISTPTR_REG; 403 break; 404 case 2: /* PCI-CardBus Bridge header */ 405 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 406 break; 407 default: 408 return (0); 409 } 410 411 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 412 while (ofs != 0) { 413 #ifdef DIAGNOSTIC 414 if ((ofs & 3) || (ofs < 0x40)) 415 panic("pci_get_capability"); 416 #endif 417 reg = pci_conf_read(pc, tag, ofs); 418 if (PCI_CAPLIST_CAP(reg) == capid) { 419 if (offset) 420 *offset = ofs; 421 if (value) 422 *value = reg; 423 return (1); 424 } 425 ofs = PCI_CAPLIST_NEXT(reg); 426 } 427 428 return (0); 429 } 430