1 /* $NetBSD: pci.c,v 1.121 2008/12/16 22:35:33 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996, 1997, 1998 5 * Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * PCI bus autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.121 2008/12/16 22:35:33 christos Exp $"); 40 41 #include "opt_pci.h" 42 43 #include <sys/param.h> 44 #include <sys/malloc.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcidevs.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <net/if.h> 55 56 #include "locators.h" 57 58 static bool pci_child_register(device_t); 59 60 #ifdef PCI_CONFIG_DUMP 61 int pci_config_dump = 1; 62 #else 63 int pci_config_dump = 0; 64 #endif 65 66 int pciprint(void *, const char *); 67 68 #ifdef PCI_MACHDEP_ENUMERATE_BUS 69 #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS 70 #else 71 int pci_enumerate_bus(struct pci_softc *, const int *, 72 int (*)(struct pci_attach_args *), struct pci_attach_args *); 73 #endif 74 75 /* 76 * Important note about PCI-ISA bridges: 77 * 78 * Callbacks are used to configure these devices so that ISA/EISA bridges 79 * can attach their child busses after PCI configuration is done. 80 * 81 * This works because: 82 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 83 * (2) any ISA/EISA bridges must be attached to primary PCI 84 * busses (i.e. bus zero). 85 * 86 * That boils down to: there can only be one of these outstanding 87 * at a time, it is cleared when configuring PCI bus 0 before any 88 * subdevices have been found, and it is run after all subdevices 89 * of PCI bus 0 have been found. 90 * 91 * This is needed because there are some (legacy) PCI devices which 92 * can show up as ISA/EISA devices as well (the prime example of which 93 * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge, 94 * and the bridge is seen before the video board is, the board can show 95 * up as an ISA device, and that can (bogusly) complicate the PCI device's 96 * attach code, or make the PCI device not be properly attached at all. 97 * 98 * We use the generic config_defer() facility to achieve this. 99 */ 100 101 int 102 pcirescan(device_t self, const char *ifattr, const int *locators) 103 { 104 struct pci_softc *sc = device_private(self); 105 106 KASSERT(ifattr && !strcmp(ifattr, "pci")); 107 KASSERT(locators); 108 109 pci_enumerate_bus(sc, locators, NULL, NULL); 110 return 0; 111 } 112 113 int 114 pcimatch(device_t parent, cfdata_t cf, void *aux) 115 { 116 struct pcibus_attach_args *pba = aux; 117 118 /* Check the locators */ 119 if (cf->cf_loc[PCIBUSCF_BUS] != PCIBUSCF_BUS_DEFAULT && 120 cf->cf_loc[PCIBUSCF_BUS] != pba->pba_bus) 121 return (0); 122 123 /* sanity */ 124 if (pba->pba_bus < 0 || pba->pba_bus > 255) 125 return (0); 126 127 /* 128 * XXX check other (hardware?) indicators 129 */ 130 131 return (1); 132 } 133 134 void 135 pciattach(device_t parent, device_t self, void *aux) 136 { 137 struct pcibus_attach_args *pba = aux; 138 struct pci_softc *sc = device_private(self); 139 int io_enabled, mem_enabled, mrl_enabled, mrm_enabled, mwi_enabled; 140 const char *sep = ""; 141 static const int wildcard[PCICF_NLOCS] = { 142 PCICF_DEV_DEFAULT, PCICF_FUNCTION_DEFAULT 143 }; 144 145 sc->sc_dev = self; 146 147 pci_attach_hook(parent, self, pba); 148 149 aprint_naive("\n"); 150 aprint_normal("\n"); 151 152 io_enabled = (pba->pba_flags & PCI_FLAGS_IO_ENABLED); 153 mem_enabled = (pba->pba_flags & PCI_FLAGS_MEM_ENABLED); 154 mrl_enabled = (pba->pba_flags & PCI_FLAGS_MRL_OKAY); 155 mrm_enabled = (pba->pba_flags & PCI_FLAGS_MRM_OKAY); 156 mwi_enabled = (pba->pba_flags & PCI_FLAGS_MWI_OKAY); 157 158 if (io_enabled == 0 && mem_enabled == 0) { 159 aprint_error_dev(self, "no spaces enabled!\n"); 160 goto fail; 161 } 162 163 #define PRINT(str) \ 164 do { \ 165 aprint_verbose("%s%s", sep, str); \ 166 sep = ", "; \ 167 } while (/*CONSTCOND*/0) 168 169 aprint_verbose_dev(self, ""); 170 171 if (io_enabled) 172 PRINT("i/o space"); 173 if (mem_enabled) 174 PRINT("memory space"); 175 aprint_verbose(" enabled"); 176 177 if (mrl_enabled || mrm_enabled || mwi_enabled) { 178 if (mrl_enabled) 179 PRINT("rd/line"); 180 if (mrm_enabled) 181 PRINT("rd/mult"); 182 if (mwi_enabled) 183 PRINT("wr/inv"); 184 aprint_verbose(" ok"); 185 } 186 187 aprint_verbose("\n"); 188 189 #undef PRINT 190 191 sc->sc_iot = pba->pba_iot; 192 sc->sc_memt = pba->pba_memt; 193 sc->sc_dmat = pba->pba_dmat; 194 sc->sc_dmat64 = pba->pba_dmat64; 195 sc->sc_pc = pba->pba_pc; 196 sc->sc_bus = pba->pba_bus; 197 sc->sc_bridgetag = pba->pba_bridgetag; 198 sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus); 199 sc->sc_intrswiz = pba->pba_intrswiz; 200 sc->sc_intrtag = pba->pba_intrtag; 201 sc->sc_flags = pba->pba_flags; 202 203 device_pmf_driver_set_child_register(sc->sc_dev, pci_child_register); 204 205 pcirescan(sc->sc_dev, "pci", wildcard); 206 207 fail: 208 if (!pmf_device_register(self, NULL, NULL)) 209 aprint_error_dev(self, "couldn't establish power handler\n"); 210 } 211 212 int 213 pcidetach(device_t self, int flags) 214 { 215 int rc; 216 217 if ((rc = config_detach_children(self, flags)) != 0) 218 return rc; 219 pmf_device_deregister(self); 220 return 0; 221 } 222 223 int 224 pciprint(void *aux, const char *pnp) 225 { 226 struct pci_attach_args *pa = aux; 227 char devinfo[256]; 228 const struct pci_quirkdata *qd; 229 230 if (pnp) { 231 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 232 aprint_normal("%s at %s", devinfo, pnp); 233 } 234 aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function); 235 if (pci_config_dump) { 236 printf(": "); 237 pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 238 if (!pnp) 239 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 240 printf("%s at %s", devinfo, pnp ? pnp : "?"); 241 printf(" dev %d function %d (", pa->pa_device, pa->pa_function); 242 #ifdef __i386__ 243 printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx", 244 *(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag, 245 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 246 #else 247 printf("intrswiz %#lx, intrpin %#lx", 248 (long)pa->pa_intrswiz, (long)pa->pa_intrpin); 249 #endif 250 printf(", i/o %s, mem %s,", 251 pa->pa_flags & PCI_FLAGS_IO_ENABLED ? "on" : "off", 252 pa->pa_flags & PCI_FLAGS_MEM_ENABLED ? "on" : "off"); 253 qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 254 PCI_PRODUCT(pa->pa_id)); 255 if (qd == NULL) { 256 printf(" no quirks"); 257 } else { 258 snprintb(devinfo, sizeof (devinfo), 259 "\002\001multifn\002singlefn\003skipfunc0" 260 "\004skipfunc1\005skipfunc2\006skipfunc3" 261 "\007skipfunc4\010skipfunc5\011skipfunc6" 262 "\012skipfunc7", qd->quirks); 263 printf(" quirks %s", devinfo); 264 } 265 printf(")"); 266 } 267 return (UNCONF); 268 } 269 270 int 271 pci_probe_device(struct pci_softc *sc, pcitag_t tag, 272 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 273 { 274 pci_chipset_tag_t pc = sc->sc_pc; 275 struct pci_attach_args pa; 276 pcireg_t id, csr, class, intr, bhlcr; 277 int ret, pin, bus, device, function; 278 int locs[PCICF_NLOCS]; 279 device_t subdev; 280 281 pci_decompose_tag(pc, tag, &bus, &device, &function); 282 283 /* a driver already attached? */ 284 if (sc->PCI_SC_DEVICESC(device, function).c_dev != NULL && !match) 285 return (0); 286 287 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 288 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 289 return (0); 290 291 id = pci_conf_read(pc, tag, PCI_ID_REG); 292 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 293 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 294 295 /* Invalid vendor ID value? */ 296 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 297 return (0); 298 /* XXX Not invalid, but we've done this ~forever. */ 299 if (PCI_VENDOR(id) == 0) 300 return (0); 301 302 pa.pa_iot = sc->sc_iot; 303 pa.pa_memt = sc->sc_memt; 304 pa.pa_dmat = sc->sc_dmat; 305 pa.pa_dmat64 = sc->sc_dmat64; 306 pa.pa_pc = pc; 307 pa.pa_bus = bus; 308 pa.pa_device = device; 309 pa.pa_function = function; 310 pa.pa_tag = tag; 311 pa.pa_id = id; 312 pa.pa_class = class; 313 314 /* 315 * Set up memory, I/O enable, and PCI command flags 316 * as appropriate. 317 */ 318 pa.pa_flags = sc->sc_flags; 319 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) 320 pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED; 321 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) 322 pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED; 323 324 /* 325 * If the cache line size is not configured, then 326 * clear the MRL/MRM/MWI command-ok flags. 327 */ 328 if (PCI_CACHELINE(bhlcr) == 0) 329 pa.pa_flags &= ~(PCI_FLAGS_MRL_OKAY| 330 PCI_FLAGS_MRM_OKAY|PCI_FLAGS_MWI_OKAY); 331 332 if (sc->sc_bridgetag == NULL) { 333 pa.pa_intrswiz = 0; 334 pa.pa_intrtag = tag; 335 } else { 336 pa.pa_intrswiz = sc->sc_intrswiz + device; 337 pa.pa_intrtag = sc->sc_intrtag; 338 } 339 340 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 341 342 pin = PCI_INTERRUPT_PIN(intr); 343 pa.pa_rawintrpin = pin; 344 if (pin == PCI_INTERRUPT_PIN_NONE) { 345 /* no interrupt */ 346 pa.pa_intrpin = 0; 347 } else { 348 /* 349 * swizzle it based on the number of busses we're 350 * behind and our device number. 351 */ 352 pa.pa_intrpin = /* XXX */ 353 ((pin + pa.pa_intrswiz - 1) % 4) + 1; 354 } 355 pa.pa_intrline = PCI_INTERRUPT_LINE(intr); 356 357 if (match != NULL) { 358 ret = (*match)(&pa); 359 if (ret != 0 && pap != NULL) 360 *pap = pa; 361 } else { 362 struct pci_child *c; 363 locs[PCICF_DEV] = device; 364 locs[PCICF_FUNCTION] = function; 365 366 subdev = config_found_sm_loc(sc->sc_dev, "pci", locs, &pa, 367 pciprint, config_stdsubmatch); 368 369 c = &sc->PCI_SC_DEVICESC(device, function); 370 c->c_dev = subdev; 371 pci_conf_capture(pc, tag, &c->c_conf); 372 if (pci_get_powerstate(pc, tag, &c->c_powerstate) == 0) 373 c->c_psok = true; 374 else 375 c->c_psok = false; 376 ret = (subdev != NULL); 377 } 378 379 return (ret); 380 } 381 382 void 383 pcidevdetached(device_t self, device_t child) 384 { 385 struct pci_softc *sc = device_private(self); 386 int d, f; 387 pcitag_t tag; 388 struct pci_child *c; 389 390 d = device_locator(child, PCICF_DEV); 391 f = device_locator(child, PCICF_FUNCTION); 392 393 c = &sc->PCI_SC_DEVICESC(d, f); 394 395 KASSERT(c->c_dev == child); 396 397 tag = pci_make_tag(sc->sc_pc, sc->sc_bus, d, f); 398 if (c->c_psok) 399 pci_set_powerstate(sc->sc_pc, tag, c->c_powerstate); 400 pci_conf_restore(sc->sc_pc, tag, &c->c_conf); 401 c->c_dev = NULL; 402 } 403 404 CFATTACH_DECL2_NEW(pci, sizeof(struct pci_softc), 405 pcimatch, pciattach, pcidetach, NULL, pcirescan, pcidevdetached); 406 407 int 408 pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid, 409 int *offset, pcireg_t *value) 410 { 411 pcireg_t reg; 412 unsigned int ofs; 413 414 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 415 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 416 return (0); 417 418 /* Determine the Capability List Pointer register to start with. */ 419 reg = pci_conf_read(pc, tag, PCI_BHLC_REG); 420 switch (PCI_HDRTYPE_TYPE(reg)) { 421 case 0: /* standard device header */ 422 case 1: /* PCI-PCI bridge header */ 423 ofs = PCI_CAPLISTPTR_REG; 424 break; 425 case 2: /* PCI-CardBus Bridge header */ 426 ofs = PCI_CARDBUS_CAPLISTPTR_REG; 427 break; 428 default: 429 return (0); 430 } 431 432 ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs)); 433 while (ofs != 0) { 434 if ((ofs & 3) || (ofs < 0x40)) { 435 int bus, device, function; 436 437 pci_decompose_tag(pc, tag, &bus, &device, &function); 438 439 printf("Skipping broken PCI header on %d:%d:%d\n", 440 bus, device, function); 441 break; 442 } 443 reg = pci_conf_read(pc, tag, ofs); 444 if (PCI_CAPLIST_CAP(reg) == capid) { 445 if (offset) 446 *offset = ofs; 447 if (value) 448 *value = reg; 449 return (1); 450 } 451 ofs = PCI_CAPLIST_NEXT(reg); 452 } 453 454 return (0); 455 } 456 457 int 458 pci_find_device(struct pci_attach_args *pa, 459 int (*match)(struct pci_attach_args *)) 460 { 461 extern struct cfdriver pci_cd; 462 device_t pcidev; 463 int i; 464 static const int wildcard[2] = { 465 PCICF_DEV_DEFAULT, 466 PCICF_FUNCTION_DEFAULT 467 }; 468 469 for (i = 0; i < pci_cd.cd_ndevs; i++) { 470 pcidev = device_lookup(&pci_cd, i); 471 if (pcidev != NULL && 472 pci_enumerate_bus(device_private(pcidev), wildcard, 473 match, pa) != 0) 474 return (1); 475 } 476 return (0); 477 } 478 479 #ifndef PCI_MACHDEP_ENUMERATE_BUS 480 /* 481 * Generic PCI bus enumeration routine. Used unless machine-dependent 482 * code needs to provide something else. 483 */ 484 int 485 pci_enumerate_bus(struct pci_softc *sc, const int *locators, 486 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 487 { 488 pci_chipset_tag_t pc = sc->sc_pc; 489 int device, function, nfunctions, ret; 490 const struct pci_quirkdata *qd; 491 pcireg_t id, bhlcr; 492 pcitag_t tag; 493 #ifdef __PCI_BUS_DEVORDER 494 char devs[32]; 495 int i; 496 #endif 497 498 #ifdef __PCI_BUS_DEVORDER 499 pci_bus_devorder(sc->sc_pc, sc->sc_bus, devs); 500 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) 501 #else 502 for (device = 0; device < sc->sc_maxndevs; device++) 503 #endif 504 { 505 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 506 (locators[PCICF_DEV] != device)) 507 continue; 508 509 tag = pci_make_tag(pc, sc->sc_bus, device, 0); 510 511 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 512 if (PCI_HDRTYPE_TYPE(bhlcr) > 2) 513 continue; 514 515 id = pci_conf_read(pc, tag, PCI_ID_REG); 516 517 /* Invalid vendor ID value? */ 518 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 519 continue; 520 /* XXX Not invalid, but we've done this ~forever. */ 521 if (PCI_VENDOR(id) == 0) 522 continue; 523 524 qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id)); 525 526 if (qd != NULL && 527 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0) 528 nfunctions = 8; 529 else if (qd != NULL && 530 (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0) 531 nfunctions = 1; 532 else 533 nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 534 535 for (function = 0; function < nfunctions; function++) { 536 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) 537 && (locators[PCICF_FUNCTION] != function)) 538 continue; 539 540 if (qd != NULL && 541 (qd->quirks & PCI_QUIRK_SKIP_FUNC(function)) != 0) 542 continue; 543 tag = pci_make_tag(pc, sc->sc_bus, device, function); 544 ret = pci_probe_device(sc, tag, match, pap); 545 if (match != NULL && ret != 0) 546 return (ret); 547 } 548 } 549 return (0); 550 } 551 #endif /* PCI_MACHDEP_ENUMERATE_BUS */ 552 553 554 /* 555 * Vital Product Data (PCI 2.2) 556 */ 557 558 int 559 pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 560 pcireg_t *data) 561 { 562 uint32_t reg; 563 int ofs, i, j; 564 565 KASSERT(data != NULL); 566 KASSERT((offset + count) < 0x7fff); 567 568 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 569 return (1); 570 571 for (i = 0; i < count; offset += sizeof(*data), i++) { 572 reg &= 0x0000ffff; 573 reg &= ~PCI_VPD_OPFLAG; 574 reg |= PCI_VPD_ADDRESS(offset); 575 pci_conf_write(pc, tag, ofs, reg); 576 577 /* 578 * PCI 2.2 does not specify how long we should poll 579 * for completion nor whether the operation can fail. 580 */ 581 j = 0; 582 do { 583 if (j++ == 20) 584 return (1); 585 delay(4); 586 reg = pci_conf_read(pc, tag, ofs); 587 } while ((reg & PCI_VPD_OPFLAG) == 0); 588 data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs)); 589 } 590 591 return (0); 592 } 593 594 int 595 pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count, 596 pcireg_t *data) 597 { 598 pcireg_t reg; 599 int ofs, i, j; 600 601 KASSERT(data != NULL); 602 KASSERT((offset + count) < 0x7fff); 603 604 if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0) 605 return (1); 606 607 for (i = 0; i < count; offset += sizeof(*data), i++) { 608 pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]); 609 610 reg &= 0x0000ffff; 611 reg |= PCI_VPD_OPFLAG; 612 reg |= PCI_VPD_ADDRESS(offset); 613 pci_conf_write(pc, tag, ofs, reg); 614 615 /* 616 * PCI 2.2 does not specify how long we should poll 617 * for completion nor whether the operation can fail. 618 */ 619 j = 0; 620 do { 621 if (j++ == 20) 622 return (1); 623 delay(1); 624 reg = pci_conf_read(pc, tag, ofs); 625 } while (reg & PCI_VPD_OPFLAG); 626 } 627 628 return (0); 629 } 630 631 int 632 pci_dma64_available(struct pci_attach_args *pa) 633 { 634 #ifdef _PCI_HAVE_DMA64 635 if (BUS_DMA_TAG_VALID(pa->pa_dmat64)) 636 return 1; 637 #endif 638 return 0; 639 } 640 641 void 642 pci_conf_capture(pci_chipset_tag_t pc, pcitag_t tag, 643 struct pci_conf_state *pcs) 644 { 645 int off; 646 647 for (off = 0; off < 16; off++) 648 pcs->reg[off] = pci_conf_read(pc, tag, (off * 4)); 649 650 return; 651 } 652 653 void 654 pci_conf_restore(pci_chipset_tag_t pc, pcitag_t tag, 655 struct pci_conf_state *pcs) 656 { 657 int off; 658 pcireg_t val; 659 660 for (off = 15; off >= 0; off--) { 661 val = pci_conf_read(pc, tag, (off * 4)); 662 if (val != pcs->reg[off]) 663 pci_conf_write(pc, tag, (off * 4), pcs->reg[off]); 664 } 665 666 return; 667 } 668 669 /* 670 * Power Management Capability (Rev 2.2) 671 */ 672 static int 673 pci_get_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state, 674 int offset) 675 { 676 pcireg_t value, now; 677 678 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 679 now = value & PCI_PMCSR_STATE_MASK; 680 switch (now) { 681 case PCI_PMCSR_STATE_D0: 682 case PCI_PMCSR_STATE_D1: 683 case PCI_PMCSR_STATE_D2: 684 case PCI_PMCSR_STATE_D3: 685 *state = now; 686 return 0; 687 default: 688 return EINVAL; 689 } 690 } 691 692 int 693 pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag , pcireg_t *state) 694 { 695 int offset; 696 pcireg_t value; 697 698 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) 699 return EOPNOTSUPP; 700 701 return pci_get_powerstate_int(pc, tag, state, offset); 702 } 703 704 static int 705 pci_set_powerstate_int(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state, 706 int offset, pcireg_t cap_reg) 707 { 708 pcireg_t value, cap, now; 709 710 cap = cap_reg >> PCI_PMCR_SHIFT; 711 value = pci_conf_read(pc, tag, offset + PCI_PMCSR); 712 now = value & PCI_PMCSR_STATE_MASK; 713 value &= ~PCI_PMCSR_STATE_MASK; 714 715 if (now == state) 716 return 0; 717 switch (state) { 718 case PCI_PMCSR_STATE_D0: 719 break; 720 case PCI_PMCSR_STATE_D1: 721 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) { 722 printf("invalid transition from %d to D1\n", (int)now); 723 return EINVAL; 724 } 725 if (!(cap & PCI_PMCR_D1SUPP)) { 726 printf("D1 not supported\n"); 727 return EOPNOTSUPP; 728 } 729 break; 730 case PCI_PMCSR_STATE_D2: 731 if (now == PCI_PMCSR_STATE_D3) { 732 printf("invalid transition from %d to D2\n", (int)now); 733 return EINVAL; 734 } 735 if (!(cap & PCI_PMCR_D2SUPP)) { 736 printf("D2 not supported\n"); 737 return EOPNOTSUPP; 738 } 739 break; 740 case PCI_PMCSR_STATE_D3: 741 break; 742 default: 743 return EINVAL; 744 } 745 value |= state; 746 pci_conf_write(pc, tag, offset + PCI_PMCSR, value); 747 /* delay according to pcipm1.2, ch. 5.6.1 */ 748 if (state == PCI_PMCSR_STATE_D3 || now == PCI_PMCSR_STATE_D3) 749 DELAY(10000); 750 else if (state == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D2) 751 DELAY(200); 752 753 return 0; 754 } 755 756 int 757 pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, pcireg_t state) 758 { 759 int offset; 760 pcireg_t value; 761 762 if (!pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, &value)) { 763 printf("pci_set_powerstate not supported\n"); 764 return EOPNOTSUPP; 765 } 766 767 return pci_set_powerstate_int(pc, tag, state, offset, value); 768 } 769 770 int 771 pci_activate(pci_chipset_tag_t pc, pcitag_t tag, device_t dev, 772 int (*wakefun)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t)) 773 { 774 pcireg_t pmode; 775 int error; 776 777 if ((error = pci_get_powerstate(pc, tag, &pmode))) 778 return error; 779 780 switch (pmode) { 781 case PCI_PMCSR_STATE_D0: 782 break; 783 case PCI_PMCSR_STATE_D3: 784 if (wakefun == NULL) { 785 /* 786 * The card has lost all configuration data in 787 * this state, so punt. 788 */ 789 aprint_error_dev(dev, 790 "unable to wake up from power state D3\n"); 791 return EOPNOTSUPP; 792 } 793 /*FALLTHROUGH*/ 794 default: 795 if (wakefun) { 796 error = (*wakefun)(pc, tag, dev, pmode); 797 if (error) 798 return error; 799 } 800 aprint_normal_dev(dev, "waking up from power state D%d\n", 801 pmode); 802 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 803 return error; 804 } 805 return 0; 806 } 807 808 int 809 pci_activate_null(pci_chipset_tag_t pc, pcitag_t tag, 810 device_t dev, pcireg_t state) 811 { 812 return 0; 813 } 814 815 /* I have disabled this code for now. --dyoung 816 * 817 * Insofar as I understand what the PCI retry timeout is [1], 818 * I see no justification for any driver to disable when it 819 * attaches/resumes a device. 820 * 821 * A PCI bus bridge may tell a bus master to retry its transaction 822 * at a later time if the resources to complete the transaction 823 * are not immediately available. Taking a guess, PCI bus masters 824 * that implement a PCI retry timeout register count down from the 825 * retry timeout to 0 while it retries a delayed PCI transaction. 826 * When it reaches 0, it stops retrying. A PCI master is *never* 827 * supposed to stop retrying a delayed transaction, though. 828 * 829 * Incidentally, I initially suspected that writing 0 to the register 830 * would not disable *retries*, but would disable the timeout. 831 * That is, any device whose retry timeout was set to 0 would 832 * *never* timeout. However, I found out, by using PCI debug 833 * facilities on the AMD Elan SC520, that if I write 0 to the retry 834 * timeout register on an ath(4) MiniPCI card, the card really does 835 * not retry transactions. 836 * 837 * Some uses of this register have mentioned "interference" with 838 * a CPU's "C3 sleep state." It seems to me that if a bus master 839 * is properly put to sleep, it will neither initiate new transactions, 840 * nor retry delayed transactions, so disabling retries should not 841 * be necessary. 842 * 843 * [1] The timeout does not appear to be documented in any PCI 844 * standard, and we have no documentation of it for the devices by 845 * Atheros, and others, that supposedly implement it. 846 */ 847 void 848 pci_disable_retry(pci_chipset_tag_t pc, pcitag_t tag) 849 { 850 #if 0 851 pcireg_t retry; 852 853 /* 854 * Disable retry timeout to keep PCI Tx retries from 855 * interfering with ACPI C3 CPU state. 856 */ 857 retry = pci_conf_read(pc, tag, PCI_RETRY_TIMEOUT_REG); 858 retry &= ~PCI_RETRY_TIMEOUT_REG_MASK; 859 pci_conf_write(pc, tag, PCI_RETRY_TIMEOUT_REG, retry); 860 #endif 861 } 862 863 struct pci_child_power { 864 struct pci_conf_state p_pciconf; 865 pci_chipset_tag_t p_pc; 866 pcitag_t p_tag; 867 bool p_has_pm; 868 int p_pm_offset; 869 pcireg_t p_pm_cap; 870 pcireg_t p_class; 871 }; 872 873 static bool 874 pci_child_suspend(device_t dv PMF_FN_ARGS) 875 { 876 struct pci_child_power *priv = device_pmf_bus_private(dv); 877 pcireg_t ocsr, csr; 878 879 pci_conf_capture(priv->p_pc, priv->p_tag, &priv->p_pciconf); 880 881 if (!priv->p_has_pm) 882 return true; /* ??? hopefully handled by ACPI */ 883 if (PCI_CLASS(priv->p_class) == PCI_CLASS_DISPLAY) 884 return true; /* XXX */ 885 886 /* disable decoding and busmastering, see pcipm1.2 ch. 8.2.1 */ 887 ocsr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 888 csr = ocsr & ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE 889 | PCI_COMMAND_MASTER_ENABLE); 890 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 891 if (pci_set_powerstate_int(priv->p_pc, priv->p_tag, 892 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) { 893 pci_conf_write(priv->p_pc, priv->p_tag, 894 PCI_COMMAND_STATUS_REG, ocsr); 895 aprint_error_dev(dv, "unsupported state, continuing.\n"); 896 return false; 897 } 898 return true; 899 } 900 901 static bool 902 pci_child_resume(device_t dv PMF_FN_ARGS) 903 { 904 struct pci_child_power *priv = device_pmf_bus_private(dv); 905 906 if (priv->p_has_pm && 907 pci_set_powerstate_int(priv->p_pc, priv->p_tag, 908 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) { 909 aprint_error_dev(dv, "unsupported state, continuing.\n"); 910 return false; 911 } 912 913 pci_conf_restore(priv->p_pc, priv->p_tag, &priv->p_pciconf); 914 915 return true; 916 } 917 918 static bool 919 pci_child_shutdown(device_t dv, int how) 920 { 921 struct pci_child_power *priv = device_pmf_bus_private(dv); 922 pcireg_t csr; 923 924 /* disable busmastering */ 925 csr = pci_conf_read(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG); 926 csr &= ~PCI_COMMAND_MASTER_ENABLE; 927 pci_conf_write(priv->p_pc, priv->p_tag, PCI_COMMAND_STATUS_REG, csr); 928 return true; 929 } 930 931 static void 932 pci_child_deregister(device_t dv) 933 { 934 struct pci_child_power *priv = device_pmf_bus_private(dv); 935 936 free(priv, M_DEVBUF); 937 } 938 939 static bool 940 pci_child_register(device_t child) 941 { 942 device_t self = device_parent(child); 943 struct pci_softc *sc = device_private(self); 944 struct pci_child_power *priv; 945 int device, function, off; 946 pcireg_t reg; 947 948 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK); 949 950 device = device_locator(child, PCICF_DEV); 951 function = device_locator(child, PCICF_FUNCTION); 952 953 priv->p_pc = sc->sc_pc; 954 priv->p_tag = pci_make_tag(priv->p_pc, sc->sc_bus, device, 955 function); 956 priv->p_class = pci_conf_read(priv->p_pc, priv->p_tag, PCI_CLASS_REG); 957 958 if (pci_get_capability(priv->p_pc, priv->p_tag, 959 PCI_CAP_PWRMGMT, &off, ®)) { 960 priv->p_has_pm = true; 961 priv->p_pm_offset = off; 962 priv->p_pm_cap = reg; 963 } else { 964 priv->p_has_pm = false; 965 priv->p_pm_offset = -1; 966 } 967 968 device_pmf_bus_register(child, priv, pci_child_suspend, 969 pci_child_resume, pci_child_shutdown, pci_child_deregister); 970 971 return true; 972 } 973