1 /* $NetBSD: pccbbvar.h,v 1.38 2009/07/23 21:22:25 dyoung Exp $ */ 2 /* 3 * Copyright (c) 1999 HAYAKAWA Koichi. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by HAYAKAWA Koichi. 16 * 4. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* require sys/device.h */ 32 /* require sys/queue.h */ 33 /* require sys/callout.h */ 34 /* require dev/ic/i82365reg.h */ 35 36 #ifndef _DEV_PCI_PCCBBVAR_H_ 37 #define _DEV_PCI_PCCBBVAR_H_ 38 39 #include <sys/mutex.h> 40 #include <sys/condvar.h> 41 42 #define PCIC_FLAG_SOCKETP 0x0001 43 #define PCIC_FLAG_CARDP 0x0002 44 45 /* Chipset ID */ 46 #define CB_UNKNOWN 0 /* NOT Cardbus-PCI bridge */ 47 #define CB_TI113X 1 /* TI PCI1130/1131 */ 48 #define CB_TI12XX 2 /* TI PCI12xx/14xx/44xx/15xx/45xx */ 49 #define CB_RX5C47X 3 /* RICOH RX5C475/476/477 */ 50 #define CB_RX5C46X 4 /* RICOH RX5C465/466/467 */ 51 #define CB_TOPIC95 5 /* Toshiba ToPIC95 */ 52 #define CB_TOPIC95B 6 /* Toshiba ToPIC95B */ 53 #define CB_TOPIC97 7 /* Toshiba ToPIC97 */ 54 #define CB_CIRRUS 8 /* Cirrus Logic CL-PD683X */ 55 #define CB_TI125X 9 /* TI PCI1250/1251(B)/1450 */ 56 #define CB_TI1420 10 /* TI PCI1420 */ 57 #define CB_O2MICRO 11 /* O2 Micro 67xx/68xx/69xx */ 58 59 struct pccbb_intrhand_list; 60 61 struct pccbb_win_chain { 62 bus_addr_t wc_start; /* Caution: region [start, end], */ 63 bus_addr_t wc_end; /* instead of [start, end). */ 64 int wc_flags; 65 bus_space_handle_t wc_handle; 66 TAILQ_ENTRY(pccbb_win_chain) wc_list; 67 }; 68 #define PCCBB_MEM_CACHABLE 1 69 70 TAILQ_HEAD(pccbb_win_chain_head, pccbb_win_chain); 71 72 struct pccbb_softc; /* forward */ 73 struct pcic_handle { 74 /* extracted from i82365var.h */ 75 int memalloc; 76 struct { 77 bus_addr_t addr; 78 bus_size_t size; 79 long offset; 80 int kind; 81 } mem[PCIC_MEM_WINS]; 82 int ioalloc; 83 struct { 84 bus_addr_t addr; 85 bus_size_t size; 86 int width; 87 } io[PCIC_IO_WINS]; 88 }; 89 90 struct pccbb_softc { 91 device_t sc_dev; 92 bus_space_tag_t sc_iot; 93 bus_space_tag_t sc_memt; 94 bus_dma_tag_t sc_dmat; 95 96 #if rbus 97 rbus_tag_t sc_rbus_iot; /* rbus for i/o donated from parent */ 98 rbus_tag_t sc_rbus_memt; /* rbus for mem donated from parent */ 99 #endif 100 101 bus_space_tag_t sc_base_memt; 102 bus_space_handle_t sc_base_memh; 103 bus_size_t sc_base_size; 104 105 struct callout sc_insert_ch; 106 107 void *sc_ih; /* interrupt handler */ 108 struct pci_attach_args sc_pa; /* copy of our attach args */ 109 u_int32_t sc_flags; 110 #define CBB_CARDEXIST 0x01 111 #define CBB_INSERTING 0x01000000 112 #define CBB_16BITCARD 0x04 113 #define CBB_32BITCARD 0x08 114 #define CBB_MEMHMAPPED 0x02000000 115 #define CBB_SPECMAPPED 0x04000000 /* "special" mapping */ 116 117 pci_chipset_tag_t sc_pc; 118 pcitag_t sc_tag; 119 int sc_chipset; /* chipset id */ 120 121 bus_addr_t sc_mem_start; /* CardBus/PCMCIA memory start */ 122 bus_addr_t sc_mem_end; /* CardBus/PCMCIA memory end */ 123 bus_addr_t sc_io_start; /* CardBus/PCMCIA io start */ 124 bus_addr_t sc_io_end; /* CardBus/PCMCIA io end */ 125 126 /* CardBus stuff */ 127 struct cardslot_softc *sc_csc; 128 129 struct pccbb_win_chain_head sc_memwindow; 130 struct pccbb_win_chain_head sc_iowindow; 131 132 /* pcmcia stuff */ 133 struct pcic_handle sc_pcmcia_h; 134 int sc_pcmcia_flags; 135 #define PCCBB_PCMCIA_IO_RELOC 0x01 /* IO addr relocatable stuff exists */ 136 #define PCCBB_PCMCIA_MEM_32 0x02 /* 32-bit memory address ready */ 137 138 volatile int sc_pwrcycle; 139 kcondvar_t sc_pwr_cv; 140 kmutex_t sc_pwr_mtx; 141 142 /* interrupt handler list on the bridge */ 143 LIST_HEAD(, pccbb_intrhand_list) sc_pil; 144 int sc_pil_intr_enable; /* can i call intr handler for child device? */ 145 }; 146 147 /* 148 * struct pccbb_intrhand_list holds interrupt handler and argument for 149 * child devices. 150 */ 151 152 struct pccbb_intrhand_list { 153 int (*pil_func)(void *); 154 void *pil_arg; 155 ipl_cookie_t pil_icookie; 156 LIST_ENTRY(pccbb_intrhand_list) pil_next; 157 }; 158 159 void pccbb_intr_route(struct pccbb_softc *sc); 160 161 162 #endif /* _DEV_PCI_PCCBBREG_H_ */ 163