1 /* $NetBSD: pccbb.c,v 1.178 2008/07/03 13:37:34 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by HAYAKAWA Koichi. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.178 2008/07/03 13:37:34 drochner Exp $"); 35 36 /* 37 #define CBB_DEBUG 38 #define SHOW_REGS 39 */ 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/errno.h> 45 #include <sys/ioctl.h> 46 #include <sys/reboot.h> /* for bootverbose */ 47 #include <sys/syslog.h> 48 #include <sys/device.h> 49 #include <sys/malloc.h> 50 #include <sys/proc.h> 51 52 #include <sys/intr.h> 53 #include <sys/bus.h> 54 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcidevs.h> 58 59 #include <dev/pci/pccbbreg.h> 60 61 #include <dev/cardbus/cardslotvar.h> 62 63 #include <dev/cardbus/cardbusvar.h> 64 65 #include <dev/pcmcia/pcmciareg.h> 66 #include <dev/pcmcia/pcmciavar.h> 67 68 #include <dev/ic/i82365reg.h> 69 #include <dev/pci/pccbbvar.h> 70 71 #ifndef __NetBSD_Version__ 72 struct cfdriver cbb_cd = { 73 NULL, "cbb", DV_DULL 74 }; 75 #endif 76 77 #ifdef CBB_DEBUG 78 #define DPRINTF(x) printf x 79 #define STATIC 80 #else 81 #define DPRINTF(x) 82 #define STATIC static 83 #endif 84 85 int pccbb_burstup = 1; 86 87 /* 88 * delay_ms() is wait in milliseconds. It should be used instead 89 * of delay() if you want to wait more than 1 ms. 90 */ 91 static inline void 92 delay_ms(int millis, void *param) 93 { 94 if (cold) 95 delay(millis * 1000); 96 else 97 tsleep(param, PWAIT, "pccbb", MAX(2, hz * millis / 1000)); 98 } 99 100 int pcicbbmatch(device_t, struct cfdata *, void *); 101 void pccbbattach(device_t, device_t, void *); 102 int pccbbdetach(device_t, int); 103 int pccbbintr(void *); 104 static void pci113x_insert(void *); 105 static int pccbbintr_function(struct pccbb_softc *); 106 107 static int pccbb_detect_card(struct pccbb_softc *); 108 109 static void pccbb_pcmcia_write(struct pccbb_softc *, int, u_int8_t); 110 static u_int8_t pccbb_pcmcia_read(struct pccbb_softc *, int); 111 #define Pcic_read(sc, reg) pccbb_pcmcia_read((sc), (reg)) 112 #define Pcic_write(sc, reg, val) pccbb_pcmcia_write((sc), (reg), (val)) 113 114 STATIC int cb_reset(struct pccbb_softc *); 115 STATIC int cb_detect_voltage(struct pccbb_softc *); 116 STATIC int cbbprint(void *, const char *); 117 118 static int cb_chipset(u_int32_t, int *); 119 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 120 struct pcmciabus_attach_args *); 121 122 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 123 STATIC int pccbb_power(struct pccbb_softc *sc, int); 124 STATIC int pccbb_power_ct(cardbus_chipset_tag_t, int); 125 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 126 #if !rbus 127 static int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 128 static int pccbb_io_close(cardbus_chipset_tag_t, int); 129 static int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t); 130 static int pccbb_mem_close(cardbus_chipset_tag_t, int); 131 #endif /* !rbus */ 132 static void *pccbb_intr_establish(struct pccbb_softc *, 133 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 134 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 135 136 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, 137 cardbus_intr_line_t irq, int level, int (*ih) (void *), void *sc); 138 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 139 140 static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 141 static void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); 142 static cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); 143 static void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, 144 cardbusreg_t); 145 static void pccbb_chipinit(struct pccbb_softc *); 146 static void pccbb_intrinit(struct pccbb_softc *); 147 148 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 149 struct pcmcia_mem_handle *); 150 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 151 struct pcmcia_mem_handle *); 152 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 153 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); 154 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 155 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 156 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 157 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 158 struct pcmcia_io_handle *); 159 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 160 bus_size_t, struct pcmcia_io_handle *, int *); 161 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 162 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 163 struct pcmcia_function *, int, int (*)(void *), void *); 164 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 165 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 166 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 167 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 168 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 169 170 static int pccbb_pcmcia_wait_ready(struct pccbb_softc *); 171 static void pccbb_pcmcia_delay(struct pccbb_softc *, int, const char *); 172 173 static void pccbb_pcmcia_do_io_map(struct pccbb_softc *, int); 174 static void pccbb_pcmcia_do_mem_map(struct pccbb_softc *, int); 175 176 /* bus-space allocation and deallocation functions */ 177 #if rbus 178 179 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 180 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 181 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 182 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 183 bus_space_handle_t, bus_size_t); 184 185 #endif /* rbus */ 186 187 #if rbus 188 189 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 190 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 191 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 192 bus_space_handle_t, bus_size_t); 193 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 194 bus_size_t, bus_space_handle_t, int); 195 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 196 bus_space_handle_t, bus_size_t); 197 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 198 bus_space_tag_t); 199 void pccbb_winlist_show(struct pccbb_win_chain *); 200 201 #endif /* rbus */ 202 203 /* for config_defer */ 204 static void pccbb_pci_callback(device_t); 205 206 static bool pccbb_suspend(device_t PMF_FN_PROTO); 207 static bool pccbb_resume(device_t PMF_FN_PROTO); 208 209 #if defined SHOW_REGS 210 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 211 bus_space_tag_t memt, bus_space_handle_t memh); 212 #endif 213 214 CFATTACH_DECL_NEW(cbb_pci, sizeof(struct pccbb_softc), 215 pcicbbmatch, pccbbattach, pccbbdetach, NULL); 216 217 static const struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 218 pccbb_pcmcia_mem_alloc, 219 pccbb_pcmcia_mem_free, 220 pccbb_pcmcia_mem_map, 221 pccbb_pcmcia_mem_unmap, 222 pccbb_pcmcia_io_alloc, 223 pccbb_pcmcia_io_free, 224 pccbb_pcmcia_io_map, 225 pccbb_pcmcia_io_unmap, 226 pccbb_pcmcia_intr_establish, 227 pccbb_pcmcia_intr_disestablish, 228 pccbb_pcmcia_socket_enable, 229 pccbb_pcmcia_socket_disable, 230 pccbb_pcmcia_socket_settype, 231 pccbb_pcmcia_card_detect 232 }; 233 234 #if rbus 235 static const struct cardbus_functions pccbb_funcs = { 236 pccbb_rbus_cb_space_alloc, 237 pccbb_rbus_cb_space_free, 238 pccbb_cb_intr_establish, 239 pccbb_cb_intr_disestablish, 240 pccbb_ctrl, 241 pccbb_power_ct, 242 pccbb_make_tag, 243 pccbb_free_tag, 244 pccbb_conf_read, 245 pccbb_conf_write, 246 }; 247 #else 248 static const struct cardbus_functions pccbb_funcs = { 249 pccbb_ctrl, 250 pccbb_power_ct, 251 pccbb_mem_open, 252 pccbb_mem_close, 253 pccbb_io_open, 254 pccbb_io_close, 255 pccbb_cb_intr_establish, 256 pccbb_cb_intr_disestablish, 257 pccbb_make_tag, 258 pccbb_conf_read, 259 pccbb_conf_write, 260 }; 261 #endif 262 263 int 264 pcicbbmatch(device_t parent, struct cfdata *match, void *aux) 265 { 266 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 267 268 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 269 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 270 PCI_INTERFACE(pa->pa_class) == 0) { 271 return 1; 272 } 273 274 return 0; 275 } 276 277 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 278 | ((prod) << PCI_PRODUCT_SHIFT)) 279 280 const struct yenta_chipinfo { 281 pcireg_t yc_id; /* vendor tag | product tag */ 282 int yc_chiptype; 283 int yc_flags; 284 } yc_chipsets[] = { 285 /* Texas Instruments chips */ 286 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 287 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 288 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 289 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 304 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 305 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 306 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 307 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 308 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 309 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 310 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 311 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 312 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 313 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 314 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 315 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 316 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 317 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 318 319 /* Ricoh chips */ 320 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 321 PCCBB_PCMCIA_MEM_32}, 322 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 323 PCCBB_PCMCIA_MEM_32}, 324 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 325 PCCBB_PCMCIA_MEM_32}, 326 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 327 PCCBB_PCMCIA_MEM_32}, 328 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 329 PCCBB_PCMCIA_MEM_32}, 330 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 331 PCCBB_PCMCIA_MEM_32}, 332 333 /* Toshiba products */ 334 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 335 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 336 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 337 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 338 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 339 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 340 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 341 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 342 343 /* Cirrus Logic products */ 344 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 345 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 346 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 347 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 348 349 /* O2 Micro products */ 350 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729), 351 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 352 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730), 353 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 354 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832), 355 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 356 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836), 357 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 358 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), 359 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 360 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6922), 361 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 362 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6933), 363 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 364 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6972), 365 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 366 367 /* sentinel, or Generic chip */ 368 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 369 }; 370 371 static int 372 cb_chipset(u_int32_t pci_id, int *flagp) 373 { 374 const struct yenta_chipinfo *yc; 375 376 /* Loop over except the last default entry. */ 377 for (yc = yc_chipsets; yc < yc_chipsets + 378 __arraycount(yc_chipsets) - 1; yc++) 379 if (pci_id == yc->yc_id) 380 break; 381 382 if (flagp != NULL) 383 *flagp = yc->yc_flags; 384 385 return (yc->yc_chiptype); 386 } 387 388 void 389 pccbbattach(device_t parent, device_t self, void *aux) 390 { 391 struct pccbb_softc *sc = device_private(self); 392 struct pci_attach_args *pa = aux; 393 pci_chipset_tag_t pc = pa->pa_pc; 394 pcireg_t busreg, reg, sock_base; 395 bus_addr_t sockbase; 396 char devinfo[256]; 397 int flags; 398 399 #ifdef __HAVE_PCCBB_ATTACH_HOOK 400 pccbb_attach_hook(parent, self, pa); 401 #endif 402 403 sc->sc_dev = self; 404 405 callout_init(&sc->sc_insert_ch, 0); 406 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 407 408 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 409 410 aprint_naive("\n"); 411 412 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 413 aprint_normal(": %s (rev. 0x%02x)", devinfo, 414 PCI_REVISION(pa->pa_class)); 415 DPRINTF((" (chipflags %x)", flags)); 416 aprint_normal("\n"); 417 418 TAILQ_INIT(&sc->sc_memwindow); 419 TAILQ_INIT(&sc->sc_iowindow); 420 421 #if rbus 422 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 423 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 424 425 #if 0 426 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 427 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 428 #endif 429 #endif /* rbus */ 430 431 sc->sc_flags &= ~CBB_MEMHMAPPED; 432 433 /* 434 * MAP socket registers and ExCA registers on memory-space 435 * When no valid address is set on socket base registers (on pci 436 * config space), get it not polite way. 437 */ 438 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 439 440 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 441 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 442 /* The address must be valid. */ 443 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 444 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, &sc->sc_base_size)) { 445 aprint_error_dev(self, 446 "can't map socket base address 0x%lx\n", 447 (unsigned long)sock_base); 448 /* 449 * I think it's funny: socket base registers must be 450 * mapped on memory space, but ... 451 */ 452 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 453 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 454 &sc->sc_base_size)) { 455 aprint_error_dev(self, 456 "can't map socket base address" 457 " 0x%lx: io mode\n", 458 (unsigned long)sockbase); 459 /* give up... allocate reg space via rbus. */ 460 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 461 } else 462 sc->sc_flags |= CBB_MEMHMAPPED; 463 } else { 464 DPRINTF(("%s: socket base address 0x%lx\n", 465 device_xname(self), 466 (unsigned long)sockbase)); 467 sc->sc_flags |= CBB_MEMHMAPPED; 468 } 469 } 470 471 sc->sc_mem_start = 0; /* XXX */ 472 sc->sc_mem_end = 0xffffffff; /* XXX */ 473 474 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); 475 476 /* pccbb_machdep.c end */ 477 478 #if defined CBB_DEBUG 479 { 480 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 481 aprint_debug_dev(self, "intrpin %s, intrtag %d\n", 482 intrname[pa->pa_intrpin], pa->pa_intrline); 483 } 484 #endif 485 486 /* setup softc */ 487 sc->sc_pc = pc; 488 sc->sc_iot = pa->pa_iot; 489 sc->sc_memt = pa->pa_memt; 490 sc->sc_dmat = pa->pa_dmat; 491 sc->sc_tag = pa->pa_tag; 492 493 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 494 495 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 496 497 /* Disable legacy register mapping. */ 498 switch (sc->sc_chipset) { 499 case CB_RX5C46X: /* fallthrough */ 500 #if 0 501 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 502 case CB_RX5C47X: 503 #endif 504 /* 505 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 506 * cannot be disabled by substituting 0 into PCI_LEGACY 507 * register. Ricoh CardBus bridges have special bits on Bridge 508 * control reg (addr 0x3e on PCI config space). 509 */ 510 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 511 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 512 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 513 break; 514 515 default: 516 /* XXX I don't know proper way to kill legacy I/O. */ 517 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 518 break; 519 } 520 521 if (!pmf_device_register(self, pccbb_suspend, pccbb_resume)) 522 aprint_error_dev(self, "couldn't establish power handler\n"); 523 524 config_defer(self, pccbb_pci_callback); 525 } 526 527 int 528 pccbbdetach(device_t self, int flags) 529 { 530 struct pccbb_softc *sc = device_private(self); 531 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 532 bus_space_tag_t bmt = sc->sc_base_memt; 533 bus_space_handle_t bmh = sc->sc_base_memh; 534 uint32_t sockmask; 535 int rc; 536 537 if ((rc = config_detach_children(self, flags)) != 0) 538 return rc; 539 540 if (!LIST_EMPTY(&sc->sc_pil)) { 541 panic("%s: interrupt handlers still registered", 542 device_xname(self)); 543 return EBUSY; 544 } 545 546 if (sc->sc_ih != NULL) { 547 pci_intr_disestablish(pc, sc->sc_ih); 548 sc->sc_ih = NULL; 549 } 550 551 /* CSC Interrupt: turn off card detect and power cycle interrupts */ 552 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 553 sockmask &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 554 CB_SOCKET_MASK_POWER); 555 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 556 /* reset interrupt */ 557 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 558 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 559 560 switch (sc->sc_flags & (CBB_MEMHMAPPED|CBB_SPECMAPPED)) { 561 case CBB_MEMHMAPPED: 562 bus_space_unmap(bmt, bmh, sc->sc_base_size); 563 break; 564 case CBB_MEMHMAPPED|CBB_SPECMAPPED: 565 #if rbus 566 { 567 pcireg_t sockbase; 568 569 sockbase = pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE); 570 rbus_space_free(sc->sc_rbus_memt, bmh, 0x1000, 571 NULL); 572 } 573 #else 574 bus_space_free(bmt, bmh, 0x1000); 575 #endif 576 } 577 sc->sc_flags &= ~(CBB_MEMHMAPPED|CBB_SPECMAPPED); 578 579 if (!TAILQ_EMPTY(&sc->sc_iowindow)) 580 aprint_error_dev(self, "i/o windows not empty"); 581 if (!TAILQ_EMPTY(&sc->sc_memwindow)) 582 aprint_error_dev(self, "memory windows not empty"); 583 584 callout_stop(&sc->sc_insert_ch); 585 callout_destroy(&sc->sc_insert_ch); 586 return 0; 587 } 588 589 /* 590 * static void pccbb_pci_callback(device_t self) 591 * 592 * The actual attach routine: get memory space for YENTA register 593 * space, setup YENTA register and route interrupt. 594 * 595 * This function should be deferred because this device may obtain 596 * memory space dynamically. This function must avoid obtaining 597 * memory area which has already kept for another device. 598 */ 599 static void 600 pccbb_pci_callback(device_t self) 601 { 602 struct pccbb_softc *sc = device_private(self); 603 pci_chipset_tag_t pc = sc->sc_pc; 604 bus_addr_t sockbase; 605 struct cbslot_attach_args cba; 606 struct pcmciabus_attach_args paa; 607 struct cardslot_attach_args caa; 608 device_t csc; 609 610 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 611 /* The socket registers aren't mapped correctly. */ 612 #if rbus 613 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 614 (sc->sc_chipset == CB_RX5C47X 615 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 616 0, &sockbase, &sc->sc_base_memh)) { 617 return; 618 } 619 sc->sc_base_memt = sc->sc_memt; 620 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 621 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 622 device_xname(self), (unsigned long)sockbase, 623 (unsigned long)pci_conf_read(pc, sc->sc_tag, 624 PCI_SOCKBASE))); 625 #else 626 sc->sc_base_memt = sc->sc_memt; 627 #if !defined CBB_PCI_BASE 628 #define CBB_PCI_BASE 0x20000000 629 #endif 630 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 631 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 632 /* cannot allocate memory space */ 633 return; 634 } 635 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 636 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 637 device_xname(self), (unsigned long)sock_base, 638 (unsigned long)pci_conf_read(pc, 639 sc->sc_tag, PCI_SOCKBASE))); 640 #endif 641 sc->sc_flags |= CBB_MEMHMAPPED; 642 } 643 644 /* clear data structure for child device interrupt handlers */ 645 LIST_INIT(&sc->sc_pil); 646 647 /* bus bridge initialization */ 648 pccbb_chipinit(sc); 649 650 sc->sc_pil_intr_enable = 1; 651 652 { 653 u_int32_t sockstat; 654 655 sockstat = bus_space_read_4(sc->sc_base_memt, 656 sc->sc_base_memh, CB_SOCKET_STAT); 657 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 658 sc->sc_flags |= CBB_CARDEXIST; 659 } 660 } 661 662 /* 663 * attach cardbus 664 */ 665 { 666 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 667 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 668 669 /* initialize cbslot_attach */ 670 cba.cba_iot = sc->sc_iot; 671 cba.cba_memt = sc->sc_memt; 672 cba.cba_dmat = sc->sc_dmat; 673 cba.cba_bus = (busreg >> 8) & 0x0ff; 674 cba.cba_cc = (void *)sc; 675 cba.cba_cf = &pccbb_funcs; 676 cba.cba_intrline = 0; /* XXX dummy */ 677 678 #if rbus 679 cba.cba_rbus_iot = sc->sc_rbus_iot; 680 cba.cba_rbus_memt = sc->sc_rbus_memt; 681 #endif 682 683 cba.cba_cacheline = PCI_CACHELINE(bhlc); 684 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 685 686 aprint_verbose_dev(self, 687 "cacheline 0x%x lattimer 0x%x\n", 688 cba.cba_cacheline, 689 cba.cba_max_lattimer); 690 aprint_verbose_dev(self, "bhlc 0x%x\n", bhlc); 691 #if defined SHOW_REGS 692 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 693 sc->sc_base_memh); 694 #endif 695 } 696 697 pccbb_pcmcia_attach_setup(sc, &paa); 698 caa.caa_cb_attach = NULL; 699 if (cba.cba_bus == 0) 700 aprint_error_dev(self, 701 "secondary bus number uninitialized; try PCI_BUS_FIXUP\n"); 702 else 703 caa.caa_cb_attach = &cba; 704 caa.caa_16_attach = &paa; 705 706 pccbb_intrinit(sc); 707 708 if (NULL != (csc = config_found_ia(self, "pcmciaslot", &caa, 709 cbbprint))) { 710 DPRINTF(("%s: found cardslot\n", __func__)); 711 sc->sc_csc = device_private(csc); 712 } 713 714 return; 715 } 716 717 718 719 720 721 /* 722 * static void pccbb_chipinit(struct pccbb_softc *sc) 723 * 724 * This function initialize YENTA chip registers listed below: 725 * 1) PCI command reg, 726 * 2) PCI and CardBus latency timer, 727 * 3) route PCI interrupt, 728 * 4) close all memory and io windows. 729 * 5) turn off bus power. 730 * 6) card detect and power cycle interrupts on. 731 * 7) clear interrupt 732 */ 733 static void 734 pccbb_chipinit(struct pccbb_softc *sc) 735 { 736 pci_chipset_tag_t pc = sc->sc_pc; 737 pcitag_t tag = sc->sc_tag; 738 bus_space_tag_t bmt = sc->sc_base_memt; 739 bus_space_handle_t bmh = sc->sc_base_memh; 740 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 741 sysctrl; 742 743 /* 744 * Set PCI command reg. 745 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 746 */ 747 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 748 /* I believe it is harmless. */ 749 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 750 PCI_COMMAND_MASTER_ENABLE); 751 752 /* All O2 Micro chips have broken parity-error reporting 753 * until proven otherwise. The OZ6933 PCI-CardBus Bridge 754 * is known to have the defect---see PR kern/38698. 755 */ 756 if (sc->sc_chipset != CB_O2MICRO) 757 csr |= PCI_COMMAND_PARITY_ENABLE; 758 759 csr |= PCI_COMMAND_SERR_ENABLE; 760 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 761 762 /* 763 * Set CardBus latency timer. 764 */ 765 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 766 if (PCI_CB_LATENCY(lscp) < 0x20) { 767 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 768 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 769 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 770 } 771 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 772 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 773 774 /* 775 * Set PCI latency timer. 776 */ 777 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 778 if (PCI_LATTIMER(bhlc) < 0x10) { 779 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 780 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 781 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 782 } 783 DPRINTF(("PCI latency timer 0x%x (%x)\n", 784 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 785 786 787 /* Route functional interrupts to PCI. */ 788 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 789 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 790 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 791 /* assert reset */ 792 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 793 /* Set master abort mode to 1, forward SERR# from secondary 794 * to primary, and detect parity errors on secondary. 795 */ 796 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 797 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 798 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 799 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 800 801 switch (sc->sc_chipset) { 802 case CB_TI113X: 803 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 804 /* This bit is shared, but may read as 0 on some chips, so set 805 it explicitly on both functions. */ 806 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 807 /* CSC intr enable */ 808 cbctl |= PCI113X_CBCTRL_PCI_CSC; 809 /* functional intr prohibit | prohibit ISA routing */ 810 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 811 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 812 break; 813 814 case CB_TI1420: 815 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 816 mrburst = pccbb_burstup 817 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 818 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 819 printf("%s: %swrite bursts enabled\n", 820 device_xname(sc->sc_dev), 821 pccbb_burstup ? "read/" : ""); 822 } else if (pccbb_burstup) { 823 printf("%s: enabling read/write bursts\n", 824 device_xname(sc->sc_dev)); 825 sysctrl |= PCI1420_SYSCTRL_MRBURST; 826 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 827 } else { 828 printf("%s: disabling read bursts, " 829 "enabling write bursts\n", 830 device_xname(sc->sc_dev)); 831 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 832 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 833 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 834 } 835 /*FALLTHROUGH*/ 836 case CB_TI12XX: 837 /* 838 * Some TI 12xx (and [14][45]xx) based pci cards 839 * sometimes have issues with the MFUNC register not 840 * being initialized due to a bad EEPROM on board. 841 * Laptops that this matters on have this register 842 * properly initialized. 843 * 844 * The TI125X parts have a different register. 845 */ 846 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 847 if (mfunc == 0) { 848 mfunc &= ~PCI12XX_MFUNC_PIN0; 849 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 850 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 851 PCI12XX_SYSCTRL_INTRTIE) == 0) { 852 mfunc &= ~PCI12XX_MFUNC_PIN1; 853 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 854 } 855 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 856 } 857 /* fallthrough */ 858 859 case CB_TI125X: 860 /* 861 * Disable zoom video. Some machines initialize this 862 * improperly and experience has shown that this helps 863 * prevent strange behavior. 864 */ 865 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 866 867 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 868 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 869 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 870 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 871 cbctl |= PCI12XX_CBCTRL_CSC; 872 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 873 break; 874 875 case CB_TOPIC95B: 876 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 877 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 878 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 879 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 880 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 881 device_xname(sc->sc_dev), slotctl)); 882 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 883 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 884 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 885 DPRINTF(("0x%x\n", slotctl)); 886 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 887 break; 888 889 case CB_TOPIC97: 890 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 891 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 892 device_xname(sc->sc_dev), slotctl)); 893 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 894 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 895 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 896 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 897 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 898 DPRINTF(("0x%x\n", slotctl)); 899 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 900 /* make sure to assert LV card support bits */ 901 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 902 0x800 + 0x3e, 903 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 904 0x800 + 0x3e) | 0x03); 905 break; 906 } 907 908 /* Close all memory and I/O windows. */ 909 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 910 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 911 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 912 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 913 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 914 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 915 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 916 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 917 918 /* reset 16-bit pcmcia bus */ 919 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 920 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 921 922 /* turn off power */ 923 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 924 } 925 926 static void 927 pccbb_intrinit(struct pccbb_softc *sc) 928 { 929 pcireg_t sockmask; 930 const char *intrstr = NULL; 931 pci_intr_handle_t ih; 932 pci_chipset_tag_t pc = sc->sc_pc; 933 bus_space_tag_t bmt = sc->sc_base_memt; 934 bus_space_handle_t bmh = sc->sc_base_memh; 935 936 /* Map and establish the interrupt. */ 937 if (pci_intr_map(&sc->sc_pa, &ih)) { 938 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 939 return; 940 } 941 intrstr = pci_intr_string(pc, ih); 942 943 /* 944 * XXX pccbbintr should be called under the priority lower 945 * than any other hard interupts. 946 */ 947 KASSERT(sc->sc_ih == NULL); 948 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 949 950 if (sc->sc_ih == NULL) { 951 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 952 if (intrstr != NULL) 953 aprint_error(" at %s\n", intrstr); 954 else 955 aprint_error("\n"); 956 return; 957 } 958 959 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 960 961 /* CSC Interrupt: Card detect and power cycle interrupts on */ 962 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 963 sockmask |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 964 CB_SOCKET_MASK_POWER; 965 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 966 /* reset interrupt */ 967 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 968 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 969 } 970 971 /* 972 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 973 * struct pcmciabus_attach_args *paa) 974 * 975 * This function attaches 16-bit PCcard bus. 976 */ 977 STATIC void 978 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 979 struct pcmciabus_attach_args *paa) 980 { 981 #if rbus 982 rbus_tag_t rb; 983 #endif 984 /* 985 * We need to do a few things here: 986 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 987 * setting the IRQ numbers to 0. 988 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 989 * routing of CSC interrupts (e.g. card removal) to PCI while in 990 * PCMCIA mode. We just leave this set all the time. 991 * 3) Enable card insertion/removal interrupts in case the chip also 992 * needs that while in PCMCIA mode. 993 * 4) Clear any pending CSC interrupt. 994 */ 995 Pcic_write(sc, PCIC_INTR, PCIC_INTR_ENABLE); 996 if (sc->sc_chipset == CB_TI113X) { 997 Pcic_write(sc, PCIC_CSC_INTR, 0); 998 } else { 999 Pcic_write(sc, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 1000 Pcic_read(sc, PCIC_CSC); 1001 } 1002 1003 /* initialize pcmcia bus attachment */ 1004 paa->paa_busname = "pcmcia"; 1005 paa->pct = &pccbb_pcmcia_funcs; 1006 paa->pch = sc; 1007 paa->iobase = 0; /* I don't use them */ 1008 paa->iosize = 0; 1009 #if rbus 1010 rb = sc->sc_rbus_iot; 1011 paa->iobase = rb->rb_start + rb->rb_offset; 1012 paa->iosize = rb->rb_end - rb->rb_start; 1013 #endif 1014 1015 return; 1016 } 1017 1018 /* 1019 * int pccbbintr(arg) 1020 * void *arg; 1021 * This routine handles the interrupt from Yenta PCI-CardBus bridge 1022 * itself. 1023 */ 1024 int 1025 pccbbintr(void *arg) 1026 { 1027 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1028 u_int32_t sockevent, sockstate; 1029 bus_space_tag_t memt = sc->sc_base_memt; 1030 bus_space_handle_t memh = sc->sc_base_memh; 1031 1032 if (!device_has_power(sc->sc_dev)) 1033 return 0; 1034 1035 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1036 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1037 Pcic_read(sc, PCIC_CSC); 1038 1039 if (sockevent != 0) { 1040 aprint_debug("%s: enter sockevent %" PRIx32 "\n", __func__, 1041 sockevent); 1042 } 1043 1044 /* Sometimes a change of CSTSCHG# accompanies the first 1045 * interrupt from an Atheros WLAN. That generates a 1046 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1047 * isn't interesting to pccbb(4), so we used to ignore the 1048 * interrupt. Now, let the child devices try to handle 1049 * the interrupt, instead. The Atheros NIC produces 1050 * interrupts more reliably, now: used to be that it would 1051 * only interrupt if the driver avoided powering down the 1052 * NIC's cardslot, and then the NIC would only work after 1053 * it was reset a second time. 1054 */ 1055 if (sockevent == 0 || 1056 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1057 /* This intr is not for me: it may be for my child devices. */ 1058 if (sc->sc_pil_intr_enable) { 1059 return pccbbintr_function(sc); 1060 } else { 1061 return 0; 1062 } 1063 } 1064 1065 if (sockevent & CB_SOCKET_EVENT_CD) { 1066 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1067 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1068 /* A card should be removed. */ 1069 if (sc->sc_flags & CBB_CARDEXIST) { 1070 DPRINTF(("%s: 0x%08x", 1071 device_xname(sc->sc_dev), sockevent)); 1072 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1073 sc->sc_flags &= ~CBB_CARDEXIST; 1074 if (sc->sc_csc->sc_status & 1075 CARDSLOT_STATUS_CARD_16) { 1076 cardslot_event_throw(sc->sc_csc, 1077 CARDSLOT_EVENT_REMOVAL_16); 1078 } else if (sc->sc_csc->sc_status & 1079 CARDSLOT_STATUS_CARD_CB) { 1080 /* Cardbus intr removed */ 1081 cardslot_event_throw(sc->sc_csc, 1082 CARDSLOT_EVENT_REMOVAL_CB); 1083 } 1084 } else if (sc->sc_flags & CBB_INSERTING) { 1085 sc->sc_flags &= ~CBB_INSERTING; 1086 callout_stop(&sc->sc_insert_ch); 1087 } 1088 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1089 /* 1090 * The pccbbintr may called from powerdown hook when 1091 * the system resumed, to detect the card 1092 * insertion/removal during suspension. 1093 */ 1094 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1095 if (sc->sc_flags & CBB_INSERTING) { 1096 callout_stop(&sc->sc_insert_ch); 1097 } 1098 callout_schedule(&sc->sc_insert_ch, hz / 5); 1099 sc->sc_flags |= CBB_INSERTING; 1100 } 1101 } 1102 1103 /* XXX sockevent == 9 does occur in the wild. handle it. */ 1104 if (sockevent & CB_SOCKET_EVENT_POWER) { 1105 DPRINTF(("Powercycling because of socket event\n")); 1106 /* XXX: Does not happen when attaching a 16-bit card */ 1107 sc->sc_pwrcycle++; 1108 wakeup(&sc->sc_pwrcycle); 1109 } 1110 1111 return (1); 1112 } 1113 1114 /* 1115 * static int pccbbintr_function(struct pccbb_softc *sc) 1116 * 1117 * This function calls each interrupt handler registered at the 1118 * bridge. The interrupt handlers are called in registered order. 1119 */ 1120 static int 1121 pccbbintr_function(struct pccbb_softc *sc) 1122 { 1123 int retval = 0, val; 1124 struct pccbb_intrhand_list *pil; 1125 int s; 1126 1127 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1128 s = splraiseipl(pil->pil_icookie); 1129 val = (*pil->pil_func)(pil->pil_arg); 1130 splx(s); 1131 1132 retval = retval == 1 ? 1 : 1133 retval == 0 ? val : val != 0 ? val : retval; 1134 } 1135 1136 return retval; 1137 } 1138 1139 static void 1140 pci113x_insert(void *arg) 1141 { 1142 struct pccbb_softc *sc = arg; 1143 u_int32_t sockevent, sockstate; 1144 1145 if (!(sc->sc_flags & CBB_INSERTING)) { 1146 /* We add a card only under inserting state. */ 1147 return; 1148 } 1149 sc->sc_flags &= ~CBB_INSERTING; 1150 1151 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1152 CB_SOCKET_EVENT); 1153 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1154 CB_SOCKET_STAT); 1155 1156 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1157 DPRINTF(("%s: 0x%08x", device_xname(sc->sc_dev), sockevent)); 1158 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1159 sc->sc_flags |= CBB_CARDEXIST; 1160 /* call pccard interrupt handler here */ 1161 if (sockstate & CB_SOCKET_STAT_16BIT) { 1162 /* 16-bit card found */ 1163 cardslot_event_throw(sc->sc_csc, 1164 CARDSLOT_EVENT_INSERTION_16); 1165 } else if (sockstate & CB_SOCKET_STAT_CB) { 1166 /* cardbus card found */ 1167 cardslot_event_throw(sc->sc_csc, 1168 CARDSLOT_EVENT_INSERTION_CB); 1169 } else { 1170 /* who are you? */ 1171 } 1172 } else { 1173 callout_schedule(&sc->sc_insert_ch, hz / 10); 1174 } 1175 } 1176 1177 #define PCCBB_PCMCIA_OFFSET 0x800 1178 static u_int8_t 1179 pccbb_pcmcia_read(struct pccbb_softc *sc, int reg) 1180 { 1181 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1182 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1183 1184 return bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 1185 PCCBB_PCMCIA_OFFSET + reg); 1186 } 1187 1188 static void 1189 pccbb_pcmcia_write(struct pccbb_softc *sc, int reg, u_int8_t val) 1190 { 1191 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 1192 PCCBB_PCMCIA_OFFSET + reg, val); 1193 1194 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1195 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1196 } 1197 1198 /* 1199 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1200 */ 1201 STATIC int 1202 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1203 { 1204 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1205 1206 switch (command) { 1207 case CARDBUS_CD: 1208 if (2 == pccbb_detect_card(sc)) { 1209 int retval = 0; 1210 int status = cb_detect_voltage(sc); 1211 if (PCCARD_VCC_5V & status) { 1212 retval |= CARDBUS_5V_CARD; 1213 } 1214 if (PCCARD_VCC_3V & status) { 1215 retval |= CARDBUS_3V_CARD; 1216 } 1217 if (PCCARD_VCC_XV & status) { 1218 retval |= CARDBUS_XV_CARD; 1219 } 1220 if (PCCARD_VCC_YV & status) { 1221 retval |= CARDBUS_YV_CARD; 1222 } 1223 return retval; 1224 } else { 1225 return 0; 1226 } 1227 case CARDBUS_RESET: 1228 return cb_reset(sc); 1229 case CARDBUS_IO_ENABLE: /* fallthrough */ 1230 case CARDBUS_IO_DISABLE: /* fallthrough */ 1231 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1232 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1233 case CARDBUS_BM_ENABLE: /* fallthrough */ 1234 case CARDBUS_BM_DISABLE: /* fallthrough */ 1235 /* XXX: I think we don't need to call this function below. */ 1236 return pccbb_cardenable(sc, command); 1237 } 1238 1239 return 0; 1240 } 1241 1242 STATIC int 1243 pccbb_power_ct(cardbus_chipset_tag_t ct, int command) 1244 { 1245 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1246 1247 return pccbb_power(sc, command); 1248 } 1249 1250 /* 1251 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1252 * This function returns true when it succeeds and returns false when 1253 * it fails. 1254 */ 1255 STATIC int 1256 pccbb_power(struct pccbb_softc *sc, int command) 1257 { 1258 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1259 bus_space_tag_t memt = sc->sc_base_memt; 1260 bus_space_handle_t memh = sc->sc_base_memh; 1261 int on = 0, pwrcycle, s, times; 1262 struct timeval before, after, diff; 1263 1264 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1265 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1266 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1267 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1268 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1269 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1270 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1271 "UNKNOWN", 1272 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1273 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1274 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1275 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1276 "UNKNOWN", command)); 1277 1278 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1279 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1280 1281 switch (command & CARDBUS_VCCMASK) { 1282 case CARDBUS_VCC_UC: 1283 break; 1284 case CARDBUS_VCC_5V: 1285 on++; 1286 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1287 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1288 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1289 } else { 1290 aprint_error_dev(sc->sc_dev, 1291 "BAD voltage request: no 5 V card\n"); 1292 return 0; 1293 } 1294 break; 1295 case CARDBUS_VCC_3V: 1296 on++; 1297 if (CB_SOCKET_STAT_3VCARD & status) { 1298 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1299 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1300 } else { 1301 aprint_error_dev(sc->sc_dev, 1302 "BAD voltage request: no 3.3 V card\n"); 1303 return 0; 1304 } 1305 break; 1306 case CARDBUS_VCC_0V: 1307 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1308 break; 1309 default: 1310 return 0; /* power NEVER changed */ 1311 } 1312 1313 switch (command & CARDBUS_VPPMASK) { 1314 case CARDBUS_VPP_UC: 1315 break; 1316 case CARDBUS_VPP_0V: 1317 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1318 break; 1319 case CARDBUS_VPP_VCC: 1320 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1321 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1322 break; 1323 case CARDBUS_VPP_12V: 1324 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1325 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1326 break; 1327 } 1328 1329 pwrcycle = sc->sc_pwrcycle; 1330 aprint_debug_dev(sc->sc_dev, "osock_ctrl %#" PRIx32 1331 " sock_ctrl %#" PRIx32 "\n", osock_ctrl, sock_ctrl); 1332 1333 microtime(&before); 1334 s = splbio(); 1335 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1336 1337 /* 1338 * Wait as long as 200ms for a power-cycle interrupt. If 1339 * interrupts are enabled, but the socket has already 1340 * changed to the desired status, keep waiting for the 1341 * interrupt. "Consuming" the interrupt in this way keeps 1342 * the interrupt from prematurely waking some subsequent 1343 * pccbb_power call. 1344 * 1345 * XXX Not every bridge interrupts on the ->OFF transition. 1346 * XXX That's ok, we will time-out after 200ms. 1347 * 1348 * XXX The power cycle event will never happen when attaching 1349 * XXX a 16-bit card. That's ok, we will time-out after 1350 * XXX 200ms. 1351 */ 1352 for (times = 5; --times >= 0; ) { 1353 if (cold) 1354 DELAY(40 * 1000); 1355 else { 1356 (void)tsleep(&sc->sc_pwrcycle, PWAIT, "pccpwr", 1357 hz / 25); 1358 if (pwrcycle == sc->sc_pwrcycle) 1359 continue; 1360 } 1361 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1362 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1363 break; 1364 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1365 break; 1366 } 1367 splx(s); 1368 microtime(&after); 1369 timersub(&after, &before, &diff); 1370 aprint_debug_dev(sc->sc_dev, "wait took%s %ld.%06lds\n", 1371 (on && times < 0) ? " too long" : "", diff.tv_sec, diff.tv_usec); 1372 1373 /* 1374 * Ok, wait a bit longer for things to settle. 1375 */ 1376 if (on && sc->sc_chipset == CB_TOPIC95B) 1377 delay_ms(100, sc); 1378 1379 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1380 1381 if (on && sc->sc_chipset != CB_TOPIC95B) { 1382 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1383 aprint_error_dev(sc->sc_dev, "power on failed?\n"); 1384 } 1385 1386 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1387 aprint_error_dev(sc->sc_dev, 1388 "bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1389 sock_ctrl, status); 1390 aprint_error_dev(sc->sc_dev, "disabling socket\n"); 1391 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1392 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1393 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1394 status &= ~CB_SOCKET_STAT_BADVCC; 1395 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1396 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1397 CB_SOCKET_STAT)); 1398 return 0; 1399 } 1400 1401 if (sc->sc_chipset == CB_TOPIC97) { 1402 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1403 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1404 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1405 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1406 else 1407 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1408 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1409 } 1410 1411 return 1; /* power changed correctly */ 1412 } 1413 1414 /* 1415 * static int pccbb_detect_card(struct pccbb_softc *sc) 1416 * return value: 0 if no card exists. 1417 * 1 if 16-bit card exists. 1418 * 2 if cardbus card exists. 1419 */ 1420 static int 1421 pccbb_detect_card(struct pccbb_softc *sc) 1422 { 1423 bus_space_handle_t base_memh = sc->sc_base_memh; 1424 bus_space_tag_t base_memt = sc->sc_base_memt; 1425 u_int32_t sockstat = 1426 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1427 int retval = 0; 1428 1429 /* CD1 and CD2 asserted */ 1430 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1431 /* card must be present */ 1432 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1433 /* NOTACARD DEASSERTED */ 1434 if (CB_SOCKET_STAT_CB & sockstat) { 1435 /* CardBus mode */ 1436 retval = 2; 1437 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1438 /* 16-bit mode */ 1439 retval = 1; 1440 } 1441 } 1442 } 1443 return retval; 1444 } 1445 1446 /* 1447 * STATIC int cb_reset(struct pccbb_softc *sc) 1448 * This function resets CardBus card. 1449 */ 1450 STATIC int 1451 cb_reset(struct pccbb_softc *sc) 1452 { 1453 /* 1454 * Reset Assert at least 20 ms 1455 * Some machines request longer duration. 1456 */ 1457 int reset_duration = 1458 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1459 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1460 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 1461 1462 /* Reset bit Assert (bit 6 at 0x3E) */ 1463 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 1464 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1465 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1466 delay_ms(reset_duration, sc); 1467 1468 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1469 /* Reset bit Deassert (bit 6 at 0x3E) */ 1470 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT); 1471 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1472 bcr); 1473 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1474 delay_ms(reset_duration, sc); 1475 aprint_debug("%s: end of delay\n", __func__); 1476 } 1477 /* No card found on the slot. Keep Reset. */ 1478 return 1; 1479 } 1480 1481 /* 1482 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1483 * This function detect card Voltage. 1484 */ 1485 STATIC int 1486 cb_detect_voltage(struct pccbb_softc *sc) 1487 { 1488 u_int32_t psr; /* socket present-state reg */ 1489 bus_space_tag_t iot = sc->sc_base_memt; 1490 bus_space_handle_t ioh = sc->sc_base_memh; 1491 int vol = PCCARD_VCC_UKN; /* set 0 */ 1492 1493 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1494 1495 if (0x400u & psr) { 1496 vol |= PCCARD_VCC_5V; 1497 } 1498 if (0x800u & psr) { 1499 vol |= PCCARD_VCC_3V; 1500 } 1501 1502 return vol; 1503 } 1504 1505 STATIC int 1506 cbbprint(void *aux, const char *pcic) 1507 { 1508 #if 0 1509 struct cbslot_attach_args *cba = aux; 1510 1511 if (cba->cba_slot >= 0) { 1512 aprint_normal(" slot %d", cba->cba_slot); 1513 } 1514 #endif 1515 return UNCONF; 1516 } 1517 1518 /* 1519 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1520 * This function enables and disables the card 1521 */ 1522 STATIC int 1523 pccbb_cardenable(struct pccbb_softc *sc, int function) 1524 { 1525 u_int32_t command = 1526 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1527 1528 DPRINTF(("pccbb_cardenable:")); 1529 switch (function) { 1530 case CARDBUS_IO_ENABLE: 1531 command |= PCI_COMMAND_IO_ENABLE; 1532 break; 1533 case CARDBUS_IO_DISABLE: 1534 command &= ~PCI_COMMAND_IO_ENABLE; 1535 break; 1536 case CARDBUS_MEM_ENABLE: 1537 command |= PCI_COMMAND_MEM_ENABLE; 1538 break; 1539 case CARDBUS_MEM_DISABLE: 1540 command &= ~PCI_COMMAND_MEM_ENABLE; 1541 break; 1542 case CARDBUS_BM_ENABLE: 1543 command |= PCI_COMMAND_MASTER_ENABLE; 1544 break; 1545 case CARDBUS_BM_DISABLE: 1546 command &= ~PCI_COMMAND_MASTER_ENABLE; 1547 break; 1548 default: 1549 return 0; 1550 } 1551 1552 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1553 DPRINTF((" command reg 0x%x\n", command)); 1554 return 1; 1555 } 1556 1557 #if !rbus 1558 static int 1559 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1560 { 1561 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1562 int basereg; 1563 int limitreg; 1564 1565 if ((win < 0) || (win > 2)) { 1566 #if defined DIAGNOSTIC 1567 printf("cardbus_io_open: window out of range %d\n", win); 1568 #endif 1569 return 0; 1570 } 1571 1572 basereg = win * 8 + PCI_CB_IOBASE0; 1573 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1574 1575 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1576 start, basereg, end, limitreg)); 1577 1578 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1579 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1580 return 1; 1581 } 1582 1583 /* 1584 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1585 */ 1586 static int 1587 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1588 { 1589 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1590 int basereg; 1591 int limitreg; 1592 1593 if ((win < 0) || (win > 2)) { 1594 #if defined DIAGNOSTIC 1595 printf("cardbus_io_close: window out of range %d\n", win); 1596 #endif 1597 return 0; 1598 } 1599 1600 basereg = win * 8 + PCI_CB_IOBASE0; 1601 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1602 1603 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1604 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1605 return 1; 1606 } 1607 1608 static int 1609 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1610 { 1611 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1612 int basereg; 1613 int limitreg; 1614 1615 if ((win < 0) || (win > 2)) { 1616 #if defined DIAGNOSTIC 1617 printf("cardbus_mem_open: window out of range %d\n", win); 1618 #endif 1619 return 0; 1620 } 1621 1622 basereg = win * 8 + PCI_CB_MEMBASE0; 1623 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1624 1625 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1626 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1627 return 1; 1628 } 1629 1630 static int 1631 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1632 { 1633 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1634 int basereg; 1635 int limitreg; 1636 1637 if ((win < 0) || (win > 2)) { 1638 #if defined DIAGNOSTIC 1639 printf("cardbus_mem_close: window out of range %d\n", win); 1640 #endif 1641 return 0; 1642 } 1643 1644 basereg = win * 8 + PCI_CB_MEMBASE0; 1645 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1646 1647 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1648 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1649 return 1; 1650 } 1651 #endif 1652 1653 /* 1654 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1655 * int irq, 1656 * int level, 1657 * int (* func)(void *), 1658 * void *arg) 1659 * 1660 * This function registers an interrupt handler at the bridge, in 1661 * order not to call the interrupt handlers of child devices when 1662 * a card-deletion interrupt occurs. 1663 * 1664 * The arguments irq and level are not used. 1665 */ 1666 static void * 1667 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, cardbus_intr_line_t irq, 1668 int level, int (*func)(void *), void *arg) 1669 { 1670 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1671 1672 return pccbb_intr_establish(sc, irq, level, func, arg); 1673 } 1674 1675 1676 /* 1677 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1678 * void *ih) 1679 * 1680 * This function removes an interrupt handler pointed by ih. 1681 */ 1682 static void 1683 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1684 { 1685 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1686 1687 pccbb_intr_disestablish(sc, ih); 1688 } 1689 1690 1691 void 1692 pccbb_intr_route(struct pccbb_softc *sc) 1693 { 1694 pcireg_t bcr, cbctrl; 1695 1696 /* initialize bridge intr routing */ 1697 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1698 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1699 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1700 1701 switch (sc->sc_chipset) { 1702 case CB_TI113X: 1703 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1704 /* functional intr enabled */ 1705 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1706 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1707 break; 1708 default: 1709 break; 1710 } 1711 } 1712 1713 /* 1714 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1715 * int irq, 1716 * int level, 1717 * int (* func)(void *), 1718 * void *arg) 1719 * 1720 * This function registers an interrupt handler at the bridge, in 1721 * order not to call the interrupt handlers of child devices when 1722 * a card-deletion interrupt occurs. 1723 * 1724 * The arguments irq is not used because pccbb selects intr vector. 1725 */ 1726 static void * 1727 pccbb_intr_establish(struct pccbb_softc *sc, cardbus_intr_line_t irq, 1728 int level, int (*func)(void *), void *arg) 1729 { 1730 struct pccbb_intrhand_list *pil, *newpil; 1731 1732 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1733 1734 if (LIST_EMPTY(&sc->sc_pil)) { 1735 pccbb_intr_route(sc); 1736 } 1737 1738 /* 1739 * Allocate a room for interrupt handler structure. 1740 */ 1741 if (NULL == (newpil = 1742 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1743 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1744 return NULL; 1745 } 1746 1747 newpil->pil_func = func; 1748 newpil->pil_arg = arg; 1749 newpil->pil_icookie = makeiplcookie(level); 1750 1751 if (LIST_EMPTY(&sc->sc_pil)) { 1752 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1753 } else { 1754 for (pil = LIST_FIRST(&sc->sc_pil); 1755 LIST_NEXT(pil, pil_next) != NULL; 1756 pil = LIST_NEXT(pil, pil_next)); 1757 LIST_INSERT_AFTER(pil, newpil, pil_next); 1758 } 1759 1760 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1761 LIST_FIRST(&sc->sc_pil))); 1762 1763 return newpil; 1764 } 1765 1766 /* 1767 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1768 * void *ih) 1769 * 1770 * This function removes an interrupt handler pointed by ih. ih 1771 * should be the value returned by cardbus_intr_establish() or 1772 * NULL. 1773 * 1774 * When ih is NULL, this function will do nothing. 1775 */ 1776 static void 1777 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1778 { 1779 struct pccbb_intrhand_list *pil; 1780 pcireg_t reg; 1781 1782 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1783 LIST_FIRST(&sc->sc_pil))); 1784 1785 if (ih == NULL) { 1786 /* intr handler is not set */ 1787 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1788 return; 1789 } 1790 1791 #ifdef DIAGNOSTIC 1792 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1793 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1794 if (pil == ih) { 1795 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1796 break; 1797 } 1798 } 1799 if (pil == NULL) { 1800 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1801 device_xname(sc->sc_dev), ih); 1802 } 1803 #endif 1804 1805 pil = (struct pccbb_intrhand_list *)ih; 1806 LIST_REMOVE(pil, pil_next); 1807 free(pil, M_DEVBUF); 1808 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1809 1810 if (LIST_EMPTY(&sc->sc_pil)) { 1811 /* No interrupt handlers */ 1812 1813 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1814 1815 /* stop routing PCI intr */ 1816 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1817 reg |= CB_BCR_INTR_IREQ_ENABLE; 1818 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1819 1820 switch (sc->sc_chipset) { 1821 case CB_TI113X: 1822 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1823 /* functional intr disabled */ 1824 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1825 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1826 break; 1827 default: 1828 break; 1829 } 1830 } 1831 } 1832 1833 #if defined SHOW_REGS 1834 static void 1835 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1836 bus_space_handle_t memh) 1837 { 1838 int i; 1839 printf("PCI config regs:"); 1840 for (i = 0; i < 0x50; i += 4) { 1841 if (i % 16 == 0) 1842 printf("\n 0x%02x:", i); 1843 printf(" %08x", pci_conf_read(pc, tag, i)); 1844 } 1845 for (i = 0x80; i < 0xb0; i += 4) { 1846 if (i % 16 == 0) 1847 printf("\n 0x%02x:", i); 1848 printf(" %08x", pci_conf_read(pc, tag, i)); 1849 } 1850 1851 if (memh == 0) { 1852 printf("\n"); 1853 return; 1854 } 1855 1856 printf("\nsocket regs:"); 1857 for (i = 0; i <= 0x10; i += 0x04) 1858 printf(" %08x", bus_space_read_4(memt, memh, i)); 1859 printf("\nExCA regs:"); 1860 for (i = 0; i < 0x08; ++i) 1861 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1862 printf("\n"); 1863 return; 1864 } 1865 #endif 1866 1867 /* 1868 * static cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1869 * int busno, int function) 1870 * This is the function to make a tag to access config space of 1871 * a CardBus Card. It works same as pci_conf_read. 1872 */ 1873 static cardbustag_t 1874 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1875 { 1876 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1877 1878 return pci_make_tag(sc->sc_pc, busno, 0, function); 1879 } 1880 1881 static void 1882 pccbb_free_tag(cardbus_chipset_tag_t cc, cardbustag_t tag) 1883 { 1884 } 1885 1886 /* 1887 * pccbb_conf_read 1888 * 1889 * This is the function to read the config space of a CardBus card. 1890 * It works the same as pci_conf_read(9). 1891 */ 1892 static cardbusreg_t 1893 pccbb_conf_read(cardbus_chipset_tag_t cc, cardbustag_t tag, int offset) 1894 { 1895 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1896 pcitag_t brtag = sc->sc_tag; 1897 cardbusreg_t reg; 1898 1899 /* 1900 * clear cardbus master abort status; it is OK to write without 1901 * reading before because all bits are r/o or w1tc 1902 */ 1903 pci_conf_write(sc->sc_pc, brtag, PCI_CBB_SECSTATUS, 1904 CBB_SECSTATUS_CBMABORT); 1905 reg = pci_conf_read(sc->sc_pc, tag, offset); 1906 /* check cardbus master abort status */ 1907 if (pci_conf_read(sc->sc_pc, brtag, PCI_CBB_SECSTATUS) 1908 & CBB_SECSTATUS_CBMABORT) 1909 return (0xffffffff); 1910 return reg; 1911 } 1912 1913 /* 1914 * pccbb_conf_write 1915 * 1916 * This is the function to write the config space of a CardBus 1917 * card. It works the same as pci_conf_write(9). 1918 */ 1919 static void 1920 pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag, int reg, 1921 cardbusreg_t val) 1922 { 1923 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1924 1925 pci_conf_write(sc->sc_pc, tag, reg, val); 1926 } 1927 1928 #if 0 1929 STATIC int 1930 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1931 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1932 int speed, int flags, 1933 bus_space_handle_t * iohp) 1934 #endif 1935 /* 1936 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1937 * bus_addr_t start, bus_size_t size, 1938 * bus_size_t align, 1939 * struct pcmcia_io_handle *pcihp 1940 * 1941 * This function only allocates I/O region for pccard. This function 1942 * never maps the allocated region to pccard I/O area. 1943 * 1944 * XXX: The interface of this function is not very good, I believe. 1945 */ 1946 STATIC int 1947 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1948 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1949 { 1950 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 1951 bus_addr_t ioaddr; 1952 int flags = 0; 1953 bus_space_tag_t iot; 1954 bus_space_handle_t ioh; 1955 bus_addr_t mask; 1956 #if rbus 1957 rbus_tag_t rb; 1958 #endif 1959 if (align == 0) { 1960 align = size; /* XXX: funny??? */ 1961 } 1962 1963 if (start != 0) { 1964 /* XXX: assume all card decode lower 10 bits by its hardware */ 1965 mask = 0x3ff; 1966 /* enforce to use only masked address */ 1967 start &= mask; 1968 } else { 1969 /* 1970 * calculate mask: 1971 * 1. get the most significant bit of size (call it msb). 1972 * 2. compare msb with the value of size. 1973 * 3. if size is larger, shift msb left once. 1974 * 4. obtain mask value to decrement msb. 1975 */ 1976 bus_size_t size_tmp = size; 1977 int shifts = 0; 1978 1979 mask = 1; 1980 while (size_tmp) { 1981 ++shifts; 1982 size_tmp >>= 1; 1983 } 1984 mask = (1 << shifts); 1985 if (mask < size) { 1986 mask <<= 1; 1987 } 1988 --mask; 1989 } 1990 1991 /* 1992 * Allocate some arbitrary I/O space. 1993 */ 1994 1995 iot = sc->sc_iot; 1996 1997 #if rbus 1998 rb = sc->sc_rbus_iot; 1999 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 2000 return 1; 2001 } 2002 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2003 (u_long) ioaddr, (u_long) size)); 2004 #else 2005 if (start) { 2006 ioaddr = start; 2007 if (bus_space_map(iot, start, size, 0, &ioh)) { 2008 return 1; 2009 } 2010 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 2011 (u_long) ioaddr, (u_long) size)); 2012 } else { 2013 flags |= PCMCIA_IO_ALLOCATED; 2014 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 2015 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 2016 size, align, 0, 0, &ioaddr, &ioh)) { 2017 /* No room be able to be get. */ 2018 return 1; 2019 } 2020 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2021 (u_long) ioaddr, (u_long) size)); 2022 } 2023 #endif 2024 2025 pcihp->iot = iot; 2026 pcihp->ioh = ioh; 2027 pcihp->addr = ioaddr; 2028 pcihp->size = size; 2029 pcihp->flags = flags; 2030 2031 return 0; 2032 } 2033 2034 /* 2035 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2036 * struct pcmcia_io_handle *pcihp) 2037 * 2038 * This function only frees I/O region for pccard. 2039 * 2040 * XXX: The interface of this function is not very good, I believe. 2041 */ 2042 void 2043 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2044 struct pcmcia_io_handle *pcihp) 2045 { 2046 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2047 #if !rbus 2048 bus_space_tag_t iot = pcihp->iot; 2049 #endif 2050 bus_space_handle_t ioh = pcihp->ioh; 2051 bus_size_t size = pcihp->size; 2052 2053 #if rbus 2054 rbus_tag_t rb = sc->sc_rbus_iot; 2055 2056 rbus_space_free(rb, ioh, size, NULL); 2057 #else 2058 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2059 bus_space_free(iot, ioh, size); 2060 else 2061 bus_space_unmap(iot, ioh, size); 2062 #endif 2063 } 2064 2065 /* 2066 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2067 * bus_addr_t offset, bus_size_t size, 2068 * struct pcmcia_io_handle *pcihp, 2069 * int *windowp) 2070 * 2071 * This function maps the allocated I/O region to pccard. This function 2072 * never allocates any I/O region for pccard I/O area. I don't 2073 * understand why the original authors of pcmciabus separated alloc and 2074 * map. I believe the two must be unite. 2075 * 2076 * XXX: no wait timing control? 2077 */ 2078 int 2079 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2080 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2081 { 2082 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2083 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2084 bus_addr_t ioaddr = pcihp->addr + offset; 2085 int i, win; 2086 #if defined CBB_DEBUG 2087 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2088 #endif 2089 2090 /* Sanity check I/O handle. */ 2091 2092 if (sc->sc_iot != pcihp->iot) { 2093 panic("pccbb_pcmcia_io_map iot is bogus"); 2094 } 2095 2096 /* XXX Sanity check offset/size. */ 2097 2098 win = -1; 2099 for (i = 0; i < PCIC_IO_WINS; i++) { 2100 if ((ph->ioalloc & (1 << i)) == 0) { 2101 win = i; 2102 ph->ioalloc |= (1 << i); 2103 break; 2104 } 2105 } 2106 2107 if (win == -1) { 2108 return 1; 2109 } 2110 2111 *windowp = win; 2112 2113 /* XXX this is pretty gross */ 2114 2115 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2116 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2117 2118 /* XXX wtf is this doing here? */ 2119 2120 #if 0 2121 printf(" port 0x%lx", (u_long) ioaddr); 2122 if (size > 1) { 2123 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2124 } 2125 #endif 2126 2127 ph->io[win].addr = ioaddr; 2128 ph->io[win].size = size; 2129 ph->io[win].width = width; 2130 2131 /* actual dirty register-value changing in the function below. */ 2132 pccbb_pcmcia_do_io_map(sc, win); 2133 2134 return 0; 2135 } 2136 2137 /* 2138 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2139 * 2140 * This function changes register-value to map I/O region for pccard. 2141 */ 2142 static void 2143 pccbb_pcmcia_do_io_map(struct pccbb_softc *sc, int win) 2144 { 2145 static u_int8_t pcic_iowidth[3] = { 2146 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2147 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2148 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2149 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2150 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2151 }; 2152 2153 #define PCIC_SIA_START_LOW 0 2154 #define PCIC_SIA_START_HIGH 1 2155 #define PCIC_SIA_STOP_LOW 2 2156 #define PCIC_SIA_STOP_HIGH 3 2157 2158 int regbase_win = 0x8 + win * 0x04; 2159 u_int8_t ioctl, enable; 2160 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2161 2162 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2163 "width %d\n", win, (unsigned long)ph->io[win].addr, 2164 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2165 2166 Pcic_write(sc, regbase_win + PCIC_SIA_START_LOW, 2167 ph->io[win].addr & 0xff); 2168 Pcic_write(sc, regbase_win + PCIC_SIA_START_HIGH, 2169 (ph->io[win].addr >> 8) & 0xff); 2170 2171 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_LOW, 2172 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2173 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_HIGH, 2174 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2175 2176 ioctl = Pcic_read(sc, PCIC_IOCTL); 2177 enable = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2178 switch (win) { 2179 case 0: 2180 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2181 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2182 PCIC_IOCTL_IO0_DATASIZE_MASK); 2183 ioctl |= pcic_iowidth[ph->io[win].width]; 2184 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2185 break; 2186 case 1: 2187 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2188 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2189 PCIC_IOCTL_IO1_DATASIZE_MASK); 2190 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2191 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2192 break; 2193 } 2194 Pcic_write(sc, PCIC_IOCTL, ioctl); 2195 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, enable); 2196 #if defined(CBB_DEBUG) 2197 { 2198 u_int8_t start_low = 2199 Pcic_read(sc, regbase_win + PCIC_SIA_START_LOW); 2200 u_int8_t start_high = 2201 Pcic_read(sc, regbase_win + PCIC_SIA_START_HIGH); 2202 u_int8_t stop_low = 2203 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_LOW); 2204 u_int8_t stop_high = 2205 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_HIGH); 2206 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2207 "stop %02x %02x, ioctl %02x enable %02x\n", 2208 start_low, start_high, stop_low, stop_high, ioctl, enable); 2209 } 2210 #endif 2211 } 2212 2213 /* 2214 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2215 * 2216 * This function unmaps I/O region. No return value. 2217 */ 2218 STATIC void 2219 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2220 { 2221 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2222 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2223 int reg; 2224 2225 if (win >= PCIC_IO_WINS || win < 0) { 2226 panic("pccbb_pcmcia_io_unmap: window out of range"); 2227 } 2228 2229 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2230 switch (win) { 2231 case 0: 2232 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2233 break; 2234 case 1: 2235 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2236 break; 2237 } 2238 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2239 2240 ph->ioalloc &= ~(1 << win); 2241 } 2242 2243 static int 2244 pccbb_pcmcia_wait_ready(struct pccbb_softc *sc) 2245 { 2246 u_int8_t stat; 2247 int i; 2248 2249 /* wait an initial 10ms for quick cards */ 2250 stat = Pcic_read(sc, PCIC_IF_STATUS); 2251 if (stat & PCIC_IF_STATUS_READY) 2252 return (0); 2253 pccbb_pcmcia_delay(sc, 10, "pccwr0"); 2254 for (i = 0; i < 50; i++) { 2255 stat = Pcic_read(sc, PCIC_IF_STATUS); 2256 if (stat & PCIC_IF_STATUS_READY) 2257 return (0); 2258 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2259 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2260 return (ENXIO); 2261 /* wait .1s (100ms) each iteration now */ 2262 pccbb_pcmcia_delay(sc, 100, "pccwr1"); 2263 } 2264 2265 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2266 return (EWOULDBLOCK); 2267 } 2268 2269 /* 2270 * Perform long (msec order) delay. timo is in milliseconds. 2271 */ 2272 static void 2273 pccbb_pcmcia_delay(struct pccbb_softc *sc, int timo, const char *wmesg) 2274 { 2275 #ifdef DIAGNOSTIC 2276 if (timo <= 0) 2277 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2278 if (!curlwp) 2279 panic("pccbb_pcmcia_delay: called in interrupt context"); 2280 #endif 2281 DPRINTF(("pccbb_pcmcia_delay: \"%s\", sleep %d ms\n", wmesg, timo)); 2282 tsleep(pccbb_pcmcia_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 2283 } 2284 2285 /* 2286 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2287 * 2288 * This function enables the card. All information is stored in 2289 * the first argument, pcmcia_chipset_handle_t. 2290 */ 2291 STATIC void 2292 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2293 { 2294 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2295 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2296 pcireg_t spsr; 2297 int voltage; 2298 int win; 2299 u_int8_t power, intr; 2300 #ifdef DIAGNOSTIC 2301 int reg; 2302 #endif 2303 2304 /* this bit is mostly stolen from pcic_attach_card */ 2305 2306 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2307 2308 /* get card Vcc info */ 2309 spsr = 2310 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2311 CB_SOCKET_STAT); 2312 if (spsr & CB_SOCKET_STAT_5VCARD) { 2313 DPRINTF(("5V card\n")); 2314 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2315 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2316 DPRINTF(("3V card\n")); 2317 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2318 } else { 2319 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2320 return; 2321 } 2322 2323 /* disable interrupts; assert RESET */ 2324 intr = Pcic_read(sc, PCIC_INTR); 2325 intr &= PCIC_INTR_ENABLE; 2326 Pcic_write(sc, PCIC_INTR, intr); 2327 2328 /* zero out the address windows */ 2329 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2330 2331 /* power down the socket to reset it, clear the card reset pin */ 2332 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2333 2334 /* power off; assert output enable bit */ 2335 power = PCIC_PWRCTL_OE; 2336 Pcic_write(sc, PCIC_PWRCTL, power); 2337 2338 /* power up the socket */ 2339 if (pccbb_power(sc, voltage) == 0) 2340 return; 2341 2342 /* 2343 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2344 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2345 * RESET Width (Th (Hi-z RESET)) = 1ms 2346 * RESET Width (Tw (RESET)) = 10us 2347 * 2348 * some machines require some more time to be settled 2349 * for example old toshiba topic bridges! 2350 * (100ms is added here). 2351 */ 2352 pccbb_pcmcia_delay(sc, 200 + 1, "pccen1"); 2353 2354 /* negate RESET */ 2355 intr |= PCIC_INTR_RESET; 2356 Pcic_write(sc, PCIC_INTR, intr); 2357 2358 /* 2359 * RESET Setup Time (Tsu (RESET)) = 20ms 2360 */ 2361 pccbb_pcmcia_delay(sc, 20, "pccen2"); 2362 2363 #ifdef DIAGNOSTIC 2364 reg = Pcic_read(sc, PCIC_IF_STATUS); 2365 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2366 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2367 #endif 2368 2369 /* wait for the chip to finish initializing */ 2370 if (pccbb_pcmcia_wait_ready(sc)) { 2371 #ifdef DIAGNOSTIC 2372 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2373 #endif 2374 /* XXX return a failure status?? */ 2375 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2376 Pcic_write(sc, PCIC_PWRCTL, 0); 2377 return; 2378 } 2379 2380 /* reinstall all the memory and io mappings */ 2381 for (win = 0; win < PCIC_MEM_WINS; ++win) 2382 if (ph->memalloc & (1 << win)) 2383 pccbb_pcmcia_do_mem_map(sc, win); 2384 for (win = 0; win < PCIC_IO_WINS; ++win) 2385 if (ph->ioalloc & (1 << win)) 2386 pccbb_pcmcia_do_io_map(sc, win); 2387 } 2388 2389 /* 2390 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2391 * 2392 * This function disables the card. All information is stored in 2393 * the first argument, pcmcia_chipset_handle_t. 2394 */ 2395 STATIC void 2396 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2397 { 2398 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2399 u_int8_t intr; 2400 2401 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2402 2403 /* disable interrupts; assert RESET */ 2404 intr = Pcic_read(sc, PCIC_INTR); 2405 intr &= PCIC_INTR_ENABLE; 2406 Pcic_write(sc, PCIC_INTR, intr); 2407 2408 /* zero out the address windows */ 2409 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2410 2411 /* power down the socket to reset it, clear the card reset pin */ 2412 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2413 2414 /* disable socket: negate output enable bit and power off */ 2415 Pcic_write(sc, PCIC_PWRCTL, 0); 2416 2417 /* 2418 * Vcc Falling Time (Tpf) = 300ms 2419 */ 2420 pccbb_pcmcia_delay(sc, 300, "pccwr1"); 2421 } 2422 2423 STATIC void 2424 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2425 { 2426 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2427 u_int8_t intr; 2428 2429 /* set the card type */ 2430 2431 intr = Pcic_read(sc, PCIC_INTR); 2432 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2433 if (type == PCMCIA_IFTYPE_IO) 2434 intr |= PCIC_INTR_CARDTYPE_IO; 2435 else 2436 intr |= PCIC_INTR_CARDTYPE_MEM; 2437 Pcic_write(sc, PCIC_INTR, intr); 2438 2439 DPRINTF(("%s: pccbb_pcmcia_socket_settype type %s %02x\n", 2440 device_xname(sc->sc_dev), 2441 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2442 } 2443 2444 /* 2445 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2446 * 2447 * This function detects whether a card is in the slot or not. 2448 * If a card is inserted, return 1. Otherwise, return 0. 2449 */ 2450 STATIC int 2451 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2452 { 2453 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2454 2455 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2456 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2457 } 2458 2459 #if 0 2460 STATIC int 2461 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2462 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2463 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2464 #endif 2465 /* 2466 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2467 * bus_size_t size, 2468 * struct pcmcia_mem_handle *pcmhp) 2469 * 2470 * This function only allocates memory region for pccard. This 2471 * function never maps the allocated region to pccard memory area. 2472 * 2473 * XXX: Why the argument of start address is not in? 2474 */ 2475 STATIC int 2476 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2477 struct pcmcia_mem_handle *pcmhp) 2478 { 2479 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2480 bus_space_handle_t memh; 2481 bus_addr_t addr; 2482 bus_size_t sizepg; 2483 #if rbus 2484 rbus_tag_t rb; 2485 #endif 2486 2487 /* Check that the card is still there. */ 2488 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2489 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2490 return 1; 2491 2492 /* out of sc->memh, allocate as many pages as necessary */ 2493 2494 /* convert size to PCIC pages */ 2495 /* 2496 * This is not enough; when the requested region is on the page 2497 * boundaries, this may calculate wrong result. 2498 */ 2499 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2500 #if 0 2501 if (sizepg > PCIC_MAX_MEM_PAGES) { 2502 return 1; 2503 } 2504 #endif 2505 2506 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2507 return 1; 2508 } 2509 2510 addr = 0; /* XXX gcc -Wuninitialized */ 2511 2512 #if rbus 2513 rb = sc->sc_rbus_memt; 2514 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2515 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2516 &addr, &memh)) { 2517 return 1; 2518 } 2519 #else 2520 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2521 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2522 0, /* boundary */ 2523 0, /* flags */ 2524 &addr, &memh)) { 2525 return 1; 2526 } 2527 #endif 2528 2529 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2530 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2531 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2532 2533 pcmhp->memt = sc->sc_memt; 2534 pcmhp->memh = memh; 2535 pcmhp->addr = addr; 2536 pcmhp->size = size; 2537 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2538 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2539 pcmhp->mhandle = 0; 2540 /* No offset??? Funny. */ 2541 2542 return 0; 2543 } 2544 2545 /* 2546 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2547 * struct pcmcia_mem_handle *pcmhp) 2548 * 2549 * This function release the memory space allocated by the function 2550 * pccbb_pcmcia_mem_alloc(). 2551 */ 2552 STATIC void 2553 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2554 struct pcmcia_mem_handle *pcmhp) 2555 { 2556 #if rbus 2557 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2558 2559 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2560 #else 2561 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2562 #endif 2563 } 2564 2565 /* 2566 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2567 * 2568 * This function release the memory space allocated by the function 2569 * pccbb_pcmcia_mem_alloc(). 2570 */ 2571 STATIC void 2572 pccbb_pcmcia_do_mem_map(struct pccbb_softc *sc, int win) 2573 { 2574 int regbase_win; 2575 bus_addr_t phys_addr; 2576 bus_addr_t phys_end; 2577 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2578 2579 #define PCIC_SMM_START_LOW 0 2580 #define PCIC_SMM_START_HIGH 1 2581 #define PCIC_SMM_STOP_LOW 2 2582 #define PCIC_SMM_STOP_HIGH 3 2583 #define PCIC_CMA_LOW 4 2584 #define PCIC_CMA_HIGH 5 2585 2586 u_int8_t start_low, start_high = 0; 2587 u_int8_t stop_low, stop_high; 2588 u_int8_t off_low, off_high; 2589 u_int8_t mem_window; 2590 int reg; 2591 2592 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2593 int mem8 = 2594 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2595 || (kind == PCMCIA_MEM_ATTR); 2596 2597 regbase_win = 0x10 + win * 0x08; 2598 2599 phys_addr = ph->mem[win].addr; 2600 phys_end = phys_addr + ph->mem[win].size; 2601 2602 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2603 (unsigned long)phys_addr, (unsigned long)phys_end, 2604 (unsigned long)ph->mem[win].offset)); 2605 2606 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2607 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2608 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2609 2610 /* bit 19:12 */ 2611 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2612 /* bit 23:20 and bit 7 on */ 2613 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2614 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2615 /* bit 31:24, for 32-bit address */ 2616 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2617 2618 Pcic_write(sc, regbase_win + PCIC_SMM_START_LOW, start_low); 2619 Pcic_write(sc, regbase_win + PCIC_SMM_START_HIGH, start_high); 2620 2621 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2622 Pcic_write(sc, 0x40 + win, mem_window); 2623 } 2624 2625 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2626 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2627 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2628 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2629 2630 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2631 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2632 2633 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2634 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2635 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2636 | ((kind == PCMCIA_MEM_ATTR) ? 2637 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2638 2639 Pcic_write(sc, regbase_win + PCIC_CMA_LOW, off_low); 2640 Pcic_write(sc, regbase_win + PCIC_CMA_HIGH, off_high); 2641 2642 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2643 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2644 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2645 2646 #if defined(CBB_DEBUG) 2647 { 2648 int r1, r2, r3, r4, r5, r6, r7 = 0; 2649 2650 r1 = Pcic_read(sc, regbase_win + PCIC_SMM_START_LOW); 2651 r2 = Pcic_read(sc, regbase_win + PCIC_SMM_START_HIGH); 2652 r3 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_LOW); 2653 r4 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_HIGH); 2654 r5 = Pcic_read(sc, regbase_win + PCIC_CMA_LOW); 2655 r6 = Pcic_read(sc, regbase_win + PCIC_CMA_HIGH); 2656 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2657 r7 = Pcic_read(sc, 0x40 + win); 2658 } 2659 2660 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2661 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2662 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2663 printf(" %02x", r7); 2664 } 2665 printf("\n"); 2666 } 2667 #endif 2668 } 2669 2670 /* 2671 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2672 * bus_addr_t card_addr, bus_size_t size, 2673 * struct pcmcia_mem_handle *pcmhp, 2674 * bus_addr_t *offsetp, int *windowp) 2675 * 2676 * This function maps memory space allocated by the function 2677 * pccbb_pcmcia_mem_alloc(). 2678 */ 2679 STATIC int 2680 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2681 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2682 bus_addr_t *offsetp, int *windowp) 2683 { 2684 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2685 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2686 bus_addr_t busaddr; 2687 long card_offset; 2688 int win; 2689 2690 /* Check that the card is still there. */ 2691 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2692 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2693 return 1; 2694 2695 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2696 if ((ph->memalloc & (1 << win)) == 0) { 2697 ph->memalloc |= (1 << win); 2698 break; 2699 } 2700 } 2701 2702 if (win == PCIC_MEM_WINS) { 2703 return 1; 2704 } 2705 2706 *windowp = win; 2707 2708 /* XXX this is pretty gross */ 2709 2710 if (sc->sc_memt != pcmhp->memt) { 2711 panic("pccbb_pcmcia_mem_map memt is bogus"); 2712 } 2713 2714 busaddr = pcmhp->addr; 2715 2716 /* 2717 * compute the address offset to the pcmcia address space for the 2718 * pcic. this is intentionally signed. The masks and shifts below 2719 * will cause TRT to happen in the pcic registers. Deal with making 2720 * sure the address is aligned, and return the alignment offset. 2721 */ 2722 2723 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2724 card_addr -= *offsetp; 2725 2726 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2727 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2728 (u_long) card_addr)); 2729 2730 /* 2731 * include the offset in the size, and decrement size by one, since 2732 * the hw wants start/stop 2733 */ 2734 size += *offsetp - 1; 2735 2736 card_offset = (((long)card_addr) - ((long)busaddr)); 2737 2738 ph->mem[win].addr = busaddr; 2739 ph->mem[win].size = size; 2740 ph->mem[win].offset = card_offset; 2741 ph->mem[win].kind = kind; 2742 2743 pccbb_pcmcia_do_mem_map(sc, win); 2744 2745 return 0; 2746 } 2747 2748 /* 2749 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2750 * int window) 2751 * 2752 * This function unmaps memory space which mapped by the function 2753 * pccbb_pcmcia_mem_map(). 2754 */ 2755 STATIC void 2756 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2757 { 2758 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2759 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2760 int reg; 2761 2762 if (window >= PCIC_MEM_WINS) { 2763 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2764 } 2765 2766 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2767 reg &= ~(1 << window); 2768 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2769 2770 ph->memalloc &= ~(1 << window); 2771 } 2772 2773 /* 2774 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2775 * struct pcmcia_function *pf, 2776 * int ipl, 2777 * int (*func)(void *), 2778 * void *arg); 2779 * 2780 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2781 */ 2782 STATIC void * 2783 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2784 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2785 { 2786 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2787 2788 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2789 /* what should I do? */ 2790 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2791 DPRINTF(("%s does not provide edge nor pulse " 2792 "interrupt\n", device_xname(sc->sc_dev))); 2793 return NULL; 2794 } 2795 /* 2796 * XXX Noooooo! The interrupt flag must set properly!! 2797 * dumb pcmcia driver!! 2798 */ 2799 } 2800 2801 return pccbb_intr_establish(sc, 0, ipl, func, arg); 2802 } 2803 2804 /* 2805 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2806 * void *ih) 2807 * 2808 * This function disables PC-Card interrupt. 2809 */ 2810 STATIC void 2811 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2812 { 2813 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2814 2815 pccbb_intr_disestablish(sc, ih); 2816 } 2817 2818 #if rbus 2819 /* 2820 * static int 2821 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2822 * bus_addr_t addr, bus_size_t size, 2823 * bus_addr_t mask, bus_size_t align, 2824 * int flags, bus_addr_t *addrp; 2825 * bus_space_handle_t *bshp) 2826 * 2827 * This function allocates a portion of memory or io space for 2828 * clients. This function is called from CardBus card drivers. 2829 */ 2830 static int 2831 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2832 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2833 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2834 { 2835 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2836 2837 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2838 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2839 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2840 2841 if (align == 0) { 2842 align = size; 2843 } 2844 2845 if (rb->rb_bt == sc->sc_memt) { 2846 if (align < 16) { 2847 return 1; 2848 } 2849 /* 2850 * XXX: align more than 0x1000 to avoid overwrapping 2851 * memory windows for two or more devices. 0x1000 2852 * means memory window's granularity. 2853 * 2854 * Two or more devices should be able to share same 2855 * memory window region. However, overrapping memory 2856 * window is not good because some devices, such as 2857 * 3Com 3C575[BC], have a broken address decoder and 2858 * intrude other's memory region. 2859 */ 2860 if (align < 0x1000) { 2861 align = 0x1000; 2862 } 2863 } else if (rb->rb_bt == sc->sc_iot) { 2864 if (align < 4) { 2865 return 1; 2866 } 2867 /* XXX: hack for avoiding ISA image */ 2868 if (mask < 0x0100) { 2869 mask = 0x3ff; 2870 addr = 0x300; 2871 } 2872 2873 } else { 2874 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2875 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2876 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2877 (unsigned long)sc->sc_memt)); 2878 return 1; 2879 /* XXX: panic here? */ 2880 } 2881 2882 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2883 aprint_normal_dev(sc->sc_dev, "<rbus> no bus space\n"); 2884 return 1; 2885 } 2886 2887 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2888 2889 return 0; 2890 } 2891 2892 /* 2893 * static int 2894 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2895 * bus_space_handle_t *bshp, bus_size_t size); 2896 * 2897 * This function is called from CardBus card drivers. 2898 */ 2899 static int 2900 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2901 bus_space_handle_t bsh, bus_size_t size) 2902 { 2903 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2904 bus_space_tag_t bt = rb->rb_bt; 2905 2906 pccbb_close_win(sc, bt, bsh, size); 2907 2908 if (bt == sc->sc_memt) { 2909 } else if (bt == sc->sc_iot) { 2910 } else { 2911 return 1; 2912 /* XXX: panic here? */ 2913 } 2914 2915 return rbus_space_free(rb, bsh, size, NULL); 2916 } 2917 #endif /* rbus */ 2918 2919 #if rbus 2920 2921 static int 2922 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 2923 bus_size_t size, bus_space_handle_t bsh, int flags) 2924 { 2925 struct pccbb_win_chain_head *head; 2926 bus_addr_t align; 2927 2928 head = &sc->sc_iowindow; 2929 align = 0x04; 2930 if (sc->sc_memt == bst) { 2931 head = &sc->sc_memwindow; 2932 align = 0x1000; 2933 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 2934 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 2935 (unsigned long)bst)); 2936 } 2937 2938 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2939 aprint_error_dev(sc->sc_dev, 2940 "pccbb_open_win: %s winlist insert failed\n", 2941 (head == &sc->sc_memwindow) ? "mem" : "io"); 2942 } 2943 pccbb_winset(align, sc, bst); 2944 2945 return 0; 2946 } 2947 2948 static int 2949 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 2950 bus_space_handle_t bsh, bus_size_t size) 2951 { 2952 struct pccbb_win_chain_head *head; 2953 bus_addr_t align; 2954 2955 head = &sc->sc_iowindow; 2956 align = 0x04; 2957 if (sc->sc_memt == bst) { 2958 head = &sc->sc_memwindow; 2959 align = 0x1000; 2960 } 2961 2962 if (pccbb_winlist_delete(head, bsh, size)) { 2963 aprint_error_dev(sc->sc_dev, 2964 "pccbb_close_win: %s winlist delete failed\n", 2965 (head == &sc->sc_memwindow) ? "mem" : "io"); 2966 } 2967 pccbb_winset(align, sc, bst); 2968 2969 return 0; 2970 } 2971 2972 static int 2973 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 2974 bus_size_t size, bus_space_handle_t bsh, int flags) 2975 { 2976 struct pccbb_win_chain *chainp, *elem; 2977 2978 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2979 M_NOWAIT)) == NULL) 2980 return (1); /* fail */ 2981 2982 elem->wc_start = start; 2983 elem->wc_end = start + (size - 1); 2984 elem->wc_handle = bsh; 2985 elem->wc_flags = flags; 2986 2987 TAILQ_FOREACH(chainp, head, wc_list) { 2988 if (chainp->wc_end >= start) 2989 break; 2990 } 2991 if (chainp != NULL) 2992 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2993 else 2994 TAILQ_INSERT_TAIL(head, elem, wc_list); 2995 return (0); 2996 } 2997 2998 static int 2999 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 3000 bus_size_t size) 3001 { 3002 struct pccbb_win_chain *chainp; 3003 3004 TAILQ_FOREACH(chainp, head, wc_list) { 3005 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 3006 break; 3007 } 3008 if (chainp == NULL) 3009 return 1; /* fail: no candidate to remove */ 3010 3011 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 3012 printf("pccbb_winlist_delete: window 0x%lx size " 3013 "inconsistent: 0x%lx, 0x%lx\n", 3014 (unsigned long)chainp->wc_start, 3015 (unsigned long)(chainp->wc_end - chainp->wc_start), 3016 (unsigned long)(size - 1)); 3017 return 1; 3018 } 3019 3020 TAILQ_REMOVE(head, chainp, wc_list); 3021 free(chainp, M_DEVBUF); 3022 3023 return 0; 3024 } 3025 3026 static void 3027 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3028 { 3029 pci_chipset_tag_t pc; 3030 pcitag_t tag; 3031 bus_addr_t mask = ~(align - 1); 3032 struct { 3033 cardbusreg_t win_start; 3034 cardbusreg_t win_limit; 3035 int win_flags; 3036 } win[2]; 3037 struct pccbb_win_chain *chainp; 3038 int offs; 3039 3040 win[0].win_start = win[1].win_start = 0xffffffff; 3041 win[0].win_limit = win[1].win_limit = 0; 3042 win[0].win_flags = win[1].win_flags = 0; 3043 3044 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3045 offs = PCI_CB_IOBASE0; 3046 if (sc->sc_memt == bst) { 3047 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3048 offs = PCI_CB_MEMBASE0; 3049 } 3050 3051 if (chainp != NULL) { 3052 win[0].win_start = chainp->wc_start & mask; 3053 win[0].win_limit = chainp->wc_end & mask; 3054 win[0].win_flags = chainp->wc_flags; 3055 chainp = TAILQ_NEXT(chainp, wc_list); 3056 } 3057 3058 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3059 if (win[1].win_start == 0xffffffff) { 3060 /* window 1 is not used */ 3061 if ((win[0].win_flags == chainp->wc_flags) && 3062 (win[0].win_limit + align >= 3063 (chainp->wc_start & mask))) { 3064 /* concatenate */ 3065 win[0].win_limit = chainp->wc_end & mask; 3066 } else { 3067 /* make new window */ 3068 win[1].win_start = chainp->wc_start & mask; 3069 win[1].win_limit = chainp->wc_end & mask; 3070 win[1].win_flags = chainp->wc_flags; 3071 } 3072 continue; 3073 } 3074 3075 /* Both windows are engaged. */ 3076 if (win[0].win_flags == win[1].win_flags) { 3077 /* same flags */ 3078 if (win[0].win_flags == chainp->wc_flags) { 3079 if (win[1].win_start - (win[0].win_limit + 3080 align) < 3081 (chainp->wc_start & mask) - 3082 ((chainp->wc_end & mask) + align)) { 3083 /* 3084 * merge window 0 and 1, and set win1 3085 * to chainp 3086 */ 3087 win[0].win_limit = win[1].win_limit; 3088 win[1].win_start = 3089 chainp->wc_start & mask; 3090 win[1].win_limit = 3091 chainp->wc_end & mask; 3092 } else { 3093 win[1].win_limit = 3094 chainp->wc_end & mask; 3095 } 3096 } else { 3097 /* different flags */ 3098 3099 /* concatenate win0 and win1 */ 3100 win[0].win_limit = win[1].win_limit; 3101 /* allocate win[1] to new space */ 3102 win[1].win_start = chainp->wc_start & mask; 3103 win[1].win_limit = chainp->wc_end & mask; 3104 win[1].win_flags = chainp->wc_flags; 3105 } 3106 } else { 3107 /* the flags of win[0] and win[1] is different */ 3108 if (win[0].win_flags == chainp->wc_flags) { 3109 win[0].win_limit = chainp->wc_end & mask; 3110 /* 3111 * XXX this creates overlapping windows, so 3112 * what should the poor bridge do if one is 3113 * cachable, and the other is not? 3114 */ 3115 aprint_error_dev(sc->sc_dev, 3116 "overlapping windows\n"); 3117 } else { 3118 win[1].win_limit = chainp->wc_end & mask; 3119 } 3120 } 3121 } 3122 3123 pc = sc->sc_pc; 3124 tag = sc->sc_tag; 3125 pci_conf_write(pc, tag, offs, win[0].win_start); 3126 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3127 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3128 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3129 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3130 (unsigned long)pci_conf_read(pc, tag, offs), 3131 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3132 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3133 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3134 3135 if (bst == sc->sc_memt) { 3136 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3137 3138 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3139 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3140 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3141 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3142 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3143 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3144 } 3145 } 3146 3147 #endif /* rbus */ 3148 3149 static bool 3150 pccbb_suspend(device_t dv PMF_FN_ARGS) 3151 { 3152 struct pccbb_softc *sc = device_private(dv); 3153 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3154 bus_space_handle_t base_memh = sc->sc_base_memh; 3155 pcireg_t reg; 3156 3157 if (sc->sc_pil_intr_enable) 3158 (void)pccbbintr_function(sc); 3159 sc->sc_pil_intr_enable = 0; 3160 3161 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3162 /* Disable interrupts. */ 3163 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 3164 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3165 /* XXX joerg Disable power to the socket? */ 3166 3167 /* XXX flush PCI write */ 3168 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3169 3170 /* reset interrupt */ 3171 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 3172 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 3173 /* XXX flush PCI write */ 3174 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3175 3176 if (sc->sc_ih != NULL) { 3177 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 3178 sc->sc_ih = NULL; 3179 } 3180 3181 return true; 3182 } 3183 3184 static bool 3185 pccbb_resume(device_t dv PMF_FN_ARGS) 3186 { 3187 struct pccbb_softc *sc = device_private(dv); 3188 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3189 bus_space_handle_t base_memh = sc->sc_base_memh; 3190 pcireg_t reg; 3191 3192 pccbb_chipinit(sc); 3193 pccbb_intrinit(sc); 3194 /* setup memory and io space window for CB */ 3195 pccbb_winset(0x1000, sc, sc->sc_memt); 3196 pccbb_winset(0x04, sc, sc->sc_iot); 3197 3198 /* CSC Interrupt: Card detect interrupt on */ 3199 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3200 /* Card detect intr is turned on. */ 3201 reg |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3202 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3203 /* reset interrupt */ 3204 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3205 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3206 3207 /* 3208 * check for card insertion or removal during suspend period. 3209 * XXX: the code can't cope with card swap (remove then 3210 * insert). how can we detect such situation? 3211 */ 3212 (void)pccbbintr(sc); 3213 3214 sc->sc_pil_intr_enable = 1; 3215 3216 return true; 3217 } 3218