1 /* $NetBSD: pccbb.c,v 1.205 2013/10/17 21:06:15 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.205 2013/10/17 21:06:15 christos Exp $"); 30 31 /* 32 #define CBB_DEBUG 33 #define SHOW_REGS 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/errno.h> 40 #include <sys/ioctl.h> 41 #include <sys/reboot.h> /* for bootverbose */ 42 #include <sys/syslog.h> 43 #include <sys/device.h> 44 #include <sys/malloc.h> 45 #include <sys/proc.h> 46 47 #include <sys/intr.h> 48 #include <sys/bus.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcidevs.h> 53 54 #include <dev/pci/pccbbreg.h> 55 56 #include <dev/cardbus/cardslotvar.h> 57 58 #include <dev/cardbus/cardbusvar.h> 59 60 #include <dev/pcmcia/pcmciareg.h> 61 #include <dev/pcmcia/pcmciavar.h> 62 63 #include <dev/ic/i82365reg.h> 64 #include <dev/pci/pccbbvar.h> 65 66 #ifndef __NetBSD_Version__ 67 struct cfdriver cbb_cd = { 68 NULL, "cbb", DV_DULL 69 }; 70 #endif 71 72 #ifdef CBB_DEBUG 73 #define DPRINTF(x) printf x 74 #define STATIC 75 #else 76 #define DPRINTF(x) 77 #define STATIC static 78 #endif 79 80 int pccbb_burstup = 1; 81 82 /* 83 * delay_ms() is wait in milliseconds. It should be used instead 84 * of delay() if you want to wait more than 1 ms. 85 */ 86 static inline void 87 delay_ms(int millis, struct pccbb_softc *sc) 88 { 89 if (cold) 90 delay(millis * 1000); 91 else 92 kpause("pccbb", false, mstohz(millis), NULL); 93 } 94 95 int pcicbbmatch(device_t, cfdata_t, void *); 96 void pccbbattach(device_t, device_t, void *); 97 void pccbbchilddet(device_t, device_t); 98 int pccbbdetach(device_t, int); 99 int pccbbintr(void *); 100 static void pci113x_insert(void *); 101 static int pccbbintr_function(struct pccbb_softc *); 102 103 static int pccbb_detect_card(struct pccbb_softc *); 104 105 static void pccbb_pcmcia_write(struct pccbb_softc *, int, u_int8_t); 106 static u_int8_t pccbb_pcmcia_read(struct pccbb_softc *, int); 107 #define Pcic_read(sc, reg) pccbb_pcmcia_read((sc), (reg)) 108 #define Pcic_write(sc, reg, val) pccbb_pcmcia_write((sc), (reg), (val)) 109 110 STATIC int cb_reset(struct pccbb_softc *); 111 STATIC int cb_detect_voltage(struct pccbb_softc *); 112 STATIC int cbbprint(void *, const char *); 113 114 static int cb_chipset(u_int32_t, int *); 115 STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *, 116 struct pcmciabus_attach_args *); 117 118 STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int); 119 STATIC int pccbb_power(struct pccbb_softc *sc, int); 120 STATIC int pccbb_power_ct(cardbus_chipset_tag_t, int); 121 STATIC int pccbb_cardenable(struct pccbb_softc * sc, int function); 122 static void *pccbb_intr_establish(struct pccbb_softc *, 123 int level, int (*ih) (void *), void *sc); 124 static void pccbb_intr_disestablish(struct pccbb_softc *, void *ih); 125 126 static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, 127 int level, int (*ih) (void *), void *sc); 128 static void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih); 129 130 static pcitag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int); 131 static pcireg_t pccbb_conf_read(cardbus_chipset_tag_t, pcitag_t, int); 132 static void pccbb_conf_write(cardbus_chipset_tag_t, pcitag_t, int, 133 pcireg_t); 134 static void pccbb_chipinit(struct pccbb_softc *); 135 static void pccbb_intrinit(struct pccbb_softc *); 136 137 STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 138 struct pcmcia_mem_handle *); 139 STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, 140 struct pcmcia_mem_handle *); 141 STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 142 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 143 STATIC void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); 144 STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 145 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 146 STATIC void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, 147 struct pcmcia_io_handle *); 148 STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 149 bus_size_t, struct pcmcia_io_handle *, int *); 150 STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); 151 STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t, 152 struct pcmcia_function *, int, int (*)(void *), void *); 153 STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); 154 STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); 155 STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); 156 STATIC void pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t, int); 157 STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch); 158 159 static int pccbb_pcmcia_wait_ready(struct pccbb_softc *); 160 static void pccbb_pcmcia_delay(struct pccbb_softc *, int, const char *); 161 162 static void pccbb_pcmcia_do_io_map(struct pccbb_softc *, int); 163 static void pccbb_pcmcia_do_mem_map(struct pccbb_softc *, int); 164 165 /* bus-space allocation and deallocation functions */ 166 167 static int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, 168 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 169 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); 170 static int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, 171 bus_space_handle_t, bus_size_t); 172 173 174 175 static int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, 176 bus_addr_t, bus_size_t, bus_space_handle_t, int flags); 177 static int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, 178 bus_space_handle_t, bus_size_t); 179 static int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, 180 bus_size_t, bus_space_handle_t, int); 181 static int pccbb_winlist_delete(struct pccbb_win_chain_head *, 182 bus_space_handle_t, bus_size_t); 183 static void pccbb_winset(bus_addr_t align, struct pccbb_softc *, 184 bus_space_tag_t); 185 void pccbb_winlist_show(struct pccbb_win_chain *); 186 187 188 /* for config_defer */ 189 static void pccbb_pci_callback(device_t); 190 191 static bool pccbb_suspend(device_t, const pmf_qual_t *); 192 static bool pccbb_resume(device_t, const pmf_qual_t *); 193 194 #if defined SHOW_REGS 195 static void cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, 196 bus_space_tag_t memt, bus_space_handle_t memh); 197 #endif 198 199 CFATTACH_DECL3_NEW(cbb_pci, sizeof(struct pccbb_softc), 200 pcicbbmatch, pccbbattach, pccbbdetach, NULL, NULL, pccbbchilddet, 201 DVF_DETACH_SHUTDOWN); 202 203 static const struct pcmcia_chip_functions pccbb_pcmcia_funcs = { 204 pccbb_pcmcia_mem_alloc, 205 pccbb_pcmcia_mem_free, 206 pccbb_pcmcia_mem_map, 207 pccbb_pcmcia_mem_unmap, 208 pccbb_pcmcia_io_alloc, 209 pccbb_pcmcia_io_free, 210 pccbb_pcmcia_io_map, 211 pccbb_pcmcia_io_unmap, 212 pccbb_pcmcia_intr_establish, 213 pccbb_pcmcia_intr_disestablish, 214 pccbb_pcmcia_socket_enable, 215 pccbb_pcmcia_socket_disable, 216 pccbb_pcmcia_socket_settype, 217 pccbb_pcmcia_card_detect 218 }; 219 220 static const struct cardbus_functions pccbb_funcs = { 221 pccbb_rbus_cb_space_alloc, 222 pccbb_rbus_cb_space_free, 223 pccbb_cb_intr_establish, 224 pccbb_cb_intr_disestablish, 225 pccbb_ctrl, 226 pccbb_power_ct, 227 pccbb_make_tag, 228 pccbb_conf_read, 229 pccbb_conf_write, 230 }; 231 232 int 233 pcicbbmatch(device_t parent, cfdata_t match, void *aux) 234 { 235 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 236 237 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 238 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && 239 PCI_INTERFACE(pa->pa_class) == 0) { 240 return 1; 241 } 242 243 return 0; 244 } 245 246 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ 247 | ((prod) << PCI_PRODUCT_SHIFT)) 248 249 const struct yenta_chipinfo { 250 pcireg_t yc_id; /* vendor tag | product tag */ 251 int yc_chiptype; 252 int yc_flags; 253 } yc_chipsets[] = { 254 /* Texas Instruments chips */ 255 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, 256 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 257 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, 258 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 259 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X, 260 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 261 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, 262 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 263 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, 264 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 265 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, 266 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 267 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X, 268 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 269 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X, 270 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 271 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, 272 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 273 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, 274 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 275 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420, 276 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 277 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X, 278 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 279 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, 280 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 281 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1510), CB_TI12XX, 282 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 283 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1520), CB_TI12XX, 284 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 285 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4410YENTA), CB_TI12XX, 286 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 287 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI4520YENTA), CB_TI12XX, 288 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 289 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI7420YENTA), CB_TI12XX, 290 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, 291 292 /* Ricoh chips */ 293 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C475), CB_RX5C47X, 294 PCCBB_PCMCIA_MEM_32}, 295 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RL5C476), CB_RX5C47X, 296 PCCBB_PCMCIA_MEM_32}, 297 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C477), CB_RX5C47X, 298 PCCBB_PCMCIA_MEM_32}, 299 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C478), CB_RX5C47X, 300 PCCBB_PCMCIA_MEM_32}, 301 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C465), CB_RX5C46X, 302 PCCBB_PCMCIA_MEM_32}, 303 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_Rx5C466), CB_RX5C46X, 304 PCCBB_PCMCIA_MEM_32}, 305 306 /* Toshiba products */ 307 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), 308 CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, 309 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), 310 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, 311 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), 312 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 313 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), 314 CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, 315 316 /* Cirrus Logic products */ 317 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), 318 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 319 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), 320 CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, 321 322 /* O2 Micro products */ 323 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729), 324 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 325 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730), 326 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 327 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832), 328 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 329 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836), 330 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 331 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), 332 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 333 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6922), 334 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 335 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6933), 336 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 337 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6972), 338 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 339 { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_7223), 340 CB_O2MICRO, PCCBB_PCMCIA_MEM_32}, 341 342 /* sentinel, or Generic chip */ 343 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, 344 }; 345 346 static int 347 cb_chipset(u_int32_t pci_id, int *flagp) 348 { 349 const struct yenta_chipinfo *yc; 350 351 /* Loop over except the last default entry. */ 352 for (yc = yc_chipsets; yc < yc_chipsets + 353 __arraycount(yc_chipsets) - 1; yc++) 354 if (pci_id == yc->yc_id) 355 break; 356 357 if (flagp != NULL) 358 *flagp = yc->yc_flags; 359 360 return (yc->yc_chiptype); 361 } 362 363 void 364 pccbbchilddet(device_t self, device_t child) 365 { 366 struct pccbb_softc *sc = device_private(self); 367 int s; 368 369 KASSERT(sc->sc_csc == device_private(child)); 370 371 s = splbio(); 372 if (sc->sc_csc == device_private(child)) 373 sc->sc_csc = NULL; 374 splx(s); 375 } 376 377 void 378 pccbbattach(device_t parent, device_t self, void *aux) 379 { 380 struct pccbb_softc *sc = device_private(self); 381 struct pci_attach_args *pa = aux; 382 pci_chipset_tag_t pc = pa->pa_pc; 383 pcireg_t reg, sock_base; 384 bus_addr_t sockbase; 385 int flags; 386 387 #ifdef __HAVE_PCCBB_ATTACH_HOOK 388 pccbb_attach_hook(parent, self, pa); 389 #endif 390 391 sc->sc_dev = self; 392 393 mutex_init(&sc->sc_pwr_mtx, MUTEX_DEFAULT, IPL_BIO); 394 cv_init(&sc->sc_pwr_cv, "pccpwr"); 395 396 callout_init(&sc->sc_insert_ch, 0); 397 callout_setfunc(&sc->sc_insert_ch, pci113x_insert, sc); 398 399 sc->sc_chipset = cb_chipset(pa->pa_id, &flags); 400 401 pci_aprint_devinfo(pa, NULL); 402 DPRINTF(("(chipflags %x)", flags)); 403 404 TAILQ_INIT(&sc->sc_memwindow); 405 TAILQ_INIT(&sc->sc_iowindow); 406 407 sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); 408 sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); 409 410 #if 0 411 printf("pa->pa_memt: %08x vs rbus_mem->rb_bt: %08x\n", 412 pa->pa_memt, sc->sc_rbus_memt->rb_bt); 413 #endif 414 415 sc->sc_flags &= ~CBB_MEMHMAPPED; 416 417 /* 418 * MAP socket registers and ExCA registers on memory-space 419 * When no valid address is set on socket base registers (on pci 420 * config space), get it not polite way. 421 */ 422 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE); 423 424 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && 425 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) { 426 /* The address must be valid. */ 427 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, 428 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, &sc->sc_base_size)) { 429 aprint_error_dev(self, 430 "can't map socket base address 0x%lx\n", 431 (unsigned long)sock_base); 432 /* 433 * I think it's funny: socket base registers must be 434 * mapped on memory space, but ... 435 */ 436 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 437 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, 438 &sc->sc_base_size)) { 439 aprint_error_dev(self, 440 "can't map socket base address" 441 " 0x%lx: io mode\n", 442 (unsigned long)sockbase); 443 /* give up... allocate reg space via rbus. */ 444 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); 445 } else 446 sc->sc_flags |= CBB_MEMHMAPPED; 447 } else { 448 DPRINTF(("%s: socket base address 0x%lx\n", 449 device_xname(self), 450 (unsigned long)sockbase)); 451 sc->sc_flags |= CBB_MEMHMAPPED; 452 } 453 } 454 455 sc->sc_mem_start = 0; /* XXX */ 456 sc->sc_mem_end = 0xffffffff; /* XXX */ 457 458 /* pccbb_machdep.c end */ 459 460 #if defined CBB_DEBUG 461 { 462 static const char *intrname[] = { "NON", "A", "B", "C", "D" }; 463 aprint_debug_dev(self, "intrpin %s, intrtag %d\n", 464 intrname[pa->pa_intrpin], pa->pa_intrline); 465 } 466 #endif 467 468 /* setup softc */ 469 sc->sc_pc = pc; 470 sc->sc_iot = pa->pa_iot; 471 sc->sc_memt = pa->pa_memt; 472 sc->sc_dmat = pa->pa_dmat; 473 sc->sc_tag = pa->pa_tag; 474 475 memcpy(&sc->sc_pa, pa, sizeof(*pa)); 476 477 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */ 478 479 /* Disable legacy register mapping. */ 480 switch (sc->sc_chipset) { 481 case CB_RX5C46X: /* fallthrough */ 482 #if 0 483 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */ 484 case CB_RX5C47X: 485 #endif 486 /* 487 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges 488 * cannot be disabled by substituting 0 into PCI_LEGACY 489 * register. Ricoh CardBus bridges have special bits on Bridge 490 * control reg (addr 0x3e on PCI config space). 491 */ 492 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG); 493 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); 494 pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg); 495 break; 496 497 default: 498 /* XXX I don't know proper way to kill legacy I/O. */ 499 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); 500 break; 501 } 502 503 if (!pmf_device_register(self, pccbb_suspend, pccbb_resume)) 504 aprint_error_dev(self, "couldn't establish power handler\n"); 505 506 config_defer(self, pccbb_pci_callback); 507 } 508 509 int 510 pccbbdetach(device_t self, int flags) 511 { 512 struct pccbb_softc *sc = device_private(self); 513 pci_chipset_tag_t pc = sc->sc_pa.pa_pc; 514 bus_space_tag_t bmt = sc->sc_base_memt; 515 bus_space_handle_t bmh = sc->sc_base_memh; 516 uint32_t sockmask; 517 int rc; 518 519 if ((rc = config_detach_children(self, flags)) != 0) 520 return rc; 521 522 if (!LIST_EMPTY(&sc->sc_pil)) { 523 panic("%s: interrupt handlers still registered", 524 device_xname(self)); 525 return EBUSY; 526 } 527 528 if (sc->sc_ih != NULL) { 529 pci_intr_disestablish(pc, sc->sc_ih); 530 sc->sc_ih = NULL; 531 } 532 533 /* CSC Interrupt: turn off card detect and power cycle interrupts */ 534 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 535 sockmask &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 536 CB_SOCKET_MASK_POWER); 537 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 538 /* reset interrupt */ 539 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 540 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 541 542 switch (sc->sc_flags & (CBB_MEMHMAPPED|CBB_SPECMAPPED)) { 543 case CBB_MEMHMAPPED: 544 bus_space_unmap(bmt, bmh, sc->sc_base_size); 545 break; 546 case CBB_MEMHMAPPED|CBB_SPECMAPPED: 547 #if rbus 548 { 549 rbus_space_free(sc->sc_rbus_memt, bmh, 0x1000, 550 NULL); 551 } 552 #else 553 bus_space_free(bmt, bmh, 0x1000); 554 #endif 555 } 556 sc->sc_flags &= ~(CBB_MEMHMAPPED|CBB_SPECMAPPED); 557 558 if (!TAILQ_EMPTY(&sc->sc_iowindow)) 559 aprint_error_dev(self, "i/o windows not empty"); 560 if (!TAILQ_EMPTY(&sc->sc_memwindow)) 561 aprint_error_dev(self, "memory windows not empty"); 562 563 callout_stop(&sc->sc_insert_ch); 564 callout_destroy(&sc->sc_insert_ch); 565 566 mutex_destroy(&sc->sc_pwr_mtx); 567 cv_destroy(&sc->sc_pwr_cv); 568 569 return 0; 570 } 571 572 /* 573 * static void pccbb_pci_callback(device_t self) 574 * 575 * The actual attach routine: get memory space for YENTA register 576 * space, setup YENTA register and route interrupt. 577 * 578 * This function should be deferred because this device may obtain 579 * memory space dynamically. This function must avoid obtaining 580 * memory area which has already kept for another device. 581 */ 582 static void 583 pccbb_pci_callback(device_t self) 584 { 585 struct pccbb_softc *sc = device_private(self); 586 pci_chipset_tag_t pc = sc->sc_pc; 587 bus_addr_t sockbase; 588 struct cbslot_attach_args cba; 589 struct pcmciabus_attach_args paa; 590 struct cardslot_attach_args caa; 591 device_t csc; 592 593 if (!(sc->sc_flags & CBB_MEMHMAPPED)) { 594 /* The socket registers aren't mapped correctly. */ 595 #if rbus 596 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, 597 (sc->sc_chipset == CB_RX5C47X 598 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 599 0, &sockbase, &sc->sc_base_memh)) { 600 return; 601 } 602 sc->sc_base_memt = sc->sc_memt; 603 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 604 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 605 device_xname(self), (unsigned long)sockbase, 606 (unsigned long)pci_conf_read(pc, sc->sc_tag, 607 PCI_SOCKBASE))); 608 #else 609 sc->sc_base_memt = sc->sc_memt; 610 #if !defined CBB_PCI_BASE 611 #define CBB_PCI_BASE 0x20000000 612 #endif 613 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 614 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) { 615 /* cannot allocate memory space */ 616 return; 617 } 618 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); 619 DPRINTF(("%s: CardBus register address 0x%lx -> 0x%lx\n", 620 device_xname(self), (unsigned long)sock_base, 621 (unsigned long)pci_conf_read(pc, 622 sc->sc_tag, PCI_SOCKBASE))); 623 #endif 624 sc->sc_flags |= CBB_MEMHMAPPED|CBB_SPECMAPPED; 625 } 626 627 /* clear data structure for child device interrupt handlers */ 628 LIST_INIT(&sc->sc_pil); 629 630 /* bus bridge initialization */ 631 pccbb_chipinit(sc); 632 633 sc->sc_pil_intr_enable = true; 634 635 { 636 u_int32_t sockstat; 637 638 sockstat = bus_space_read_4(sc->sc_base_memt, 639 sc->sc_base_memh, CB_SOCKET_STAT); 640 if (0 == (sockstat & CB_SOCKET_STAT_CD)) { 641 sc->sc_flags |= CBB_CARDEXIST; 642 } 643 } 644 645 /* 646 * attach cardbus 647 */ 648 { 649 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); 650 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG); 651 652 /* initialize cbslot_attach */ 653 cba.cba_iot = sc->sc_iot; 654 cba.cba_memt = sc->sc_memt; 655 cba.cba_dmat = sc->sc_dmat; 656 cba.cba_bus = (busreg >> 8) & 0x0ff; 657 cba.cba_cc = (void *)sc; 658 cba.cba_cf = &pccbb_funcs; 659 660 #if rbus 661 cba.cba_rbus_iot = sc->sc_rbus_iot; 662 cba.cba_rbus_memt = sc->sc_rbus_memt; 663 #endif 664 665 cba.cba_cacheline = PCI_CACHELINE(bhlc); 666 cba.cba_max_lattimer = PCI_LATTIMER(bhlc); 667 668 aprint_verbose_dev(self, 669 "cacheline 0x%x lattimer 0x%x\n", 670 cba.cba_cacheline, 671 cba.cba_max_lattimer); 672 aprint_verbose_dev(self, "bhlc 0x%x\n", bhlc); 673 #if defined SHOW_REGS 674 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, 675 sc->sc_base_memh); 676 #endif 677 } 678 679 pccbb_pcmcia_attach_setup(sc, &paa); 680 caa.caa_cb_attach = NULL; 681 if (cba.cba_bus == 0) 682 aprint_error_dev(self, 683 "secondary bus number uninitialized; try PCI_BUS_FIXUP\n"); 684 else 685 caa.caa_cb_attach = &cba; 686 caa.caa_16_attach = &paa; 687 688 pccbb_intrinit(sc); 689 690 if (NULL != (csc = config_found_ia(self, "pcmciaslot", &caa, 691 cbbprint))) { 692 DPRINTF(("%s: found cardslot\n", __func__)); 693 sc->sc_csc = device_private(csc); 694 } 695 696 return; 697 } 698 699 700 701 702 703 /* 704 * static void pccbb_chipinit(struct pccbb_softc *sc) 705 * 706 * This function initialize YENTA chip registers listed below: 707 * 1) PCI command reg, 708 * 2) PCI and CardBus latency timer, 709 * 3) route PCI interrupt, 710 * 4) close all memory and io windows. 711 * 5) turn off bus power. 712 * 6) card detect and power cycle interrupts on. 713 * 7) clear interrupt 714 */ 715 static void 716 pccbb_chipinit(struct pccbb_softc *sc) 717 { 718 pci_chipset_tag_t pc = sc->sc_pc; 719 pcitag_t tag = sc->sc_tag; 720 bus_space_tag_t bmt = sc->sc_base_memt; 721 bus_space_handle_t bmh = sc->sc_base_memh; 722 pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl, 723 sysctrl; 724 725 /* 726 * Set PCI command reg. 727 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip. 728 */ 729 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 730 /* I believe it is harmless. */ 731 csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 732 PCI_COMMAND_MASTER_ENABLE); 733 734 /* All O2 Micro chips have broken parity-error reporting 735 * until proven otherwise. The OZ6933 PCI-CardBus Bridge 736 * is known to have the defect---see PR kern/38698. 737 */ 738 if (sc->sc_chipset != CB_O2MICRO) 739 csr |= PCI_COMMAND_PARITY_ENABLE; 740 741 csr |= PCI_COMMAND_SERR_ENABLE; 742 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 743 744 /* 745 * Set CardBus latency timer. 746 */ 747 lscp = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); 748 if (PCI_CB_LATENCY(lscp) < 0x20) { 749 lscp &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); 750 lscp |= (0x20 << PCI_CB_LATENCY_SHIFT); 751 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, lscp); 752 } 753 DPRINTF(("CardBus latency timer 0x%x (%x)\n", 754 PCI_CB_LATENCY(lscp), pci_conf_read(pc, tag, PCI_CB_LSCP_REG))); 755 756 /* 757 * Set PCI latency timer. 758 */ 759 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 760 if (PCI_LATTIMER(bhlc) < 0x10) { 761 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 762 bhlc |= (0x10 << PCI_LATTIMER_SHIFT); 763 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 764 } 765 DPRINTF(("PCI latency timer 0x%x (%x)\n", 766 PCI_LATTIMER(bhlc), pci_conf_read(pc, tag, PCI_BHLC_REG))); 767 768 769 /* Route functional interrupts to PCI. */ 770 bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 771 bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */ 772 bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */ 773 /* assert reset */ 774 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 775 /* Set master abort mode to 1, forward SERR# from secondary 776 * to primary, and detect parity errors on secondary. 777 */ 778 bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT; 779 bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT; 780 bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT; 781 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 782 783 switch (sc->sc_chipset) { 784 case CB_TI113X: 785 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 786 /* This bit is shared, but may read as 0 on some chips, so set 787 it explicitly on both functions. */ 788 cbctl |= PCI113X_CBCTRL_PCI_IRQ_ENA; 789 /* CSC intr enable */ 790 cbctl |= PCI113X_CBCTRL_PCI_CSC; 791 /* functional intr prohibit | prohibit ISA routing */ 792 cbctl &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); 793 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 794 break; 795 796 case CB_TI1420: 797 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 798 mrburst = pccbb_burstup 799 ? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN; 800 if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) { 801 printf("%s: %swrite bursts enabled\n", 802 device_xname(sc->sc_dev), 803 pccbb_burstup ? "read/" : ""); 804 } else if (pccbb_burstup) { 805 printf("%s: enabling read/write bursts\n", 806 device_xname(sc->sc_dev)); 807 sysctrl |= PCI1420_SYSCTRL_MRBURST; 808 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 809 } else { 810 printf("%s: disabling read bursts, " 811 "enabling write bursts\n", 812 device_xname(sc->sc_dev)); 813 sysctrl |= PCI1420_SYSCTRL_MRBURSTDN; 814 sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP; 815 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 816 } 817 /*FALLTHROUGH*/ 818 case CB_TI12XX: 819 /* 820 * Some TI 12xx (and [14][45]xx) based pci cards 821 * sometimes have issues with the MFUNC register not 822 * being initialized due to a bad EEPROM on board. 823 * Laptops that this matters on have this register 824 * properly initialized. 825 * 826 * The TI125X parts have a different register. 827 */ 828 mfunc = pci_conf_read(pc, tag, PCI12XX_MFUNC); 829 if ((mfunc & (PCI12XX_MFUNC_PIN0 | PCI12XX_MFUNC_PIN1)) == 0) { 830 /* Enable PCI interrupt /INTA */ 831 mfunc |= PCI12XX_MFUNC_PIN0_INTA; 832 833 /* XXX this is TI1520 only */ 834 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) & 835 PCI12XX_SYSCTRL_INTRTIE) == 0) 836 /* Enable PCI interrupt /INTB */ 837 mfunc |= PCI12XX_MFUNC_PIN1_INTB; 838 839 pci_conf_write(pc, tag, PCI12XX_MFUNC, mfunc); 840 } 841 /* fallthrough */ 842 843 case CB_TI125X: 844 /* 845 * Disable zoom video. Some machines initialize this 846 * improperly and experience has shown that this helps 847 * prevent strange behavior. 848 */ 849 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0); 850 851 sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL); 852 sysctrl |= PCI12XX_SYSCTRL_VCCPROT; 853 pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl); 854 cbctl = pci_conf_read(pc, tag, PCI_CBCTRL); 855 cbctl |= PCI12XX_CBCTRL_CSC; 856 pci_conf_write(pc, tag, PCI_CBCTRL, cbctl); 857 break; 858 859 case CB_TOPIC95B: 860 sockctl = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); 861 sockctl |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; 862 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, sockctl); 863 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 864 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 865 device_xname(sc->sc_dev), slotctl)); 866 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 867 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 868 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 869 DPRINTF(("0x%x\n", slotctl)); 870 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 871 break; 872 873 case CB_TOPIC97: 874 slotctl = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); 875 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", 876 device_xname(sc->sc_dev), slotctl)); 877 slotctl |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | 878 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); 879 slotctl &= ~TOPIC_SLOT_CTRL_SWDETECT; 880 slotctl |= TOPIC97_SLOT_CTRL_PCIINT; 881 slotctl &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP); 882 DPRINTF(("0x%x\n", slotctl)); 883 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, slotctl); 884 /* make sure to assert LV card support bits */ 885 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 886 0x800 + 0x3e, 887 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 888 0x800 + 0x3e) | 0x03); 889 break; 890 } 891 892 /* Close all memory and I/O windows. */ 893 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); 894 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); 895 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); 896 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); 897 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); 898 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); 899 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); 900 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0); 901 902 /* reset 16-bit pcmcia bus */ 903 bus_space_write_1(bmt, bmh, 0x800 + PCIC_INTR, 904 bus_space_read_1(bmt, bmh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET); 905 906 /* turn off power */ 907 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 908 } 909 910 static void 911 pccbb_intrinit(struct pccbb_softc *sc) 912 { 913 pcireg_t sockmask; 914 const char *intrstr = NULL; 915 pci_intr_handle_t ih; 916 pci_chipset_tag_t pc = sc->sc_pc; 917 bus_space_tag_t bmt = sc->sc_base_memt; 918 bus_space_handle_t bmh = sc->sc_base_memh; 919 920 /* Map and establish the interrupt. */ 921 if (pci_intr_map(&sc->sc_pa, &ih)) { 922 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 923 return; 924 } 925 intrstr = pci_intr_string(pc, ih); 926 927 /* 928 * XXX pccbbintr should be called under the priority lower 929 * than any other hard interrupts. 930 */ 931 KASSERT(sc->sc_ih == NULL); 932 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc); 933 934 if (sc->sc_ih == NULL) { 935 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 936 if (intrstr != NULL) 937 aprint_error(" at %s\n", intrstr); 938 else 939 aprint_error("\n"); 940 return; 941 } 942 943 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 944 945 /* CSC Interrupt: Card detect and power cycle interrupts on */ 946 sockmask = bus_space_read_4(bmt, bmh, CB_SOCKET_MASK); 947 sockmask |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | 948 CB_SOCKET_MASK_POWER; 949 bus_space_write_4(bmt, bmh, CB_SOCKET_MASK, sockmask); 950 /* reset interrupt */ 951 bus_space_write_4(bmt, bmh, CB_SOCKET_EVENT, 952 bus_space_read_4(bmt, bmh, CB_SOCKET_EVENT)); 953 } 954 955 /* 956 * STATIC void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 957 * struct pcmciabus_attach_args *paa) 958 * 959 * This function attaches 16-bit PCcard bus. 960 */ 961 STATIC void 962 pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, 963 struct pcmciabus_attach_args *paa) 964 { 965 /* 966 * We need to do a few things here: 967 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by 968 * setting the IRQ numbers to 0. 969 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable 970 * routing of CSC interrupts (e.g. card removal) to PCI while in 971 * PCMCIA mode. We just leave this set all the time. 972 * 3) Enable card insertion/removal interrupts in case the chip also 973 * needs that while in PCMCIA mode. 974 * 4) Clear any pending CSC interrupt. 975 */ 976 Pcic_write(sc, PCIC_INTR, PCIC_INTR_ENABLE); 977 if (sc->sc_chipset == CB_TI113X) { 978 Pcic_write(sc, PCIC_CSC_INTR, 0); 979 } else { 980 Pcic_write(sc, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); 981 Pcic_read(sc, PCIC_CSC); 982 } 983 984 /* initialize pcmcia bus attachment */ 985 paa->paa_busname = "pcmcia"; 986 paa->pct = &pccbb_pcmcia_funcs; 987 paa->pch = sc; 988 return; 989 } 990 991 /* 992 * int pccbbintr(arg) 993 * void *arg; 994 * This routine handles the interrupt from Yenta PCI-CardBus bridge 995 * itself. 996 */ 997 int 998 pccbbintr(void *arg) 999 { 1000 struct pccbb_softc *sc = (struct pccbb_softc *)arg; 1001 struct cardslot_softc *csc; 1002 u_int32_t sockevent, sockstate; 1003 bus_space_tag_t memt = sc->sc_base_memt; 1004 bus_space_handle_t memh = sc->sc_base_memh; 1005 1006 if (!device_has_power(sc->sc_dev)) 1007 return 0; 1008 1009 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); 1010 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); 1011 Pcic_read(sc, PCIC_CSC); 1012 1013 if (sockevent != 0) { 1014 DPRINTF(("%s: enter sockevent %" PRIx32 "\n", 1015 __func__, sockevent)); 1016 } 1017 1018 /* XXX sockevent == CB_SOCKET_EVENT_CSTS|CB_SOCKET_EVENT_POWER 1019 * does occur in the wild. Check for a _POWER event before 1020 * possibly exiting because of an _CSTS event. 1021 */ 1022 if (sockevent & CB_SOCKET_EVENT_POWER) { 1023 DPRINTF(("Powercycling because of socket event\n")); 1024 /* XXX: Does not happen when attaching a 16-bit card */ 1025 mutex_enter(&sc->sc_pwr_mtx); 1026 sc->sc_pwrcycle++; 1027 cv_signal(&sc->sc_pwr_cv); 1028 mutex_exit(&sc->sc_pwr_mtx); 1029 } 1030 1031 /* Sometimes a change of CSTSCHG# accompanies the first 1032 * interrupt from an Atheros WLAN. That generates a 1033 * CB_SOCKET_EVENT_CSTS event on the bridge. The event 1034 * isn't interesting to pccbb(4), so we used to ignore the 1035 * interrupt. Now, let the child devices try to handle 1036 * the interrupt, instead. The Atheros NIC produces 1037 * interrupts more reliably, now: used to be that it would 1038 * only interrupt if the driver avoided powering down the 1039 * NIC's cardslot, and then the NIC would only work after 1040 * it was reset a second time. 1041 */ 1042 if (sockevent == 0 || 1043 (sockevent & ~(CB_SOCKET_EVENT_POWER|CB_SOCKET_EVENT_CD)) != 0) { 1044 /* This intr is not for me: it may be for my child devices. */ 1045 if (sc->sc_pil_intr_enable) { 1046 return pccbbintr_function(sc); 1047 } else { 1048 return 0; 1049 } 1050 } 1051 1052 if (sockevent & CB_SOCKET_EVENT_CD) { 1053 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1054 if (0x00 != (sockstate & CB_SOCKET_STAT_CD)) { 1055 /* A card should be removed. */ 1056 if (sc->sc_flags & CBB_CARDEXIST) { 1057 DPRINTF(("%s: 0x%08x", 1058 device_xname(sc->sc_dev), sockevent)); 1059 DPRINTF((" card removed, 0x%08x\n", sockstate)); 1060 sc->sc_flags &= ~CBB_CARDEXIST; 1061 if ((csc = sc->sc_csc) == NULL) 1062 ; 1063 else if (csc->sc_status & 1064 CARDSLOT_STATUS_CARD_16) { 1065 cardslot_event_throw(csc, 1066 CARDSLOT_EVENT_REMOVAL_16); 1067 } else if (csc->sc_status & 1068 CARDSLOT_STATUS_CARD_CB) { 1069 /* Cardbus intr removed */ 1070 cardslot_event_throw(csc, 1071 CARDSLOT_EVENT_REMOVAL_CB); 1072 } 1073 } else if (sc->sc_flags & CBB_INSERTING) { 1074 sc->sc_flags &= ~CBB_INSERTING; 1075 callout_stop(&sc->sc_insert_ch); 1076 } 1077 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) && 1078 /* 1079 * The pccbbintr may called from powerdown hook when 1080 * the system resumed, to detect the card 1081 * insertion/removal during suspension. 1082 */ 1083 (sc->sc_flags & CBB_CARDEXIST) == 0) { 1084 if (sc->sc_flags & CBB_INSERTING) { 1085 callout_stop(&sc->sc_insert_ch); 1086 } 1087 callout_schedule(&sc->sc_insert_ch, mstohz(200)); 1088 sc->sc_flags |= CBB_INSERTING; 1089 } 1090 } 1091 1092 return (1); 1093 } 1094 1095 /* 1096 * static int pccbbintr_function(struct pccbb_softc *sc) 1097 * 1098 * This function calls each interrupt handler registered at the 1099 * bridge. The interrupt handlers are called in registered order. 1100 */ 1101 static int 1102 pccbbintr_function(struct pccbb_softc *sc) 1103 { 1104 int retval = 0, val; 1105 struct pccbb_intrhand_list *pil; 1106 int s; 1107 1108 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1109 s = splraiseipl(pil->pil_icookie); 1110 val = (*pil->pil_func)(pil->pil_arg); 1111 splx(s); 1112 1113 retval = retval == 1 ? 1 : 1114 retval == 0 ? val : val != 0 ? val : retval; 1115 } 1116 1117 return retval; 1118 } 1119 1120 static void 1121 pci113x_insert(void *arg) 1122 { 1123 struct pccbb_softc *sc = arg; 1124 struct cardslot_softc *csc; 1125 u_int32_t sockevent, sockstate; 1126 1127 if (!(sc->sc_flags & CBB_INSERTING)) { 1128 /* We add a card only under inserting state. */ 1129 return; 1130 } 1131 sc->sc_flags &= ~CBB_INSERTING; 1132 1133 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1134 CB_SOCKET_EVENT); 1135 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 1136 CB_SOCKET_STAT); 1137 1138 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */ 1139 #ifdef CBB_DEBUG 1140 DPRINTF(("%s: 0x%08x", device_xname(sc->sc_dev), sockevent)); 1141 #else 1142 __USE(sockevent); 1143 #endif 1144 1145 DPRINTF((" card inserted, 0x%08x\n", sockstate)); 1146 sc->sc_flags |= CBB_CARDEXIST; 1147 /* call pccard interrupt handler here */ 1148 if ((csc = sc->sc_csc) == NULL) 1149 ; 1150 else if (sockstate & CB_SOCKET_STAT_16BIT) { 1151 /* 16-bit card found */ 1152 cardslot_event_throw(csc, CARDSLOT_EVENT_INSERTION_16); 1153 } else if (sockstate & CB_SOCKET_STAT_CB) { 1154 /* cardbus card found */ 1155 cardslot_event_throw(csc, CARDSLOT_EVENT_INSERTION_CB); 1156 } else { 1157 /* who are you? */ 1158 } 1159 } else { 1160 callout_schedule(&sc->sc_insert_ch, mstohz(100)); 1161 } 1162 } 1163 1164 #define PCCBB_PCMCIA_OFFSET 0x800 1165 static u_int8_t 1166 pccbb_pcmcia_read(struct pccbb_softc *sc, int reg) 1167 { 1168 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1169 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ); 1170 1171 return bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 1172 PCCBB_PCMCIA_OFFSET + reg); 1173 } 1174 1175 static void 1176 pccbb_pcmcia_write(struct pccbb_softc *sc, int reg, u_int8_t val) 1177 { 1178 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 1179 PCCBB_PCMCIA_OFFSET + reg, val); 1180 1181 bus_space_barrier(sc->sc_base_memt, sc->sc_base_memh, 1182 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE); 1183 } 1184 1185 /* 1186 * STATIC int pccbb_ctrl(cardbus_chipset_tag_t, int) 1187 */ 1188 STATIC int 1189 pccbb_ctrl(cardbus_chipset_tag_t ct, int command) 1190 { 1191 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1192 1193 switch (command) { 1194 case CARDBUS_CD: 1195 if (2 == pccbb_detect_card(sc)) { 1196 int retval = 0; 1197 int status = cb_detect_voltage(sc); 1198 if (PCCARD_VCC_5V & status) { 1199 retval |= CARDBUS_5V_CARD; 1200 } 1201 if (PCCARD_VCC_3V & status) { 1202 retval |= CARDBUS_3V_CARD; 1203 } 1204 if (PCCARD_VCC_XV & status) { 1205 retval |= CARDBUS_XV_CARD; 1206 } 1207 if (PCCARD_VCC_YV & status) { 1208 retval |= CARDBUS_YV_CARD; 1209 } 1210 return retval; 1211 } else { 1212 return 0; 1213 } 1214 case CARDBUS_RESET: 1215 return cb_reset(sc); 1216 case CARDBUS_IO_ENABLE: /* fallthrough */ 1217 case CARDBUS_IO_DISABLE: /* fallthrough */ 1218 case CARDBUS_MEM_ENABLE: /* fallthrough */ 1219 case CARDBUS_MEM_DISABLE: /* fallthrough */ 1220 case CARDBUS_BM_ENABLE: /* fallthrough */ 1221 case CARDBUS_BM_DISABLE: /* fallthrough */ 1222 /* XXX: I think we don't need to call this function below. */ 1223 return pccbb_cardenable(sc, command); 1224 } 1225 1226 return 0; 1227 } 1228 1229 STATIC int 1230 pccbb_power_ct(cardbus_chipset_tag_t ct, int command) 1231 { 1232 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1233 1234 return pccbb_power(sc, command); 1235 } 1236 1237 /* 1238 * STATIC int pccbb_power(cardbus_chipset_tag_t, int) 1239 * This function returns true when it succeeds and returns false when 1240 * it fails. 1241 */ 1242 STATIC int 1243 pccbb_power(struct pccbb_softc *sc, int command) 1244 { 1245 u_int32_t status, osock_ctrl, sock_ctrl, reg_ctrl; 1246 bus_space_tag_t memt = sc->sc_base_memt; 1247 bus_space_handle_t memh = sc->sc_base_memh; 1248 int on = 0, pwrcycle, times; 1249 struct timeval before, after, diff; 1250 1251 DPRINTF(("pccbb_power: %s and %s [0x%x]\n", 1252 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : 1253 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : 1254 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : 1255 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : 1256 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : 1257 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : 1258 "UNKNOWN", 1259 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : 1260 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : 1261 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : 1262 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : 1263 "UNKNOWN", command)); 1264 1265 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1266 osock_ctrl = sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL); 1267 1268 switch (command & CARDBUS_VCCMASK) { 1269 case CARDBUS_VCC_UC: 1270 break; 1271 case CARDBUS_VCC_5V: 1272 on++; 1273 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */ 1274 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1275 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; 1276 } else { 1277 aprint_error_dev(sc->sc_dev, 1278 "BAD voltage request: no 5 V card\n"); 1279 return 0; 1280 } 1281 break; 1282 case CARDBUS_VCC_3V: 1283 on++; 1284 if (CB_SOCKET_STAT_3VCARD & status) { 1285 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1286 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; 1287 } else { 1288 aprint_error_dev(sc->sc_dev, 1289 "BAD voltage request: no 3.3 V card\n"); 1290 return 0; 1291 } 1292 break; 1293 case CARDBUS_VCC_0V: 1294 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1295 break; 1296 default: 1297 return 0; /* power NEVER changed */ 1298 } 1299 1300 switch (command & CARDBUS_VPPMASK) { 1301 case CARDBUS_VPP_UC: 1302 break; 1303 case CARDBUS_VPP_0V: 1304 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1305 break; 1306 case CARDBUS_VPP_VCC: 1307 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1308 sock_ctrl |= ((sock_ctrl >> 4) & 0x07); 1309 break; 1310 case CARDBUS_VPP_12V: 1311 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1312 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; 1313 break; 1314 } 1315 aprint_debug_dev(sc->sc_dev, "osock_ctrl %#" PRIx32 1316 " sock_ctrl %#" PRIx32 "\n", osock_ctrl, sock_ctrl); 1317 1318 microtime(&before); 1319 mutex_enter(&sc->sc_pwr_mtx); 1320 pwrcycle = sc->sc_pwrcycle; 1321 1322 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1323 1324 /* 1325 * Wait as long as 200ms for a power-cycle interrupt. If 1326 * interrupts are enabled, but the socket has already 1327 * changed to the desired status, keep waiting for the 1328 * interrupt. "Consuming" the interrupt in this way keeps 1329 * the interrupt from prematurely waking some subsequent 1330 * pccbb_power call. 1331 * 1332 * XXX Not every bridge interrupts on the ->OFF transition. 1333 * XXX That's ok, we will time-out after 200ms. 1334 * 1335 * XXX The power cycle event will never happen when attaching 1336 * XXX a 16-bit card. That's ok, we will time-out after 1337 * XXX 200ms. 1338 */ 1339 for (times = 5; --times >= 0; ) { 1340 if (cold) 1341 DELAY(40 * 1000); 1342 else { 1343 (void)cv_timedwait(&sc->sc_pwr_cv, &sc->sc_pwr_mtx, 1344 mstohz(40)); 1345 if (pwrcycle == sc->sc_pwrcycle) 1346 continue; 1347 } 1348 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1349 if ((status & CB_SOCKET_STAT_PWRCYCLE) != 0 && on) 1350 break; 1351 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0 && !on) 1352 break; 1353 } 1354 mutex_exit(&sc->sc_pwr_mtx); 1355 microtime(&after); 1356 timersub(&after, &before, &diff); 1357 aprint_debug_dev(sc->sc_dev, "wait took%s %lld.%06lds\n", 1358 (on && times < 0) ? " too long" : "", (long long)diff.tv_sec, 1359 (long)diff.tv_usec); 1360 1361 /* 1362 * Ok, wait a bit longer for things to settle. 1363 */ 1364 if (on && sc->sc_chipset == CB_TOPIC95B) 1365 delay_ms(100, sc); 1366 1367 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); 1368 1369 if (on && sc->sc_chipset != CB_TOPIC95B) { 1370 if ((status & CB_SOCKET_STAT_PWRCYCLE) == 0) 1371 aprint_error_dev(sc->sc_dev, "power on failed?\n"); 1372 } 1373 1374 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */ 1375 aprint_error_dev(sc->sc_dev, 1376 "bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", 1377 sock_ctrl, status); 1378 aprint_error_dev(sc->sc_dev, "disabling socket\n"); 1379 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; 1380 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; 1381 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); 1382 status &= ~CB_SOCKET_STAT_BADVCC; 1383 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, status); 1384 printf("new status 0x%x\n", bus_space_read_4(memt, memh, 1385 CB_SOCKET_STAT)); 1386 return 0; 1387 } 1388 1389 if (sc->sc_chipset == CB_TOPIC97) { 1390 reg_ctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL); 1391 reg_ctrl &= ~TOPIC97_REG_CTRL_TESTMODE; 1392 if ((command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V) 1393 reg_ctrl &= ~TOPIC97_REG_CTRL_CLKRUN_ENA; 1394 else 1395 reg_ctrl |= TOPIC97_REG_CTRL_CLKRUN_ENA; 1396 pci_conf_write(sc->sc_pc, sc->sc_tag, TOPIC_REG_CTRL, reg_ctrl); 1397 } 1398 1399 return 1; /* power changed correctly */ 1400 } 1401 1402 /* 1403 * static int pccbb_detect_card(struct pccbb_softc *sc) 1404 * return value: 0 if no card exists. 1405 * 1 if 16-bit card exists. 1406 * 2 if cardbus card exists. 1407 */ 1408 static int 1409 pccbb_detect_card(struct pccbb_softc *sc) 1410 { 1411 bus_space_handle_t base_memh = sc->sc_base_memh; 1412 bus_space_tag_t base_memt = sc->sc_base_memt; 1413 u_int32_t sockstat = 1414 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); 1415 int retval = 0; 1416 1417 /* CD1 and CD2 asserted */ 1418 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) { 1419 /* card must be present */ 1420 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) { 1421 /* NOTACARD DEASSERTED */ 1422 if (CB_SOCKET_STAT_CB & sockstat) { 1423 /* CardBus mode */ 1424 retval = 2; 1425 } else if (CB_SOCKET_STAT_16BIT & sockstat) { 1426 /* 16-bit mode */ 1427 retval = 1; 1428 } 1429 } 1430 } 1431 return retval; 1432 } 1433 1434 /* 1435 * STATIC int cb_reset(struct pccbb_softc *sc) 1436 * This function resets CardBus card. 1437 */ 1438 STATIC int 1439 cb_reset(struct pccbb_softc *sc) 1440 { 1441 /* 1442 * Reset Assert at least 20 ms 1443 * Some machines request longer duration. 1444 */ 1445 int reset_duration = 1446 (sc->sc_chipset == CB_RX5C47X ? 400 : 50); 1447 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1448 aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr); 1449 1450 /* Reset bit Assert (bit 6 at 0x3E) */ 1451 bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT; 1452 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1453 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1454 delay_ms(reset_duration, sc); 1455 1456 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */ 1457 /* Reset bit Deassert (bit 6 at 0x3E) */ 1458 bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT); 1459 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, 1460 bcr); 1461 aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr); 1462 delay_ms(reset_duration, sc); 1463 aprint_debug("%s: end of delay\n", __func__); 1464 } 1465 /* No card found on the slot. Keep Reset. */ 1466 return 1; 1467 } 1468 1469 /* 1470 * STATIC int cb_detect_voltage(struct pccbb_softc *sc) 1471 * This function detect card Voltage. 1472 */ 1473 STATIC int 1474 cb_detect_voltage(struct pccbb_softc *sc) 1475 { 1476 u_int32_t psr; /* socket present-state reg */ 1477 bus_space_tag_t iot = sc->sc_base_memt; 1478 bus_space_handle_t ioh = sc->sc_base_memh; 1479 int vol = PCCARD_VCC_UKN; /* set 0 */ 1480 1481 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT); 1482 1483 if (0x400u & psr) { 1484 vol |= PCCARD_VCC_5V; 1485 } 1486 if (0x800u & psr) { 1487 vol |= PCCARD_VCC_3V; 1488 } 1489 1490 return vol; 1491 } 1492 1493 STATIC int 1494 cbbprint(void *aux, const char *pcic) 1495 { 1496 #if 0 1497 struct cbslot_attach_args *cba = aux; 1498 1499 if (cba->cba_slot >= 0) { 1500 aprint_normal(" slot %d", cba->cba_slot); 1501 } 1502 #endif 1503 return UNCONF; 1504 } 1505 1506 /* 1507 * STATIC int pccbb_cardenable(struct pccbb_softc *sc, int function) 1508 * This function enables and disables the card 1509 */ 1510 STATIC int 1511 pccbb_cardenable(struct pccbb_softc *sc, int function) 1512 { 1513 u_int32_t command = 1514 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 1515 1516 DPRINTF(("pccbb_cardenable:")); 1517 switch (function) { 1518 case CARDBUS_IO_ENABLE: 1519 command |= PCI_COMMAND_IO_ENABLE; 1520 break; 1521 case CARDBUS_IO_DISABLE: 1522 command &= ~PCI_COMMAND_IO_ENABLE; 1523 break; 1524 case CARDBUS_MEM_ENABLE: 1525 command |= PCI_COMMAND_MEM_ENABLE; 1526 break; 1527 case CARDBUS_MEM_DISABLE: 1528 command &= ~PCI_COMMAND_MEM_ENABLE; 1529 break; 1530 case CARDBUS_BM_ENABLE: 1531 command |= PCI_COMMAND_MASTER_ENABLE; 1532 break; 1533 case CARDBUS_BM_DISABLE: 1534 command &= ~PCI_COMMAND_MASTER_ENABLE; 1535 break; 1536 default: 1537 return 0; 1538 } 1539 1540 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); 1541 DPRINTF((" command reg 0x%x\n", command)); 1542 return 1; 1543 } 1544 1545 #if !rbus 1546 static int 1547 pccbb_io_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1548 { 1549 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1550 int basereg; 1551 int limitreg; 1552 1553 if ((win < 0) || (win > 2)) { 1554 #if defined DIAGNOSTIC 1555 printf("cardbus_io_open: window out of range %d\n", win); 1556 #endif 1557 return 0; 1558 } 1559 1560 basereg = win * 8 + PCI_CB_IOBASE0; 1561 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1562 1563 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", 1564 start, basereg, end, limitreg)); 1565 1566 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1567 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1568 return 1; 1569 } 1570 1571 /* 1572 * int pccbb_io_close(cardbus_chipset_tag_t, int) 1573 */ 1574 static int 1575 pccbb_io_close(cardbus_chipset_tag_t ct, int win) 1576 { 1577 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1578 int basereg; 1579 int limitreg; 1580 1581 if ((win < 0) || (win > 2)) { 1582 #if defined DIAGNOSTIC 1583 printf("cardbus_io_close: window out of range %d\n", win); 1584 #endif 1585 return 0; 1586 } 1587 1588 basereg = win * 8 + PCI_CB_IOBASE0; 1589 limitreg = win * 8 + PCI_CB_IOLIMIT0; 1590 1591 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1592 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1593 return 1; 1594 } 1595 1596 static int 1597 pccbb_mem_open(cardbus_chipset_tag_t ct, int win, uint32_t start, uint32_t end) 1598 { 1599 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1600 int basereg; 1601 int limitreg; 1602 1603 if ((win < 0) || (win > 2)) { 1604 #if defined DIAGNOSTIC 1605 printf("cardbus_mem_open: window out of range %d\n", win); 1606 #endif 1607 return 0; 1608 } 1609 1610 basereg = win * 8 + PCI_CB_MEMBASE0; 1611 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1612 1613 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); 1614 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); 1615 return 1; 1616 } 1617 1618 static int 1619 pccbb_mem_close(cardbus_chipset_tag_t ct, int win) 1620 { 1621 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1622 int basereg; 1623 int limitreg; 1624 1625 if ((win < 0) || (win > 2)) { 1626 #if defined DIAGNOSTIC 1627 printf("cardbus_mem_close: window out of range %d\n", win); 1628 #endif 1629 return 0; 1630 } 1631 1632 basereg = win * 8 + PCI_CB_MEMBASE0; 1633 limitreg = win * 8 + PCI_CB_MEMLIMIT0; 1634 1635 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); 1636 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); 1637 return 1; 1638 } 1639 #endif 1640 1641 /* 1642 * static void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, 1643 * int level, 1644 * int (* func)(void *), 1645 * void *arg) 1646 * 1647 * This function registers an interrupt handler at the bridge, in 1648 * order not to call the interrupt handlers of child devices when 1649 * a card-deletion interrupt occurs. 1650 * 1651 * The argument level is not used. 1652 */ 1653 static void * 1654 pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, int level, 1655 int (*func)(void *), void *arg) 1656 { 1657 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1658 1659 return pccbb_intr_establish(sc, level, func, arg); 1660 } 1661 1662 1663 /* 1664 * static void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, 1665 * void *ih) 1666 * 1667 * This function removes an interrupt handler pointed by ih. 1668 */ 1669 static void 1670 pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih) 1671 { 1672 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 1673 1674 pccbb_intr_disestablish(sc, ih); 1675 } 1676 1677 1678 void 1679 pccbb_intr_route(struct pccbb_softc *sc) 1680 { 1681 pcireg_t bcr, cbctrl; 1682 1683 /* initialize bridge intr routing */ 1684 bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1685 bcr &= ~CB_BCR_INTR_IREQ_ENABLE; 1686 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr); 1687 1688 switch (sc->sc_chipset) { 1689 case CB_TI113X: 1690 cbctrl = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1691 /* functional intr enabled */ 1692 cbctrl |= PCI113X_CBCTRL_PCI_INTR; 1693 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, cbctrl); 1694 break; 1695 default: 1696 break; 1697 } 1698 } 1699 1700 /* 1701 * static void *pccbb_intr_establish(struct pccbb_softc *sc, 1702 * int irq, 1703 * int level, 1704 * int (* func)(void *), 1705 * void *arg) 1706 * 1707 * This function registers an interrupt handler at the bridge, in 1708 * order not to call the interrupt handlers of child devices when 1709 * a card-deletion interrupt occurs. 1710 * 1711 */ 1712 static void * 1713 pccbb_intr_establish(struct pccbb_softc *sc, int level, 1714 int (*func)(void *), void *arg) 1715 { 1716 struct pccbb_intrhand_list *pil, *newpil; 1717 1718 DPRINTF(("pccbb_intr_establish start. %p\n", LIST_FIRST(&sc->sc_pil))); 1719 1720 if (LIST_EMPTY(&sc->sc_pil)) { 1721 pccbb_intr_route(sc); 1722 } 1723 1724 /* 1725 * Allocate a room for interrupt handler structure. 1726 */ 1727 if (NULL == (newpil = 1728 (struct pccbb_intrhand_list *)malloc(sizeof(struct 1729 pccbb_intrhand_list), M_DEVBUF, M_WAITOK))) { 1730 return NULL; 1731 } 1732 1733 newpil->pil_func = func; 1734 newpil->pil_arg = arg; 1735 newpil->pil_icookie = makeiplcookie(level); 1736 1737 if (LIST_EMPTY(&sc->sc_pil)) { 1738 LIST_INSERT_HEAD(&sc->sc_pil, newpil, pil_next); 1739 } else { 1740 for (pil = LIST_FIRST(&sc->sc_pil); 1741 LIST_NEXT(pil, pil_next) != NULL; 1742 pil = LIST_NEXT(pil, pil_next)); 1743 LIST_INSERT_AFTER(pil, newpil, pil_next); 1744 } 1745 1746 DPRINTF(("pccbb_intr_establish add pil. %p\n", 1747 LIST_FIRST(&sc->sc_pil))); 1748 1749 return newpil; 1750 } 1751 1752 /* 1753 * static void *pccbb_intr_disestablish(struct pccbb_softc *sc, 1754 * void *ih) 1755 * 1756 * This function removes an interrupt handler pointed by ih. ih 1757 * should be the value returned by cardbus_intr_establish() or 1758 * NULL. 1759 * 1760 * When ih is NULL, this function will do nothing. 1761 */ 1762 static void 1763 pccbb_intr_disestablish(struct pccbb_softc *sc, void *ih) 1764 { 1765 struct pccbb_intrhand_list *pil; 1766 pcireg_t reg; 1767 1768 DPRINTF(("pccbb_intr_disestablish start. %p\n", 1769 LIST_FIRST(&sc->sc_pil))); 1770 1771 if (ih == NULL) { 1772 /* intr handler is not set */ 1773 DPRINTF(("pccbb_intr_disestablish: no ih\n")); 1774 return; 1775 } 1776 1777 #ifdef DIAGNOSTIC 1778 LIST_FOREACH(pil, &sc->sc_pil, pil_next) { 1779 DPRINTF(("pccbb_intr_disestablish: pil %p\n", pil)); 1780 if (pil == ih) { 1781 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1782 break; 1783 } 1784 } 1785 if (pil == NULL) { 1786 panic("pccbb_intr_disestablish: %s cannot find pil %p", 1787 device_xname(sc->sc_dev), ih); 1788 } 1789 #endif 1790 1791 pil = (struct pccbb_intrhand_list *)ih; 1792 LIST_REMOVE(pil, pil_next); 1793 free(pil, M_DEVBUF); 1794 DPRINTF(("pccbb_intr_disestablish frees one pil\n")); 1795 1796 if (LIST_EMPTY(&sc->sc_pil)) { 1797 /* No interrupt handlers */ 1798 1799 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n")); 1800 1801 /* stop routing PCI intr */ 1802 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG); 1803 reg |= CB_BCR_INTR_IREQ_ENABLE; 1804 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, reg); 1805 1806 switch (sc->sc_chipset) { 1807 case CB_TI113X: 1808 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL); 1809 /* functional intr disabled */ 1810 reg &= ~PCI113X_CBCTRL_PCI_INTR; 1811 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg); 1812 break; 1813 default: 1814 break; 1815 } 1816 } 1817 } 1818 1819 #if defined SHOW_REGS 1820 static void 1821 cb_show_regs(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt, 1822 bus_space_handle_t memh) 1823 { 1824 int i; 1825 printf("PCI config regs:"); 1826 for (i = 0; i < 0x50; i += 4) { 1827 if (i % 16 == 0) 1828 printf("\n 0x%02x:", i); 1829 printf(" %08x", pci_conf_read(pc, tag, i)); 1830 } 1831 for (i = 0x80; i < 0xb0; i += 4) { 1832 if (i % 16 == 0) 1833 printf("\n 0x%02x:", i); 1834 printf(" %08x", pci_conf_read(pc, tag, i)); 1835 } 1836 1837 if (memh == 0) { 1838 printf("\n"); 1839 return; 1840 } 1841 1842 printf("\nsocket regs:"); 1843 for (i = 0; i <= 0x10; i += 0x04) 1844 printf(" %08x", bus_space_read_4(memt, memh, i)); 1845 printf("\nExCA regs:"); 1846 for (i = 0; i < 0x08; ++i) 1847 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i)); 1848 printf("\n"); 1849 return; 1850 } 1851 #endif 1852 1853 /* 1854 * static pcitag_t pccbb_make_tag(cardbus_chipset_tag_t cc, 1855 * int busno, int function) 1856 * This is the function to make a tag to access config space of 1857 * a CardBus Card. It works same as pci_conf_read. 1858 */ 1859 static pcitag_t 1860 pccbb_make_tag(cardbus_chipset_tag_t cc, int busno, int function) 1861 { 1862 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1863 1864 return pci_make_tag(sc->sc_pc, busno, 0, function); 1865 } 1866 1867 /* 1868 * pccbb_conf_read 1869 * 1870 * This is the function to read the config space of a CardBus card. 1871 * It works the same as pci_conf_read(9). 1872 */ 1873 static pcireg_t 1874 pccbb_conf_read(cardbus_chipset_tag_t cc, pcitag_t tag, int offset) 1875 { 1876 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1877 pcitag_t brtag = sc->sc_tag; 1878 pcireg_t reg; 1879 1880 /* 1881 * clear cardbus master abort status; it is OK to write without 1882 * reading before because all bits are r/o or w1tc 1883 */ 1884 pci_conf_write(sc->sc_pc, brtag, PCI_CBB_SECSTATUS, 1885 CBB_SECSTATUS_CBMABORT); 1886 reg = pci_conf_read(sc->sc_pc, tag, offset); 1887 /* check cardbus master abort status */ 1888 if (pci_conf_read(sc->sc_pc, brtag, PCI_CBB_SECSTATUS) 1889 & CBB_SECSTATUS_CBMABORT) 1890 return (0xffffffff); 1891 return reg; 1892 } 1893 1894 /* 1895 * pccbb_conf_write 1896 * 1897 * This is the function to write the config space of a CardBus 1898 * card. It works the same as pci_conf_write(9). 1899 */ 1900 static void 1901 pccbb_conf_write(cardbus_chipset_tag_t cc, pcitag_t tag, int reg, pcireg_t val) 1902 { 1903 struct pccbb_softc *sc = (struct pccbb_softc *)cc; 1904 1905 pci_conf_write(sc->sc_pc, tag, reg, val); 1906 } 1907 1908 #if 0 1909 STATIC int 1910 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1911 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask, 1912 int speed, int flags, 1913 bus_space_handle_t * iohp) 1914 #endif 1915 /* 1916 * STATIC int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, 1917 * bus_addr_t start, bus_size_t size, 1918 * bus_size_t align, 1919 * struct pcmcia_io_handle *pcihp 1920 * 1921 * This function only allocates I/O region for pccard. This function 1922 * never maps the allocated region to pccard I/O area. 1923 * 1924 * XXX: The interface of this function is not very good, I believe. 1925 */ 1926 STATIC int 1927 pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 1928 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 1929 { 1930 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 1931 bus_addr_t ioaddr; 1932 int flags = 0; 1933 bus_space_tag_t iot; 1934 bus_space_handle_t ioh; 1935 bus_addr_t mask; 1936 #if rbus 1937 rbus_tag_t rb; 1938 #endif 1939 if (align == 0) { 1940 align = size; /* XXX: funny??? */ 1941 } 1942 1943 if (start != 0) { 1944 /* XXX: assume all card decode lower 10 bits by its hardware */ 1945 mask = 0x3ff; 1946 /* enforce to use only masked address */ 1947 start &= mask; 1948 } else { 1949 /* 1950 * calculate mask: 1951 * 1. get the most significant bit of size (call it msb). 1952 * 2. compare msb with the value of size. 1953 * 3. if size is larger, shift msb left once. 1954 * 4. obtain mask value to decrement msb. 1955 */ 1956 bus_size_t size_tmp = size; 1957 int shifts = 0; 1958 1959 mask = 1; 1960 while (size_tmp) { 1961 ++shifts; 1962 size_tmp >>= 1; 1963 } 1964 mask = (1 << shifts); 1965 if (mask < size) { 1966 mask <<= 1; 1967 } 1968 --mask; 1969 } 1970 1971 /* 1972 * Allocate some arbitrary I/O space. 1973 */ 1974 1975 iot = sc->sc_iot; 1976 1977 #if rbus 1978 rb = sc->sc_rbus_iot; 1979 if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) { 1980 return 1; 1981 } 1982 DPRINTF(("pccbb_pcmcia_io_alloc alloc port 0x%lx+0x%lx\n", 1983 (u_long) ioaddr, (u_long) size)); 1984 #else 1985 if (start) { 1986 ioaddr = start; 1987 if (bus_space_map(iot, start, size, 0, &ioh)) { 1988 return 1; 1989 } 1990 DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n", 1991 (u_long) ioaddr, (u_long) size)); 1992 } else { 1993 flags |= PCMCIA_IO_ALLOCATED; 1994 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ , 1995 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */ 1996 size, align, 0, 0, &ioaddr, &ioh)) { 1997 /* No room be able to be get. */ 1998 return 1; 1999 } 2000 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n", 2001 (u_long) ioaddr, (u_long) size)); 2002 } 2003 #endif 2004 2005 pcihp->iot = iot; 2006 pcihp->ioh = ioh; 2007 pcihp->addr = ioaddr; 2008 pcihp->size = size; 2009 pcihp->flags = flags; 2010 2011 return 0; 2012 } 2013 2014 /* 2015 * STATIC int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2016 * struct pcmcia_io_handle *pcihp) 2017 * 2018 * This function only frees I/O region for pccard. 2019 * 2020 * XXX: The interface of this function is not very good, I believe. 2021 */ 2022 void 2023 pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch, 2024 struct pcmcia_io_handle *pcihp) 2025 { 2026 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2027 #if !rbus 2028 bus_space_tag_t iot = pcihp->iot; 2029 #endif 2030 bus_space_handle_t ioh = pcihp->ioh; 2031 bus_size_t size = pcihp->size; 2032 2033 #if rbus 2034 rbus_tag_t rb = sc->sc_rbus_iot; 2035 2036 rbus_space_free(rb, ioh, size, NULL); 2037 #else 2038 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 2039 bus_space_free(iot, ioh, size); 2040 else 2041 bus_space_unmap(iot, ioh, size); 2042 #endif 2043 } 2044 2045 /* 2046 * STATIC int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, 2047 * bus_addr_t offset, bus_size_t size, 2048 * struct pcmcia_io_handle *pcihp, 2049 * int *windowp) 2050 * 2051 * This function maps the allocated I/O region to pccard. This function 2052 * never allocates any I/O region for pccard I/O area. I don't 2053 * understand why the original authors of pcmciabus separated alloc and 2054 * map. I believe the two must be unite. 2055 * 2056 * XXX: no wait timing control? 2057 */ 2058 int 2059 pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 2060 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 2061 { 2062 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2063 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2064 bus_addr_t ioaddr = pcihp->addr + offset; 2065 int i, win; 2066 #if defined CBB_DEBUG 2067 static const char *width_names[] = { "dynamic", "io8", "io16" }; 2068 #endif 2069 2070 /* Sanity check I/O handle. */ 2071 2072 if (!bus_space_is_equal(sc->sc_iot, pcihp->iot)) { 2073 panic("pccbb_pcmcia_io_map iot is bogus"); 2074 } 2075 2076 /* XXX Sanity check offset/size. */ 2077 2078 win = -1; 2079 for (i = 0; i < PCIC_IO_WINS; i++) { 2080 if ((ph->ioalloc & (1 << i)) == 0) { 2081 win = i; 2082 ph->ioalloc |= (1 << i); 2083 break; 2084 } 2085 } 2086 2087 if (win == -1) { 2088 return 1; 2089 } 2090 2091 *windowp = win; 2092 2093 /* XXX this is pretty gross */ 2094 2095 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n", 2096 win, width_names[width], (u_long) ioaddr, (u_long) size)); 2097 2098 /* XXX wtf is this doing here? */ 2099 2100 #if 0 2101 printf(" port 0x%lx", (u_long) ioaddr); 2102 if (size > 1) { 2103 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 2104 } 2105 #endif 2106 2107 ph->io[win].addr = ioaddr; 2108 ph->io[win].size = size; 2109 ph->io[win].width = width; 2110 2111 /* actual dirty register-value changing in the function below. */ 2112 pccbb_pcmcia_do_io_map(sc, win); 2113 2114 return 0; 2115 } 2116 2117 /* 2118 * STATIC void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win) 2119 * 2120 * This function changes register-value to map I/O region for pccard. 2121 */ 2122 static void 2123 pccbb_pcmcia_do_io_map(struct pccbb_softc *sc, int win) 2124 { 2125 static u_int8_t pcic_iowidth[3] = { 2126 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 2127 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2128 PCIC_IOCTL_IO0_DATASIZE_8BIT, 2129 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 2130 PCIC_IOCTL_IO0_DATASIZE_16BIT, 2131 }; 2132 2133 #define PCIC_SIA_START_LOW 0 2134 #define PCIC_SIA_START_HIGH 1 2135 #define PCIC_SIA_STOP_LOW 2 2136 #define PCIC_SIA_STOP_HIGH 3 2137 2138 int regbase_win = 0x8 + win * 0x04; 2139 u_int8_t ioctl, enable; 2140 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2141 2142 DPRINTF(("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx " 2143 "width %d\n", win, (unsigned long)ph->io[win].addr, 2144 (unsigned long)ph->io[win].size, ph->io[win].width * 8)); 2145 2146 Pcic_write(sc, regbase_win + PCIC_SIA_START_LOW, 2147 ph->io[win].addr & 0xff); 2148 Pcic_write(sc, regbase_win + PCIC_SIA_START_HIGH, 2149 (ph->io[win].addr >> 8) & 0xff); 2150 2151 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_LOW, 2152 (ph->io[win].addr + ph->io[win].size - 1) & 0xff); 2153 Pcic_write(sc, regbase_win + PCIC_SIA_STOP_HIGH, 2154 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff); 2155 2156 ioctl = Pcic_read(sc, PCIC_IOCTL); 2157 enable = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2158 switch (win) { 2159 case 0: 2160 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 2161 PCIC_IOCTL_IO0_IOCS16SRC_MASK | 2162 PCIC_IOCTL_IO0_DATASIZE_MASK); 2163 ioctl |= pcic_iowidth[ph->io[win].width]; 2164 enable |= PCIC_ADDRWIN_ENABLE_IO0; 2165 break; 2166 case 1: 2167 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 2168 PCIC_IOCTL_IO1_IOCS16SRC_MASK | 2169 PCIC_IOCTL_IO1_DATASIZE_MASK); 2170 ioctl |= (pcic_iowidth[ph->io[win].width] << 4); 2171 enable |= PCIC_ADDRWIN_ENABLE_IO1; 2172 break; 2173 } 2174 Pcic_write(sc, PCIC_IOCTL, ioctl); 2175 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, enable); 2176 #if defined(CBB_DEBUG) 2177 { 2178 u_int8_t start_low = 2179 Pcic_read(sc, regbase_win + PCIC_SIA_START_LOW); 2180 u_int8_t start_high = 2181 Pcic_read(sc, regbase_win + PCIC_SIA_START_HIGH); 2182 u_int8_t stop_low = 2183 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_LOW); 2184 u_int8_t stop_high = 2185 Pcic_read(sc, regbase_win + PCIC_SIA_STOP_HIGH); 2186 printf("pccbb_pcmcia_do_io_map start %02x %02x, " 2187 "stop %02x %02x, ioctl %02x enable %02x\n", 2188 start_low, start_high, stop_low, stop_high, ioctl, enable); 2189 } 2190 #endif 2191 } 2192 2193 /* 2194 * STATIC void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win) 2195 * 2196 * This function unmaps I/O region. No return value. 2197 */ 2198 STATIC void 2199 pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t pch, int win) 2200 { 2201 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2202 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2203 int reg; 2204 2205 if (win >= PCIC_IO_WINS || win < 0) { 2206 panic("pccbb_pcmcia_io_unmap: window out of range"); 2207 } 2208 2209 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2210 switch (win) { 2211 case 0: 2212 reg &= ~PCIC_ADDRWIN_ENABLE_IO0; 2213 break; 2214 case 1: 2215 reg &= ~PCIC_ADDRWIN_ENABLE_IO1; 2216 break; 2217 } 2218 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2219 2220 ph->ioalloc &= ~(1 << win); 2221 } 2222 2223 static int 2224 pccbb_pcmcia_wait_ready(struct pccbb_softc *sc) 2225 { 2226 u_int8_t stat; 2227 int i; 2228 2229 /* wait an initial 10ms for quick cards */ 2230 stat = Pcic_read(sc, PCIC_IF_STATUS); 2231 if (stat & PCIC_IF_STATUS_READY) 2232 return (0); 2233 pccbb_pcmcia_delay(sc, 10, "pccwr0"); 2234 for (i = 0; i < 50; i++) { 2235 stat = Pcic_read(sc, PCIC_IF_STATUS); 2236 if (stat & PCIC_IF_STATUS_READY) 2237 return (0); 2238 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 2239 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2240 return (ENXIO); 2241 /* wait .1s (100ms) each iteration now */ 2242 pccbb_pcmcia_delay(sc, 100, "pccwr1"); 2243 } 2244 2245 printf("pccbb_pcmcia_wait_ready: ready never happened, status=%02x\n", stat); 2246 return (EWOULDBLOCK); 2247 } 2248 2249 /* 2250 * Perform long (msec order) delay. timo is in milliseconds. 2251 */ 2252 static void 2253 pccbb_pcmcia_delay(struct pccbb_softc *sc, int timo, const char *wmesg) 2254 { 2255 #ifdef DIAGNOSTIC 2256 if (timo <= 0) 2257 panic("pccbb_pcmcia_delay: called with timeout %d", timo); 2258 if (!curlwp) 2259 panic("pccbb_pcmcia_delay: called in interrupt context"); 2260 #endif 2261 DPRINTF(("pccbb_pcmcia_delay: \"%s\", sleep %d ms\n", wmesg, timo)); 2262 kpause(wmesg, false, max(mstohz(timo), 1), NULL); 2263 } 2264 2265 /* 2266 * STATIC void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2267 * 2268 * This function enables the card. All information is stored in 2269 * the first argument, pcmcia_chipset_handle_t. 2270 */ 2271 STATIC void 2272 pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch) 2273 { 2274 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2275 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2276 pcireg_t spsr; 2277 int voltage; 2278 int win; 2279 u_int8_t power, intr; 2280 #ifdef DIAGNOSTIC 2281 int reg; 2282 #endif 2283 2284 /* this bit is mostly stolen from pcic_attach_card */ 2285 2286 DPRINTF(("pccbb_pcmcia_socket_enable: ")); 2287 2288 /* get card Vcc info */ 2289 spsr = 2290 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, 2291 CB_SOCKET_STAT); 2292 if (spsr & CB_SOCKET_STAT_5VCARD) { 2293 DPRINTF(("5V card\n")); 2294 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC; 2295 } else if (spsr & CB_SOCKET_STAT_3VCARD) { 2296 DPRINTF(("3V card\n")); 2297 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC; 2298 } else { 2299 DPRINTF(("?V card, 0x%x\n", spsr)); /* XXX */ 2300 return; 2301 } 2302 2303 /* disable interrupts; assert RESET */ 2304 intr = Pcic_read(sc, PCIC_INTR); 2305 intr &= PCIC_INTR_ENABLE; 2306 Pcic_write(sc, PCIC_INTR, intr); 2307 2308 /* zero out the address windows */ 2309 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2310 2311 /* power down the socket to reset it, clear the card reset pin */ 2312 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2313 2314 /* power off; assert output enable bit */ 2315 power = PCIC_PWRCTL_OE; 2316 Pcic_write(sc, PCIC_PWRCTL, power); 2317 2318 /* power up the socket */ 2319 if (pccbb_power(sc, voltage) == 0) 2320 return; 2321 2322 /* 2323 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 2324 * Vcc Rising Time (Tpr) = 100ms (handled in pccbb_power() above) 2325 * RESET Width (Th (Hi-z RESET)) = 1ms 2326 * RESET Width (Tw (RESET)) = 10us 2327 * 2328 * some machines require some more time to be settled 2329 * for example old toshiba topic bridges! 2330 * (100ms is added here). 2331 */ 2332 pccbb_pcmcia_delay(sc, 200 + 1, "pccen1"); 2333 2334 /* negate RESET */ 2335 intr |= PCIC_INTR_RESET; 2336 Pcic_write(sc, PCIC_INTR, intr); 2337 2338 /* 2339 * RESET Setup Time (Tsu (RESET)) = 20ms 2340 */ 2341 pccbb_pcmcia_delay(sc, 20, "pccen2"); 2342 2343 #ifdef DIAGNOSTIC 2344 reg = Pcic_read(sc, PCIC_IF_STATUS); 2345 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 2346 printf("pccbb_pcmcia_socket_enable: no power, status=%x\n", reg); 2347 #endif 2348 2349 /* wait for the chip to finish initializing */ 2350 if (pccbb_pcmcia_wait_ready(sc)) { 2351 #ifdef DIAGNOSTIC 2352 printf("pccbb_pcmcia_socket_enable: never became ready\n"); 2353 #endif 2354 /* XXX return a failure status?? */ 2355 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2356 Pcic_write(sc, PCIC_PWRCTL, 0); 2357 return; 2358 } 2359 2360 /* reinstall all the memory and io mappings */ 2361 for (win = 0; win < PCIC_MEM_WINS; ++win) 2362 if (ph->memalloc & (1 << win)) 2363 pccbb_pcmcia_do_mem_map(sc, win); 2364 for (win = 0; win < PCIC_IO_WINS; ++win) 2365 if (ph->ioalloc & (1 << win)) 2366 pccbb_pcmcia_do_io_map(sc, win); 2367 } 2368 2369 /* 2370 * STATIC void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph) 2371 * 2372 * This function disables the card. All information is stored in 2373 * the first argument, pcmcia_chipset_handle_t. 2374 */ 2375 STATIC void 2376 pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t pch) 2377 { 2378 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2379 u_int8_t intr; 2380 2381 DPRINTF(("pccbb_pcmcia_socket_disable\n")); 2382 2383 /* disable interrupts; assert RESET */ 2384 intr = Pcic_read(sc, PCIC_INTR); 2385 intr &= PCIC_INTR_ENABLE; 2386 Pcic_write(sc, PCIC_INTR, intr); 2387 2388 /* zero out the address windows */ 2389 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, 0); 2390 2391 /* power down the socket to reset it, clear the card reset pin */ 2392 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); 2393 2394 /* disable socket: negate output enable bit and power off */ 2395 Pcic_write(sc, PCIC_PWRCTL, 0); 2396 2397 /* 2398 * Vcc Falling Time (Tpf) = 300ms 2399 */ 2400 pccbb_pcmcia_delay(sc, 300, "pccwr1"); 2401 } 2402 2403 STATIC void 2404 pccbb_pcmcia_socket_settype(pcmcia_chipset_handle_t pch, int type) 2405 { 2406 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2407 u_int8_t intr; 2408 2409 /* set the card type */ 2410 2411 intr = Pcic_read(sc, PCIC_INTR); 2412 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 2413 if (type == PCMCIA_IFTYPE_IO) 2414 intr |= PCIC_INTR_CARDTYPE_IO; 2415 else 2416 intr |= PCIC_INTR_CARDTYPE_MEM; 2417 Pcic_write(sc, PCIC_INTR, intr); 2418 2419 DPRINTF(("%s: pccbb_pcmcia_socket_settype type %s %02x\n", 2420 device_xname(sc->sc_dev), 2421 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 2422 } 2423 2424 /* 2425 * STATIC int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph) 2426 * 2427 * This function detects whether a card is in the slot or not. 2428 * If a card is inserted, return 1. Otherwise, return 0. 2429 */ 2430 STATIC int 2431 pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch) 2432 { 2433 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2434 2435 DPRINTF(("pccbb_pcmcia_card_detect\n")); 2436 return pccbb_detect_card(sc) == 1 ? 1 : 0; 2437 } 2438 2439 #if 0 2440 STATIC int 2441 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2442 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags, 2443 bus_space_tag_t * memtp bus_space_handle_t * memhp) 2444 #endif 2445 /* 2446 * STATIC int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, 2447 * bus_size_t size, 2448 * struct pcmcia_mem_handle *pcmhp) 2449 * 2450 * This function only allocates memory region for pccard. This 2451 * function never maps the allocated region to pccard memory area. 2452 * 2453 * XXX: Why the argument of start address is not in? 2454 */ 2455 STATIC int 2456 pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 2457 struct pcmcia_mem_handle *pcmhp) 2458 { 2459 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2460 bus_space_handle_t memh; 2461 bus_addr_t addr; 2462 bus_size_t sizepg; 2463 #if rbus 2464 rbus_tag_t rb; 2465 #endif 2466 2467 /* Check that the card is still there. */ 2468 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2469 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2470 return 1; 2471 2472 /* out of sc->memh, allocate as many pages as necessary */ 2473 2474 /* convert size to PCIC pages */ 2475 /* 2476 * This is not enough; when the requested region is on the page 2477 * boundaries, this may calculate wrong result. 2478 */ 2479 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE; 2480 #if 0 2481 if (sizepg > PCIC_MAX_MEM_PAGES) { 2482 return 1; 2483 } 2484 #endif 2485 2486 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) { 2487 return 1; 2488 } 2489 2490 addr = 0; /* XXX gcc -Wuninitialized */ 2491 2492 #if rbus 2493 rb = sc->sc_rbus_memt; 2494 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE, 2495 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0, 2496 &addr, &memh)) { 2497 return 1; 2498 } 2499 #else 2500 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end, 2501 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE, 2502 0, /* boundary */ 2503 0, /* flags */ 2504 &addr, &memh)) { 2505 return 1; 2506 } 2507 #endif 2508 2509 DPRINTF(("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, " 2510 "realsize 0x%lx\n", (unsigned long)addr, (unsigned long)size, 2511 (unsigned long)sizepg * PCIC_MEM_PAGESIZE)); 2512 2513 pcmhp->memt = sc->sc_memt; 2514 pcmhp->memh = memh; 2515 pcmhp->addr = addr; 2516 pcmhp->size = size; 2517 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 2518 /* What is mhandle? I feel it is very dirty and it must go trush. */ 2519 pcmhp->mhandle = 0; 2520 /* No offset??? Funny. */ 2521 2522 return 0; 2523 } 2524 2525 /* 2526 * STATIC void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2527 * struct pcmcia_mem_handle *pcmhp) 2528 * 2529 * This function release the memory space allocated by the function 2530 * pccbb_pcmcia_mem_alloc(). 2531 */ 2532 STATIC void 2533 pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch, 2534 struct pcmcia_mem_handle *pcmhp) 2535 { 2536 #if rbus 2537 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2538 2539 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL); 2540 #else 2541 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize); 2542 #endif 2543 } 2544 2545 /* 2546 * STATIC void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win) 2547 * 2548 * This function release the memory space allocated by the function 2549 * pccbb_pcmcia_mem_alloc(). 2550 */ 2551 STATIC void 2552 pccbb_pcmcia_do_mem_map(struct pccbb_softc *sc, int win) 2553 { 2554 int regbase_win; 2555 bus_addr_t phys_addr; 2556 bus_addr_t phys_end; 2557 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2558 2559 #define PCIC_SMM_START_LOW 0 2560 #define PCIC_SMM_START_HIGH 1 2561 #define PCIC_SMM_STOP_LOW 2 2562 #define PCIC_SMM_STOP_HIGH 3 2563 #define PCIC_CMA_LOW 4 2564 #define PCIC_CMA_HIGH 5 2565 2566 u_int8_t start_low, start_high = 0; 2567 u_int8_t stop_low, stop_high; 2568 u_int8_t off_low, off_high; 2569 u_int8_t mem_window; 2570 int reg; 2571 2572 int kind = ph->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 2573 int mem8 = 2574 (ph->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 2575 || (kind == PCMCIA_MEM_ATTR); 2576 2577 regbase_win = 0x10 + win * 0x08; 2578 2579 phys_addr = ph->mem[win].addr; 2580 phys_end = phys_addr + ph->mem[win].size; 2581 2582 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n", 2583 (unsigned long)phys_addr, (unsigned long)phys_end, 2584 (unsigned long)ph->mem[win].offset)); 2585 2586 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT 2587 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8) 2588 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12) 2589 2590 /* bit 19:12 */ 2591 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2592 /* bit 23:20 and bit 7 on */ 2593 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2594 |(mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT); 2595 /* bit 31:24, for 32-bit address */ 2596 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff; 2597 2598 Pcic_write(sc, regbase_win + PCIC_SMM_START_LOW, start_low); 2599 Pcic_write(sc, regbase_win + PCIC_SMM_START_HIGH, start_high); 2600 2601 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2602 Pcic_write(sc, 0x40 + win, mem_window); 2603 } 2604 2605 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff; 2606 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f) 2607 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */ 2608 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */ 2609 2610 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_LOW, stop_low); 2611 Pcic_write(sc, regbase_win + PCIC_SMM_STOP_HIGH, stop_high); 2612 2613 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff; 2614 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) 2615 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) 2616 | ((kind == PCMCIA_MEM_ATTR) ? 2617 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0); 2618 2619 Pcic_write(sc, regbase_win + PCIC_CMA_LOW, off_low); 2620 Pcic_write(sc, regbase_win + PCIC_CMA_HIGH, off_high); 2621 2622 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2623 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16); 2624 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2625 2626 #if defined(CBB_DEBUG) 2627 { 2628 int r1, r2, r3, r4, r5, r6, r7 = 0; 2629 2630 r1 = Pcic_read(sc, regbase_win + PCIC_SMM_START_LOW); 2631 r2 = Pcic_read(sc, regbase_win + PCIC_SMM_START_HIGH); 2632 r3 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_LOW); 2633 r4 = Pcic_read(sc, regbase_win + PCIC_SMM_STOP_HIGH); 2634 r5 = Pcic_read(sc, regbase_win + PCIC_CMA_LOW); 2635 r6 = Pcic_read(sc, regbase_win + PCIC_CMA_HIGH); 2636 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2637 r7 = Pcic_read(sc, 0x40 + win); 2638 } 2639 2640 printf("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x " 2641 "%02x%02x", win, r1, r2, r3, r4, r5, r6); 2642 if (sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) { 2643 printf(" %02x", r7); 2644 } 2645 printf("\n"); 2646 } 2647 #endif 2648 } 2649 2650 /* 2651 * STATIC int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2652 * bus_addr_t card_addr, bus_size_t size, 2653 * struct pcmcia_mem_handle *pcmhp, 2654 * bus_addr_t *offsetp, int *windowp) 2655 * 2656 * This function maps memory space allocated by the function 2657 * pccbb_pcmcia_mem_alloc(). 2658 */ 2659 STATIC int 2660 pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind, 2661 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 2662 bus_size_t *offsetp, int *windowp) 2663 { 2664 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2665 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2666 bus_addr_t busaddr; 2667 long card_offset; 2668 int win; 2669 2670 /* Check that the card is still there. */ 2671 if ((Pcic_read(sc, PCIC_IF_STATUS) & PCIC_IF_STATUS_CARDDETECT_MASK) != 2672 PCIC_IF_STATUS_CARDDETECT_PRESENT) 2673 return 1; 2674 2675 for (win = 0; win < PCIC_MEM_WINS; ++win) { 2676 if ((ph->memalloc & (1 << win)) == 0) { 2677 ph->memalloc |= (1 << win); 2678 break; 2679 } 2680 } 2681 2682 if (win == PCIC_MEM_WINS) { 2683 return 1; 2684 } 2685 2686 *windowp = win; 2687 2688 /* XXX this is pretty gross */ 2689 2690 if (!bus_space_is_equal(sc->sc_memt, pcmhp->memt)) { 2691 panic("pccbb_pcmcia_mem_map memt is bogus"); 2692 } 2693 2694 busaddr = pcmhp->addr; 2695 2696 /* 2697 * compute the address offset to the pcmcia address space for the 2698 * pcic. this is intentionally signed. The masks and shifts below 2699 * will cause TRT to happen in the pcic registers. Deal with making 2700 * sure the address is aligned, and return the alignment offset. 2701 */ 2702 2703 *offsetp = card_addr % PCIC_MEM_PAGESIZE; 2704 card_addr -= *offsetp; 2705 2706 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr " 2707 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 2708 (u_long) card_addr)); 2709 2710 /* 2711 * include the offset in the size, and decrement size by one, since 2712 * the hw wants start/stop 2713 */ 2714 size += *offsetp - 1; 2715 2716 card_offset = (((long)card_addr) - ((long)busaddr)); 2717 2718 ph->mem[win].addr = busaddr; 2719 ph->mem[win].size = size; 2720 ph->mem[win].offset = card_offset; 2721 ph->mem[win].kind = kind; 2722 2723 pccbb_pcmcia_do_mem_map(sc, win); 2724 2725 return 0; 2726 } 2727 2728 /* 2729 * STATIC int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, 2730 * int window) 2731 * 2732 * This function unmaps memory space which mapped by the function 2733 * pccbb_pcmcia_mem_map(). 2734 */ 2735 STATIC void 2736 pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch, int window) 2737 { 2738 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2739 struct pcic_handle *ph = &sc->sc_pcmcia_h; 2740 int reg; 2741 2742 if (window >= PCIC_MEM_WINS) { 2743 panic("pccbb_pcmcia_mem_unmap: window out of range"); 2744 } 2745 2746 reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE); 2747 reg &= ~(1 << window); 2748 Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg); 2749 2750 ph->memalloc &= ~(1 << window); 2751 } 2752 2753 /* 2754 * STATIC void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2755 * struct pcmcia_function *pf, 2756 * int ipl, 2757 * int (*func)(void *), 2758 * void *arg); 2759 * 2760 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line. 2761 */ 2762 STATIC void * 2763 pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch, 2764 struct pcmcia_function *pf, int ipl, int (*func)(void *), void *arg) 2765 { 2766 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2767 2768 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2769 /* what should I do? */ 2770 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) { 2771 DPRINTF(("%s does not provide edge nor pulse " 2772 "interrupt\n", device_xname(sc->sc_dev))); 2773 return NULL; 2774 } 2775 /* 2776 * XXX Noooooo! The interrupt flag must set properly!! 2777 * dumb pcmcia driver!! 2778 */ 2779 } 2780 2781 return pccbb_intr_establish(sc, ipl, func, arg); 2782 } 2783 2784 /* 2785 * STATIC void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, 2786 * void *ih) 2787 * 2788 * This function disables PC-Card interrupt. 2789 */ 2790 STATIC void 2791 pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 2792 { 2793 struct pccbb_softc *sc = (struct pccbb_softc *)pch; 2794 2795 pccbb_intr_disestablish(sc, ih); 2796 } 2797 2798 #if rbus 2799 /* 2800 * static int 2801 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2802 * bus_addr_t addr, bus_size_t size, 2803 * bus_addr_t mask, bus_size_t align, 2804 * int flags, bus_addr_t *addrp; 2805 * bus_space_handle_t *bshp) 2806 * 2807 * This function allocates a portion of memory or io space for 2808 * clients. This function is called from CardBus card drivers. 2809 */ 2810 static int 2811 pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2812 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, 2813 int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 2814 { 2815 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2816 2817 DPRINTF(("pccbb_rbus_cb_space_alloc: addr 0x%lx, size 0x%lx, " 2818 "mask 0x%lx, align 0x%lx\n", (unsigned long)addr, 2819 (unsigned long)size, (unsigned long)mask, (unsigned long)align)); 2820 2821 if (align == 0) { 2822 align = size; 2823 } 2824 2825 if (bus_space_is_equal(rb->rb_bt, sc->sc_memt)) { 2826 if (align < 16) { 2827 return 1; 2828 } 2829 /* 2830 * XXX: align more than 0x1000 to avoid overwrapping 2831 * memory windows for two or more devices. 0x1000 2832 * means memory window's granularity. 2833 * 2834 * Two or more devices should be able to share same 2835 * memory window region. However, overrapping memory 2836 * window is not good because some devices, such as 2837 * 3Com 3C575[BC], have a broken address decoder and 2838 * intrude other's memory region. 2839 */ 2840 if (align < 0x1000) { 2841 align = 0x1000; 2842 } 2843 } else if (bus_space_is_equal(rb->rb_bt, sc->sc_iot)) { 2844 if (align < 4) { 2845 return 1; 2846 } 2847 /* XXX: hack for avoiding ISA image */ 2848 if (mask < 0x0100) { 2849 mask = 0x3ff; 2850 addr = 0x300; 2851 } 2852 2853 } else { 2854 DPRINTF(("pccbb_rbus_cb_space_alloc: Bus space tag 0x%lx is " 2855 "NOT used. io: 0x%lx, mem: 0x%lx\n", 2856 (unsigned long)rb->rb_bt, (unsigned long)sc->sc_iot, 2857 (unsigned long)sc->sc_memt)); 2858 return 1; 2859 /* XXX: panic here? */ 2860 } 2861 2862 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) { 2863 aprint_normal_dev(sc->sc_dev, "<rbus> no bus space\n"); 2864 return 1; 2865 } 2866 2867 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0); 2868 2869 return 0; 2870 } 2871 2872 /* 2873 * static int 2874 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb, 2875 * bus_space_handle_t *bshp, bus_size_t size); 2876 * 2877 * This function is called from CardBus card drivers. 2878 */ 2879 static int 2880 pccbb_rbus_cb_space_free(cardbus_chipset_tag_t ct, rbus_tag_t rb, 2881 bus_space_handle_t bsh, bus_size_t size) 2882 { 2883 struct pccbb_softc *sc = (struct pccbb_softc *)ct; 2884 bus_space_tag_t bt = rb->rb_bt; 2885 2886 pccbb_close_win(sc, bt, bsh, size); 2887 2888 if (bus_space_is_equal(bt, sc->sc_memt)) { 2889 } else if (bus_space_is_equal(bt, sc->sc_iot)) { 2890 } else { 2891 return 1; 2892 /* XXX: panic here? */ 2893 } 2894 2895 return rbus_space_free(rb, bsh, size, NULL); 2896 } 2897 #endif /* rbus */ 2898 2899 #if rbus 2900 2901 static int 2902 pccbb_open_win(struct pccbb_softc *sc, bus_space_tag_t bst, bus_addr_t addr, 2903 bus_size_t size, bus_space_handle_t bsh, int flags) 2904 { 2905 struct pccbb_win_chain_head *head; 2906 bus_addr_t align; 2907 2908 head = &sc->sc_iowindow; 2909 align = 0x04; 2910 if (bus_space_is_equal(sc->sc_memt, bst)) { 2911 head = &sc->sc_memwindow; 2912 align = 0x1000; 2913 DPRINTF(("using memory window, 0x%lx 0x%lx 0x%lx\n\n", 2914 (unsigned long)sc->sc_iot, (unsigned long)sc->sc_memt, 2915 (unsigned long)bst)); 2916 } 2917 2918 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) { 2919 aprint_error_dev(sc->sc_dev, 2920 "pccbb_open_win: %s winlist insert failed\n", 2921 (head == &sc->sc_memwindow) ? "mem" : "io"); 2922 } 2923 pccbb_winset(align, sc, bst); 2924 2925 return 0; 2926 } 2927 2928 static int 2929 pccbb_close_win(struct pccbb_softc *sc, bus_space_tag_t bst, 2930 bus_space_handle_t bsh, bus_size_t size) 2931 { 2932 struct pccbb_win_chain_head *head; 2933 bus_addr_t align; 2934 2935 head = &sc->sc_iowindow; 2936 align = 0x04; 2937 if (bus_space_is_equal(sc->sc_memt, bst)) { 2938 head = &sc->sc_memwindow; 2939 align = 0x1000; 2940 } 2941 2942 if (pccbb_winlist_delete(head, bsh, size)) { 2943 aprint_error_dev(sc->sc_dev, 2944 "pccbb_close_win: %s winlist delete failed\n", 2945 (head == &sc->sc_memwindow) ? "mem" : "io"); 2946 } 2947 pccbb_winset(align, sc, bst); 2948 2949 return 0; 2950 } 2951 2952 static int 2953 pccbb_winlist_insert(struct pccbb_win_chain_head *head, bus_addr_t start, 2954 bus_size_t size, bus_space_handle_t bsh, int flags) 2955 { 2956 struct pccbb_win_chain *chainp, *elem; 2957 2958 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF, 2959 M_NOWAIT)) == NULL) 2960 return (1); /* fail */ 2961 2962 elem->wc_start = start; 2963 elem->wc_end = start + (size - 1); 2964 elem->wc_handle = bsh; 2965 elem->wc_flags = flags; 2966 2967 TAILQ_FOREACH(chainp, head, wc_list) { 2968 if (chainp->wc_end >= start) 2969 break; 2970 } 2971 if (chainp != NULL) 2972 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list); 2973 else 2974 TAILQ_INSERT_TAIL(head, elem, wc_list); 2975 return (0); 2976 } 2977 2978 static int 2979 pccbb_winlist_delete(struct pccbb_win_chain_head *head, bus_space_handle_t bsh, 2980 bus_size_t size) 2981 { 2982 struct pccbb_win_chain *chainp; 2983 2984 TAILQ_FOREACH(chainp, head, wc_list) { 2985 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)) == 0) 2986 break; 2987 } 2988 if (chainp == NULL) 2989 return 1; /* fail: no candidate to remove */ 2990 2991 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) { 2992 printf("pccbb_winlist_delete: window 0x%lx size " 2993 "inconsistent: 0x%lx, 0x%lx\n", 2994 (unsigned long)chainp->wc_start, 2995 (unsigned long)(chainp->wc_end - chainp->wc_start), 2996 (unsigned long)(size - 1)); 2997 return 1; 2998 } 2999 3000 TAILQ_REMOVE(head, chainp, wc_list); 3001 free(chainp, M_DEVBUF); 3002 3003 return 0; 3004 } 3005 3006 static void 3007 pccbb_winset(bus_addr_t align, struct pccbb_softc *sc, bus_space_tag_t bst) 3008 { 3009 pci_chipset_tag_t pc; 3010 pcitag_t tag; 3011 bus_addr_t mask = ~(align - 1); 3012 struct { 3013 pcireg_t win_start; 3014 pcireg_t win_limit; 3015 int win_flags; 3016 } win[2]; 3017 struct pccbb_win_chain *chainp; 3018 int offs; 3019 3020 win[0].win_start = win[1].win_start = 0xffffffff; 3021 win[0].win_limit = win[1].win_limit = 0; 3022 win[0].win_flags = win[1].win_flags = 0; 3023 3024 chainp = TAILQ_FIRST(&sc->sc_iowindow); 3025 offs = PCI_CB_IOBASE0; 3026 if (bus_space_is_equal(sc->sc_memt, bst)) { 3027 chainp = TAILQ_FIRST(&sc->sc_memwindow); 3028 offs = PCI_CB_MEMBASE0; 3029 } 3030 3031 if (chainp != NULL) { 3032 win[0].win_start = chainp->wc_start & mask; 3033 win[0].win_limit = chainp->wc_end & mask; 3034 win[0].win_flags = chainp->wc_flags; 3035 chainp = TAILQ_NEXT(chainp, wc_list); 3036 } 3037 3038 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) { 3039 if (win[1].win_start == 0xffffffff) { 3040 /* window 1 is not used */ 3041 if ((win[0].win_flags == chainp->wc_flags) && 3042 (win[0].win_limit + align >= 3043 (chainp->wc_start & mask))) { 3044 /* concatenate */ 3045 win[0].win_limit = chainp->wc_end & mask; 3046 } else { 3047 /* make new window */ 3048 win[1].win_start = chainp->wc_start & mask; 3049 win[1].win_limit = chainp->wc_end & mask; 3050 win[1].win_flags = chainp->wc_flags; 3051 } 3052 continue; 3053 } 3054 3055 /* Both windows are engaged. */ 3056 if (win[0].win_flags == win[1].win_flags) { 3057 /* same flags */ 3058 if (win[0].win_flags == chainp->wc_flags) { 3059 if (win[1].win_start - (win[0].win_limit + 3060 align) < 3061 (chainp->wc_start & mask) - 3062 ((chainp->wc_end & mask) + align)) { 3063 /* 3064 * merge window 0 and 1, and set win1 3065 * to chainp 3066 */ 3067 win[0].win_limit = win[1].win_limit; 3068 win[1].win_start = 3069 chainp->wc_start & mask; 3070 win[1].win_limit = 3071 chainp->wc_end & mask; 3072 } else { 3073 win[1].win_limit = 3074 chainp->wc_end & mask; 3075 } 3076 } else { 3077 /* different flags */ 3078 3079 /* concatenate win0 and win1 */ 3080 win[0].win_limit = win[1].win_limit; 3081 /* allocate win[1] to new space */ 3082 win[1].win_start = chainp->wc_start & mask; 3083 win[1].win_limit = chainp->wc_end & mask; 3084 win[1].win_flags = chainp->wc_flags; 3085 } 3086 } else { 3087 /* the flags of win[0] and win[1] is different */ 3088 if (win[0].win_flags == chainp->wc_flags) { 3089 win[0].win_limit = chainp->wc_end & mask; 3090 /* 3091 * XXX this creates overlapping windows, so 3092 * what should the poor bridge do if one is 3093 * cachable, and the other is not? 3094 */ 3095 aprint_error_dev(sc->sc_dev, 3096 "overlapping windows\n"); 3097 } else { 3098 win[1].win_limit = chainp->wc_end & mask; 3099 } 3100 } 3101 } 3102 3103 pc = sc->sc_pc; 3104 tag = sc->sc_tag; 3105 pci_conf_write(pc, tag, offs, win[0].win_start); 3106 pci_conf_write(pc, tag, offs + 4, win[0].win_limit); 3107 pci_conf_write(pc, tag, offs + 8, win[1].win_start); 3108 pci_conf_write(pc, tag, offs + 12, win[1].win_limit); 3109 DPRINTF(("--pccbb_winset: win0 [0x%lx, 0x%lx), win1 [0x%lx, 0x%lx)\n", 3110 (unsigned long)pci_conf_read(pc, tag, offs), 3111 (unsigned long)pci_conf_read(pc, tag, offs + 4) + align, 3112 (unsigned long)pci_conf_read(pc, tag, offs + 8), 3113 (unsigned long)pci_conf_read(pc, tag, offs + 12) + align)); 3114 3115 if (bus_space_is_equal(bst, sc->sc_memt)) { 3116 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BRIDGE_CONTROL_REG); 3117 3118 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1); 3119 if (win[0].win_flags & PCCBB_MEM_CACHABLE) 3120 bcr |= CB_BCR_PREFETCH_MEMWIN0; 3121 if (win[1].win_flags & PCCBB_MEM_CACHABLE) 3122 bcr |= CB_BCR_PREFETCH_MEMWIN1; 3123 pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr); 3124 } 3125 } 3126 3127 #endif /* rbus */ 3128 3129 static bool 3130 pccbb_suspend(device_t dv, const pmf_qual_t *qual) 3131 { 3132 struct pccbb_softc *sc = device_private(dv); 3133 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3134 bus_space_handle_t base_memh = sc->sc_base_memh; 3135 pcireg_t reg; 3136 3137 if (sc->sc_pil_intr_enable) 3138 (void)pccbbintr_function(sc); 3139 sc->sc_pil_intr_enable = false; 3140 3141 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3142 /* Disable interrupts. */ 3143 reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER); 3144 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3145 /* XXX joerg Disable power to the socket? */ 3146 3147 /* XXX flush PCI write */ 3148 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3149 3150 /* reset interrupt */ 3151 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, 3152 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT)); 3153 /* XXX flush PCI write */ 3154 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3155 3156 if (sc->sc_ih != NULL) { 3157 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 3158 sc->sc_ih = NULL; 3159 } 3160 3161 return true; 3162 } 3163 3164 static bool 3165 pccbb_resume(device_t dv, const pmf_qual_t *qual) 3166 { 3167 struct pccbb_softc *sc = device_private(dv); 3168 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */ 3169 bus_space_handle_t base_memh = sc->sc_base_memh; 3170 pcireg_t reg; 3171 3172 pccbb_chipinit(sc); 3173 pccbb_intrinit(sc); 3174 /* setup memory and io space window for CB */ 3175 pccbb_winset(0x1000, sc, sc->sc_memt); 3176 pccbb_winset(0x04, sc, sc->sc_iot); 3177 3178 /* CSC Interrupt: Card detect interrupt on */ 3179 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); 3180 /* Card detect intr is turned on. */ 3181 reg |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER; 3182 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg); 3183 /* reset interrupt */ 3184 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT); 3185 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg); 3186 3187 /* 3188 * check for card insertion or removal during suspend period. 3189 * XXX: the code can't cope with card swap (remove then 3190 * insert). how can we detect such situation? 3191 */ 3192 (void)pccbbintr(sc); 3193 3194 sc->sc_pil_intr_enable = true; 3195 3196 return true; 3197 } 3198