xref: /netbsd-src/sys/dev/pci/ohci_pci.c (revision b7b7574d3bf8eeb51a1fa3977b59142ec6434a55)
1 /*	$NetBSD: ohci_pci.c,v 1.52 2014/03/29 19:28:25 christos Exp $	*/
2 
3 /*
4  * Copyright (c) 1998 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Lennart Augustsson (lennart@augustsson.net) at
9  * Carlstedt Research & Technology.
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the distribution.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30  * POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 #include <sys/cdefs.h>
34 __KERNEL_RCSID(0, "$NetBSD: ohci_pci.c,v 1.52 2014/03/29 19:28:25 christos Exp $");
35 
36 #include "ehci.h"
37 
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/device.h>
42 #include <sys/proc.h>
43 #include <sys/queue.h>
44 
45 #include <sys/bus.h>
46 
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcidevs.h>
49 #include <dev/pci/usb_pci.h>
50 
51 #include <dev/usb/usb.h>
52 #include <dev/usb/usbdi.h>
53 #include <dev/usb/usbdivar.h>
54 #include <dev/usb/usb_mem.h>
55 
56 #include <dev/usb/ohcireg.h>
57 #include <dev/usb/ohcivar.h>
58 
59 struct ohci_pci_softc {
60 	ohci_softc_t		sc;
61 #if NEHCI > 0
62 	struct usb_pci		sc_pci;
63 #endif
64 	pci_chipset_tag_t	sc_pc;
65 	pcitag_t		sc_tag;
66 	void 			*sc_ih;		/* interrupt vectoring */
67 };
68 
69 static int
70 ohci_pci_match(device_t parent, cfdata_t match, void *aux)
71 {
72 	struct pci_attach_args *pa = (struct pci_attach_args *) aux;
73 
74 	if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS &&
75 	    PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB &&
76 	    PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_OHCI)
77 		return 1;
78 
79 	return 0;
80 }
81 
82 static void
83 ohci_pci_attach(device_t parent, device_t self, void *aux)
84 {
85 	struct ohci_pci_softc *sc = device_private(self);
86 	struct pci_attach_args *pa = (struct pci_attach_args *)aux;
87 	pci_chipset_tag_t pc = pa->pa_pc;
88 	pcitag_t tag = pa->pa_tag;
89 	char const *intrstr;
90 	pci_intr_handle_t ih;
91 	pcireg_t csr;
92 	usbd_status r;
93 	const char *vendor;
94 	char intrbuf[PCI_INTRSTR_LEN];
95 
96 	sc->sc.sc_dev = self;
97 	sc->sc.sc_bus.hci_private = sc;
98 
99 	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS &&
100 	    PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NS_USB) {
101 		sc->sc.sc_flags = OHCIF_SUPERIO;
102 	}
103 
104 	pci_aprint_devinfo(pa, "USB Controller");
105 
106 	/* check if memory space access is enabled */
107 	csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
108 #ifdef DEBUG
109 	printf("csr: %08x\n", csr);
110 #endif
111 	if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) {
112 		aprint_error_dev(self, "memory access is disabled\n");
113 		return;
114 	}
115 
116 	/* Map I/O registers */
117 	if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0,
118 			   &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) {
119 		sc->sc.sc_size = 0;
120 		aprint_error_dev(self, "can't map mem space\n");
121 		return;
122 	}
123 
124 	/* Disable interrupts, so we don't get any spurious ones. */
125 	bus_space_write_4(sc->sc.iot, sc->sc.ioh, OHCI_INTERRUPT_DISABLE,
126 			  OHCI_ALL_INTRS);
127 
128 	sc->sc_pc = pc;
129 	sc->sc_tag = tag;
130 	sc->sc.sc_bus.dmatag = pa->pa_dmat;
131 
132 	/* Enable the device. */
133 	pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
134 		       csr | PCI_COMMAND_MASTER_ENABLE);
135 
136 	/* Map and establish the interrupt. */
137 	if (pci_intr_map(pa, &ih)) {
138 		aprint_error_dev(self, "couldn't map interrupt\n");
139 		goto fail;
140 	}
141 
142 	/*
143 	 * Allocate IRQ
144 	 */
145 	intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf));
146 	sc->sc_ih = pci_intr_establish(pc, ih, IPL_SCHED, ohci_intr, sc);
147 	if (sc->sc_ih == NULL) {
148 		aprint_error_dev(self, "couldn't establish interrupt");
149 		if (intrstr != NULL)
150 			aprint_error(" at %s", intrstr);
151 		aprint_error("\n");
152 		goto fail;
153 	}
154 	aprint_normal_dev(self, "interrupting at %s\n", intrstr);
155 
156 	/* Figure out vendor for root hub descriptor. */
157 	vendor = pci_findvendor(pa->pa_id);
158 	sc->sc.sc_id_vendor = PCI_VENDOR(pa->pa_id);
159 	if (vendor)
160 		strlcpy(sc->sc.sc_vendor, vendor, sizeof(sc->sc.sc_vendor));
161 	else
162 		snprintf(sc->sc.sc_vendor, sizeof(sc->sc.sc_vendor),
163 		    "vendor 0x%04x", PCI_VENDOR(pa->pa_id));
164 
165 	r = ohci_init(&sc->sc);
166 	if (r != USBD_NORMAL_COMPLETION) {
167 		aprint_error_dev(self, "init failed, error=%d\n", r);
168 		goto fail;
169 	}
170 
171 #if NEHCI > 0
172 	usb_pci_add(&sc->sc_pci, pa, self);
173 #endif
174 
175 	if (!pmf_device_register1(self, ohci_suspend, ohci_resume,
176 	                          ohci_shutdown))
177 		aprint_error_dev(self, "couldn't establish power handler\n");
178 
179 	/* Attach usb device. */
180 	sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint);
181 	return;
182 
183 fail:
184 	if (sc->sc_ih) {
185 		pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
186 		sc->sc_ih = NULL;
187 	}
188 	if (sc->sc.sc_size) {
189 		bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
190 		sc->sc.sc_size = 0;
191 	}
192 	return;
193 }
194 
195 static int
196 ohci_pci_detach(device_t self, int flags)
197 {
198 	struct ohci_pci_softc *sc = device_private(self);
199 	int rv;
200 
201 	rv = ohci_detach(&sc->sc, flags);
202 	if (rv)
203 		return rv;
204 
205 	pmf_device_deregister(self);
206 
207 	ohci_shutdown(self, flags);
208 
209 	if (sc->sc.sc_size) {
210 		/* Disable interrupts, so we don't get any spurious ones. */
211 		bus_space_write_4(sc->sc.iot, sc->sc.ioh,
212 				  OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
213 	}
214 
215 	if (sc->sc_ih != NULL) {
216 		pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
217 		sc->sc_ih = NULL;
218 	}
219 	if (sc->sc.sc_size) {
220 		bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
221 		sc->sc.sc_size = 0;
222 	}
223 #if NEHCI > 0
224 	usb_pci_rem(&sc->sc_pci);
225 #endif
226 	return 0;
227 }
228 
229 CFATTACH_DECL3_NEW(ohci_pci, sizeof(struct ohci_pci_softc),
230     ohci_pci_match, ohci_pci_attach, ohci_pci_detach, ohci_activate, NULL,
231     ohci_childdet, DVF_DETACH_SHUTDOWN);
232