1 /* $NetBSD: nside.c,v 1.2 2011/04/04 20:37:56 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: nside.c,v 1.2 2011/04/04 20:37:56 dyoung Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 33 #include <dev/pci/pcivar.h> 34 #include <dev/pci/pcidevs.h> 35 #include <dev/pci/pciidereg.h> 36 #include <dev/pci/pciidevar.h> 37 #include <dev/pci/pciide_natsemi_reg.h> 38 39 static void natsemi_chip_map(struct pciide_softc *, 40 const struct pci_attach_args *); 41 static void natsemi_setup_channel(struct ata_channel *); 42 static int natsemi_pci_intr(void *); 43 static void natsemi_irqack(struct ata_channel *); 44 45 static int nside_match(device_t, cfdata_t, void *); 46 static void nside_attach(device_t, device_t, void *); 47 48 struct nside_softc { 49 struct pciide_softc pciide_sc; 50 struct pci_attach_args pcib_pa; 51 }; 52 53 CFATTACH_DECL_NEW(nside, sizeof(struct nside_softc), 54 nside_match, nside_attach, NULL, NULL); 55 56 static const struct pciide_product_desc pciide_natsemi_products[] = { 57 { PCI_PRODUCT_NS_PC87415, /* National Semi PC87415 IDE */ 58 0, 59 "National Semiconductor PC87415 IDE Controller", 60 natsemi_chip_map, 61 }, 62 { 0, 63 0, 64 NULL, 65 NULL 66 } 67 }; 68 69 static int 70 nside_match(device_t parent, cfdata_t match, void *aux) 71 { 72 struct pci_attach_args *pa = aux; 73 74 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS && 75 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 76 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 77 if (pciide_lookup_product(pa->pa_id, pciide_natsemi_products)) 78 return 2; 79 } 80 return 0; 81 } 82 83 static void 84 nside_attach(device_t parent, device_t self, void *aux) 85 { 86 struct pci_attach_args *pa = aux; 87 struct pciide_softc *sc = device_private(self); 88 89 sc->sc_wdcdev.sc_atac.atac_dev = self; 90 91 pciide_common_attach(sc, pa, 92 pciide_lookup_product(pa->pa_id, pciide_natsemi_products)); 93 } 94 95 static void 96 natsemi_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 97 { 98 struct pciide_channel *cp; 99 int channel; 100 pcireg_t interface, ctl; 101 102 if (pciide_chipen(sc, pa) == 0) 103 return; 104 105 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 106 "bus-master DMA support present"); 107 pciide_mapreg_dma(sc, pa); 108 aprint_verbose("\n"); 109 110 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 111 112 if (sc->sc_dma_ok) { 113 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 114 sc->sc_wdcdev.irqack = natsemi_irqack; 115 } 116 117 pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CCBT, 0xb7); 118 119 /* 120 * Mask off interrupts from both channels, appropriate channel(s) 121 * will be unmasked later. 122 */ 123 pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2, 124 pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2) | 125 NATSEMI_CHMASK(0) | NATSEMI_CHMASK(1)); 126 127 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 128 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 129 sc->sc_wdcdev.sc_atac.atac_set_modes = natsemi_setup_channel; 130 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 131 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 132 133 interface = PCI_INTERFACE(pa->pa_class); 134 interface &= ~PCIIDE_CHANSTATUS_EN; /* Reserved on PC87415 */ 135 136 /* If we're in PCIIDE mode, unmask INTA, otherwise mask it. */ 137 ctl = pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL1); 138 if (interface & (PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1))) 139 ctl &= ~NATSEMI_CTRL1_INTAMASK; 140 else 141 ctl |= NATSEMI_CTRL1_INTAMASK; 142 pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL1, ctl); 143 144 wdc_allocate_regs(&sc->sc_wdcdev); 145 146 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; channel++) { 147 cp = &sc->pciide_channels[channel]; 148 if (pciide_chansetup(sc, channel, interface) == 0) 149 continue; 150 151 pciide_mapchan(pa, cp, interface, natsemi_pci_intr); 152 153 pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2, 154 pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2) & 155 ~(NATSEMI_CHMASK(channel))); 156 } 157 } 158 159 void 160 natsemi_setup_channel(struct ata_channel *chp) 161 { 162 struct ata_drive_datas *drvp; 163 int drive, ndrives = 0; 164 uint32_t idedma_ctl = 0; 165 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 166 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 167 uint8_t tim; 168 169 /* setup DMA if needed */ 170 pciide_channel_dma_setup(cp); 171 172 for (drive = 0; drive < 2; drive++) { 173 drvp = &chp->ch_drive[drive]; 174 /* If no drive, skip */ 175 if ((drvp->drive_flags & DRIVE) == 0) 176 continue; 177 178 ndrives++; 179 /* add timing values, setup DMA if needed */ 180 if ((drvp->drive_flags & DRIVE_DMA) == 0) { 181 tim = natsemi_pio_pulse[drvp->PIO_mode] | 182 (natsemi_pio_recover[drvp->PIO_mode] << 4); 183 } else { 184 /* 185 * use Multiword DMA 186 * Timings will be used for both PIO and DMA, 187 * so adjust DMA mode if needed 188 */ 189 if (drvp->PIO_mode >= 3 && 190 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 191 drvp->DMA_mode = drvp->PIO_mode - 2; 192 } 193 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 194 tim = natsemi_dma_pulse[drvp->DMA_mode] | 195 (natsemi_dma_recover[drvp->DMA_mode] << 4); 196 197 } 198 199 pciide_pci_write(sc->sc_pc, sc->sc_tag, 200 NATSEMI_RTREG(chp->ch_channel, drive), tim); 201 pciide_pci_write(sc->sc_pc, sc->sc_tag, 202 NATSEMI_WTREG(chp->ch_channel, drive), tim); 203 } 204 205 if (idedma_ctl != 0) { 206 /* Add software bits in status register */ 207 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 208 idedma_ctl); 209 210 } 211 /* Go ahead and ack interrupts generated during probe. */ 212 natsemi_irqack(chp); 213 } 214 215 void 216 natsemi_irqack(struct ata_channel *chp) 217 { 218 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 219 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 220 uint8_t clr; 221 222 /* Errata: The "clear" bits are in the wrong register *sigh* */ 223 clr = bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0); 224 clr |= bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0) & 225 (IDEDMA_CTL_ERR | IDEDMA_CTL_INTR); 226 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, clr); 227 } 228 229 int 230 natsemi_pci_intr(void *arg) 231 { 232 struct pciide_softc *sc = arg; 233 struct pciide_channel *cp; 234 struct ata_channel *wdc_cp; 235 int i, rv, crv; 236 uint8_t msk; 237 238 rv = 0; 239 msk = pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2); 240 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 241 cp = &sc->pciide_channels[i]; 242 wdc_cp = &cp->ata_channel; 243 244 /* If a compat channel skip. */ 245 if (cp->compat) 246 continue; 247 248 /* If this channel is masked, skip it. */ 249 if (msk & NATSEMI_CHMASK(i)) 250 continue; 251 252 crv = wdcintr(wdc_cp); 253 if (crv == 0) 254 ; /* leave alone */ 255 else if (crv == 1) 256 rv = 1; /* claim the intr */ 257 else if (rv == 0) /* crv should be -1 in this case */ 258 rv = crv; /* if we've done no better, take it */ 259 } 260 return (rv); 261 } 262