1 /* $NetBSD: nfsmb.c,v 1.15 2008/10/15 02:21:48 pgoyette Exp $ */ 2 /* 3 * Copyright (c) 2007 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: nfsmb.c,v 1.15 2008/10/15 02:21:48 pgoyette Exp $"); 30 31 #include <sys/param.h> 32 #include <sys/device.h> 33 #include <sys/errno.h> 34 #include <sys/kernel.h> 35 #include <sys/rwlock.h> 36 #include <sys/proc.h> 37 38 #include <sys/bus.h> 39 40 #include <dev/i2c/i2cvar.h> 41 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pcidevs.h> 45 46 #include <dev/pci/nfsmbreg.h> 47 48 49 struct nfsmbc_attach_args { 50 int nfsmb_num; 51 bus_space_tag_t nfsmb_iot; 52 int nfsmb_addr; 53 }; 54 55 struct nfsmb_softc; 56 struct nfsmbc_softc { 57 device_t sc_dev; 58 59 pci_chipset_tag_t sc_pc; 60 pcitag_t sc_tag; 61 struct pci_attach_args *sc_pa; 62 63 bus_space_tag_t sc_iot; 64 struct device *sc_nfsmb[2]; 65 }; 66 67 struct nfsmb_softc { 68 device_t sc_dev; 69 int sc_num; 70 struct device *sc_nfsmbc; 71 72 bus_space_tag_t sc_iot; 73 bus_space_handle_t sc_ioh; 74 75 struct i2c_controller sc_i2c; /* i2c controller info */ 76 krwlock_t sc_rwlock; 77 }; 78 79 80 static int nfsmbc_match(device_t, struct cfdata *, void *); 81 static void nfsmbc_attach(device_t, device_t, void *); 82 static int nfsmbc_print(void *, const char *); 83 84 static int nfsmb_match(device_t, struct cfdata *, void *); 85 static void nfsmb_attach(device_t, device_t, void *); 86 static int nfsmb_acquire_bus(void *, int); 87 static void nfsmb_release_bus(void *, int); 88 static int nfsmb_exec( 89 void *, i2c_op_t, i2c_addr_t, const void *, size_t, void *, size_t, int); 90 static int nfsmb_check_done(struct nfsmb_softc *); 91 static int 92 nfsmb_send_1(struct nfsmb_softc *, uint8_t, i2c_addr_t, i2c_op_t, int); 93 static int nfsmb_write_1( 94 struct nfsmb_softc *, uint8_t, uint8_t, i2c_addr_t, i2c_op_t, int); 95 static int nfsmb_write_2( 96 struct nfsmb_softc *, uint8_t, uint16_t, i2c_addr_t, i2c_op_t, int); 97 static int nfsmb_receive_1(struct nfsmb_softc *, i2c_addr_t, i2c_op_t, int); 98 static int 99 nfsmb_read_1(struct nfsmb_softc *, uint8_t, i2c_addr_t, i2c_op_t, int); 100 static int 101 nfsmb_read_2(struct nfsmb_softc *, uint8_t, i2c_addr_t, i2c_op_t, int); 102 103 104 CFATTACH_DECL_NEW(nfsmbc, sizeof(struct nfsmbc_softc), 105 nfsmbc_match, nfsmbc_attach, NULL, NULL); 106 107 static int 108 nfsmbc_match(device_t parent, struct cfdata *match, void *aux) 109 { 110 struct pci_attach_args *pa = aux; 111 112 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NVIDIA) { 113 switch (PCI_PRODUCT(pa->pa_id)) { 114 case PCI_PRODUCT_NVIDIA_NFORCE2_SMBUS: 115 case PCI_PRODUCT_NVIDIA_NFORCE2_400_SMBUS: 116 case PCI_PRODUCT_NVIDIA_NFORCE3_SMBUS: 117 case PCI_PRODUCT_NVIDIA_NFORCE3_250_SMBUS: 118 case PCI_PRODUCT_NVIDIA_NFORCE4_SMBUS: 119 case PCI_PRODUCT_NVIDIA_NFORCE430_SMBUS: 120 case PCI_PRODUCT_NVIDIA_MCP04_SMBUS: 121 case PCI_PRODUCT_NVIDIA_MCP55_SMB: 122 case PCI_PRODUCT_NVIDIA_MCP61_SMB: 123 case PCI_PRODUCT_NVIDIA_MCP65_SMB: 124 case PCI_PRODUCT_NVIDIA_MCP67_SMB: 125 case PCI_PRODUCT_NVIDIA_MCP73_SMB: 126 return 1; 127 } 128 } 129 130 return 0; 131 } 132 133 static void 134 nfsmbc_attach(device_t parent, device_t self, void *aux) 135 { 136 struct nfsmbc_softc *sc = device_private(self); 137 struct pci_attach_args *pa = aux; 138 struct nfsmbc_attach_args nfsmbca; 139 pcireg_t reg; 140 int baseregs[2]; 141 char devinfo[256]; 142 143 aprint_naive("\n"); 144 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 145 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 146 PCI_REVISION(pa->pa_class)); 147 148 sc->sc_dev = self; 149 sc->sc_pc = pa->pa_pc; 150 sc->sc_tag = pa->pa_tag; 151 sc->sc_pa = pa; 152 sc->sc_iot = pa->pa_iot; 153 154 nfsmbca.nfsmb_iot = sc->sc_iot; 155 156 switch (PCI_PRODUCT(pa->pa_id)) { 157 case PCI_PRODUCT_NVIDIA_NFORCE2_SMBUS: 158 case PCI_PRODUCT_NVIDIA_NFORCE2_400_SMBUS: 159 case PCI_PRODUCT_NVIDIA_NFORCE3_SMBUS: 160 case PCI_PRODUCT_NVIDIA_NFORCE3_250_SMBUS: 161 case PCI_PRODUCT_NVIDIA_NFORCE4_SMBUS: 162 baseregs[0] = NFORCE_OLD_SMB1; 163 baseregs[1] = NFORCE_OLD_SMB2; 164 break; 165 default: 166 baseregs[0] = NFORCE_SMB1; 167 baseregs[1] = NFORCE_SMB2; 168 break; 169 } 170 171 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, baseregs[0]); 172 nfsmbca.nfsmb_num = 1; 173 nfsmbca.nfsmb_addr = NFORCE_SMBBASE(reg); 174 sc->sc_nfsmb[0] = config_found(sc->sc_dev, &nfsmbca, nfsmbc_print); 175 176 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, baseregs[1]); 177 nfsmbca.nfsmb_num = 2; 178 nfsmbca.nfsmb_addr = NFORCE_SMBBASE(reg); 179 sc->sc_nfsmb[1] = config_found(sc->sc_dev, &nfsmbca, nfsmbc_print); 180 181 /* This driver is similar to an ISA bridge that doesn't 182 * need any special handling. So registering NULL handlers 183 * are sufficent. */ 184 if (!pmf_device_register(self, NULL, NULL)) 185 aprint_error_dev(self, "couldn't establish power handler\n"); 186 } 187 188 static int 189 nfsmbc_print(void *aux, const char *pnp) 190 { 191 struct nfsmbc_attach_args *nfsmbcap = aux; 192 193 if (pnp) 194 aprint_normal("nfsmb SMBus %d at %s", 195 nfsmbcap->nfsmb_num, pnp); 196 else 197 aprint_normal(" SMBus %d", nfsmbcap->nfsmb_num); 198 return UNCONF; 199 } 200 201 202 CFATTACH_DECL_NEW(nfsmb, sizeof(struct nfsmb_softc), 203 nfsmb_match, nfsmb_attach, NULL, NULL); 204 205 static int 206 nfsmb_match(device_t parent, struct cfdata *match, void *aux) 207 { 208 struct nfsmbc_attach_args *nfsmbcap = aux; 209 210 if (nfsmbcap->nfsmb_num == 1 || nfsmbcap->nfsmb_num == 2) 211 return 1; 212 return 0; 213 } 214 215 static void 216 nfsmb_attach(device_t parent, device_t self, void *aux) 217 { 218 struct nfsmb_softc *sc = device_private(self); 219 struct nfsmbc_attach_args *nfsmbcap = aux; 220 struct i2cbus_attach_args iba; 221 222 aprint_naive("\n"); 223 aprint_normal("\n"); 224 225 sc->sc_dev = self; 226 sc->sc_nfsmbc = parent; 227 sc->sc_num = nfsmbcap->nfsmb_num; 228 sc->sc_iot = nfsmbcap->nfsmb_iot; 229 230 /* register with iic */ 231 sc->sc_i2c.ic_cookie = sc; 232 sc->sc_i2c.ic_acquire_bus = nfsmb_acquire_bus; 233 sc->sc_i2c.ic_release_bus = nfsmb_release_bus; 234 sc->sc_i2c.ic_send_start = NULL; 235 sc->sc_i2c.ic_send_stop = NULL; 236 sc->sc_i2c.ic_initiate_xfer = NULL; 237 sc->sc_i2c.ic_read_byte = NULL; 238 sc->sc_i2c.ic_write_byte = NULL; 239 sc->sc_i2c.ic_exec = nfsmb_exec; 240 241 rw_init(&sc->sc_rwlock); 242 243 if (bus_space_map(sc->sc_iot, nfsmbcap->nfsmb_addr, NFORCE_SMBSIZE, 0, 244 &sc->sc_ioh) != 0) { 245 aprint_error_dev(self, "failed to map SMBus space\n"); 246 return; 247 } 248 249 iba.iba_type = I2C_TYPE_SMBUS; 250 iba.iba_tag = &sc->sc_i2c; 251 (void) config_found_ia(sc->sc_dev, "i2cbus", &iba, iicbus_print); 252 253 /* This driver is similar to an ISA bridge that doesn't 254 * need any special handling. So registering NULL handlers 255 * are sufficent. */ 256 if (!pmf_device_register(self, NULL, NULL)) 257 aprint_error_dev(self, "couldn't establish power handler\n"); 258 } 259 260 static int 261 nfsmb_acquire_bus(void *cookie, int flags) 262 { 263 struct nfsmb_softc *sc = cookie; 264 265 rw_enter(&sc->sc_rwlock, RW_WRITER); 266 return 0; 267 } 268 269 static void 270 nfsmb_release_bus(void *cookie, int flags) 271 { 272 struct nfsmb_softc *sc = cookie; 273 274 rw_exit(&sc->sc_rwlock); 275 } 276 277 static int 278 nfsmb_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *cmd, 279 size_t cmdlen, void *vbuf, size_t buflen, int flags) 280 { 281 struct nfsmb_softc *sc = (struct nfsmb_softc *)cookie; 282 uint8_t *p = vbuf; 283 int rv; 284 285 if (I2C_OP_READ_P(op) && (cmdlen == 0) && (buflen == 1)) { 286 rv = nfsmb_receive_1(sc, addr, op, flags); 287 if (rv == -1) 288 return -1; 289 *p = (uint8_t)rv; 290 return 0; 291 } 292 293 if ((I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 1)) { 294 rv = nfsmb_read_1(sc, *(const uint8_t*)cmd, addr, op, flags); 295 if (rv == -1) 296 return -1; 297 *p = (uint8_t)rv; 298 return 0; 299 } 300 301 if ((I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 2)) { 302 rv = nfsmb_read_2(sc, *(const uint8_t*)cmd, addr, op, flags); 303 if (rv == -1) 304 return -1; 305 *(uint16_t *)p = (uint16_t)rv; 306 return 0; 307 } 308 309 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 0) && (buflen == 1)) 310 return nfsmb_send_1(sc, *(uint8_t*)vbuf, addr, op, flags); 311 312 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 1)) 313 return nfsmb_write_1(sc, *(const uint8_t*)cmd, *(uint8_t*)vbuf, 314 addr, op, flags); 315 316 if ((I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 2)) 317 return nfsmb_write_2(sc, 318 *(const uint8_t*)cmd, *((uint16_t *)vbuf), addr, op, flags); 319 320 return -1; 321 } 322 323 static int 324 nfsmb_check_done(struct nfsmb_softc *sc) 325 { 326 int us; 327 uint8_t stat; 328 329 us = 10 * 1000; /* XXXX: wait maximum 10 msec */ 330 do { 331 delay(10); 332 us -= 10; 333 if (us <= 0) 334 return -1; 335 } while (bus_space_read_1(sc->sc_iot, sc->sc_ioh, 336 NFORCE_SMB_PROTOCOL) != 0); 337 338 stat = bus_space_read_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_STATUS); 339 if ((stat & NFORCE_SMB_STATUS_DONE) && 340 !(stat & NFORCE_SMB_STATUS_STATUS)) 341 return 0; 342 return -1; 343 } 344 345 /* ARGSUSED */ 346 static int 347 nfsmb_send_1(struct nfsmb_softc *sc, uint8_t val, i2c_addr_t addr, i2c_op_t op, 348 int flags) 349 { 350 uint8_t data; 351 352 /* store cmd */ 353 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_COMMAND, val); 354 355 /* write smbus slave address to register */ 356 data = addr << 1; 357 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_ADDRESS, data); 358 359 /* write smbus protocol to register */ 360 data = I2C_OP_READ_P(op) | NFORCE_SMB_PROTOCOL_BYTE; 361 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_PROTOCOL, data); 362 363 return nfsmb_check_done(sc); 364 } 365 366 /* ARGSUSED */ 367 static int 368 nfsmb_write_1(struct nfsmb_softc *sc, uint8_t cmd, uint8_t val, i2c_addr_t addr, 369 i2c_op_t op, int flags) 370 { 371 uint8_t data; 372 373 /* store cmd */ 374 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_COMMAND, cmd); 375 376 /* store data */ 377 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_DATA, val); 378 379 /* write smbus slave address to register */ 380 data = addr << 1; 381 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_ADDRESS, data); 382 383 /* write smbus protocol to register */ 384 data = I2C_OP_READ_P(op) | NFORCE_SMB_PROTOCOL_BYTE_DATA; 385 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_PROTOCOL, data); 386 387 return nfsmb_check_done(sc); 388 } 389 390 static int 391 nfsmb_write_2(struct nfsmb_softc *sc, uint8_t cmd, uint16_t val, 392 i2c_addr_t addr, i2c_op_t op, int flags) 393 { 394 uint8_t data, low, high; 395 396 /* store cmd */ 397 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_COMMAND, cmd); 398 399 /* store data */ 400 low = val; 401 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_DATA, low); 402 high = val >> 8; 403 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_DATA, high); 404 405 /* write smbus slave address to register */ 406 data = addr << 1; 407 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_ADDRESS, data); 408 409 /* write smbus protocol to register */ 410 data = I2C_OP_READ_P(op) | NFORCE_SMB_PROTOCOL_WORD_DATA; 411 if (flags & I2C_F_PEC) 412 data |= NFORCE_SMB_PROTOCOL_PEC; 413 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_PROTOCOL, data); 414 415 return nfsmb_check_done(sc); 416 } 417 418 /* ARGSUSED */ 419 static int 420 nfsmb_receive_1(struct nfsmb_softc *sc, i2c_addr_t addr, i2c_op_t op, int flags) 421 { 422 uint8_t data; 423 424 /* write smbus slave address to register */ 425 data = addr << 1; 426 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_ADDRESS, data); 427 428 /* write smbus protocol to register */ 429 data = I2C_OP_READ_P(op) | NFORCE_SMB_PROTOCOL_BYTE; 430 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_PROTOCOL, data); 431 432 /* check for errors */ 433 if (nfsmb_check_done(sc) < 0) 434 return -1; 435 436 /* read data */ 437 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_DATA); 438 } 439 440 /* ARGSUSED */ 441 static int 442 nfsmb_read_1(struct nfsmb_softc *sc, uint8_t cmd, i2c_addr_t addr, i2c_op_t op, 443 int flags) 444 { 445 uint8_t data; 446 447 /* store cmd */ 448 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_COMMAND, cmd); 449 450 /* write smbus slave address to register */ 451 data = addr << 1; 452 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_ADDRESS, data); 453 454 /* write smbus protocol to register */ 455 data = I2C_OP_READ_P(op) | NFORCE_SMB_PROTOCOL_BYTE_DATA; 456 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_PROTOCOL, data); 457 458 /* check for errors */ 459 if (nfsmb_check_done(sc) < 0) 460 return -1; 461 462 /* read data */ 463 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_DATA); 464 } 465 466 static int 467 nfsmb_read_2(struct nfsmb_softc *sc, uint8_t cmd, i2c_addr_t addr, i2c_op_t op, 468 int flags) 469 { 470 uint8_t data, low, high; 471 472 /* store cmd */ 473 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_COMMAND, cmd); 474 475 /* write smbus slave address to register */ 476 data = addr << 1; 477 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_ADDRESS, data); 478 479 /* write smbus protocol to register */ 480 data = I2C_OP_READ_P(op) | NFORCE_SMB_PROTOCOL_BYTE_DATA; 481 if (flags & I2C_F_PEC) 482 data |= NFORCE_SMB_PROTOCOL_PEC; 483 bus_space_write_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_PROTOCOL, data); 484 485 /* check for errors */ 486 if (nfsmb_check_done(sc) < 0) 487 return -1; 488 489 /* read data */ 490 low = bus_space_read_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_DATA); 491 high = bus_space_read_1(sc->sc_iot, sc->sc_ioh, NFORCE_SMB_DATA); 492 return low | high << 8; 493 } 494