1 /* $NetBSD: mvsata_pci.c,v 1.4 2010/07/13 12:53:43 kiyohara Exp $ */ 2 /* 3 * Copyright (c) 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: mvsata_pci.c,v 1.4 2010/07/13 12:53:43 kiyohara Exp $"); 30 31 #include <sys/param.h> 32 #include <sys/bus.h> 33 #include <sys/device.h> 34 #include <sys/errno.h> 35 #include <sys/pmf.h> 36 37 #include <dev/pci/pcivar.h> 38 #include <dev/pci/pcidevs.h> 39 #include <dev/pci/pciidereg.h> 40 #include <dev/pci/pciidevar.h> 41 42 #include <dev/ic/mvsatareg.h> 43 #include <dev/ic/mvsatavar.h> 44 45 #define MVSATA_PCI_HCARBITER_SPACE_OFFSET 0x20000 46 47 #define MVSATA_PCI_COMMAND 0x00c00 48 #define MVSATA_PCI_COMMAND_MWRITECOMBINE (1 << 4) 49 #define MVSATA_PCI_COMMAND_MREADCOMBINE (1 << 5) 50 #define MVSATA_PCI_SERRMASK 0x00c28 51 #define MVSATA_PCI_MSITRIGGER 0x00c38 52 #define MVSATA_PCI_MODE 0x00d00 53 #define MVSATA_PCI_DISCTIMER 0x00d04 54 #define MVSATA_PCI_EROMBAR 0x00d2c 55 #define MVSATA_PCI_MAINCS 0x00d30 56 #define MVSATA_PCI_MAINCS_SPM (1 << 2) /* stop pci master */ 57 #define MVSATA_PCI_MAINCS_PME (1 << 3) /* pci master empty */ 58 #define MVSATA_PCI_MAINCS_GSR (1 << 4) /* glab soft reset */ 59 #define MVSATA_PCI_E_IRQCAUSE 0x01900 60 #define MVSATA_PCI_E_IRQMASK 0x01910 61 #define MVSATA_PCI_XBARTIMEOUT 0x01d04 62 #define MVSATA_PCI_ERRLOWADDR 0x01d40 63 #define MVSATA_PCI_ERRHIGHADDR 0x01d44 64 #define MVSATA_PCI_ERRATTRIBUTE 0x01d48 65 #define MVSATA_PCI_ERRCOMMAND 0x01d50 66 #define MVSATA_PCI_IRQCAUSE 0x01d58 67 #define MVSATA_PCI_IRQMASK 0x01d5c 68 #define MVSATA_PCI_MAINIRQCAUSE 0x01d60 69 #define MVSATA_PCI_MAINIRQMASK 0x01d64 70 #define MVSATA_PCI_MAINIRQ_SATAERR(hc, port) \ 71 (1 << (((port) << 1) + (hc) * 9)) 72 #define MVSATA_PCI_MAINIRQ_SATADONE(hc, port) \ 73 (1 << (((port) << 1) + (hc) * 9 + 1)) 74 #define MVSATA_PCI_MAINIRQ_SATACOALDONE(hc) (1 << ((hc) * 9 + 8)) 75 #define MVSATA_PCI_MAINIRQ_PCI (1 << 18) 76 #define MVSATA_PCI_FLASHCTL 0x1046c 77 #define MVSATA_PCI_GPIOPORTCTL 0x104f0 78 #define MVSATA_PCI_RESETCFG 0x180d8 79 80 #define MVSATA_PCI_DEV(psc) (psc->psc_sc.sc_wdcdev.sc_atac.atac_dev) 81 82 83 struct mvsata_pci_softc { 84 struct mvsata_softc psc_sc; 85 86 pci_chipset_tag_t psc_pc; 87 pcitag_t psc_tag; 88 89 bus_space_tag_t psc_iot; 90 bus_space_handle_t psc_ioh; 91 92 void *psc_ih; 93 }; 94 95 96 static int mvsata_pci_match(device_t, struct cfdata *, void *); 97 static void mvsata_pci_attach(device_t, device_t, void *); 98 static int mvsata_pci_detach(device_t, int); 99 100 static int mvsata_pci_intr(void *); 101 static bool mvsata_pci_resume(device_t, const pmf_qual_t *qual); 102 103 static int mvsata_pci_sreset(struct mvsata_softc *); 104 static int mvsata_pci_misc_reset(struct mvsata_softc *); 105 static void mvsata_pci_enable_intr(struct mvsata_port *, int); 106 107 108 CFATTACH_DECL_NEW(mvsata_pci, sizeof(struct mvsata_pci_softc), 109 mvsata_pci_match, mvsata_pci_attach, mvsata_pci_detach, NULL); 110 111 struct mvsata_product mvsata_pci_products[] = { 112 #define PCI_VP(v, p) PCI_VENDOR_ ## v, PCI_PRODUCT_ ## v ## _ ## p 113 { PCI_VP(MARVELL, 88SX5040), 1, 4, gen1, 0 }, 114 { PCI_VP(MARVELL, 88SX5041), 1, 4, gen1, 0 }, 115 { PCI_VP(MARVELL, 88SX5080), 2, 4, gen1, 0 }, 116 { PCI_VP(MARVELL, 88SX5081), 2, 4, gen1, 0 }, 117 { PCI_VP(MARVELL, 88SX6040), 1, 4, gen2, 0 }, 118 { PCI_VP(MARVELL, 88SX6041), 1, 4, gen2, 0 }, 119 { PCI_VP(MARVELL, 88SX6042), 1, 4, gen2e, 0 }, 120 { PCI_VP(MARVELL, 88SX6080), 2, 4, gen2, MVSATA_FLAGS_PCIE }, 121 { PCI_VP(MARVELL, 88SX6081), 2, 4, gen2, MVSATA_FLAGS_PCIE }, 122 { PCI_VP(ADP2, 1420SA), 2, 4, gen2, MVSATA_FLAGS_PCIE }, 123 { PCI_VP(MARVELL, 88SX7042), 1, 4, gen2e, 0 }, 124 { PCI_VP(ADP2, 1430SA), 1, 4, gen2e, 0 }, 125 { PCI_VP(TRIONES, ROCKETRAID_2310), 1, 4, gen2e, 0 }, 126 #undef PCI_VP 127 128 { -1, -1, 0, 0, gen_unknown, 0 } 129 }; 130 131 132 /* 133 * mvsata_pci_match() 134 * This function returns 2, because mvsata is high priority more than pciide. 135 */ 136 static int 137 mvsata_pci_match(device_t parent, struct cfdata *match, void *aux) 138 { 139 struct pci_attach_args *pa = aux; 140 int i; 141 142 for (i = 0; i < __arraycount(mvsata_pci_products); i++) 143 if (PCI_VENDOR(pa->pa_id) == mvsata_pci_products[i].vendor && 144 PCI_PRODUCT(pa->pa_id) == mvsata_pci_products[i].model) 145 return 2; 146 return 0; 147 } 148 149 static void 150 mvsata_pci_attach(device_t parent, device_t self, void *aux) 151 { 152 struct pci_attach_args *pa = aux; 153 struct mvsata_pci_softc *psc = device_private(self); 154 struct mvsata_softc *sc = &psc->psc_sc; 155 pci_intr_handle_t intrhandle; 156 pcireg_t csr; 157 bus_size_t size; 158 uint32_t reg, mask; 159 int read_pre_amps, hc, port, rv, i; 160 char devinfo[256]; 161 const char *intrstr; 162 163 sc->sc_wdcdev.sc_atac.atac_dev = self; 164 sc->sc_model = PCI_PRODUCT(pa->pa_id); 165 sc->sc_rev = PCI_REVISION(pa->pa_class); 166 sc->sc_dmat = pa->pa_dmat; 167 sc->sc_enable_intr = mvsata_pci_enable_intr; 168 169 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 170 aprint_naive(": Marvell Serial-ATA Host Controller\n"); 171 aprint_normal(": %s\n", devinfo); 172 173 /* Map I/O register */ 174 if (pci_mapreg_map(pa, PCI_MAPREG_START, 175 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 176 &psc->psc_iot, &psc->psc_ioh, NULL, &size) != 0) { 177 aprint_error_dev(self, "can't map registers\n"); 178 return; 179 } 180 psc->psc_pc = pa->pa_pc; 181 psc->psc_tag = pa->pa_tag; 182 183 if (bus_space_subregion(psc->psc_iot, psc->psc_ioh, 184 MVSATA_PCI_HCARBITER_SPACE_OFFSET, 185 size - MVSATA_PCI_HCARBITER_SPACE_OFFSET, &sc->sc_ioh)) { 186 aprint_error_dev(self, "can't subregion registers\n"); 187 return; 188 } 189 sc->sc_iot = psc->psc_iot; 190 191 /* Enable device */ 192 csr = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 193 csr |= PCI_COMMAND_MASTER_ENABLE; 194 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG, csr); 195 196 if (pci_intr_map(pa, &intrhandle) != 0) { 197 aprint_error_dev(self, "couldn't map interrupt\n"); 198 return; 199 } 200 intrstr = pci_intr_string(psc->psc_pc, intrhandle); 201 psc->psc_ih = pci_intr_establish(psc->psc_pc, intrhandle, IPL_BIO, 202 mvsata_pci_intr, sc); 203 if (psc->psc_ih == NULL) { 204 aprint_error_dev(self, "couldn't establish interrupt\n"); 205 return; 206 } 207 aprint_normal_dev(self, "interrupting at %s\n", 208 intrstr ? intrstr : "unknown interrupt"); 209 210 /* 211 * Check if TWSI serial ROM initialization was triggered. 212 * If so, then PRE/AMP configuration probably are set after 213 * reset by serial ROM. If not then override the PRE/AMP 214 * values. 215 */ 216 reg = bus_space_read_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_RESETCFG); 217 read_pre_amps = (reg & 0x00000001) ? 1 : 0; 218 219 for (i = 0; i < __arraycount(mvsata_pci_products); i++) 220 if (PCI_VENDOR(pa->pa_id) == mvsata_pci_products[i].vendor && 221 PCI_PRODUCT(pa->pa_id) == mvsata_pci_products[i].model) 222 break; 223 KASSERT(i < __arraycount(mvsata_pci_products)); 224 225 rv = mvsata_attach(sc, &mvsata_pci_products[i], 226 mvsata_pci_sreset, mvsata_pci_misc_reset, read_pre_amps); 227 if (rv != 0) { 228 pci_intr_disestablish(psc->psc_pc, psc->psc_ih); 229 return; 230 } 231 232 mask = MVSATA_PCI_MAINIRQ_PCI; 233 for (hc = 0; hc < sc->sc_hc; hc++) 234 for (port = 0; port < sc->sc_port; port++) 235 mask |= 236 MVSATA_PCI_MAINIRQ_SATAERR(hc, port) | 237 MVSATA_PCI_MAINIRQ_SATADONE(hc, port); 238 bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINIRQMASK, 239 mask); 240 241 if (!pmf_device_register(self, NULL, mvsata_pci_resume)) 242 aprint_error_dev(self, "couldn't establish power handler\n"); 243 } 244 245 static int 246 mvsata_pci_detach(device_t self, int flags) 247 { 248 struct mvsata_pci_softc *psc = device_private(self); 249 250 /* XXXX: needs reset ? */ 251 252 pci_intr_disestablish(psc->psc_pc, psc->psc_ih); 253 pmf_device_deregister(self); 254 return 0; 255 } 256 257 static int 258 mvsata_pci_intr(void *arg) 259 { 260 struct mvsata_pci_softc *psc = (struct mvsata_pci_softc *)arg; 261 struct mvsata_softc *sc = &psc->psc_sc; 262 uint32_t cause; 263 int hc, port, handled = 0; 264 265 cause = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 266 MVSATA_PCI_MAINIRQCAUSE); 267 for (hc = 0; hc < sc->sc_hc; hc++) 268 for (port = 0; port < sc->sc_port; port++) 269 if (cause & MVSATA_PCI_MAINIRQ_SATAERR(hc, port)) { 270 struct mvsata_port *mvport; 271 272 mvport = sc->sc_hcs[hc].hc_ports[port]; 273 handled |= mvsata_error(mvport); 274 } 275 for (hc = 0; hc < sc->sc_hc; hc++) 276 if (cause & 277 (MVSATA_PCI_MAINIRQ_SATADONE(hc, 0) | 278 MVSATA_PCI_MAINIRQ_SATADONE(hc, 1) | 279 MVSATA_PCI_MAINIRQ_SATADONE(hc, 2) | 280 MVSATA_PCI_MAINIRQ_SATADONE(hc, 3))) 281 handled |= mvsata_intr(&sc->sc_hcs[hc]); 282 283 if (cause & MVSATA_PCI_MAINIRQ_PCI) { 284 uint32_t pe_cause; 285 286 if (sc->sc_flags & MVSATA_FLAGS_PCIE) { 287 pe_cause = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 288 MVSATA_PCI_E_IRQCAUSE); 289 aprint_error_dev(MVSATA_PCI_DEV(psc), 290 "PCIe error: 0x%x\n", pe_cause); 291 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 292 MVSATA_PCI_E_IRQCAUSE, ~pe_cause); 293 } else { 294 pe_cause = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 295 MVSATA_PCI_IRQCAUSE); 296 aprint_error_dev(MVSATA_PCI_DEV(psc), 297 "PCI error: 0x%x\n", pe_cause); 298 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 299 MVSATA_PCI_IRQCAUSE, ~pe_cause); 300 } 301 302 handled = 1; /* XXXXX */ 303 } 304 305 return handled; 306 } 307 308 static bool 309 mvsata_pci_resume(device_t dev, const pmf_qual_t *qual) 310 { 311 312 /* not yet... */ 313 314 return true; 315 } 316 317 318 static int 319 mvsata_pci_sreset(struct mvsata_softc *sc) 320 { 321 struct mvsata_pci_softc *psc = (struct mvsata_pci_softc *)sc; 322 uint32_t val; 323 int i; 324 325 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS); 326 val |= MVSATA_PCI_MAINCS_SPM; 327 bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS, val); 328 329 for (i = 0; i < 1000; i++) { 330 delay(1); 331 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 332 MVSATA_PCI_MAINCS); 333 if (val & MVSATA_PCI_MAINCS_PME) 334 break; 335 } 336 if (!(val & MVSATA_PCI_MAINCS_PME)) { 337 aprint_error_dev(MVSATA_PCI_DEV(psc), 338 "PCI master won't flush\n"); 339 return -1; 340 } 341 342 /* reset */ 343 bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS, 344 val | MVSATA_PCI_MAINCS_GSR); 345 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS); 346 delay(5); 347 if (!(val & MVSATA_PCI_MAINCS_GSR)) { 348 aprint_error_dev(MVSATA_PCI_DEV(psc), 349 "can't set global reset\n"); 350 return -1; 351 } 352 353 /* clear reset and *reenable the PCI master* (not mentioned in spec) */ 354 val &= ~(MVSATA_PCI_MAINCS_GSR | MVSATA_PCI_MAINCS_SPM); 355 bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS, val); 356 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINCS); 357 delay(5); 358 if (val & MVSATA_PCI_MAINCS_GSR) { 359 aprint_error_dev(MVSATA_PCI_DEV(psc), 360 "can't set global reset\n"); 361 return -1; 362 } 363 364 return 0; 365 } 366 367 static int 368 mvsata_pci_misc_reset(struct mvsata_softc *sc) 369 { 370 struct mvsata_pci_softc *psc = (struct mvsata_pci_softc *)sc; 371 #define MVSATA_PCI_COMMAND_DEFAULT 0x0107e371 372 #define MVSATA_PCI_COMMAND_PCI_CONVENTIONAL_ONLY 0x800003e0 373 uint32_t val, pci_command = MVSATA_PCI_COMMAND_DEFAULT; 374 375 bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_FLASHCTL, 376 0x0fcfffff); 377 378 if (sc->sc_gen == gen2 || sc->sc_gen == gen2e) { 379 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 380 MVSATA_PCI_GPIOPORTCTL); 381 val &= 0x3; 382 #if 0 383 val |= 0x00000060; 384 #else /* XXXX */ 385 val |= 0x00000070; 386 #endif 387 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 388 MVSATA_PCI_GPIOPORTCTL, val); 389 } 390 391 if (sc->sc_gen == gen1) { 392 /* Expansion ROM BAR Enable */ 393 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 394 MVSATA_PCI_EROMBAR); 395 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 396 MVSATA_PCI_EROMBAR, val | 0x00000001); 397 } 398 399 if (sc->sc_flags & MVSATA_FLAGS_PCIE) { 400 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 401 MVSATA_PCI_MAINIRQMASK, 0); 402 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 403 MVSATA_PCI_E_IRQCAUSE, 0); 404 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 405 MVSATA_PCI_E_IRQMASK, 0); 406 } else { 407 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 408 MVSATA_PCI_MODE); 409 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 410 MVSATA_PCI_MODE, val & 0xff00ffff); 411 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 412 MVSATA_PCI_DISCTIMER, 0); 413 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 414 MVSATA_PCI_MSITRIGGER, 0); 415 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 416 MVSATA_PCI_XBARTIMEOUT, 0x000100ff); 417 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 418 MVSATA_PCI_MAINIRQMASK, 0); 419 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 420 MVSATA_PCI_SERRMASK, 0); 421 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 422 MVSATA_PCI_IRQCAUSE, 0); 423 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 424 MVSATA_PCI_IRQMASK, 0); 425 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 426 MVSATA_PCI_ERRLOWADDR, 0); 427 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 428 MVSATA_PCI_ERRHIGHADDR, 0); 429 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 430 MVSATA_PCI_ERRATTRIBUTE, 0); 431 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 432 MVSATA_PCI_ERRCOMMAND, 0); 433 } 434 435 /* Enable LED */ 436 if (sc->sc_gen == gen1) { 437 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 438 MVSATA_PCI_GPIOPORTCTL, 0); 439 440 /* XXXX: 50xxB2 errata ? */ 441 #if 0 442 if (sc->sc_rev == 3) { 443 int port; 444 445 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 446 MVSATA_PCI_GPIOPORTCTL); 447 448 /* XXXX: check HDD connected */ 449 450 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 451 MVSATA_PCI_GPIOPORTCTL, val); 452 } 453 #endif 454 455 /* Disable Flash controller clock */ 456 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 457 MVSATA_PCI_EROMBAR); 458 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 459 MVSATA_PCI_EROMBAR, val & ~0x00000001); 460 } else 461 #if 0 462 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 463 MVSATA_PCI_GPIOPORTCTL, 0x00000060); 464 #else /* XXXX */ 465 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 466 MVSATA_PCI_GPIOPORTCTL, 0x00000070); 467 #endif 468 469 if (sc->sc_flags & MVSATA_FLAGS_PCIE) 470 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 471 MVSATA_PCI_E_IRQMASK, 0x0000070a); 472 else { 473 val = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 474 MVSATA_PCI_MODE); 475 if ((val & 0x30) >> 4) { /* PCI-X */ 476 int mv60x1b2 = 477 ((sc->sc_model == PCI_PRODUCT_MARVELL_88SX6041 || 478 sc->sc_model == PCI_PRODUCT_MARVELL_88SX6081) && 479 sc->sc_rev == 7); 480 481 pci_command &= 482 ~MVSATA_PCI_COMMAND_PCI_CONVENTIONAL_ONLY; 483 if (sc->sc_gen == gen1 || mv60x1b2) 484 pci_command &= 485 ~MVSATA_PCI_COMMAND_MWRITECOMBINE; 486 } else 487 if (sc->sc_gen == gen1) 488 pci_command &= 489 ~(MVSATA_PCI_COMMAND_MWRITECOMBINE | 490 MVSATA_PCI_COMMAND_MREADCOMBINE); 491 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 492 MVSATA_PCI_COMMAND, pci_command); 493 494 #define MVSATA_PCI_INTERRUPT_MASK 0x00d77fe6 495 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 496 MVSATA_PCI_SERRMASK, MVSATA_PCI_INTERRUPT_MASK); 497 bus_space_write_4(psc->psc_iot, psc->psc_ioh, 498 MVSATA_PCI_IRQMASK, MVSATA_PCI_INTERRUPT_MASK); 499 } 500 501 return 0; 502 } 503 504 static void 505 mvsata_pci_enable_intr(struct mvsata_port *mvport, int on) 506 { 507 struct mvsata_pci_softc *psc = 508 device_private(mvport->port_ata_channel.ch_atac->atac_dev); 509 uint32_t mask; 510 int hc = mvport->port_hc->hc, port = mvport->port; 511 512 mask = bus_space_read_4(psc->psc_iot, psc->psc_ioh, 513 MVSATA_PCI_MAINIRQMASK); 514 if (on) 515 mask |= MVSATA_PCI_MAINIRQ_SATADONE(hc, port); 516 else 517 mask &= ~MVSATA_PCI_MAINIRQ_SATADONE(hc, port); 518 bus_space_write_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_MAINIRQMASK, 519 mask); 520 } 521