1 /* $NetBSD: machfb.c,v 1.71 2011/08/04 00:57:33 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Bang Jun-Young 5 * Copyright (c) 2005, 2006, 2007 Michael Lorenz 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, 37 "$NetBSD: machfb.c,v 1.71 2011/08/04 00:57:33 jakllsch Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/callout.h> 45 #include <sys/lwp.h> 46 #include <sys/kauth.h> 47 48 #include <dev/videomode/videomode.h> 49 #include <dev/videomode/edidvar.h> 50 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcidevs.h> 54 #include <dev/pci/pciio.h> 55 #include <dev/pci/machfbreg.h> 56 57 #ifdef __sparc__ 58 #include <dev/sun/fbio.h> 59 #include <dev/sun/fbvar.h> 60 #include <sys/conf.h> 61 #else 62 #include <dev/wscons/wsdisplayvar.h> 63 #endif 64 65 #include <dev/wscons/wsconsio.h> 66 #include <dev/wsfont/wsfont.h> 67 #include <dev/rasops/rasops.h> 68 #include <dev/pci/wsdisplay_pci.h> 69 70 #include <dev/wscons/wsdisplay_vconsvar.h> 71 72 #include "opt_wsemul.h" 73 #include "opt_machfb.h" 74 75 #define MACH64_REG_SIZE 1024 76 #define MACH64_REG_OFF 0x7ffc00 77 78 #define NBARS 3 /* number of Mach64 PCI BARs */ 79 80 struct vga_bar { 81 bus_addr_t vb_base; 82 pcireg_t vb_busaddr; 83 bus_size_t vb_size; 84 pcireg_t vb_type; 85 int vb_flags; 86 }; 87 88 struct mach64_softc { 89 device_t sc_dev; 90 #ifdef __sparc__ 91 struct fbdevice sc_fb; 92 #endif 93 pci_chipset_tag_t sc_pc; 94 pcitag_t sc_pcitag; 95 96 struct vga_bar sc_bars[NBARS]; 97 struct vga_bar sc_rom; 98 99 #define sc_aperbase sc_bars[0].vb_base 100 #define sc_apersize sc_bars[0].vb_size 101 #define sc_aperphys sc_bars[0].vb_busaddr 102 103 #define sc_iobase sc_bars[1].vb_base 104 #define sc_iosize sc_bars[1].vb_size 105 106 #define sc_regbase sc_bars[2].vb_base 107 #define sc_regsize sc_bars[2].vb_size 108 #define sc_regphys sc_bars[2].vb_busaddr 109 110 bus_space_tag_t sc_regt; 111 bus_space_tag_t sc_memt; 112 bus_space_tag_t sc_iot; 113 bus_space_handle_t sc_regh; 114 bus_space_handle_t sc_memh; 115 void *sc_aperture; /* mapped aperture vaddr */ 116 void *sc_registers; /* mapped registers vaddr */ 117 118 uint32_t sc_nbus, sc_ndev, sc_nfunc; 119 size_t memsize; 120 int memtype; 121 122 int sc_mode; 123 int sc_bg; 124 int sc_locked; 125 126 int has_dsp; 127 int bits_per_pixel; 128 int max_x; 129 int max_y; 130 int virt_x; 131 int virt_y; 132 int color_depth; 133 134 int mem_freq; 135 int ramdac_freq; 136 int ref_freq; 137 138 int ref_div; 139 int log2_vclk_post_div; 140 int vclk_post_div; 141 int vclk_fb_div; 142 int mclk_post_div; 143 int mclk_fb_div; 144 int sc_clock; /* which clock to use */ 145 146 struct videomode *sc_my_mode; 147 int sc_edid_size; 148 uint8_t sc_edid_data[1024]; 149 150 u_char sc_cmap_red[256]; 151 u_char sc_cmap_green[256]; 152 u_char sc_cmap_blue[256]; 153 int sc_dacw, sc_blanked, sc_console; 154 struct vcons_data vd; 155 struct wsdisplay_accessops sc_accessops; 156 }; 157 158 struct mach64_crtcregs { 159 uint32_t h_total_disp; 160 uint32_t h_sync_strt_wid; 161 uint32_t v_total_disp; 162 uint32_t v_sync_strt_wid; 163 uint32_t gen_cntl; 164 uint32_t clock_cntl; 165 uint32_t color_depth; 166 uint32_t dot_clock; 167 }; 168 169 static struct { 170 uint16_t chip_id; 171 uint32_t ramdac_freq; 172 } const mach64_info[] = { 173 { PCI_PRODUCT_ATI_MACH64_GX, 135000 }, 174 { PCI_PRODUCT_ATI_MACH64_CX, 135000 }, 175 { PCI_PRODUCT_ATI_MACH64_CT, 135000 }, 176 { PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 }, 177 { PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 }, 178 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 }, 179 { PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 }, 180 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 }, 181 { PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 }, 182 { PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 }, 183 { PCI_PRODUCT_ATI_RAGE_XL_PCI66, 230000 }, 184 { PCI_PRODUCT_ATI_RAGE_II, 135000 }, 185 { PCI_PRODUCT_ATI_RAGE_IIP, 200000 }, 186 { PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 }, 187 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 }, 188 { PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 }, 189 #if 0 190 { PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 }, 191 { PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 }, 192 { PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 }, 193 #endif 194 { PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 }, 195 { PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 }, 196 { PCI_PRODUCT_ATI_RAGE_LT, 230000 }, 197 { PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 }, 198 { PCI_PRODUCT_ATI_MACH64_VT, 170000 }, 199 { PCI_PRODUCT_ATI_MACH64_VTB, 200000 }, 200 { PCI_PRODUCT_ATI_MACH64_VT4, 230000 } 201 }; 202 203 static int mach64_chip_id, mach64_chip_rev; 204 static struct videomode default_mode = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 205 206 static const char *mach64_gx_memtype_names[] = { 207 "DRAM", "VRAM", "VRAM", "DRAM", 208 "DRAM", "VRAM", "VRAM", "(unknown type)" 209 }; 210 211 static const char *mach64_memtype_names[] = { 212 "(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM", 213 "(unknown type)" 214 }; 215 216 static struct videomode mach64_modes[] = { 217 /* 640x400 @ 70 Hz, 31.5 kHz */ 218 { 25175, 640, 664, 760, 800, 400, 409, 411, 450, 0, NULL, }, 219 /* 640x480 @ 72 Hz, 36.5 kHz */ 220 { 25175, 640, 664, 760, 800, 480, 491, 493, 525, 0, NULL, }, 221 /* 800x600 @ 72 Hz, 48.0 kHz */ 222 { 50000, 800, 856, 976, 1040, 600, 637, 643, 666, 223 VID_PHSYNC | VID_PVSYNC, NULL, }, 224 /* 1024x768 @ 70 Hz, 56.5 kHz */ 225 { 75000, 1024, 1048, 1184, 1328, 768, 771, 777, 806, 226 VID_NHSYNC | VID_NVSYNC, NULL, }, 227 /* 1152x864 @ 70 Hz, 62.4 kHz */ 228 { 92000, 1152, 1208, 1368, 1474, 864, 865, 875, 895, 0, NULL, }, 229 /* 1280x1024 @ 70 Hz, 74.59 kHz */ 230 { 126500, 1280, 1312, 1472, 1696, 1024, 1032, 1040, 1068, 231 VID_NHSYNC | VID_NVSYNC, NULL, } 232 }; 233 234 extern const u_char rasops_cmap[768]; 235 236 static int mach64_match(device_t, cfdata_t, void *); 237 static void mach64_attach(device_t, device_t, void *); 238 239 CFATTACH_DECL_NEW(machfb, sizeof(struct mach64_softc), mach64_match, mach64_attach, 240 NULL, NULL); 241 242 static void mach64_init(struct mach64_softc *); 243 static int mach64_get_memsize(struct mach64_softc *); 244 static int mach64_get_max_ramdac(struct mach64_softc *); 245 246 #if defined(__sparc__) || defined(__powerpc__) 247 static void mach64_get_mode(struct mach64_softc *, struct videomode *); 248 #endif 249 250 static int mach64_calc_crtcregs(struct mach64_softc *, 251 struct mach64_crtcregs *, 252 struct videomode *); 253 static void mach64_set_crtcregs(struct mach64_softc *, 254 struct mach64_crtcregs *); 255 256 static int mach64_modeswitch(struct mach64_softc *, struct videomode *); 257 static void mach64_set_dsp(struct mach64_softc *); 258 static void mach64_set_pll(struct mach64_softc *, int); 259 static void mach64_reset_engine(struct mach64_softc *); 260 static void mach64_init_engine(struct mach64_softc *); 261 #if 0 262 static void mach64_adjust_frame(struct mach64_softc *, int, int); 263 #endif 264 static void mach64_init_lut(struct mach64_softc *); 265 266 static void mach64_init_screen(void *, struct vcons_screen *, int, long *); 267 static int mach64_set_screentype(struct mach64_softc *, 268 const struct wsscreen_descr *); 269 static int mach64_is_console(struct mach64_softc *); 270 271 static void mach64_cursor(void *, int, int, int); 272 #if 0 273 static int mach64_mapchar(void *, int, u_int *); 274 #endif 275 static void mach64_putchar(void *, int, int, u_int, long); 276 static void mach64_copycols(void *, int, int, int, int); 277 static void mach64_erasecols(void *, int, int, int, long); 278 static void mach64_copyrows(void *, int, int, int); 279 static void mach64_eraserows(void *, int, int, long); 280 static void mach64_clearscreen(struct mach64_softc *); 281 282 static int mach64_putcmap(struct mach64_softc *, struct wsdisplay_cmap *); 283 static int mach64_getcmap(struct mach64_softc *, struct wsdisplay_cmap *); 284 static int mach64_putpalreg(struct mach64_softc *, uint8_t, uint8_t, 285 uint8_t, uint8_t); 286 static void mach64_bitblt(struct mach64_softc *, int, int, int, int, int, 287 int, int, int) ; 288 static void mach64_rectfill(struct mach64_softc *, int, int, int, int, int); 289 static void mach64_setup_mono(struct mach64_softc *, int, int, int, int, 290 uint32_t, uint32_t); 291 static void mach64_feed_bytes(struct mach64_softc *, int, uint8_t *); 292 #if 0 293 static void mach64_showpal(struct mach64_softc *); 294 #endif 295 296 static void set_address(struct rasops_info *, void *); 297 static void machfb_blank(struct mach64_softc *, int); 298 static int machfb_drm_print(void *, const char *); 299 300 static struct wsscreen_descr mach64_defaultscreen = { 301 "default", 302 80, 30, 303 NULL, 304 8, 16, 305 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 306 &default_mode 307 }, mach64_80x25_screen = { 308 "80x25", 80, 25, 309 NULL, 310 8, 16, 311 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 312 &mach64_modes[0] 313 }, mach64_80x30_screen = { 314 "80x30", 80, 30, 315 NULL, 316 8, 16, 317 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 318 &mach64_modes[1] 319 }, mach64_80x40_screen = { 320 "80x40", 80, 40, 321 NULL, 322 8, 10, 323 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 324 &mach64_modes[0] 325 }, mach64_80x50_screen = { 326 "80x50", 80, 50, 327 NULL, 328 8, 8, 329 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 330 &mach64_modes[0] 331 }, mach64_100x37_screen = { 332 "100x37", 100, 37, 333 NULL, 334 8, 16, 335 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 336 &mach64_modes[2] 337 }, mach64_128x48_screen = { 338 "128x48", 128, 48, 339 NULL, 340 8, 16, 341 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 342 &mach64_modes[3] 343 }, mach64_144x54_screen = { 344 "144x54", 144, 54, 345 NULL, 346 8, 16, 347 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 348 &mach64_modes[4] 349 }, mach64_160x64_screen = { 350 "160x54", 160, 64, 351 NULL, 352 8, 16, 353 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 354 &mach64_modes[5] 355 }; 356 357 static const struct wsscreen_descr *_mach64_scrlist[] = { 358 &mach64_defaultscreen, 359 &mach64_80x25_screen, 360 &mach64_80x30_screen, 361 &mach64_80x40_screen, 362 &mach64_80x50_screen, 363 &mach64_100x37_screen, 364 &mach64_128x48_screen, 365 &mach64_144x54_screen, 366 &mach64_160x64_screen 367 }; 368 369 static struct wsscreen_list mach64_screenlist = { 370 __arraycount(_mach64_scrlist), 371 _mach64_scrlist 372 }; 373 374 static int mach64_ioctl(void *, void *, u_long, void *, int, 375 struct lwp *); 376 static paddr_t mach64_mmap(void *, void *, off_t, int); 377 378 #if 0 379 static int mach64_load_font(void *, void *, struct wsdisplay_font *); 380 #endif 381 382 383 static struct vcons_screen mach64_console_screen; 384 385 /* framebuffer device, SPARC-only so far */ 386 #ifdef __sparc__ 387 388 static void machfb_unblank(device_t); 389 static void machfb_fbattach(struct mach64_softc *); 390 391 extern struct cfdriver machfb_cd; 392 393 dev_type_open(machfb_fbopen); 394 dev_type_close(machfb_fbclose); 395 dev_type_ioctl(machfb_fbioctl); 396 dev_type_mmap(machfb_fbmmap); 397 398 /* frame buffer generic driver */ 399 static struct fbdriver machfb_fbdriver = { 400 machfb_unblank, machfb_fbopen, machfb_fbclose, machfb_fbioctl, nopoll, 401 machfb_fbmmap, nokqfilter 402 }; 403 404 #endif /* __sparc__ */ 405 406 /* 407 * Inline functions for getting access to register aperture. 408 */ 409 410 static inline uint32_t 411 regr(struct mach64_softc *sc, uint32_t index) 412 { 413 return bus_space_read_4(sc->sc_regt, sc->sc_regh, index); 414 } 415 416 static inline uint8_t 417 regrb(struct mach64_softc *sc, uint32_t index) 418 { 419 return bus_space_read_1(sc->sc_regt, sc->sc_regh, index); 420 } 421 422 static inline void 423 regw(struct mach64_softc *sc, uint32_t index, uint32_t data) 424 { 425 bus_space_write_4(sc->sc_regt, sc->sc_regh, index, data); 426 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4, 427 BUS_SPACE_BARRIER_WRITE); 428 } 429 430 static inline void 431 regwb(struct mach64_softc *sc, uint32_t index, uint8_t data) 432 { 433 bus_space_write_1(sc->sc_regt, sc->sc_regh, index, data); 434 bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 1, 435 BUS_SPACE_BARRIER_WRITE); 436 } 437 438 static inline void 439 regwb_pll(struct mach64_softc *sc, uint32_t index, uint8_t data) 440 { 441 uint32_t reg; 442 443 reg = regr(sc, CLOCK_CNTL); 444 reg |= PLL_WR_EN; 445 regw(sc, CLOCK_CNTL, reg); 446 reg &= ~(PLL_ADDR | PLL_DATA); 447 reg |= (index & 0x3f) << PLL_ADDR_SHIFT; 448 reg |= data << PLL_DATA_SHIFT; 449 reg |= CLOCK_STROBE; 450 regw(sc, CLOCK_CNTL, reg); 451 reg &= ~PLL_WR_EN; 452 regw(sc, CLOCK_CNTL, reg); 453 } 454 455 static inline uint8_t 456 regrb_pll(struct mach64_softc *sc, uint32_t index) 457 { 458 459 regwb(sc, CLOCK_CNTL + 1, index << 2); 460 return regrb(sc, CLOCK_CNTL + 2); 461 } 462 463 static inline void 464 wait_for_fifo(struct mach64_softc *sc, uint8_t v) 465 { 466 while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v)) 467 continue; 468 } 469 470 static inline void 471 wait_for_idle(struct mach64_softc *sc) 472 { 473 wait_for_fifo(sc, 16); 474 while ((regr(sc, GUI_STAT) & 1) != 0) 475 continue; 476 } 477 478 static int 479 mach64_match(device_t parent, cfdata_t match, void *aux) 480 { 481 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 482 int i; 483 484 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 485 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 486 return 0; 487 488 for (i = 0; i < __arraycount(mach64_info); i++) 489 if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) { 490 mach64_chip_id = PCI_PRODUCT(pa->pa_id); 491 mach64_chip_rev = PCI_REVISION(pa->pa_class); 492 return 100; 493 } 494 495 return 0; 496 } 497 498 static void 499 mach64_attach(device_t parent, device_t self, void *aux) 500 { 501 struct mach64_softc *sc = device_private(self); 502 struct pci_attach_args *pa = aux; 503 struct rasops_info *ri; 504 prop_data_t edid_data; 505 #if defined(__sparc__) || defined(__powerpc__) 506 const struct videomode *mode = NULL; 507 #endif 508 char devinfo[256]; 509 int bar, id, expected_id; 510 int is_gx; 511 const char **memtype_names; 512 struct wsemuldisplaydev_attach_args aa; 513 long defattr; 514 int setmode, width, height; 515 pcireg_t screg; 516 uint32_t reg; 517 const pcireg_t enables = PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE; 518 519 sc->sc_dev = self; 520 sc->sc_pc = pa->pa_pc; 521 sc->sc_pcitag = pa->pa_tag; 522 sc->sc_dacw = -1; 523 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 524 sc->sc_nbus = pa->pa_bus; 525 sc->sc_ndev = pa->pa_device; 526 sc->sc_nfunc = pa->pa_function; 527 sc->sc_locked = 0; 528 sc->sc_iot = pa->pa_iot; 529 sc->sc_accessops.ioctl = mach64_ioctl; 530 sc->sc_accessops.mmap = mach64_mmap; 531 532 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 533 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 534 PCI_REVISION(pa->pa_class)); 535 aprint_naive(": Graphics processor\n"); 536 #ifdef MACHFB_DEBUG 537 printf(prop_dictionary_externalize(device_properties(self))); 538 #endif 539 540 /* enable memory and disable IO access */ 541 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 542 if ((screg & enables) != enables) { 543 screg |= enables; 544 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 545 PCI_COMMAND_STATUS_REG, screg); 546 } 547 for (bar = 0; bar < NBARS; bar++) { 548 reg = PCI_MAPREG_START + (bar * 4); 549 sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc, 550 sc->sc_pcitag, reg); 551 (void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg, 552 sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base, 553 &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags); 554 sc->sc_bars[bar].vb_busaddr = pci_conf_read(sc->sc_pc, 555 sc->sc_pcitag, reg) & 0xfffffff0; 556 } 557 printf("%s: aperture size %08x\n", device_xname(sc->sc_dev), 558 (uint32_t)sc->sc_apersize); 559 560 sc->sc_rom.vb_type = PCI_MAPREG_TYPE_ROM; 561 pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, PCI_MAPREG_ROM, 562 sc->sc_rom.vb_type, &sc->sc_rom.vb_base, 563 &sc->sc_rom.vb_size, &sc->sc_rom.vb_flags); 564 sc->sc_memt = pa->pa_memt; 565 566 if (bus_space_map(sc->sc_memt, sc->sc_aperbase, sc->sc_apersize, 567 BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) { 568 panic("%s: failed to map aperture", device_xname(sc->sc_dev)); 569 } 570 sc->sc_aperture = (void *)bus_space_vaddr(sc->sc_memt, sc->sc_memh); 571 572 /* If the BAR was never mapped, fix it up in MMIO. */ 573 if(sc->sc_regsize == 0) { 574 sc->sc_regsize = MACH64_REG_SIZE; 575 sc->sc_regbase = sc->sc_aperbase + MACH64_REG_OFF; 576 sc->sc_regphys = sc->sc_aperphys + MACH64_REG_OFF; 577 } 578 579 sc->sc_regt = sc->sc_memt; 580 bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF, 581 sc->sc_regsize, &sc->sc_regh); 582 sc->sc_registers = (char *)sc->sc_aperture + 0x7ffc00; 583 584 mach64_init(sc); 585 586 aprint_normal_dev(sc->sc_dev, 587 "%d MB aperture at 0x%08x, %d KB registers at 0x%08x\n", 588 (u_int)(sc->sc_apersize / (1024 * 1024)), 589 (u_int)sc->sc_aperphys, (u_int)(sc->sc_regsize / 1024), 590 (u_int)sc->sc_regphys); 591 592 printf("%s: %d KB ROM at 0x%08x\n", device_xname(sc->sc_dev), 593 (int)sc->sc_rom.vb_size >> 10, (uint32_t)sc->sc_rom.vb_base); 594 595 prop_dictionary_get_uint32(device_properties(self), "width", &width); 596 prop_dictionary_get_uint32(device_properties(self), "height", &height); 597 598 if ((edid_data = prop_dictionary_get(device_properties(self), "EDID")) 599 != NULL) { 600 struct edid_info ei; 601 602 sc->sc_edid_size = min(1024, prop_data_size(edid_data)); 603 memset(sc->sc_edid_data, 0, sizeof(sc->sc_edid_data)); 604 memcpy(sc->sc_edid_data, prop_data_data_nocopy(edid_data), 605 sc->sc_edid_size); 606 607 edid_parse(sc->sc_edid_data, &ei); 608 609 #ifdef MACHFB_DEBUG 610 edid_print(&ei); 611 #endif 612 } 613 614 is_gx = 0; 615 switch(mach64_chip_id) { 616 case PCI_PRODUCT_ATI_MACH64_GX: 617 case PCI_PRODUCT_ATI_MACH64_CX: 618 is_gx = 1; 619 case PCI_PRODUCT_ATI_MACH64_CT: 620 sc->has_dsp = 0; 621 break; 622 case PCI_PRODUCT_ATI_MACH64_VT: 623 case PCI_PRODUCT_ATI_RAGE_II: 624 if((mach64_chip_rev & 0x07) == 0) { 625 sc->has_dsp = 0; 626 break; 627 } 628 /* Otherwise fall through. */ 629 default: 630 sc->has_dsp = 1; 631 } 632 633 memtype_names = is_gx ? mach64_gx_memtype_names : mach64_memtype_names; 634 635 sc->memsize = mach64_get_memsize(sc); 636 if (sc->memsize == 8192) 637 /* The last page is used as register aperture. */ 638 sc->memsize -= 4; 639 if(is_gx) 640 sc->memtype = (regr(sc, CONFIG_STAT0) >> 3) & 0x07; 641 else 642 sc->memtype = regr(sc, CONFIG_STAT0) & 0x07; 643 644 /* XXX is there any way to calculate reference frequency from 645 known values? */ 646 if ((mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) || 647 ((mach64_chip_id >= PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI) && 648 (mach64_chip_id <= PCI_PRODUCT_ATI_RAGE_LT_PRO))) { 649 aprint_normal_dev(sc->sc_dev, "ref_freq=29.498MHz\n"); 650 sc->ref_freq = 29498; 651 } else 652 sc->ref_freq = 14318; 653 654 reg = regr(sc, CLOCK_CNTL); 655 printf("CLOCK_CNTL: %08x\n", reg); 656 sc->sc_clock = reg & 3; 657 printf("using clock %d\n", sc->sc_clock); 658 659 sc->ref_div = regrb_pll(sc, PLL_REF_DIV); 660 printf("ref_div: %d\n", sc->ref_div); 661 sc->mclk_fb_div = regrb_pll(sc, MCLK_FB_DIV); 662 printf("mclk_fb_div: %d\n", sc->mclk_fb_div); 663 sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) / 664 (sc->ref_div * 2); 665 sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) / 666 (sc->mem_freq * sc->ref_div); 667 sc->ramdac_freq = mach64_get_max_ramdac(sc); 668 aprint_normal_dev(sc->sc_dev, 669 "%ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n", 670 (u_long)sc->memsize, 671 memtype_names[sc->memtype], 672 sc->mem_freq / 1000, sc->mem_freq % 1000, 673 sc->ramdac_freq / 1000); 674 675 id = regr(sc, CONFIG_CHIP_ID) & 0xffff; 676 switch(mach64_chip_id) { 677 case PCI_PRODUCT_ATI_MACH64_GX: 678 expected_id = 0x00d7; 679 break; 680 case PCI_PRODUCT_ATI_MACH64_CX: 681 expected_id = 0x0057; 682 break; 683 default: 684 /* Most chip IDs match their PCI product ID. */ 685 expected_id = mach64_chip_id; 686 } 687 688 if (id != expected_id) { 689 aprint_error_dev(sc->sc_dev, 690 "chip ID mismatch, 0x%x != 0x%x\n", id, expected_id); 691 return; 692 } 693 694 sc->sc_console = mach64_is_console(sc); 695 #ifdef DIAGNOSTIC 696 aprint_normal("gen_cntl: %08x\n", regr(sc, CRTC_GEN_CNTL)); 697 #endif 698 #if defined(__sparc__) || defined(__powerpc__) 699 if (sc->sc_console) { 700 if (mode != NULL) { 701 memcpy(&default_mode, mode, sizeof(struct videomode)); 702 setmode = 1; 703 } else { 704 mach64_get_mode(sc, &default_mode); 705 setmode = 0; 706 } 707 sc->sc_my_mode = &default_mode; 708 } else { 709 /* fill in default_mode if it's empty */ 710 mach64_get_mode(sc, &default_mode); 711 if (default_mode.dot_clock == 0) { 712 memcpy(&default_mode, &mach64_modes[4], 713 sizeof(default_mode)); 714 } 715 sc->sc_my_mode = &default_mode; 716 setmode = 1; 717 } 718 #else 719 if (default_mode.dot_clock == 0) { 720 memcpy(&default_mode, &mach64_modes[0], 721 sizeof(default_mode)); 722 } 723 sc->sc_my_mode = &mach64_modes[0]; 724 setmode = 1; 725 #endif 726 727 sc->bits_per_pixel = 8; 728 sc->virt_x = sc->sc_my_mode->hdisplay; 729 sc->virt_y = sc->sc_my_mode->vdisplay; 730 sc->max_x = sc->virt_x - 1; 731 sc->max_y = (sc->memsize * 1024) / 732 (sc->virt_x * (sc->bits_per_pixel / 8)) - 1; 733 734 sc->color_depth = CRTC_PIX_WIDTH_8BPP; 735 736 mach64_init_engine(sc); 737 738 if (setmode) 739 mach64_modeswitch(sc, sc->sc_my_mode); 740 741 aprint_normal_dev(sc->sc_dev, 742 "initial resolution %dx%d at %d bpp\n", 743 sc->sc_my_mode->hdisplay, sc->sc_my_mode->vdisplay, 744 sc->bits_per_pixel); 745 746 #ifdef __sparc__ 747 machfb_fbattach(sc); 748 #endif 749 750 wsfont_init(); 751 752 sc->sc_bg = WS_DEFAULT_BG; 753 vcons_init(&sc->vd, sc, &mach64_defaultscreen, &sc->sc_accessops); 754 sc->vd.init_screen = mach64_init_screen; 755 756 mach64_init_lut(sc); 757 mach64_clearscreen(sc); 758 machfb_blank(sc, 0); /* unblank the screen */ 759 760 if (sc->sc_console) { 761 762 vcons_init_screen(&sc->vd, &mach64_console_screen, 1, 763 &defattr); 764 mach64_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 765 766 ri = &mach64_console_screen.scr_ri; 767 mach64_defaultscreen.textops = &ri->ri_ops; 768 mach64_defaultscreen.capabilities = ri->ri_caps; 769 mach64_defaultscreen.nrows = ri->ri_rows; 770 mach64_defaultscreen.ncols = ri->ri_cols; 771 772 wsdisplay_cnattach(&mach64_defaultscreen, ri, 0, 0, defattr); 773 vcons_replay_msgbuf(&mach64_console_screen); 774 } else { 775 /* 776 * since we're not the console we can postpone the rest 777 * until someone actually allocates a screen for us 778 */ 779 mach64_modeswitch(sc, sc->sc_my_mode); 780 } 781 782 aa.console = sc->sc_console; 783 aa.scrdata = &mach64_screenlist; 784 aa.accessops = &sc->sc_accessops; 785 aa.accesscookie = &sc->vd; 786 787 config_found(self, &aa, wsemuldisplaydevprint); 788 789 config_found_ia(self, "drm", aux, machfb_drm_print); 790 } 791 792 static int 793 machfb_drm_print(void *aux, const char *pnp) 794 { 795 if (pnp) 796 aprint_normal("direct rendering for %s", pnp); 797 return (UNSUPP); 798 } 799 800 static void 801 mach64_init_screen(void *cookie, struct vcons_screen *scr, int existing, 802 long *defattr) 803 { 804 struct mach64_softc *sc = cookie; 805 struct rasops_info *ri = &scr->scr_ri; 806 807 /* XXX for now */ 808 #define setmode 0 809 810 ri->ri_depth = sc->bits_per_pixel; 811 ri->ri_width = sc->sc_my_mode->hdisplay; 812 ri->ri_height = sc->sc_my_mode->vdisplay; 813 ri->ri_stride = ri->ri_width; 814 ri->ri_flg = RI_CENTER; 815 set_address(ri, sc->sc_aperture); 816 817 #ifdef VCONS_DRAW_INTR 818 scr->scr_flags |= VCONS_DONT_READ; 819 #endif 820 821 if (existing) { 822 if (setmode && mach64_set_screentype(sc, scr->scr_type)) { 823 panic("%s: failed to switch video mode", 824 device_xname(sc->sc_dev)); 825 } 826 } 827 828 rasops_init(ri, sc->sc_my_mode->vdisplay / 8, 829 sc->sc_my_mode->hdisplay / 8); 830 ri->ri_caps = WSSCREEN_WSCOLORS; 831 rasops_reconfig(ri, sc->sc_my_mode->vdisplay / ri->ri_font->fontheight, 832 sc->sc_my_mode->hdisplay / ri->ri_font->fontwidth); 833 834 /* enable acceleration */ 835 ri->ri_hw = scr; 836 ri->ri_ops.copyrows = mach64_copyrows; 837 ri->ri_ops.copycols = mach64_copycols; 838 ri->ri_ops.eraserows = mach64_eraserows; 839 ri->ri_ops.erasecols = mach64_erasecols; 840 ri->ri_ops.cursor = mach64_cursor; 841 ri->ri_ops.putchar = mach64_putchar; 842 } 843 844 static void 845 mach64_init(struct mach64_softc *sc) 846 { 847 uint32_t *p32, saved_value; 848 uint8_t *p; 849 int need_swap; 850 851 /* 852 * Test whether the aperture is byte swapped or not 853 */ 854 p32 = (uint32_t*)sc->sc_aperture; 855 saved_value = *p32; 856 p = (uint8_t*)(u_long)sc->sc_aperture; 857 *p32 = 0x12345678; 858 if (p[0] == 0x12 && p[1] == 0x34 && p[2] == 0x56 && p[3] == 0x78) 859 need_swap = 0; 860 else 861 need_swap = 1; 862 if (need_swap) { 863 sc->sc_aperture = (char *)sc->sc_aperture + 0x800000; 864 #if 0 865 /* what the fsck is this for? */ 866 sc->sc_aperbase += 0x800000; 867 sc->sc_apersize -= 0x800000; 868 #endif 869 } 870 *p32 = saved_value; 871 872 sc->sc_blanked = 0; 873 } 874 875 static int 876 mach64_get_memsize(struct mach64_softc *sc) 877 { 878 int tmp, memsize; 879 int mem_tab[] = { 880 512, 1024, 2048, 4096, 6144, 8192, 12288, 16384 881 }; 882 tmp = regr(sc, MEM_CNTL); 883 #ifdef DIAGNOSTIC 884 aprint_debug_dev(sc->sc_dev, "memctl %08x\n", tmp); 885 #endif 886 if (sc->has_dsp) { 887 tmp &= 0x0000000f; 888 if (tmp < 8) 889 memsize = (tmp + 1) * 512; 890 else if (tmp < 12) 891 memsize = (tmp - 3) * 1024; 892 else 893 memsize = (tmp - 7) * 2048; 894 } else { 895 memsize = mem_tab[tmp & 0x07]; 896 } 897 898 return memsize; 899 } 900 901 static int 902 mach64_get_max_ramdac(struct mach64_softc *sc) 903 { 904 int i; 905 906 if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 907 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) && 908 (mach64_chip_rev & 0x07)) 909 return 170000; 910 911 for (i = 0; i < __arraycount(mach64_info); i++) 912 if (mach64_chip_id == mach64_info[i].chip_id) 913 return mach64_info[i].ramdac_freq; 914 915 if (sc->bits_per_pixel == 8) 916 return 135000; 917 else 918 return 80000; 919 } 920 921 #if defined(__sparc__) || defined(__powerpc__) 922 static void 923 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode) 924 { 925 struct mach64_crtcregs crtc; 926 927 crtc.h_total_disp = regr(sc, CRTC_H_TOTAL_DISP); 928 crtc.h_sync_strt_wid = regr(sc, CRTC_H_SYNC_STRT_WID); 929 crtc.v_total_disp = regr(sc, CRTC_V_TOTAL_DISP); 930 crtc.v_sync_strt_wid = regr(sc, CRTC_V_SYNC_STRT_WID); 931 932 mode->htotal = ((crtc.h_total_disp & 0xffff) + 1) << 3; 933 mode->hdisplay = ((crtc.h_total_disp >> 16) + 1) << 3; 934 mode->hsync_start = ((crtc.h_sync_strt_wid & 0xffff) + 1) << 3; 935 mode->hsync_end = ((crtc.h_sync_strt_wid >> 16) << 3) + 936 mode->hsync_start; 937 mode->vtotal = (crtc.v_total_disp & 0xffff) + 1; 938 mode->vdisplay = (crtc.v_total_disp >> 16) + 1; 939 mode->vsync_start = (crtc.v_sync_strt_wid & 0xffff) + 1; 940 mode->vsync_end = (crtc.v_sync_strt_wid >> 16) + mode->vsync_start; 941 942 #ifdef MACHFB_DEBUG 943 printf("mach64_get_mode: %d %d %d %d %d %d %d %d\n", 944 mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, 945 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal); 946 #endif 947 } 948 #endif 949 950 static int 951 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc, 952 struct videomode *mode) 953 { 954 955 if (mode->dot_clock > sc->ramdac_freq) 956 /* Clock too high. */ 957 return 1; 958 959 crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) | 960 ((mode->htotal >> 3) - 1); 961 crtc->h_sync_strt_wid = 962 (((mode->hsync_end - mode->hsync_start) >> 3) << 16) | 963 ((mode->hsync_start >> 3) - 1); 964 965 crtc->v_total_disp = ((mode->vdisplay - 1) << 16) | 966 (mode->vtotal - 1); 967 crtc->v_sync_strt_wid = 968 ((mode->vsync_end - mode->vsync_start) << 16) | 969 (mode->vsync_start - 1); 970 971 if (mode->flags & VID_NVSYNC) 972 crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG; 973 974 switch (sc->bits_per_pixel) { 975 case 8: 976 crtc->color_depth = CRTC_PIX_WIDTH_8BPP; 977 break; 978 case 16: 979 crtc->color_depth = CRTC_PIX_WIDTH_16BPP; 980 break; 981 case 32: 982 crtc->color_depth = CRTC_PIX_WIDTH_32BPP; 983 break; 984 } 985 986 crtc->gen_cntl = 0; 987 if (mode->flags & VID_INTERLACE) 988 crtc->gen_cntl |= CRTC_INTERLACE_EN; 989 990 if (mode->flags & VID_CSYNC) 991 crtc->gen_cntl |= CRTC_CSYNC_EN; 992 993 crtc->dot_clock = mode->dot_clock; 994 995 return 0; 996 } 997 998 static void 999 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc) 1000 { 1001 1002 mach64_set_pll(sc, crtc->dot_clock); 1003 1004 if (sc->has_dsp) 1005 mach64_set_dsp(sc); 1006 #if 1 1007 regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp); 1008 regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 1009 regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp); 1010 regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 1011 1012 regw(sc, CRTC_VLINE_CRNT_VLINE, 0); 1013 1014 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 1015 1016 regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth | 1017 /* XXX this unconditionally enables composite sync on SPARC */ 1018 #ifdef __sparc__ 1019 CRTC_CSYNC_EN | 1020 #endif 1021 CRTC_EXT_DISP_EN | CRTC_EXT_EN); 1022 #endif 1023 } 1024 1025 static int 1026 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode) 1027 { 1028 struct mach64_crtcregs crtc; 1029 1030 memset(&crtc, 0, sizeof crtc); /* XXX gcc */ 1031 1032 if (mach64_calc_crtcregs(sc, &crtc, mode)) 1033 return 1; 1034 aprint_debug("crtc dot clock: %d\n", crtc.dot_clock); 1035 if (crtc.dot_clock == 0) { 1036 aprint_error("%s: preposterous dot clock (%d)\n", 1037 device_xname(sc->sc_dev), crtc.dot_clock); 1038 return 1; 1039 } 1040 mach64_set_crtcregs(sc, &crtc); 1041 return 0; 1042 } 1043 1044 static void 1045 mach64_reset_engine(struct mach64_softc *sc) 1046 { 1047 1048 /* Reset engine.*/ 1049 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE); 1050 1051 /* Enable engine. */ 1052 regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE); 1053 1054 /* Ensure engine is not locked up by clearing any FIFO or 1055 host errors. */ 1056 regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK | 1057 BUS_FIFO_ERR_ACK); 1058 } 1059 1060 static void 1061 mach64_init_engine(struct mach64_softc *sc) 1062 { 1063 uint32_t pitch_value; 1064 1065 pitch_value = sc->virt_x; 1066 1067 if (sc->bits_per_pixel == 24) 1068 pitch_value *= 3; 1069 1070 mach64_reset_engine(sc); 1071 1072 wait_for_fifo(sc, 14); 1073 1074 regw(sc, CONTEXT_MASK, 0xffffffff); 1075 1076 regw(sc, DST_OFF_PITCH, (pitch_value / 8) << 22); 1077 1078 /* make sure the visible area starts where we're going to draw */ 1079 regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22); 1080 1081 regw(sc, DST_Y_X, 0); 1082 regw(sc, DST_HEIGHT, 0); 1083 regw(sc, DST_BRES_ERR, 0); 1084 regw(sc, DST_BRES_INC, 0); 1085 regw(sc, DST_BRES_DEC, 0); 1086 1087 regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT | 1088 DST_Y_TOP_TO_BOTTOM); 1089 1090 regw(sc, SRC_OFF_PITCH, (pitch_value / 8) << 22); 1091 1092 regw(sc, SRC_Y_X, 0); 1093 regw(sc, SRC_HEIGHT1_WIDTH1, 1); 1094 regw(sc, SRC_Y_X_START, 0); 1095 regw(sc, SRC_HEIGHT2_WIDTH2, 1); 1096 1097 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1098 1099 wait_for_fifo(sc, 13); 1100 regw(sc, HOST_CNTL, 0); 1101 1102 regw(sc, PAT_REG0, 0); 1103 regw(sc, PAT_REG1, 0); 1104 regw(sc, PAT_CNTL, 0); 1105 1106 regw(sc, SC_LEFT, 0); 1107 regw(sc, SC_TOP, 0); 1108 regw(sc, SC_BOTTOM, sc->sc_my_mode->vdisplay - 1); 1109 regw(sc, SC_RIGHT, pitch_value - 1); 1110 1111 regw(sc, DP_BKGD_CLR, WS_DEFAULT_BG); 1112 regw(sc, DP_FRGD_CLR, WS_DEFAULT_FG); 1113 regw(sc, DP_WRITE_MASK, 0xffffffff); 1114 regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST); 1115 1116 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1117 1118 wait_for_fifo(sc, 3); 1119 regw(sc, CLR_CMP_CLR, 0); 1120 regw(sc, CLR_CMP_MASK, 0xffffffff); 1121 regw(sc, CLR_CMP_CNTL, 0); 1122 1123 wait_for_fifo(sc, 2); 1124 switch (sc->bits_per_pixel) { 1125 case 8: 1126 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_8BPP | DST_8BPP); 1127 regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP); 1128 /* We want 8 bit per channel */ 1129 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1130 break; 1131 case 32: 1132 regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_32BPP | DST_32BPP); 1133 regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP); 1134 regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN); 1135 break; 1136 } 1137 1138 wait_for_fifo(sc, 5); 1139 regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20); 1140 regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1141 1142 wait_for_idle(sc); 1143 } 1144 1145 #if 0 1146 static void 1147 mach64_adjust_frame(struct mach64_softc *sc, int x, int y) 1148 { 1149 int offset; 1150 1151 offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3; 1152 1153 regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) | 1154 offset); 1155 } 1156 #endif 1157 1158 static void 1159 mach64_set_dsp(struct mach64_softc *sc) 1160 { 1161 uint32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency; 1162 uint32_t dsp_off, dsp_on, dsp_xclks_per_qw; 1163 uint32_t xclks_per_qw, y; 1164 uint32_t fifo_off, fifo_on; 1165 1166 aprint_normal_dev(sc->sc_dev, "initializing the DSP\n"); 1167 1168 if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT || 1169 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II || 1170 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP || 1171 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI || 1172 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B || 1173 mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) { 1174 dsp_loop_latency = 0; 1175 fifo_depth = 24; 1176 } else { 1177 dsp_loop_latency = 2; 1178 fifo_depth = 32; 1179 } 1180 1181 dsp_precision = 0; 1182 xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) / 1183 (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel); 1184 y = (xclks_per_qw * fifo_depth) >> 11; 1185 while (y) { 1186 y >>= 1; 1187 dsp_precision++; 1188 } 1189 dsp_precision -= 5; 1190 fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6); 1191 1192 switch (sc->memtype) { 1193 case DRAM: 1194 case EDO_DRAM: 1195 case PSEUDO_EDO: 1196 if (sc->memsize > 1024) { 1197 page_size = 9; 1198 dsp_loop_latency += 6; 1199 } else { 1200 page_size = 10; 1201 if (sc->memtype == DRAM) 1202 dsp_loop_latency += 8; 1203 else 1204 dsp_loop_latency += 7; 1205 } 1206 break; 1207 case SDRAM: 1208 case SGRAM: 1209 if (sc->memsize > 1024) { 1210 page_size = 8; 1211 dsp_loop_latency += 8; 1212 } else { 1213 page_size = 10; 1214 dsp_loop_latency += 9; 1215 } 1216 break; 1217 default: 1218 page_size = 10; 1219 dsp_loop_latency += 9; 1220 break; 1221 } 1222 1223 if (xclks_per_qw >= (page_size << 11)) 1224 fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5); 1225 else 1226 fifo_on = (3 * page_size + 2) << 6; 1227 1228 dsp_xclks_per_qw = xclks_per_qw >> dsp_precision; 1229 dsp_on = fifo_on >> dsp_precision; 1230 dsp_off = fifo_off >> dsp_precision; 1231 1232 #ifdef MACHFB_DEBUG 1233 printf("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n" 1234 "dsp_precision = %d, dsp_loop_latency = %d,\n" 1235 "mclk_fb_div = %d, vclk_fb_div = %d,\n" 1236 "mclk_post_div = %d, vclk_post_div = %d\n", 1237 dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency, 1238 sc->mclk_fb_div, sc->vclk_fb_div, 1239 sc->mclk_post_div, sc->vclk_post_div); 1240 #endif 1241 1242 regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF)); 1243 regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) | 1244 ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) | 1245 (dsp_xclks_per_qw & DSP_XCLKS_PER_QW)); 1246 } 1247 1248 static void 1249 mach64_set_pll(struct mach64_softc *sc, int clock) 1250 { 1251 uint32_t q, clockreg; 1252 int clockshift = sc->sc_clock << 1; 1253 uint8_t reg, vclk_ctl; 1254 1255 q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq); 1256 #ifdef MACHFB_DEBUG 1257 printf("q = %d\n", q); 1258 #endif 1259 if (q > 25500) { 1260 printf("Warning: q > 25500\n"); 1261 q = 25500; 1262 sc->vclk_post_div = 1; 1263 sc->log2_vclk_post_div = 0; 1264 } else if (q > 12750) { 1265 sc->vclk_post_div = 1; 1266 sc->log2_vclk_post_div = 0; 1267 } else if (q > 6350) { 1268 sc->vclk_post_div = 2; 1269 sc->log2_vclk_post_div = 1; 1270 } else if (q > 3150) { 1271 sc->vclk_post_div = 4; 1272 sc->log2_vclk_post_div = 2; 1273 } else if (q >= 1600) { 1274 sc->vclk_post_div = 8; 1275 sc->log2_vclk_post_div = 3; 1276 } else { 1277 printf("Warning: q < 1600\n"); 1278 sc->vclk_post_div = 8; 1279 sc->log2_vclk_post_div = 3; 1280 } 1281 sc->vclk_fb_div = q * sc->vclk_post_div / 100; 1282 printf("post_div: %d log2_post_div: %d mclk_div: %d\n", sc->vclk_post_div, sc->log2_vclk_post_div, sc->mclk_fb_div); 1283 1284 vclk_ctl = regrb_pll(sc, PLL_VCLK_CNTL); 1285 printf("vclk_ctl: %02x\n", vclk_ctl); 1286 vclk_ctl |= PLL_VCLK_RESET; 1287 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1288 1289 regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div); 1290 reg = regrb_pll(sc, VCLK_POST_DIV); 1291 reg &= ~(3 << clockshift); 1292 reg |= (sc->log2_vclk_post_div << clockshift); 1293 regwb_pll(sc, VCLK_POST_DIV, reg); 1294 regwb_pll(sc, VCLK0_FB_DIV + sc->sc_clock, sc->vclk_fb_div); 1295 1296 vclk_ctl &= ~PLL_VCLK_RESET; 1297 regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl); 1298 1299 clockreg = regr(sc, CLOCK_CNTL); 1300 clockreg &= ~CLOCK_SEL; 1301 clockreg |= sc->sc_clock | CLOCK_STROBE; 1302 regw(sc, CLOCK_CNTL, clockreg); 1303 } 1304 1305 static void 1306 mach64_init_lut(struct mach64_softc *sc) 1307 { 1308 int i, idx; 1309 1310 idx = 0; 1311 for (i = 0; i < 256; i++) { 1312 mach64_putpalreg(sc, i, rasops_cmap[idx], rasops_cmap[idx + 1], 1313 rasops_cmap[idx + 2]); 1314 idx += 3; 1315 } 1316 } 1317 1318 static int 1319 mach64_putpalreg(struct mach64_softc *sc, uint8_t index, uint8_t r, uint8_t g, 1320 uint8_t b) 1321 { 1322 sc->sc_cmap_red[index] = r; 1323 sc->sc_cmap_green[index] = g; 1324 sc->sc_cmap_blue[index] = b; 1325 /* 1326 * writing the dac index takes a while, in theory we can poll some 1327 * register to see when it's ready - but we better avoid writing it 1328 * unnecessarily 1329 */ 1330 if (index != sc->sc_dacw) { 1331 regwb(sc, DAC_MASK, 0xff); 1332 regwb(sc, DAC_WINDEX, index); 1333 } 1334 sc->sc_dacw = index + 1; 1335 regwb(sc, DAC_DATA, r); 1336 regwb(sc, DAC_DATA, g); 1337 regwb(sc, DAC_DATA, b); 1338 return 0; 1339 } 1340 1341 static int 1342 mach64_putcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1343 { 1344 uint index = cm->index; 1345 uint count = cm->count; 1346 int i, error; 1347 uint8_t rbuf[256], gbuf[256], bbuf[256]; 1348 uint8_t *r, *g, *b; 1349 1350 if (cm->index >= 256 || cm->count > 256 || 1351 (cm->index + cm->count) > 256) 1352 return EINVAL; 1353 error = copyin(cm->red, &rbuf[index], count); 1354 if (error) 1355 return error; 1356 error = copyin(cm->green, &gbuf[index], count); 1357 if (error) 1358 return error; 1359 error = copyin(cm->blue, &bbuf[index], count); 1360 if (error) 1361 return error; 1362 1363 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 1364 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 1365 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 1366 1367 r = &sc->sc_cmap_red[index]; 1368 g = &sc->sc_cmap_green[index]; 1369 b = &sc->sc_cmap_blue[index]; 1370 1371 for (i = 0; i < count; i++) { 1372 mach64_putpalreg(sc, index, *r, *g, *b); 1373 index++; 1374 r++, g++, b++; 1375 } 1376 return 0; 1377 } 1378 1379 static int 1380 mach64_getcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm) 1381 { 1382 u_int index = cm->index; 1383 u_int count = cm->count; 1384 int error; 1385 1386 if (index >= 255 || count > 256 || index + count > 256) 1387 return EINVAL; 1388 1389 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 1390 if (error) 1391 return error; 1392 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 1393 if (error) 1394 return error; 1395 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 1396 if (error) 1397 return error; 1398 1399 return 0; 1400 } 1401 1402 static int 1403 mach64_set_screentype(struct mach64_softc *sc, const struct wsscreen_descr *des) 1404 { 1405 struct mach64_crtcregs regs; 1406 1407 if (mach64_calc_crtcregs(sc, ®s, 1408 (struct videomode *)des->modecookie)) 1409 return 1; 1410 1411 mach64_set_crtcregs(sc, ®s); 1412 return 0; 1413 } 1414 1415 static int 1416 mach64_is_console(struct mach64_softc *sc) 1417 { 1418 bool console = 0; 1419 1420 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1421 "is_console", &console); 1422 return console; 1423 } 1424 1425 /* 1426 * wsdisplay_emulops 1427 */ 1428 1429 static void 1430 mach64_cursor(void *cookie, int on, int row, int col) 1431 { 1432 struct rasops_info *ri = cookie; 1433 struct vcons_screen *scr = ri->ri_hw; 1434 struct mach64_softc *sc = scr->scr_cookie; 1435 int x, y, wi, he; 1436 1437 wi = ri->ri_font->fontwidth; 1438 he = ri->ri_font->fontheight; 1439 1440 if ((!sc->sc_locked) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1441 x = ri->ri_ccol * wi + ri->ri_xorigin; 1442 y = ri->ri_crow * he + ri->ri_yorigin; 1443 if (ri->ri_flg & RI_CURSOR) { 1444 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1445 0xff); 1446 ri->ri_flg &= ~RI_CURSOR; 1447 } 1448 ri->ri_crow = row; 1449 ri->ri_ccol = col; 1450 if (on) { 1451 x = ri->ri_ccol * wi + ri->ri_xorigin; 1452 y = ri->ri_crow * he + ri->ri_yorigin; 1453 mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC, 1454 0xff); 1455 ri->ri_flg |= RI_CURSOR; 1456 } 1457 } else { 1458 scr->scr_ri.ri_crow = row; 1459 scr->scr_ri.ri_ccol = col; 1460 scr->scr_ri.ri_flg &= ~RI_CURSOR; 1461 } 1462 } 1463 1464 #if 0 1465 static int 1466 mach64_mapchar(void *cookie, int uni, u_int *index) 1467 { 1468 return 0; 1469 } 1470 #endif 1471 1472 static void 1473 mach64_putchar(void *cookie, int row, int col, u_int c, long attr) 1474 { 1475 struct rasops_info *ri = cookie; 1476 struct wsdisplay_font *font = PICK_FONT(ri, c); 1477 struct vcons_screen *scr = ri->ri_hw; 1478 struct mach64_softc *sc = scr->scr_cookie; 1479 1480 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1481 int fg, bg, uc; 1482 uint8_t *data; 1483 int x, y, wi, he; 1484 wi = font->fontwidth; 1485 he = font->fontheight; 1486 1487 if (!CHAR_IN_FONT(c, font)) 1488 return; 1489 bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0x0f]; 1490 fg = (u_char)ri->ri_devcmap[(attr >> 24) & 0x0f]; 1491 x = ri->ri_xorigin + col * wi; 1492 y = ri->ri_yorigin + row * he; 1493 if (c == 0x20) { 1494 mach64_rectfill(sc, x, y, wi, he, bg); 1495 } else { 1496 uc = c - font->firstchar; 1497 data = (uint8_t *)font->data + uc * 1498 ri->ri_fontscale; 1499 1500 mach64_setup_mono(sc, x, y, wi, he, fg, bg); 1501 mach64_feed_bytes(sc, ri->ri_fontscale, data); 1502 } 1503 } 1504 } 1505 1506 1507 static void 1508 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1509 { 1510 struct rasops_info *ri = cookie; 1511 struct vcons_screen *scr = ri->ri_hw; 1512 struct mach64_softc *sc = scr->scr_cookie; 1513 int32_t xs, xd, y, width, height; 1514 1515 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1516 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1517 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1518 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1519 width = ri->ri_font->fontwidth * ncols; 1520 height = ri->ri_font->fontheight; 1521 mach64_bitblt(sc, xs, y, xd, y, width, height, MIX_SRC, 0xff); 1522 } 1523 } 1524 1525 static void 1526 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1527 { 1528 struct rasops_info *ri = cookie; 1529 struct vcons_screen *scr = ri->ri_hw; 1530 struct mach64_softc *sc = scr->scr_cookie; 1531 int32_t x, y, width, height, fg, bg, ul; 1532 1533 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1534 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1535 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1536 width = ri->ri_font->fontwidth * ncols; 1537 height = ri->ri_font->fontheight; 1538 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1539 1540 mach64_rectfill(sc, x, y, width, height, bg); 1541 } 1542 } 1543 1544 static void 1545 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1546 { 1547 struct rasops_info *ri = cookie; 1548 struct vcons_screen *scr = ri->ri_hw; 1549 struct mach64_softc *sc = scr->scr_cookie; 1550 int32_t x, ys, yd, width, height; 1551 1552 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1553 x = ri->ri_xorigin; 1554 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1555 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1556 width = ri->ri_emuwidth; 1557 height = ri->ri_font->fontheight*nrows; 1558 mach64_bitblt(sc, x, ys, x, yd, width, height, MIX_SRC, 0xff); 1559 } 1560 } 1561 1562 static void 1563 mach64_eraserows(void *cookie, int row, int nrows, long fillattr) 1564 { 1565 struct rasops_info *ri = cookie; 1566 struct vcons_screen *scr = ri->ri_hw; 1567 struct mach64_softc *sc = scr->scr_cookie; 1568 int32_t x, y, width, height, fg, bg, ul; 1569 1570 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1571 x = ri->ri_xorigin; 1572 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1573 width = ri->ri_emuwidth; 1574 height = ri->ri_font->fontheight * nrows; 1575 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1576 1577 mach64_rectfill(sc, x, y, width, height, bg); 1578 } 1579 } 1580 1581 static void 1582 mach64_bitblt(struct mach64_softc *sc, int xs, int ys, int xd, int yd, int width, int height, int rop, int mask) 1583 { 1584 uint32_t dest_ctl = 0; 1585 1586 wait_for_idle(sc); 1587 regw(sc, DP_WRITE_MASK, mask); /* XXX only good for 8 bit */ 1588 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1589 regw(sc, DP_SRC, FRGD_SRC_BLIT); 1590 regw(sc, DP_MIX, (rop & 0xffff) << 16); 1591 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1592 if (yd < ys) { 1593 dest_ctl = DST_Y_TOP_TO_BOTTOM; 1594 } else { 1595 ys += height - 1; 1596 yd += height - 1; 1597 dest_ctl = DST_Y_BOTTOM_TO_TOP; 1598 } 1599 if (xd < xs) { 1600 dest_ctl |= DST_X_LEFT_TO_RIGHT; 1601 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1602 } else { 1603 dest_ctl |= DST_X_RIGHT_TO_LEFT; 1604 xs += width - 1; 1605 xd += width - 1; 1606 regw(sc, SRC_CNTL, SRC_LINE_X_RIGHT_TO_LEFT); 1607 } 1608 regw(sc, DST_CNTL, dest_ctl); 1609 1610 regw(sc, SRC_Y_X, (xs << 16) | ys); 1611 regw(sc, SRC_WIDTH1, width); 1612 regw(sc, DST_Y_X, (xd << 16) | yd); 1613 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1614 } 1615 1616 static void 1617 mach64_setup_mono(struct mach64_softc *sc, int xd, int yd, int width, 1618 int height, uint32_t fg, uint32_t bg) 1619 { 1620 wait_for_idle(sc); 1621 regw(sc, DP_WRITE_MASK, 0xff); /* XXX only good for 8 bit */ 1622 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_1BPP | HOST_1BPP); 1623 regw(sc, DP_SRC, MONO_SRC_HOST | BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR); 1624 regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC); 1625 regw(sc, CLR_CMP_CNTL ,0); /* no transparency */ 1626 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1627 regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT); 1628 regw(sc, HOST_CNTL, HOST_BYTE_ALIGN); 1629 regw(sc, DP_BKGD_CLR, bg); 1630 regw(sc, DP_FRGD_CLR, fg); 1631 regw(sc, SRC_Y_X, 0); 1632 regw(sc, SRC_WIDTH1, width); 1633 regw(sc, DST_Y_X, (xd << 16) | yd); 1634 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1635 /* now feed the data into the chip */ 1636 } 1637 1638 static void 1639 mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data) 1640 { 1641 int i; 1642 uint32_t latch = 0, bork; 1643 int shift = 0; 1644 int reg = 0; 1645 1646 for (i = 0; i < count; i++) { 1647 bork = data[i]; 1648 latch |= (bork << shift); 1649 if (shift == 24) { 1650 regw(sc, HOST_DATA0 + reg, latch); 1651 latch = 0; 1652 shift = 0; 1653 reg = (reg + 4) & 0x3c; 1654 } else 1655 shift += 8; 1656 } 1657 if (shift != 0) /* 24 */ 1658 regw(sc, HOST_DATA0 + reg, latch); 1659 } 1660 1661 1662 static void 1663 mach64_rectfill(struct mach64_softc *sc, int x, int y, int width, int height, 1664 int colour) 1665 { 1666 wait_for_idle(sc); 1667 regw(sc, DP_WRITE_MASK, 0xff); 1668 regw(sc, DP_FRGD_CLR, colour); 1669 regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP); 1670 regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR); 1671 regw(sc, DP_MIX, MIX_SRC << 16); 1672 regw(sc, CLR_CMP_CNTL, 0); /* no transparency */ 1673 regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT); 1674 regw(sc, DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 1675 1676 regw(sc, SRC_Y_X, (x << 16) | y); 1677 regw(sc, SRC_WIDTH1, width); 1678 regw(sc, DST_Y_X, (x << 16) | y); 1679 regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height); 1680 } 1681 1682 static void 1683 mach64_clearscreen(struct mach64_softc *sc) 1684 { 1685 mach64_rectfill(sc, 0, 0, sc->virt_x, sc->virt_y, sc->sc_bg); 1686 } 1687 1688 1689 #if 0 1690 static void 1691 mach64_showpal(struct mach64_softc *sc) 1692 { 1693 int i, x = 0; 1694 1695 for (i = 0; i < 16; i++) { 1696 mach64_rectfill(sc, x, 0, 64, 64, i); 1697 x += 64; 1698 } 1699 } 1700 #endif 1701 1702 /* 1703 * wsdisplay_accessops 1704 */ 1705 1706 static int 1707 mach64_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, 1708 struct lwp *l) 1709 { 1710 struct vcons_data *vd = v; 1711 struct mach64_softc *sc = vd->cookie; 1712 struct wsdisplay_fbinfo *wdf; 1713 struct vcons_screen *ms = vd->active; 1714 1715 switch (cmd) { 1716 case WSDISPLAYIO_GTYPE: 1717 /* XXX is this the right type to return? */ 1718 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 1719 return 0; 1720 1721 case WSDISPLAYIO_LINEBYTES: 1722 *(u_int *)data = sc->virt_x * sc->bits_per_pixel / 8; 1723 return 0; 1724 1725 case WSDISPLAYIO_GINFO: 1726 wdf = (void *)data; 1727 wdf->height = sc->virt_y; 1728 wdf->width = sc->virt_x; 1729 wdf->depth = sc->bits_per_pixel; 1730 wdf->cmsize = 256; 1731 return 0; 1732 1733 case WSDISPLAYIO_GETCMAP: 1734 return mach64_getcmap(sc, 1735 (struct wsdisplay_cmap *)data); 1736 1737 case WSDISPLAYIO_PUTCMAP: 1738 return mach64_putcmap(sc, 1739 (struct wsdisplay_cmap *)data); 1740 1741 /* PCI config read/write passthrough. */ 1742 case PCI_IOC_CFGREAD: 1743 case PCI_IOC_CFGWRITE: 1744 return pci_devioctl(sc->sc_pc, sc->sc_pcitag, 1745 cmd, data, flag, l); 1746 1747 case WSDISPLAYIO_GET_BUSID: 1748 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1749 sc->sc_pcitag, data); 1750 1751 case WSDISPLAYIO_SMODE: { 1752 int new_mode = *(int*)data; 1753 if (new_mode != sc->sc_mode) { 1754 sc->sc_mode = new_mode; 1755 if ((new_mode == WSDISPLAYIO_MODE_EMUL) 1756 && (ms != NULL)) 1757 { 1758 /* restore initial video mode */ 1759 mach64_init(sc); 1760 mach64_init_engine(sc); 1761 mach64_init_lut(sc); 1762 mach64_modeswitch(sc, sc->sc_my_mode); 1763 vcons_redraw_screen(ms); 1764 } 1765 } 1766 } 1767 return 0; 1768 case WSDISPLAYIO_GET_EDID: { 1769 struct wsdisplayio_edid_info *d = data; 1770 return wsdisplayio_get_edid(sc->sc_dev, d); 1771 } 1772 } 1773 return EPASSTHROUGH; 1774 } 1775 1776 static paddr_t 1777 mach64_mmap(void *v, void *vs, off_t offset, int prot) 1778 { 1779 struct vcons_data *vd = v; 1780 struct mach64_softc *sc = vd->cookie; 1781 paddr_t pa; 1782 pcireg_t reg; 1783 1784 #ifndef __sparc64__ 1785 /* 1786 *'regular' framebuffer mmap()ing 1787 * disabled on sparc64 because some ATI firmware likes to map some PCI 1788 * resources to addresses that would collide with this ( like some Rage 1789 * IIc which uses 0x2000 for the 2nd register block ) 1790 * Other 64bit architectures might run into similar problems. 1791 */ 1792 if (offset<sc->sc_apersize) { 1793 pa = bus_space_mmap(sc->sc_memt, sc->sc_aperbase, offset, 1794 prot, BUS_SPACE_MAP_LINEAR); 1795 return pa; 1796 } 1797 #endif 1798 1799 /* 1800 * restrict all other mappings to processes with superuser privileges 1801 * or the kernel itself 1802 */ 1803 if (kauth_authorize_generic(kauth_cred_get(), KAUTH_GENERIC_ISSUSER, 1804 NULL) != 0) { 1805 return -1; 1806 } 1807 1808 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x18) & 0xffffff00); 1809 if (reg != sc->sc_regphys) { 1810 #ifdef DIAGNOSTIC 1811 printf("%s: BAR 0x18 changed! (%x %x)\n", 1812 device_xname(sc->sc_dev), (uint32_t)sc->sc_regphys, 1813 (uint32_t)reg); 1814 #endif 1815 sc->sc_regphys = reg; 1816 } 1817 1818 reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x10) & 0xffffff00); 1819 if (reg != sc->sc_aperphys) { 1820 #ifdef DIAGNOSTIC 1821 printf("%s: BAR 0x10 changed! (%x %x)\n", 1822 device_xname(sc->sc_dev), (uint32_t)sc->sc_aperphys, 1823 (uint32_t)reg); 1824 #endif 1825 sc->sc_aperphys = reg; 1826 } 1827 1828 if ((offset >= sc->sc_aperphys) && 1829 (offset < (sc->sc_aperphys + sc->sc_apersize))) { 1830 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1831 BUS_SPACE_MAP_LINEAR); 1832 return pa; 1833 } 1834 1835 if ((offset >= sc->sc_regphys) && 1836 (offset < (sc->sc_regphys + sc->sc_regsize))) { 1837 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1838 BUS_SPACE_MAP_LINEAR); 1839 return pa; 1840 } 1841 1842 if ((offset >= sc->sc_rom.vb_base) && 1843 (offset < (sc->sc_rom.vb_base + sc->sc_rom.vb_size))) { 1844 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 1845 BUS_SPACE_MAP_LINEAR); 1846 return pa; 1847 } 1848 1849 #ifdef PCI_MAGIC_IO_RANGE 1850 if ((offset >= PCI_MAGIC_IO_RANGE) && 1851 (offset <= PCI_MAGIC_IO_RANGE + 0x10000)) { 1852 return bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1853 0, prot, BUS_SPACE_MAP_LINEAR); 1854 } 1855 #endif 1856 1857 return -1; 1858 } 1859 1860 /* set ri->ri_bits according to fb, ri_xorigin and ri_yorigin */ 1861 static void 1862 set_address(struct rasops_info *ri, void *fb) 1863 { 1864 #ifdef notdef 1865 printf(" %d %d %d\n", ri->ri_xorigin, ri->ri_yorigin, ri->ri_stride); 1866 #endif 1867 ri->ri_bits = (void *)((char *)fb + ri->ri_stride * ri->ri_yorigin + 1868 ri->ri_xorigin); 1869 } 1870 1871 #if 0 1872 static int 1873 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data) 1874 { 1875 1876 return 0; 1877 } 1878 #endif 1879 1880 void 1881 machfb_blank(struct mach64_softc *sc, int blank) 1882 { 1883 uint32_t reg; 1884 1885 #define MACH64_BLANK (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS) 1886 1887 switch (blank) 1888 { 1889 case 0: 1890 reg = regr(sc, CRTC_GEN_CNTL); 1891 regw(sc, CRTC_GEN_CNTL, reg & ~(MACH64_BLANK)); 1892 sc->sc_blanked = 0; 1893 break; 1894 case 1: 1895 reg = regr(sc, CRTC_GEN_CNTL); 1896 regw(sc, CRTC_GEN_CNTL, reg | (MACH64_BLANK)); 1897 sc->sc_blanked = 1; 1898 break; 1899 default: 1900 break; 1901 } 1902 } 1903 1904 /* framebuffer device support */ 1905 #ifdef __sparc__ 1906 1907 static void 1908 machfb_unblank(device_t dev) 1909 { 1910 struct mach64_softc *sc = device_private(dev); 1911 1912 machfb_blank(sc, 0); 1913 } 1914 1915 static void 1916 machfb_fbattach(struct mach64_softc *sc) 1917 { 1918 struct fbdevice *fb = &sc->sc_fb; 1919 1920 fb->fb_device = sc->sc_dev; 1921 fb->fb_driver = &machfb_fbdriver; 1922 1923 fb->fb_type.fb_cmsize = 256; 1924 fb->fb_type.fb_size = sc->memsize; 1925 1926 fb->fb_type.fb_type = FBTYPE_GENERIC_PCI; 1927 fb->fb_flags = sc->sc_dev->dv_cfdata->cf_flags & FB_USERMASK; 1928 fb->fb_type.fb_depth = sc->bits_per_pixel; 1929 fb->fb_type.fb_width = sc->virt_x; 1930 fb->fb_type.fb_height = sc->virt_y; 1931 1932 fb->fb_pixels = sc->sc_aperture; 1933 fb_attach(fb, sc->sc_console); 1934 } 1935 1936 int 1937 machfb_fbopen(dev_t dev, int flags, int mode, struct lwp *l) 1938 { 1939 struct mach64_softc *sc; 1940 1941 sc = device_lookup_private(&machfb_cd, minor(dev)); 1942 if (sc == NULL) 1943 return ENXIO; 1944 sc->sc_locked = 1; 1945 1946 #ifdef MACHFB_DEBUG 1947 printf("machfb_fbopen(%d)\n", minor(dev)); 1948 #endif 1949 return 0; 1950 } 1951 1952 int 1953 machfb_fbclose(dev_t dev, int flags, int mode, struct lwp *l) 1954 { 1955 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 1956 1957 #ifdef MACHFB_DEBUG 1958 printf("machfb_fbclose()\n"); 1959 #endif 1960 mach64_init_engine(sc); 1961 mach64_init_lut(sc); 1962 sc->sc_locked = 0; 1963 return 0; 1964 } 1965 1966 int 1967 machfb_fbioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 1968 { 1969 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 1970 1971 #ifdef MACHFB_DEBUG 1972 printf("machfb_fbioctl(%d, %lx)\n", minor(dev), cmd); 1973 #endif 1974 switch (cmd) { 1975 case FBIOGTYPE: 1976 *(struct fbtype *)data = sc->sc_fb.fb_type; 1977 break; 1978 1979 case FBIOGATTR: 1980 #define fba ((struct fbgattr *)data) 1981 fba->real_type = sc->sc_fb.fb_type.fb_type; 1982 fba->owner = 0; /* XXX ??? */ 1983 fba->fbtype = sc->sc_fb.fb_type; 1984 fba->sattr.flags = 0; 1985 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 1986 fba->sattr.dev_specific[0] = sc->sc_nbus; 1987 fba->sattr.dev_specific[1] = sc->sc_ndev; 1988 fba->sattr.dev_specific[2] = sc->sc_nfunc; 1989 fba->sattr.dev_specific[3] = -1; 1990 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 1991 fba->emu_types[1] = -1; 1992 #undef fba 1993 break; 1994 1995 #if 0 1996 case FBIOGETCMAP: 1997 #define p ((struct fbcmap *)data) 1998 return bt_getcmap(p, &sc->sc_cmap, 256, 1); 1999 2000 case FBIOPUTCMAP: 2001 /* copy to software map */ 2002 error = bt_putcmap(p, &sc->sc_cmap, 256, 1); 2003 if (error) 2004 return error; 2005 /* now blast them into the chip */ 2006 /* XXX should use retrace interrupt */ 2007 cg6_loadcmap(sc, p->index, p->count); 2008 #undef p 2009 break; 2010 #endif 2011 case FBIOGVIDEO: 2012 *(int *)data = sc->sc_blanked; 2013 break; 2014 2015 case FBIOSVIDEO: 2016 machfb_blank(sc, *(int *)data); 2017 break; 2018 2019 #if 0 2020 case FBIOGCURSOR: 2021 break; 2022 2023 case FBIOSCURSOR: 2024 break; 2025 2026 case FBIOGCURPOS: 2027 *(struct fbcurpos *)data = sc->sc_cursor.cc_pos; 2028 break; 2029 2030 case FBIOSCURPOS: 2031 sc->sc_cursor.cc_pos = *(struct fbcurpos *)data; 2032 break; 2033 2034 case FBIOGCURMAX: 2035 /* max cursor size is 32x32 */ 2036 ((struct fbcurpos *)data)->x = 32; 2037 ((struct fbcurpos *)data)->y = 32; 2038 break; 2039 #endif 2040 case PCI_IOC_CFGREAD: 2041 case PCI_IOC_CFGWRITE: { 2042 int ret; 2043 ret = pci_devioctl(sc->sc_pc, sc->sc_pcitag, 2044 cmd, data, flags, l); 2045 2046 #ifdef MACHFB_DEBUG 2047 printf("pci_devioctl: %d\n", ret); 2048 #endif 2049 return ret; 2050 } 2051 2052 case WSDISPLAYIO_GET_BUSID: 2053 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 2054 sc->sc_pcitag, data); 2055 2056 default: 2057 return ENOTTY; 2058 } 2059 #ifdef MACHFB_DEBUG 2060 printf("machfb_fbioctl done\n"); 2061 #endif 2062 return 0; 2063 } 2064 2065 paddr_t 2066 machfb_fbmmap(dev_t dev, off_t off, int prot) 2067 { 2068 struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev)); 2069 2070 if (sc != NULL) 2071 return mach64_mmap(&sc->vd, NULL, off, prot); 2072 2073 return 0; 2074 } 2075 2076 #endif /* __sparc__ */ 2077