xref: /netbsd-src/sys/dev/pci/machfb.c (revision 46f5119e40af2e51998f686b2fdcc76b5488f7f3)
1 /*	$NetBSD: machfb.c,v 1.65 2011/05/10 18:31:33 dyoung Exp $	*/
2 
3 /*
4  * Copyright (c) 2002 Bang Jun-Young
5  * Copyright (c) 2005, 2006, 2007 Michael Lorenz
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. The name of the author may not be used to endorse or promote products
17  *    derived from this software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29  */
30 
31 /*
32  * Some code is derived from ATI Rage Pro and Derivatives Programmer's Guide.
33  */
34 
35 #include <sys/cdefs.h>
36 __KERNEL_RCSID(0,
37 	"$NetBSD: machfb.c,v 1.65 2011/05/10 18:31:33 dyoung Exp $");
38 
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/kernel.h>
42 #include <sys/device.h>
43 #include <sys/malloc.h>
44 #include <sys/callout.h>
45 #include <sys/lwp.h>
46 #include <sys/kauth.h>
47 
48 #include <dev/videomode/videomode.h>
49 #include <dev/videomode/edidvar.h>
50 
51 #include <dev/pci/pcivar.h>
52 #include <dev/pci/pcireg.h>
53 #include <dev/pci/pcidevs.h>
54 #include <dev/pci/pciio.h>
55 #include <dev/pci/machfbreg.h>
56 
57 #ifdef __sparc__
58 #include <dev/sun/fbio.h>
59 #include <dev/sun/fbvar.h>
60 #include <sys/conf.h>
61 #else
62 #include <dev/wscons/wsdisplayvar.h>
63 #endif
64 
65 #include <dev/wscons/wsconsio.h>
66 #include <dev/wsfont/wsfont.h>
67 #include <dev/rasops/rasops.h>
68 #include <dev/pci/wsdisplay_pci.h>
69 
70 #include <dev/wscons/wsdisplay_vconsvar.h>
71 
72 #include "opt_wsemul.h"
73 #include "opt_machfb.h"
74 
75 #define MACH64_REG_SIZE		1024
76 #define MACH64_REG_OFF		0x7ffc00
77 
78 #define	NBARS		3	/* number of Mach64 PCI BARs */
79 
80 struct vga_bar {
81 	bus_addr_t vb_base;
82 	pcireg_t vb_busaddr;
83 	bus_size_t vb_size;
84 	pcireg_t vb_type;
85 	int vb_flags;
86 };
87 
88 struct mach64_softc {
89 	device_t sc_dev;
90 #ifdef __sparc__
91 	struct fbdevice sc_fb;
92 #endif
93 	pci_chipset_tag_t sc_pc;
94 	pcitag_t sc_pcitag;
95 
96 	struct vga_bar sc_bars[NBARS];
97 	struct vga_bar sc_rom;
98 
99 #define sc_aperbase 	sc_bars[0].vb_base
100 #define sc_apersize	sc_bars[0].vb_size
101 #define sc_aperphys 	sc_bars[0].vb_busaddr
102 
103 #define sc_iobase	sc_bars[1].vb_base
104 #define sc_iosize	sc_bars[1].vb_size
105 
106 #define sc_regbase	sc_bars[2].vb_base
107 #define sc_regsize	sc_bars[2].vb_size
108 #define sc_regphys	sc_bars[2].vb_busaddr
109 
110 	bus_space_tag_t sc_regt;
111 	bus_space_tag_t sc_memt;
112 	bus_space_tag_t sc_iot;
113 	bus_space_handle_t sc_regh;
114 	bus_space_handle_t sc_memh;
115 	void *sc_aperture;		/* mapped aperture vaddr */
116 	void *sc_registers;		/* mapped registers vaddr */
117 
118 	uint32_t sc_nbus, sc_ndev, sc_nfunc;
119 	size_t memsize;
120 	int memtype;
121 
122 	int sc_mode;
123 	int sc_bg;
124 	int sc_locked;
125 
126 	int has_dsp;
127 	int bits_per_pixel;
128 	int max_x;
129 	int max_y;
130 	int virt_x;
131 	int virt_y;
132 	int color_depth;
133 
134 	int mem_freq;
135 	int ramdac_freq;
136 	int ref_freq;
137 
138 	int ref_div;
139 	int log2_vclk_post_div;
140 	int vclk_post_div;
141 	int vclk_fb_div;
142 	int mclk_post_div;
143 	int mclk_fb_div;
144 	int sc_clock;	/* which clock to use */
145 
146 	struct videomode *sc_my_mode;
147 	int sc_edid_size;
148 	uint8_t sc_edid_data[1024];
149 
150 	u_char sc_cmap_red[256];
151 	u_char sc_cmap_green[256];
152 	u_char sc_cmap_blue[256];
153 	int sc_dacw, sc_blanked, sc_console;
154 	struct vcons_data vd;
155 };
156 
157 struct mach64_crtcregs {
158 	uint32_t h_total_disp;
159 	uint32_t h_sync_strt_wid;
160 	uint32_t v_total_disp;
161 	uint32_t v_sync_strt_wid;
162 	uint32_t gen_cntl;
163 	uint32_t clock_cntl;
164 	uint32_t color_depth;
165 	uint32_t dot_clock;
166 };
167 
168 static struct {
169 	uint16_t chip_id;
170 	uint32_t ramdac_freq;
171 } const mach64_info[] = {
172 	{ PCI_PRODUCT_ATI_MACH64_GX, 135000 },
173 	{ PCI_PRODUCT_ATI_MACH64_CX, 135000 },
174 	{ PCI_PRODUCT_ATI_MACH64_CT, 135000 },
175 	{ PCI_PRODUCT_ATI_RAGE_PRO_AGP, 230000 },
176 	{ PCI_PRODUCT_ATI_RAGE_PRO_AGP1X, 230000 },
177 	{ PCI_PRODUCT_ATI_RAGE_PRO_PCI_B, 230000 },
178 	{ PCI_PRODUCT_ATI_RAGE_XL_AGP, 230000 },
179 	{ PCI_PRODUCT_ATI_RAGE_PRO_PCI_P, 230000 },
180 	{ PCI_PRODUCT_ATI_RAGE_PRO_PCI_L, 230000 },
181 	{ PCI_PRODUCT_ATI_RAGE_XL_PCI, 230000 },
182 	{ PCI_PRODUCT_ATI_RAGE_XL_PCI66, 230000 },
183 	{ PCI_PRODUCT_ATI_RAGE_II, 135000 },
184 	{ PCI_PRODUCT_ATI_RAGE_IIP, 200000 },
185 	{ PCI_PRODUCT_ATI_RAGE_IIC_PCI, 230000 },
186 	{ PCI_PRODUCT_ATI_RAGE_IIC_AGP_B, 230000 },
187 	{ PCI_PRODUCT_ATI_RAGE_IIC_AGP_P, 230000 },
188 #if 0
189 	{ PCI_PRODUCT_ATI_RAGE_MOB_M3_PCI, 230000 },
190 	{ PCI_PRODUCT_ATI_RAGE_MOB_M3_AGP, 230000 },
191 	{ PCI_PRODUCT_ATI_RAGE_MOBILITY, 230000 },
192 #endif
193 	{ PCI_PRODUCT_ATI_RAGE_LT_PRO_AGP, 230000 },
194 	{ PCI_PRODUCT_ATI_RAGE_LT_PRO, 230000 },
195 	{ PCI_PRODUCT_ATI_RAGE_LT, 230000 },
196 	{ PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI, 230000 },
197 	{ PCI_PRODUCT_ATI_MACH64_VT, 170000 },
198 	{ PCI_PRODUCT_ATI_MACH64_VTB, 200000 },
199 	{ PCI_PRODUCT_ATI_MACH64_VT4, 230000 }
200 };
201 
202 static int mach64_chip_id, mach64_chip_rev;
203 static struct videomode default_mode = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
204 
205 static const char *mach64_gx_memtype_names[] = {
206 	"DRAM", "VRAM", "VRAM", "DRAM",
207 	"DRAM", "VRAM", "VRAM", "(unknown type)"
208 };
209 
210 static const char *mach64_memtype_names[] = {
211 	"(N/A)", "DRAM", "EDO DRAM", "EDO DRAM", "SDRAM", "SGRAM", "WRAM",
212 	"(unknown type)"
213 };
214 
215 static struct videomode mach64_modes[] = {
216 	/* 640x400 @ 70 Hz, 31.5 kHz */
217 	{ 25175, 640, 664, 760, 800, 400, 409, 411, 450, 0, NULL, },
218 	/* 640x480 @ 72 Hz, 36.5 kHz */
219 	{ 25175, 640, 664, 760, 800, 480, 491, 493, 525, 0, NULL, },
220 	/* 800x600 @ 72 Hz, 48.0 kHz */
221 	{ 50000, 800, 856, 976, 1040, 600, 637, 643, 666,
222 	  VID_PHSYNC | VID_PVSYNC, NULL, },
223 	/* 1024x768 @ 70 Hz, 56.5 kHz */
224 	{ 75000, 1024, 1048, 1184, 1328, 768, 771, 777, 806,
225 	  VID_NHSYNC | VID_NVSYNC, NULL, },
226 	/* 1152x864 @ 70 Hz, 62.4 kHz */
227 	{ 92000, 1152, 1208, 1368, 1474, 864, 865, 875, 895, 0, NULL, },
228 	/* 1280x1024 @ 70 Hz, 74.59 kHz */
229 	{ 126500, 1280, 1312, 1472, 1696, 1024, 1032, 1040, 1068,
230 	  VID_NHSYNC | VID_NVSYNC, NULL, }
231 };
232 
233 extern const u_char rasops_cmap[768];
234 
235 static int	mach64_match(device_t, cfdata_t, void *);
236 static void	mach64_attach(device_t, device_t, void *);
237 
238 CFATTACH_DECL_NEW(machfb, sizeof(struct mach64_softc), mach64_match, mach64_attach,
239     NULL, NULL);
240 
241 static void	mach64_init(struct mach64_softc *);
242 static int	mach64_get_memsize(struct mach64_softc *);
243 static int	mach64_get_max_ramdac(struct mach64_softc *);
244 
245 #if defined(__sparc__) || defined(__powerpc__)
246 static void	mach64_get_mode(struct mach64_softc *, struct videomode *);
247 #endif
248 
249 static int	mach64_calc_crtcregs(struct mach64_softc *,
250 				     struct mach64_crtcregs *,
251 				     struct videomode *);
252 static void	mach64_set_crtcregs(struct mach64_softc *,
253 				    struct mach64_crtcregs *);
254 
255 static int	mach64_modeswitch(struct mach64_softc *, struct videomode *);
256 static void	mach64_set_dsp(struct mach64_softc *);
257 static void	mach64_set_pll(struct mach64_softc *, int);
258 static void	mach64_reset_engine(struct mach64_softc *);
259 static void	mach64_init_engine(struct mach64_softc *);
260 #if 0
261 static void	mach64_adjust_frame(struct mach64_softc *, int, int);
262 #endif
263 static void	mach64_init_lut(struct mach64_softc *);
264 
265 static void	mach64_init_screen(void *, struct vcons_screen *, int, long *);
266 static int 	mach64_set_screentype(struct mach64_softc *,
267 				      const struct wsscreen_descr *);
268 static int	mach64_is_console(struct mach64_softc *);
269 
270 static void	mach64_cursor(void *, int, int, int);
271 #if 0
272 static int	mach64_mapchar(void *, int, u_int *);
273 #endif
274 static void	mach64_putchar(void *, int, int, u_int, long);
275 static void	mach64_copycols(void *, int, int, int, int);
276 static void	mach64_erasecols(void *, int, int, int, long);
277 static void	mach64_copyrows(void *, int, int, int);
278 static void	mach64_eraserows(void *, int, int, long);
279 static void 	mach64_clearscreen(struct mach64_softc *);
280 
281 static int	mach64_putcmap(struct mach64_softc *, struct wsdisplay_cmap *);
282 static int	mach64_getcmap(struct mach64_softc *, struct wsdisplay_cmap *);
283 static int	mach64_putpalreg(struct mach64_softc *, uint8_t, uint8_t,
284 				 uint8_t, uint8_t);
285 static void	mach64_bitblt(struct mach64_softc *, int, int, int, int, int,
286 			      int, int, int) ;
287 static void	mach64_rectfill(struct mach64_softc *, int, int, int, int, int);
288 static void	mach64_setup_mono(struct mach64_softc *, int, int, int, int,
289 				  uint32_t, uint32_t);
290 static void	mach64_feed_bytes(struct mach64_softc *, int, uint8_t *);
291 #if 0
292 static void	mach64_showpal(struct mach64_softc *);
293 #endif
294 
295 static void	set_address(struct rasops_info *, void *);
296 static void	machfb_blank(struct mach64_softc *, int);
297 static int	machfb_drm_print(void *, const char *);
298 
299 static struct wsscreen_descr mach64_defaultscreen = {
300 	"default",
301 	80, 30,
302 	NULL,
303 	8, 16,
304 	WSSCREEN_WSCOLORS | WSSCREEN_HILIT,
305 	&default_mode
306 }, mach64_80x25_screen = {
307 	"80x25", 80, 25,
308 	NULL,
309 	8, 16,
310 	WSSCREEN_WSCOLORS | WSSCREEN_HILIT,
311 	&mach64_modes[0]
312 }, mach64_80x30_screen = {
313 	"80x30", 80, 30,
314 	NULL,
315 	8, 16,
316 	WSSCREEN_WSCOLORS | WSSCREEN_HILIT,
317 	&mach64_modes[1]
318 }, mach64_80x40_screen = {
319 	"80x40", 80, 40,
320 	NULL,
321 	8, 10,
322 	WSSCREEN_WSCOLORS | WSSCREEN_HILIT,
323 	&mach64_modes[0]
324 }, mach64_80x50_screen = {
325 	"80x50", 80, 50,
326 	NULL,
327 	8, 8,
328 	WSSCREEN_WSCOLORS | WSSCREEN_HILIT,
329 	&mach64_modes[0]
330 }, mach64_100x37_screen = {
331 	"100x37", 100, 37,
332 	NULL,
333 	8, 16,
334 	WSSCREEN_WSCOLORS | WSSCREEN_HILIT,
335 	&mach64_modes[2]
336 }, mach64_128x48_screen = {
337 	"128x48", 128, 48,
338 	NULL,
339 	8, 16,
340 	WSSCREEN_WSCOLORS | WSSCREEN_HILIT,
341 	&mach64_modes[3]
342 }, mach64_144x54_screen = {
343 	"144x54", 144, 54,
344 	NULL,
345 	8, 16,
346 	WSSCREEN_WSCOLORS | WSSCREEN_HILIT,
347 	&mach64_modes[4]
348 }, mach64_160x64_screen = {
349 	"160x54", 160, 64,
350 	NULL,
351 	8, 16,
352 	WSSCREEN_WSCOLORS | WSSCREEN_HILIT,
353 	&mach64_modes[5]
354 };
355 
356 static const struct wsscreen_descr *_mach64_scrlist[] = {
357 	&mach64_defaultscreen,
358 	&mach64_80x25_screen,
359 	&mach64_80x30_screen,
360 	&mach64_80x40_screen,
361 	&mach64_80x50_screen,
362 	&mach64_100x37_screen,
363 	&mach64_128x48_screen,
364 	&mach64_144x54_screen,
365 	&mach64_160x64_screen
366 };
367 
368 static struct wsscreen_list mach64_screenlist = {
369 	__arraycount(_mach64_scrlist),
370 	_mach64_scrlist
371 };
372 
373 static int	mach64_ioctl(void *, void *, u_long, void *, int,
374 		             struct lwp *);
375 static paddr_t	mach64_mmap(void *, void *, off_t, int);
376 
377 #if 0
378 static int	mach64_load_font(void *, void *, struct wsdisplay_font *);
379 #endif
380 
381 static struct wsdisplay_accessops mach64_accessops = {
382 	mach64_ioctl,
383 	mach64_mmap,
384 	NULL,			/* vcons_alloc_screen */
385 	NULL,			/* vcons_free_screen */
386 	NULL,			/* vcons_show_screen */
387 	NULL,			/* load_font */
388 	NULL,			/* polls */
389 	NULL,			/* scroll */
390 };
391 
392 static struct vcons_screen mach64_console_screen;
393 
394 /* framebuffer device, SPARC-only so far */
395 #ifdef __sparc__
396 
397 static void	machfb_unblank(device_t);
398 static void	machfb_fbattach(struct mach64_softc *);
399 
400 extern struct cfdriver machfb_cd;
401 
402 dev_type_open(machfb_fbopen);
403 dev_type_close(machfb_fbclose);
404 dev_type_ioctl(machfb_fbioctl);
405 dev_type_mmap(machfb_fbmmap);
406 
407 /* frame buffer generic driver */
408 static struct fbdriver machfb_fbdriver = {
409 	machfb_unblank, machfb_fbopen, machfb_fbclose, machfb_fbioctl, nopoll,
410 	machfb_fbmmap, nokqfilter
411 };
412 
413 #endif /* __sparc__ */
414 
415 /*
416  * Inline functions for getting access to register aperture.
417  */
418 
419 static inline uint32_t
420 regr(struct mach64_softc *sc, uint32_t index)
421 {
422 	return bus_space_read_4(sc->sc_regt, sc->sc_regh, index);
423 }
424 
425 static inline uint8_t
426 regrb(struct mach64_softc *sc, uint32_t index)
427 {
428 	return bus_space_read_1(sc->sc_regt, sc->sc_regh, index);
429 }
430 
431 static inline void
432 regw(struct mach64_softc *sc, uint32_t index, uint32_t data)
433 {
434 	bus_space_write_4(sc->sc_regt, sc->sc_regh, index, data);
435 	bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 4,
436 	    BUS_SPACE_BARRIER_WRITE);
437 }
438 
439 static inline void
440 regwb(struct mach64_softc *sc, uint32_t index, uint8_t data)
441 {
442 	bus_space_write_1(sc->sc_regt, sc->sc_regh, index, data);
443 	bus_space_barrier(sc->sc_regt, sc->sc_regh, index, 1,
444 	    BUS_SPACE_BARRIER_WRITE);
445 }
446 
447 static inline void
448 regwb_pll(struct mach64_softc *sc, uint32_t index, uint8_t data)
449 {
450 	uint32_t reg;
451 
452 	reg = regr(sc, CLOCK_CNTL);
453 	reg |= PLL_WR_EN;
454 	regw(sc, CLOCK_CNTL, reg);
455 	reg &= ~(PLL_ADDR | PLL_DATA);
456 	reg |= (index & 0x3f) << PLL_ADDR_SHIFT;
457 	reg |= data << PLL_DATA_SHIFT;
458 	reg |= CLOCK_STROBE;
459 	regw(sc, CLOCK_CNTL, reg);
460 	reg &= ~PLL_WR_EN;
461 	regw(sc, CLOCK_CNTL, reg);
462 }
463 
464 static inline uint8_t
465 regrb_pll(struct mach64_softc *sc, uint32_t index)
466 {
467 
468 	regwb(sc, CLOCK_CNTL + 1, index << 2);
469 	return regrb(sc, CLOCK_CNTL + 2);
470 }
471 
472 static inline void
473 wait_for_fifo(struct mach64_softc *sc, uint8_t v)
474 {
475 	while ((regr(sc, FIFO_STAT) & 0xffff) > (0x8000 >> v))
476 		continue;
477 }
478 
479 static inline void
480 wait_for_idle(struct mach64_softc *sc)
481 {
482 	wait_for_fifo(sc, 16);
483 	while ((regr(sc, GUI_STAT) & 1) != 0)
484 		continue;
485 }
486 
487 static int
488 mach64_match(device_t parent, cfdata_t match, void *aux)
489 {
490 	struct pci_attach_args *pa = (struct pci_attach_args *)aux;
491 	int i;
492 
493 	if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY ||
494 	    PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA)
495 		return 0;
496 
497 	for (i = 0; i < __arraycount(mach64_info); i++)
498 		if (PCI_PRODUCT(pa->pa_id) == mach64_info[i].chip_id) {
499 			mach64_chip_id = PCI_PRODUCT(pa->pa_id);
500 			mach64_chip_rev = PCI_REVISION(pa->pa_class);
501 			return 100;
502 		}
503 
504 	return 0;
505 }
506 
507 static void
508 mach64_attach(device_t parent, device_t self, void *aux)
509 {
510 	struct mach64_softc *sc = device_private(self);
511 	struct pci_attach_args *pa = aux;
512 	struct rasops_info *ri;
513 	prop_data_t edid_data;
514 	const struct videomode *mode = NULL;
515 	char devinfo[256];
516 	int bar, id, expected_id;
517 	int is_gx;
518 	const char **memtype_names;
519 	struct wsemuldisplaydev_attach_args aa;
520 	long defattr;
521 	int setmode, width, height;
522 	pcireg_t screg;
523 	uint32_t reg;
524 	const pcireg_t enables = PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE;
525 
526 	sc->sc_dev = self;
527 	sc->sc_pc = pa->pa_pc;
528 	sc->sc_pcitag = pa->pa_tag;
529 	sc->sc_dacw = -1;
530 	sc->sc_mode = WSDISPLAYIO_MODE_EMUL;
531 	sc->sc_nbus = pa->pa_bus;
532 	sc->sc_ndev = pa->pa_device;
533 	sc->sc_nfunc = pa->pa_function;
534 	sc->sc_locked = 0;
535 	sc->sc_iot = pa->pa_iot;
536 
537 	pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo));
538 	aprint_normal(": %s (rev. 0x%02x)\n", devinfo,
539 	    PCI_REVISION(pa->pa_class));
540 	aprint_naive(": Graphics processor\n");
541 #ifdef MACHFB_DEBUG
542 	printf(prop_dictionary_externalize(device_properties(self)));
543 #endif
544 
545 	/* enable memory and disable IO access */
546 	screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG);
547 	if ((screg & enables) != enables) {
548 		screg |= enables;
549 		pci_conf_write(sc->sc_pc, sc->sc_pcitag,
550 		    PCI_COMMAND_STATUS_REG, screg);
551 	}
552 	for (bar = 0; bar < NBARS; bar++) {
553 		reg = PCI_MAPREG_START + (bar * 4);
554 		sc->sc_bars[bar].vb_type = pci_mapreg_type(sc->sc_pc,
555 		    sc->sc_pcitag, reg);
556 		(void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg,
557 		    sc->sc_bars[bar].vb_type, &sc->sc_bars[bar].vb_base,
558 		    &sc->sc_bars[bar].vb_size, &sc->sc_bars[bar].vb_flags);
559 		sc->sc_bars[bar].vb_busaddr = pci_conf_read(sc->sc_pc,
560 		    sc->sc_pcitag, reg) & 0xfffffff0;
561 	}
562 	printf("%s: aperture size %08x\n", device_xname(sc->sc_dev),
563 	    (uint32_t)sc->sc_apersize);
564 
565 	sc->sc_rom.vb_type = PCI_MAPREG_TYPE_ROM;
566 	pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, PCI_MAPREG_ROM,
567 		    sc->sc_rom.vb_type, &sc->sc_rom.vb_base,
568 		    &sc->sc_rom.vb_size, &sc->sc_rom.vb_flags);
569 	sc->sc_memt = pa->pa_memt;
570 
571 	if (bus_space_map(sc->sc_memt, sc->sc_aperbase, sc->sc_apersize,
572 		BUS_SPACE_MAP_LINEAR, &sc->sc_memh)) {
573 		panic("%s: failed to map aperture", device_xname(sc->sc_dev));
574 	}
575 	sc->sc_aperture = (void *)bus_space_vaddr(sc->sc_memt, sc->sc_memh);
576 
577 	/* If the BAR was never mapped, fix it up in MMIO. */
578 	if(sc->sc_regsize == 0) {
579 		sc->sc_regsize = MACH64_REG_SIZE;
580 		sc->sc_regbase = sc->sc_aperbase + MACH64_REG_OFF;
581 		sc->sc_regphys = sc->sc_aperphys + MACH64_REG_OFF;
582 	}
583 
584 	sc->sc_regt = sc->sc_memt;
585 	bus_space_subregion(sc->sc_regt, sc->sc_memh, MACH64_REG_OFF,
586 	    sc->sc_regsize, &sc->sc_regh);
587 	sc->sc_registers = (char *)sc->sc_aperture + 0x7ffc00;
588 
589 	mach64_init(sc);
590 
591 	aprint_normal_dev(sc->sc_dev,
592 	    "%d MB aperture at 0x%08x, %d KB registers at 0x%08x\n",
593 	    (u_int)(sc->sc_apersize / (1024 * 1024)),
594 	    (u_int)sc->sc_aperphys, (u_int)(sc->sc_regsize / 1024),
595 	    (u_int)sc->sc_regphys);
596 
597 	printf("%s: %d KB ROM at 0x%08x\n", device_xname(sc->sc_dev),
598 	    (int)sc->sc_rom.vb_size >> 10, (uint32_t)sc->sc_rom.vb_base);
599 
600 	prop_dictionary_get_uint32(device_properties(self), "width", &width);
601 	prop_dictionary_get_uint32(device_properties(self), "height", &height);
602 
603 	if ((edid_data = prop_dictionary_get(device_properties(self), "EDID"))
604 	    != NULL) {
605 	    	struct edid_info ei;
606 
607 		sc->sc_edid_size = min(1024, prop_data_size(edid_data));
608 		memset(sc->sc_edid_data, 0, sizeof(sc->sc_edid_data));
609 		memcpy(sc->sc_edid_data, prop_data_data_nocopy(edid_data),
610 		    sc->sc_edid_size);
611 
612 		edid_parse(sc->sc_edid_data, &ei);
613 
614 #ifdef MACHFB_DEBUG
615 		edid_print(&ei);
616 #endif
617 		if (ei.edid_have_range) {
618 
619 			/* ei has dotclock in MHz, struct videomode in kHz */
620 			mode = pick_mode_by_dotclock(width, height,
621 			    ei.edid_range.er_max_clock * 1000);
622 			if (mode != NULL)
623 				printf("mode: %s\n", mode->name);
624 		}
625 	}
626 
627 	is_gx = 0;
628 	switch(mach64_chip_id) {
629 		case PCI_PRODUCT_ATI_MACH64_GX:
630 		case PCI_PRODUCT_ATI_MACH64_CX:
631 			is_gx = 1;
632 		case PCI_PRODUCT_ATI_MACH64_CT:
633 			sc->has_dsp = 0;
634 			break;
635 		case PCI_PRODUCT_ATI_MACH64_VT:
636 		case PCI_PRODUCT_ATI_RAGE_II:
637 			if((mach64_chip_rev & 0x07) == 0) {
638 				sc->has_dsp = 0;
639 				break;
640 			}
641 			/* Otherwise fall through. */
642 		default:
643 			sc->has_dsp = 1;
644 	}
645 
646 	memtype_names = is_gx ? mach64_gx_memtype_names : mach64_memtype_names;
647 
648 	sc->memsize = mach64_get_memsize(sc);
649 	if (sc->memsize == 8192)
650 		/* The last page is used as register aperture. */
651 		sc->memsize -= 4;
652 	if(is_gx)
653 		sc->memtype = (regr(sc, CONFIG_STAT0) >> 3) & 0x07;
654 	else
655 		sc->memtype = regr(sc, CONFIG_STAT0) & 0x07;
656 
657 	/* XXX is there any way to calculate reference frequency from
658 	   known values? */
659 	if ((mach64_chip_id == PCI_PRODUCT_ATI_RAGE_XL_PCI) ||
660 	    ((mach64_chip_id >= PCI_PRODUCT_ATI_RAGE_LT_PRO_PCI) &&
661 	    (mach64_chip_id <= PCI_PRODUCT_ATI_RAGE_LT_PRO))) {
662 		aprint_normal_dev(sc->sc_dev, "ref_freq=29.498MHz\n");
663 		sc->ref_freq = 29498;
664 	} else
665 		sc->ref_freq = 14318;
666 
667 	reg = regr(sc, CLOCK_CNTL);
668 	printf("CLOCK_CNTL: %08x\n", reg);
669 	sc->sc_clock = reg & 3;
670 	printf("using clock %d\n", sc->sc_clock);
671 
672 	sc->ref_div = regrb_pll(sc, PLL_REF_DIV);
673 	printf("ref_div: %d\n", sc->ref_div);
674 	sc->mclk_fb_div = regrb_pll(sc, MCLK_FB_DIV);
675 	printf("mclk_fb_div: %d\n", sc->mclk_fb_div);
676 	sc->mem_freq = (2 * sc->ref_freq * sc->mclk_fb_div) /
677 	    (sc->ref_div * 2);
678 	sc->mclk_post_div = (sc->mclk_fb_div * 2 * sc->ref_freq) /
679 	    (sc->mem_freq * sc->ref_div);
680 	sc->ramdac_freq = mach64_get_max_ramdac(sc);
681 	aprint_normal_dev(sc->sc_dev,
682 	    "%ld KB %s %d.%d MHz, maximum RAMDAC clock %d MHz\n",
683 	    (u_long)sc->memsize,
684 	    memtype_names[sc->memtype],
685 	    sc->mem_freq / 1000, sc->mem_freq % 1000,
686 	    sc->ramdac_freq / 1000);
687 
688 	id = regr(sc, CONFIG_CHIP_ID) & 0xffff;
689 	switch(mach64_chip_id) {
690 		case PCI_PRODUCT_ATI_MACH64_GX:
691 			expected_id = 0x00d7;
692 			break;
693 		case PCI_PRODUCT_ATI_MACH64_CX:
694 			expected_id = 0x0057;
695 			break;
696 		default:
697 			/* Most chip IDs match their PCI product ID. */
698 			expected_id = mach64_chip_id;
699 	}
700 
701 	if (id != expected_id) {
702 		aprint_error_dev(sc->sc_dev,
703 		    "chip ID mismatch, 0x%x != 0x%x\n", id, expected_id);
704 		return;
705 	}
706 
707 	sc->sc_console = mach64_is_console(sc);
708 #ifdef DIAGNOSTIC
709 	aprint_normal("gen_cntl: %08x\n", regr(sc, CRTC_GEN_CNTL));
710 #endif
711 #if defined(__sparc__) || defined(__powerpc__)
712 	if (sc->sc_console) {
713 		if (mode != NULL) {
714 			memcpy(&default_mode, mode, sizeof(struct videomode));
715 			setmode = 1;
716 		} else {
717 			mach64_get_mode(sc, &default_mode);
718 			setmode = 0;
719 		}
720 		sc->sc_my_mode = &default_mode;
721 	} else {
722 		/* fill in default_mode if it's empty */
723 		mach64_get_mode(sc, &default_mode);
724 		if (default_mode.dot_clock == 0) {
725 			memcpy(&default_mode, &mach64_modes[4],
726 			    sizeof(default_mode));
727 		}
728 		sc->sc_my_mode = &default_mode;
729 		setmode = 1;
730 	}
731 #else
732 	if (default_mode.dot_clock == 0) {
733 		memcpy(&default_mode, &mach64_modes[0],
734 		    sizeof(default_mode));
735 	}
736 	sc->sc_my_mode = &mach64_modes[0];
737 	setmode = 1;
738 #endif
739 
740 	sc->bits_per_pixel = 8;
741 	sc->virt_x = sc->sc_my_mode->hdisplay;
742 	sc->virt_y = sc->sc_my_mode->vdisplay;
743 	sc->max_x = sc->virt_x - 1;
744 	sc->max_y = (sc->memsize * 1024) /
745 	    (sc->virt_x * (sc->bits_per_pixel / 8)) - 1;
746 
747 	sc->color_depth = CRTC_PIX_WIDTH_8BPP;
748 
749 	mach64_init_engine(sc);
750 
751 	if (setmode)
752 		mach64_modeswitch(sc, sc->sc_my_mode);
753 
754 	aprint_normal_dev(sc->sc_dev,
755 	    "initial resolution %dx%d at %d bpp\n",
756 	    sc->sc_my_mode->hdisplay, sc->sc_my_mode->vdisplay,
757 	    sc->bits_per_pixel);
758 
759 #ifdef __sparc__
760 	machfb_fbattach(sc);
761 #endif
762 
763 	wsfont_init();
764 
765 	sc->sc_bg = WS_DEFAULT_BG;
766 	vcons_init(&sc->vd, sc, &mach64_defaultscreen, &mach64_accessops);
767 	sc->vd.init_screen = mach64_init_screen;
768 
769 	mach64_init_lut(sc);
770 	mach64_clearscreen(sc);
771 	machfb_blank(sc, 0);	/* unblank the screen */
772 
773 	if (sc->sc_console) {
774 
775 		vcons_init_screen(&sc->vd, &mach64_console_screen, 1,
776 		    &defattr);
777 		mach64_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC;
778 
779 		ri = &mach64_console_screen.scr_ri;
780 		mach64_defaultscreen.textops = &ri->ri_ops;
781 		mach64_defaultscreen.capabilities = ri->ri_caps;
782 		mach64_defaultscreen.nrows = ri->ri_rows;
783 		mach64_defaultscreen.ncols = ri->ri_cols;
784 
785 		wsdisplay_cnattach(&mach64_defaultscreen, ri, 0, 0, defattr);
786 		vcons_replay_msgbuf(&mach64_console_screen);
787 	} else {
788 		/*
789 		 * since we're not the console we can postpone the rest
790 		 * until someone actually allocates a screen for us
791 		 */
792 		mach64_modeswitch(sc, sc->sc_my_mode);
793 	}
794 
795 	aa.console = sc->sc_console;
796 	aa.scrdata = &mach64_screenlist;
797 	aa.accessops = &mach64_accessops;
798 	aa.accesscookie = &sc->vd;
799 
800 	config_found(self, &aa, wsemuldisplaydevprint);
801 
802 	config_found_ia(self, "drm", aux, machfb_drm_print);
803 }
804 
805 static int
806 machfb_drm_print(void *aux, const char *pnp)
807 {
808 	if (pnp)
809 		aprint_normal("direct rendering for %s", pnp);
810 	return (UNSUPP);
811 }
812 
813 static void
814 mach64_init_screen(void *cookie, struct vcons_screen *scr, int existing,
815     long *defattr)
816 {
817 	struct mach64_softc *sc = cookie;
818 	struct rasops_info *ri = &scr->scr_ri;
819 
820 /* XXX for now */
821 #define setmode 0
822 
823 	ri->ri_depth = sc->bits_per_pixel;
824 	ri->ri_width = sc->sc_my_mode->hdisplay;
825 	ri->ri_height = sc->sc_my_mode->vdisplay;
826 	ri->ri_stride = ri->ri_width;
827 	ri->ri_flg = RI_CENTER;
828 	set_address(ri, sc->sc_aperture);
829 
830 	if (existing) {
831 		ri->ri_flg |= RI_CLEAR;
832 		if (setmode && mach64_set_screentype(sc, scr->scr_type)) {
833 			panic("%s: failed to switch video mode",
834 			    device_xname(sc->sc_dev));
835 		}
836 	}
837 
838 	rasops_init(ri, sc->sc_my_mode->vdisplay / 8,
839 	    sc->sc_my_mode->hdisplay / 8);
840 	ri->ri_caps = WSSCREEN_WSCOLORS;
841 
842 	rasops_reconfig(ri, sc->sc_my_mode->vdisplay / ri->ri_font->fontheight,
843 		    sc->sc_my_mode->hdisplay / ri->ri_font->fontwidth);
844 
845 	/* enable acceleration */
846 	ri->ri_hw = scr;
847 	ri->ri_ops.copyrows = mach64_copyrows;
848 	ri->ri_ops.copycols = mach64_copycols;
849 	ri->ri_ops.eraserows = mach64_eraserows;
850 	ri->ri_ops.erasecols = mach64_erasecols;
851 	ri->ri_ops.cursor = mach64_cursor;
852 	ri->ri_ops.putchar = mach64_putchar;
853 }
854 
855 static void
856 mach64_init(struct mach64_softc *sc)
857 {
858 	uint32_t *p32, saved_value;
859 	uint8_t *p;
860 	int need_swap;
861 
862 	/*
863 	 * Test wether the aperture is byte swapped or not
864 	 */
865 	p32 = (uint32_t*)sc->sc_aperture;
866 	saved_value = *p32;
867 	p = (uint8_t*)(u_long)sc->sc_aperture;
868 	*p32 = 0x12345678;
869 	if (p[0] == 0x12 && p[1] == 0x34 && p[2] == 0x56 && p[3] == 0x78)
870 		need_swap = 0;
871 	else
872 		need_swap = 1;
873 	if (need_swap) {
874 		sc->sc_aperture = (char *)sc->sc_aperture + 0x800000;
875 #if 0
876 		/* what the fsck is this for? */
877 		sc->sc_aperbase += 0x800000;
878 		sc->sc_apersize -= 0x800000;
879 #endif
880 	}
881 	*p32 = saved_value;
882 
883 	sc->sc_blanked = 0;
884 }
885 
886 static int
887 mach64_get_memsize(struct mach64_softc *sc)
888 {
889 	int tmp, memsize;
890 	int mem_tab[] = {
891 		512, 1024, 2048, 4096, 6144, 8192, 12288, 16384
892 	};
893 	tmp = regr(sc, MEM_CNTL);
894 #ifdef DIAGNOSTIC
895 	aprint_debug_dev(sc->sc_dev, "memctl %08x\n", tmp);
896 #endif
897 	if (sc->has_dsp) {
898 		tmp &= 0x0000000f;
899 		if (tmp < 8)
900 			memsize = (tmp + 1) * 512;
901 		else if (tmp < 12)
902 			memsize = (tmp - 3) * 1024;
903 		else
904 			memsize = (tmp - 7) * 2048;
905 	} else {
906 		memsize = mem_tab[tmp & 0x07];
907 	}
908 
909 	return memsize;
910 }
911 
912 static int
913 mach64_get_max_ramdac(struct mach64_softc *sc)
914 {
915 	int i;
916 
917 	if ((mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT ||
918 	     mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II) &&
919 	     (mach64_chip_rev & 0x07))
920 		return 170000;
921 
922 	for (i = 0; i < __arraycount(mach64_info); i++)
923 		if (mach64_chip_id == mach64_info[i].chip_id)
924 			return mach64_info[i].ramdac_freq;
925 
926 	if (sc->bits_per_pixel == 8)
927 		return 135000;
928 	else
929 		return 80000;
930 }
931 
932 #if defined(__sparc__) || defined(__powerpc__)
933 static void
934 mach64_get_mode(struct mach64_softc *sc, struct videomode *mode)
935 {
936 	struct mach64_crtcregs crtc;
937 
938 	crtc.h_total_disp = regr(sc, CRTC_H_TOTAL_DISP);
939 	crtc.h_sync_strt_wid = regr(sc, CRTC_H_SYNC_STRT_WID);
940 	crtc.v_total_disp = regr(sc, CRTC_V_TOTAL_DISP);
941 	crtc.v_sync_strt_wid = regr(sc, CRTC_V_SYNC_STRT_WID);
942 
943 	mode->htotal = ((crtc.h_total_disp & 0xffff) + 1) << 3;
944 	mode->hdisplay = ((crtc.h_total_disp >> 16) + 1) << 3;
945 	mode->hsync_start = ((crtc.h_sync_strt_wid & 0xffff) + 1) << 3;
946 	mode->hsync_end = ((crtc.h_sync_strt_wid >> 16) << 3) +
947 	    mode->hsync_start;
948 	mode->vtotal = (crtc.v_total_disp & 0xffff) + 1;
949 	mode->vdisplay = (crtc.v_total_disp >> 16) + 1;
950 	mode->vsync_start = (crtc.v_sync_strt_wid & 0xffff) + 1;
951 	mode->vsync_end = (crtc.v_sync_strt_wid >> 16) + mode->vsync_start;
952 
953 #ifdef MACHFB_DEBUG
954 	printf("mach64_get_mode: %d %d %d %d %d %d %d %d\n",
955 	    mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal,
956 	    mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal);
957 #endif
958 }
959 #endif
960 
961 static int
962 mach64_calc_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc,
963     struct videomode *mode)
964 {
965 
966 	if (mode->dot_clock > sc->ramdac_freq)
967 		/* Clock too high. */
968 		return 1;
969 
970 	crtc->h_total_disp = (((mode->hdisplay >> 3) - 1) << 16) |
971 	    ((mode->htotal >> 3) - 1);
972 	crtc->h_sync_strt_wid =
973 	    (((mode->hsync_end - mode->hsync_start) >> 3) << 16) |
974 	    ((mode->hsync_start >> 3) - 1);
975 
976 	crtc->v_total_disp = ((mode->vdisplay - 1) << 16) |
977 	    (mode->vtotal - 1);
978 	crtc->v_sync_strt_wid =
979 	    ((mode->vsync_end - mode->vsync_start) << 16) |
980 	    (mode->vsync_start - 1);
981 
982 	if (mode->flags & VID_NVSYNC)
983 		crtc->v_sync_strt_wid |= CRTC_VSYNC_NEG;
984 
985 	switch (sc->bits_per_pixel) {
986 	case 8:
987 		crtc->color_depth = CRTC_PIX_WIDTH_8BPP;
988 		break;
989 	case 16:
990 		crtc->color_depth = CRTC_PIX_WIDTH_16BPP;
991 		break;
992 	case 32:
993 		crtc->color_depth = CRTC_PIX_WIDTH_32BPP;
994 		break;
995 	}
996 
997 	crtc->gen_cntl = 0;
998 	if (mode->flags & VID_INTERLACE)
999 		crtc->gen_cntl |= CRTC_INTERLACE_EN;
1000 
1001 	if (mode->flags & VID_CSYNC)
1002 		crtc->gen_cntl |= CRTC_CSYNC_EN;
1003 
1004 	crtc->dot_clock = mode->dot_clock;
1005 
1006 	return 0;
1007 }
1008 
1009 static void
1010 mach64_set_crtcregs(struct mach64_softc *sc, struct mach64_crtcregs *crtc)
1011 {
1012 
1013 	mach64_set_pll(sc, crtc->dot_clock);
1014 
1015 	if (sc->has_dsp)
1016 		mach64_set_dsp(sc);
1017 #if 1
1018 	regw(sc, CRTC_H_TOTAL_DISP, crtc->h_total_disp);
1019 	regw(sc, CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid);
1020 	regw(sc, CRTC_V_TOTAL_DISP, crtc->v_total_disp);
1021 	regw(sc, CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid);
1022 
1023 	regw(sc, CRTC_VLINE_CRNT_VLINE, 0);
1024 
1025 	regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22);
1026 
1027 	regw(sc, CRTC_GEN_CNTL, crtc->gen_cntl | crtc->color_depth |
1028 /* XXX this unconditionally enables composite sync on SPARC */
1029 #ifdef __sparc__
1030 	    CRTC_CSYNC_EN |
1031 #endif
1032 	    CRTC_EXT_DISP_EN | CRTC_EXT_EN);
1033 #endif
1034 }
1035 
1036 static int
1037 mach64_modeswitch(struct mach64_softc *sc, struct videomode *mode)
1038 {
1039 	struct mach64_crtcregs crtc;
1040 
1041 	memset(&crtc, 0, sizeof crtc);	/* XXX gcc */
1042 
1043 	if (mach64_calc_crtcregs(sc, &crtc, mode))
1044 		return 1;
1045 	aprint_debug("crtc dot clock: %d\n", crtc.dot_clock);
1046 	if (crtc.dot_clock == 0) {
1047 		aprint_error("%s: preposterous dot clock (%d)\n",
1048 		    device_xname(sc->sc_dev), crtc.dot_clock);
1049 		return 1;
1050 	}
1051 	mach64_set_crtcregs(sc, &crtc);
1052 	return 0;
1053 }
1054 
1055 static void
1056 mach64_reset_engine(struct mach64_softc *sc)
1057 {
1058 
1059 	/* Reset engine.*/
1060 	regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE);
1061 
1062 	/* Enable engine. */
1063 	regw(sc, GEN_TEST_CNTL, regr(sc, GEN_TEST_CNTL) | GUI_ENGINE_ENABLE);
1064 
1065 	/* Ensure engine is not locked up by clearing any FIFO or
1066 	   host errors. */
1067 	regw(sc, BUS_CNTL, regr(sc, BUS_CNTL) | BUS_HOST_ERR_ACK |
1068 	    BUS_FIFO_ERR_ACK);
1069 }
1070 
1071 static void
1072 mach64_init_engine(struct mach64_softc *sc)
1073 {
1074 	uint32_t pitch_value;
1075 
1076 	pitch_value = sc->virt_x;
1077 
1078 	if (sc->bits_per_pixel == 24)
1079 		pitch_value *= 3;
1080 
1081 	mach64_reset_engine(sc);
1082 
1083 	wait_for_fifo(sc, 14);
1084 
1085 	regw(sc, CONTEXT_MASK, 0xffffffff);
1086 
1087 	regw(sc, DST_OFF_PITCH, (pitch_value / 8) << 22);
1088 
1089 	/* make sure the visible area starts where we're going to draw */
1090 	regw(sc, CRTC_OFF_PITCH, (sc->virt_x >> 3) << 22);
1091 
1092 	regw(sc, DST_Y_X, 0);
1093 	regw(sc, DST_HEIGHT, 0);
1094 	regw(sc, DST_BRES_ERR, 0);
1095 	regw(sc, DST_BRES_INC, 0);
1096 	regw(sc, DST_BRES_DEC, 0);
1097 
1098 	regw(sc, DST_CNTL, DST_LAST_PEL | DST_X_LEFT_TO_RIGHT |
1099 	    DST_Y_TOP_TO_BOTTOM);
1100 
1101 	regw(sc, SRC_OFF_PITCH, (pitch_value / 8) << 22);
1102 
1103 	regw(sc, SRC_Y_X, 0);
1104 	regw(sc, SRC_HEIGHT1_WIDTH1, 1);
1105 	regw(sc, SRC_Y_X_START, 0);
1106 	regw(sc, SRC_HEIGHT2_WIDTH2, 1);
1107 
1108 	regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT);
1109 
1110 	wait_for_fifo(sc, 13);
1111 	regw(sc, HOST_CNTL, 0);
1112 
1113 	regw(sc, PAT_REG0, 0);
1114 	regw(sc, PAT_REG1, 0);
1115 	regw(sc, PAT_CNTL, 0);
1116 
1117 	regw(sc, SC_LEFT, 0);
1118 	regw(sc, SC_TOP, 0);
1119 	regw(sc, SC_BOTTOM, sc->sc_my_mode->vdisplay - 1);
1120 	regw(sc, SC_RIGHT, pitch_value - 1);
1121 
1122 	regw(sc, DP_BKGD_CLR, 0);
1123 	regw(sc, DP_FRGD_CLR, 0xffffffff);
1124 	regw(sc, DP_WRITE_MASK, 0xffffffff);
1125 	regw(sc, DP_MIX, (MIX_SRC << 16) | MIX_DST);
1126 
1127 	regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR);
1128 
1129 	wait_for_fifo(sc, 3);
1130 	regw(sc, CLR_CMP_CLR, 0);
1131 	regw(sc, CLR_CMP_MASK, 0xffffffff);
1132 	regw(sc, CLR_CMP_CNTL, 0);
1133 
1134 	wait_for_fifo(sc, 2);
1135 	switch (sc->bits_per_pixel) {
1136 	case 8:
1137 		regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_8BPP | DST_8BPP);
1138 		regw(sc, DP_CHAIN_MASK, DP_CHAIN_8BPP);
1139 		/* We want 8 bit per channel */
1140 		regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN);
1141 		break;
1142 	case 32:
1143 		regw(sc, DP_PIX_WIDTH, HOST_1BPP | SRC_32BPP | DST_32BPP);
1144 		regw(sc, DP_CHAIN_MASK, DP_CHAIN_32BPP);
1145 		regw(sc, DAC_CNTL, regr(sc, DAC_CNTL) | DAC_8BIT_EN);
1146 		break;
1147 	}
1148 
1149 	wait_for_fifo(sc, 5);
1150 	regw(sc, CRTC_INT_CNTL, regr(sc, CRTC_INT_CNTL) & ~0x20);
1151 	regw(sc, GUI_TRAJ_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
1152 
1153 	wait_for_idle(sc);
1154 }
1155 
1156 #if 0
1157 static void
1158 mach64_adjust_frame(struct mach64_softc *sc, int x, int y)
1159 {
1160 	int offset;
1161 
1162 	offset = ((x + y * sc->virt_x) * (sc->bits_per_pixel >> 3)) >> 3;
1163 
1164 	regw(sc, CRTC_OFF_PITCH, (regr(sc, CRTC_OFF_PITCH) & 0xfff00000) |
1165 	     offset);
1166 }
1167 #endif
1168 
1169 static void
1170 mach64_set_dsp(struct mach64_softc *sc)
1171 {
1172 	uint32_t fifo_depth, page_size, dsp_precision, dsp_loop_latency;
1173 	uint32_t dsp_off, dsp_on, dsp_xclks_per_qw;
1174 	uint32_t xclks_per_qw, y;
1175 	uint32_t fifo_off, fifo_on;
1176 
1177 	aprint_normal_dev(sc->sc_dev, "initializing the DSP\n");
1178 
1179 	if (mach64_chip_id == PCI_PRODUCT_ATI_MACH64_VT ||
1180 	    mach64_chip_id == PCI_PRODUCT_ATI_RAGE_II ||
1181 	    mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIP ||
1182 	    mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_PCI ||
1183 	    mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_B ||
1184 	    mach64_chip_id == PCI_PRODUCT_ATI_RAGE_IIC_AGP_P) {
1185 		dsp_loop_latency = 0;
1186 		fifo_depth = 24;
1187 	} else {
1188 		dsp_loop_latency = 2;
1189 		fifo_depth = 32;
1190 	}
1191 
1192 	dsp_precision = 0;
1193 	xclks_per_qw = (sc->mclk_fb_div * sc->vclk_post_div * 64 << 11) /
1194 	    (sc->vclk_fb_div * sc->mclk_post_div * sc->bits_per_pixel);
1195 	y = (xclks_per_qw * fifo_depth) >> 11;
1196 	while (y) {
1197 		y >>= 1;
1198 		dsp_precision++;
1199 	}
1200 	dsp_precision -= 5;
1201 	fifo_off = ((xclks_per_qw * (fifo_depth - 1)) >> 5) + (3 << 6);
1202 
1203 	switch (sc->memtype) {
1204 	case DRAM:
1205 	case EDO_DRAM:
1206 	case PSEUDO_EDO:
1207 		if (sc->memsize > 1024) {
1208 			page_size = 9;
1209 			dsp_loop_latency += 6;
1210 		} else {
1211 			page_size = 10;
1212 			if (sc->memtype == DRAM)
1213 				dsp_loop_latency += 8;
1214 			else
1215 				dsp_loop_latency += 7;
1216 		}
1217 		break;
1218 	case SDRAM:
1219 	case SGRAM:
1220 		if (sc->memsize > 1024) {
1221 			page_size = 8;
1222 			dsp_loop_latency += 8;
1223 		} else {
1224 			page_size = 10;
1225 			dsp_loop_latency += 9;
1226 		}
1227 		break;
1228 	default:
1229 		page_size = 10;
1230 		dsp_loop_latency += 9;
1231 		break;
1232 	}
1233 
1234 	if (xclks_per_qw >= (page_size << 11))
1235 		fifo_on = ((2 * page_size + 1) << 6) + (xclks_per_qw >> 5);
1236 	else
1237 		fifo_on = (3 * page_size + 2) << 6;
1238 
1239 	dsp_xclks_per_qw = xclks_per_qw >> dsp_precision;
1240 	dsp_on = fifo_on >> dsp_precision;
1241 	dsp_off = fifo_off >> dsp_precision;
1242 
1243 #ifdef MACHFB_DEBUG
1244 	printf("dsp_xclks_per_qw = %d, dsp_on = %d, dsp_off = %d,\n"
1245 	    "dsp_precision = %d, dsp_loop_latency = %d,\n"
1246 	    "mclk_fb_div = %d, vclk_fb_div = %d,\n"
1247 	    "mclk_post_div = %d, vclk_post_div = %d\n",
1248 	    dsp_xclks_per_qw, dsp_on, dsp_off, dsp_precision, dsp_loop_latency,
1249 	    sc->mclk_fb_div, sc->vclk_fb_div,
1250 	    sc->mclk_post_div, sc->vclk_post_div);
1251 #endif
1252 
1253 	regw(sc, DSP_ON_OFF, ((dsp_on << 16) & DSP_ON) | (dsp_off & DSP_OFF));
1254 	regw(sc, DSP_CONFIG, ((dsp_precision << 20) & DSP_PRECISION) |
1255 	    ((dsp_loop_latency << 16) & DSP_LOOP_LATENCY) |
1256 	    (dsp_xclks_per_qw & DSP_XCLKS_PER_QW));
1257 }
1258 
1259 static void
1260 mach64_set_pll(struct mach64_softc *sc, int clock)
1261 {
1262 	uint32_t q, clockreg;
1263 	int clockshift = sc->sc_clock << 1;
1264 	uint8_t reg, vclk_ctl;
1265 
1266 	q = (clock * sc->ref_div * 100) / (2 * sc->ref_freq);
1267 #ifdef MACHFB_DEBUG
1268 	printf("q = %d\n", q);
1269 #endif
1270 	if (q > 25500) {
1271 		printf("Warning: q > 25500\n");
1272 		q = 25500;
1273 		sc->vclk_post_div = 1;
1274 		sc->log2_vclk_post_div = 0;
1275 	} else if (q > 12750) {
1276 		sc->vclk_post_div = 1;
1277 		sc->log2_vclk_post_div = 0;
1278 	} else if (q > 6350) {
1279 		sc->vclk_post_div = 2;
1280 		sc->log2_vclk_post_div = 1;
1281 	} else if (q > 3150) {
1282 		sc->vclk_post_div = 4;
1283 		sc->log2_vclk_post_div = 2;
1284 	} else if (q >= 1600) {
1285 		sc->vclk_post_div = 8;
1286 		sc->log2_vclk_post_div = 3;
1287 	} else {
1288 		printf("Warning: q < 1600\n");
1289 		sc->vclk_post_div = 8;
1290 		sc->log2_vclk_post_div = 3;
1291 	}
1292 	sc->vclk_fb_div = q * sc->vclk_post_div / 100;
1293 	printf("post_div: %d log2_post_div: %d mclk_div: %d\n", sc->vclk_post_div, sc->log2_vclk_post_div, sc->mclk_fb_div);
1294 
1295 	vclk_ctl = regrb_pll(sc, PLL_VCLK_CNTL);
1296 	printf("vclk_ctl: %02x\n", vclk_ctl);
1297 	vclk_ctl |= PLL_VCLK_RESET;
1298 	regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl);
1299 
1300 	regwb_pll(sc, MCLK_FB_DIV, sc->mclk_fb_div);
1301 	reg = regrb_pll(sc, VCLK_POST_DIV);
1302 	reg &= ~(3 << clockshift);
1303 	reg |= (sc->log2_vclk_post_div << clockshift);
1304 	regwb_pll(sc, VCLK_POST_DIV, reg);
1305 	regwb_pll(sc, VCLK0_FB_DIV + sc->sc_clock, sc->vclk_fb_div);
1306 
1307 	vclk_ctl &= ~PLL_VCLK_RESET;
1308 	regwb_pll(sc, PLL_VCLK_CNTL, vclk_ctl);
1309 
1310 	clockreg = regr(sc, CLOCK_CNTL);
1311 	clockreg &= ~CLOCK_SEL;
1312 	clockreg |= sc->sc_clock | CLOCK_STROBE;
1313 	regw(sc, CLOCK_CNTL, clockreg);
1314 }
1315 
1316 static void
1317 mach64_init_lut(struct mach64_softc *sc)
1318 {
1319 	int i, idx;
1320 
1321 	idx = 0;
1322 	for (i = 0; i < 256; i++) {
1323 		mach64_putpalreg(sc, i, rasops_cmap[idx], rasops_cmap[idx + 1],
1324 		    rasops_cmap[idx + 2]);
1325 		idx += 3;
1326 	}
1327 }
1328 
1329 static int
1330 mach64_putpalreg(struct mach64_softc *sc, uint8_t index, uint8_t r, uint8_t g,
1331     uint8_t b)
1332 {
1333 	sc->sc_cmap_red[index] = r;
1334 	sc->sc_cmap_green[index] = g;
1335 	sc->sc_cmap_blue[index] = b;
1336 	/*
1337 	 * writing the dac index takes a while, in theory we can poll some
1338 	 * register to see when it's ready - but we better avoid writing it
1339 	 * unnecessarily
1340 	 */
1341 	if (index != sc->sc_dacw) {
1342 		regwb(sc, DAC_MASK, 0xff);
1343 		regwb(sc, DAC_WINDEX, index);
1344 	}
1345 	sc->sc_dacw = index + 1;
1346 	regwb(sc, DAC_DATA, r);
1347 	regwb(sc, DAC_DATA, g);
1348 	regwb(sc, DAC_DATA, b);
1349 	return 0;
1350 }
1351 
1352 static int
1353 mach64_putcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm)
1354 {
1355 	uint index = cm->index;
1356 	uint count = cm->count;
1357 	int i, error;
1358 	uint8_t rbuf[256], gbuf[256], bbuf[256];
1359 	uint8_t *r, *g, *b;
1360 
1361 	if (cm->index >= 256 || cm->count > 256 ||
1362 	    (cm->index + cm->count) > 256)
1363 		return EINVAL;
1364 	error = copyin(cm->red, &rbuf[index], count);
1365 	if (error)
1366 		return error;
1367 	error = copyin(cm->green, &gbuf[index], count);
1368 	if (error)
1369 		return error;
1370 	error = copyin(cm->blue, &bbuf[index], count);
1371 	if (error)
1372 		return error;
1373 
1374 	memcpy(&sc->sc_cmap_red[index], &rbuf[index], count);
1375 	memcpy(&sc->sc_cmap_green[index], &gbuf[index], count);
1376 	memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count);
1377 
1378 	r = &sc->sc_cmap_red[index];
1379 	g = &sc->sc_cmap_green[index];
1380 	b = &sc->sc_cmap_blue[index];
1381 
1382 	for (i = 0; i < count; i++) {
1383 		mach64_putpalreg(sc, index, *r, *g, *b);
1384 		index++;
1385 		r++, g++, b++;
1386 	}
1387 	return 0;
1388 }
1389 
1390 static int
1391 mach64_getcmap(struct mach64_softc *sc, struct wsdisplay_cmap *cm)
1392 {
1393 	u_int index = cm->index;
1394 	u_int count = cm->count;
1395 	int error;
1396 
1397 	if (index >= 255 || count > 256 || index + count > 256)
1398 		return EINVAL;
1399 
1400 	error = copyout(&sc->sc_cmap_red[index],   cm->red,   count);
1401 	if (error)
1402 		return error;
1403 	error = copyout(&sc->sc_cmap_green[index], cm->green, count);
1404 	if (error)
1405 		return error;
1406 	error = copyout(&sc->sc_cmap_blue[index],  cm->blue,  count);
1407 	if (error)
1408 		return error;
1409 
1410 	return 0;
1411 }
1412 
1413 static int
1414 mach64_set_screentype(struct mach64_softc *sc, const struct wsscreen_descr *des)
1415 {
1416 	struct mach64_crtcregs regs;
1417 
1418 	if (mach64_calc_crtcregs(sc, &regs,
1419 	    (struct videomode *)des->modecookie))
1420 		return 1;
1421 
1422 	mach64_set_crtcregs(sc, &regs);
1423 	return 0;
1424 }
1425 
1426 static int
1427 mach64_is_console(struct mach64_softc *sc)
1428 {
1429 	bool console = 0;
1430 
1431 	prop_dictionary_get_bool(device_properties(sc->sc_dev),
1432 	    "is_console", &console);
1433 	return console;
1434 }
1435 
1436 /*
1437  * wsdisplay_emulops
1438  */
1439 
1440 static void
1441 mach64_cursor(void *cookie, int on, int row, int col)
1442 {
1443 	struct rasops_info *ri = cookie;
1444 	struct vcons_screen *scr = ri->ri_hw;
1445 	struct mach64_softc *sc = scr->scr_cookie;
1446 	int x, y, wi, he;
1447 
1448 	wi = ri->ri_font->fontwidth;
1449 	he = ri->ri_font->fontheight;
1450 
1451 	if ((!sc->sc_locked) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) {
1452 		x = ri->ri_ccol * wi + ri->ri_xorigin;
1453 		y = ri->ri_crow * he + ri->ri_yorigin;
1454 		if (ri->ri_flg & RI_CURSOR) {
1455 			mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC,
1456 			    0xff);
1457 			ri->ri_flg &= ~RI_CURSOR;
1458 		}
1459 		ri->ri_crow = row;
1460 		ri->ri_ccol = col;
1461 		if (on) {
1462 			x = ri->ri_ccol * wi + ri->ri_xorigin;
1463 			y = ri->ri_crow * he + ri->ri_yorigin;
1464 			mach64_bitblt(sc, x, y, x, y, wi, he, MIX_NOT_SRC,
1465 			    0xff);
1466 			ri->ri_flg |= RI_CURSOR;
1467 		}
1468 	} else {
1469 		scr->scr_ri.ri_crow = row;
1470 		scr->scr_ri.ri_ccol = col;
1471 		scr->scr_ri.ri_flg &= ~RI_CURSOR;
1472 	}
1473 }
1474 
1475 #if 0
1476 static int
1477 mach64_mapchar(void *cookie, int uni, u_int *index)
1478 {
1479 	return 0;
1480 }
1481 #endif
1482 
1483 static void
1484 mach64_putchar(void *cookie, int row, int col, u_int c, long attr)
1485 {
1486 	struct rasops_info *ri = cookie;
1487 	struct wsdisplay_font *font = PICK_FONT(ri, c);
1488 	struct vcons_screen *scr = ri->ri_hw;
1489 	struct mach64_softc *sc = scr->scr_cookie;
1490 
1491 	if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) {
1492 		int fg, bg, uc;
1493 		uint8_t *data;
1494 		int x, y, wi, he;
1495 		wi = font->fontwidth;
1496 		he = font->fontheight;
1497 
1498 		if (!CHAR_IN_FONT(c, font))
1499 			return;
1500 		bg = (u_char)ri->ri_devcmap[(attr >> 16) & 0x0f];
1501 		fg = (u_char)ri->ri_devcmap[(attr >> 24) & 0x0f];
1502 		x = ri->ri_xorigin + col * wi;
1503 		y = ri->ri_yorigin + row * he;
1504 		if (c == 0x20) {
1505 			mach64_rectfill(sc, x, y, wi, he, bg);
1506 		} else {
1507 			uc = c - font->firstchar;
1508 			data = (uint8_t *)font->data + uc *
1509 			    ri->ri_fontscale;
1510 
1511 			mach64_setup_mono(sc, x, y, wi, he, fg, bg);
1512 			mach64_feed_bytes(sc, ri->ri_fontscale, data);
1513 		}
1514 	}
1515 }
1516 
1517 
1518 static void
1519 mach64_copycols(void *cookie, int row, int srccol, int dstcol, int ncols)
1520 {
1521 	struct rasops_info *ri = cookie;
1522 	struct vcons_screen *scr = ri->ri_hw;
1523 	struct mach64_softc *sc = scr->scr_cookie;
1524 	int32_t xs, xd, y, width, height;
1525 
1526 	if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) {
1527 		xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol;
1528 		xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol;
1529 		y = ri->ri_yorigin + ri->ri_font->fontheight * row;
1530 		width = ri->ri_font->fontwidth * ncols;
1531 		height = ri->ri_font->fontheight;
1532 		mach64_bitblt(sc, xs, y, xd, y, width, height, MIX_SRC, 0xff);
1533 	}
1534 }
1535 
1536 static void
1537 mach64_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr)
1538 {
1539 	struct rasops_info *ri = cookie;
1540 	struct vcons_screen *scr = ri->ri_hw;
1541 	struct mach64_softc *sc = scr->scr_cookie;
1542 	int32_t x, y, width, height, fg, bg, ul;
1543 
1544 	if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) {
1545 		x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol;
1546 		y = ri->ri_yorigin + ri->ri_font->fontheight * row;
1547 		width = ri->ri_font->fontwidth * ncols;
1548 		height = ri->ri_font->fontheight;
1549 		rasops_unpack_attr(fillattr, &fg, &bg, &ul);
1550 
1551 		mach64_rectfill(sc, x, y, width, height, bg);
1552 	}
1553 }
1554 
1555 static void
1556 mach64_copyrows(void *cookie, int srcrow, int dstrow, int nrows)
1557 {
1558 	struct rasops_info *ri = cookie;
1559 	struct vcons_screen *scr = ri->ri_hw;
1560 	struct mach64_softc *sc = scr->scr_cookie;
1561 	int32_t x, ys, yd, width, height;
1562 
1563 	if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) {
1564 		x = ri->ri_xorigin;
1565 		ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow;
1566 		yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow;
1567 		width = ri->ri_emuwidth;
1568 		height = ri->ri_font->fontheight*nrows;
1569 		mach64_bitblt(sc, x, ys, x, yd, width, height, MIX_SRC, 0xff);
1570 	}
1571 }
1572 
1573 static void
1574 mach64_eraserows(void *cookie, int row, int nrows, long fillattr)
1575 {
1576 	struct rasops_info *ri = cookie;
1577 	struct vcons_screen *scr = ri->ri_hw;
1578 	struct mach64_softc *sc = scr->scr_cookie;
1579 	int32_t x, y, width, height, fg, bg, ul;
1580 
1581 	if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) {
1582 		x = ri->ri_xorigin;
1583 		y = ri->ri_yorigin + ri->ri_font->fontheight * row;
1584 		width = ri->ri_emuwidth;
1585 		height = ri->ri_font->fontheight * nrows;
1586 		rasops_unpack_attr(fillattr, &fg, &bg, &ul);
1587 
1588 		mach64_rectfill(sc, x, y, width, height, bg);
1589 	}
1590 }
1591 
1592 static void
1593 mach64_bitblt(struct mach64_softc *sc, int xs, int ys, int xd, int yd, int width, int height, int rop, int mask)
1594 {
1595 	uint32_t dest_ctl = 0;
1596 
1597 	wait_for_idle(sc);
1598 	regw(sc, DP_WRITE_MASK, mask);	/* XXX only good for 8 bit */
1599 	regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP);
1600 	regw(sc, DP_SRC, FRGD_SRC_BLIT);
1601 	regw(sc, DP_MIX, (rop & 0xffff) << 16);
1602 	regw(sc, CLR_CMP_CNTL, 0);	/* no transparency */
1603 	if (yd < ys) {
1604 		dest_ctl = DST_Y_TOP_TO_BOTTOM;
1605 	} else {
1606 		ys += height - 1;
1607 		yd += height - 1;
1608 		dest_ctl = DST_Y_BOTTOM_TO_TOP;
1609 	}
1610 	if (xd < xs) {
1611 		dest_ctl |= DST_X_LEFT_TO_RIGHT;
1612 		regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT);
1613 	} else {
1614 		dest_ctl |= DST_X_RIGHT_TO_LEFT;
1615 		xs += width - 1;
1616 		xd += width - 1;
1617 		regw(sc, SRC_CNTL, SRC_LINE_X_RIGHT_TO_LEFT);
1618 	}
1619 	regw(sc, DST_CNTL, dest_ctl);
1620 
1621 	regw(sc, SRC_Y_X, (xs << 16) | ys);
1622 	regw(sc, SRC_WIDTH1, width);
1623 	regw(sc, DST_Y_X, (xd << 16) | yd);
1624 	regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height);
1625 }
1626 
1627 static void
1628 mach64_setup_mono(struct mach64_softc *sc, int xd, int yd, int width,
1629      int height, uint32_t fg, uint32_t bg)
1630 {
1631 	wait_for_idle(sc);
1632 	regw(sc, DP_WRITE_MASK, 0xff);	/* XXX only good for 8 bit */
1633 	regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_1BPP | HOST_1BPP);
1634 	regw(sc, DP_SRC, MONO_SRC_HOST | BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR);
1635 	regw(sc, DP_MIX, ((MIX_SRC & 0xffff) << 16) | MIX_SRC);
1636 	regw(sc, CLR_CMP_CNTL ,0);	/* no transparency */
1637 	regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT);
1638 	regw(sc, DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT);
1639 	regw(sc, HOST_CNTL, HOST_BYTE_ALIGN);
1640 	regw(sc, DP_BKGD_CLR, bg);
1641 	regw(sc, DP_FRGD_CLR, fg);
1642 	regw(sc, SRC_Y_X, 0);
1643 	regw(sc, SRC_WIDTH1, width);
1644 	regw(sc, DST_Y_X, (xd << 16) | yd);
1645 	regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height);
1646 	/* now feed the data into the chip */
1647 }
1648 
1649 static void
1650 mach64_feed_bytes(struct mach64_softc *sc, int count, uint8_t *data)
1651 {
1652 	int i;
1653 	uint32_t latch = 0, bork;
1654 	int shift = 0;
1655 	int reg = 0;
1656 
1657 	for (i = 0; i < count; i++) {
1658 		bork = data[i];
1659 		latch |= (bork << shift);
1660 		if (shift == 24) {
1661 			regw(sc, HOST_DATA0 + reg, latch);
1662 			latch = 0;
1663 			shift = 0;
1664 			reg = (reg + 4) & 0x3c;
1665 		} else
1666 			shift += 8;
1667 	}
1668 	if (shift != 0)	/* 24 */
1669 		regw(sc, HOST_DATA0 + reg, latch);
1670 }
1671 
1672 
1673 static void
1674 mach64_rectfill(struct mach64_softc *sc, int x, int y, int width, int height,
1675     int colour)
1676 {
1677 	wait_for_idle(sc);
1678 	regw(sc, DP_WRITE_MASK, 0xff);
1679 	regw(sc, DP_FRGD_CLR, colour);
1680 	regw(sc, DP_PIX_WIDTH, DST_8BPP | SRC_8BPP | HOST_8BPP);
1681 	regw(sc, DP_SRC, FRGD_SRC_FRGD_CLR);
1682 	regw(sc, DP_MIX, MIX_SRC << 16);
1683 	regw(sc, CLR_CMP_CNTL, 0);	/* no transparency */
1684 	regw(sc, SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT);
1685 	regw(sc, DST_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
1686 
1687 	regw(sc, SRC_Y_X, (x << 16) | y);
1688 	regw(sc, SRC_WIDTH1, width);
1689 	regw(sc, DST_Y_X, (x << 16) | y);
1690 	regw(sc, DST_HEIGHT_WIDTH, (width << 16) | height);
1691 }
1692 
1693 static void
1694 mach64_clearscreen(struct mach64_softc *sc)
1695 {
1696 	mach64_rectfill(sc, 0, 0, sc->virt_x, sc->virt_y, sc->sc_bg);
1697 }
1698 
1699 
1700 #if 0
1701 static void
1702 mach64_showpal(struct mach64_softc *sc)
1703 {
1704 	int i, x = 0;
1705 
1706 	for (i = 0; i < 16; i++) {
1707 		mach64_rectfill(sc, x, 0, 64, 64, i);
1708 		x += 64;
1709 	}
1710 }
1711 #endif
1712 
1713 /*
1714  * wsdisplay_accessops
1715  */
1716 
1717 static int
1718 mach64_ioctl(void *v, void *vs, u_long cmd, void *data, int flag,
1719 	struct lwp *l)
1720 {
1721 	struct vcons_data *vd = v;
1722 	struct mach64_softc *sc = vd->cookie;
1723 	struct wsdisplay_fbinfo *wdf;
1724 	struct vcons_screen *ms = vd->active;
1725 
1726 	switch (cmd) {
1727 	case WSDISPLAYIO_GTYPE:
1728 		/* XXX is this the right type to return? */
1729 		*(u_int *)data = WSDISPLAY_TYPE_PCIMISC;
1730 		return 0;
1731 
1732 	case WSDISPLAYIO_LINEBYTES:
1733 		*(u_int *)data = sc->virt_x * sc->bits_per_pixel / 8;
1734 		return 0;
1735 
1736 	case WSDISPLAYIO_GINFO:
1737 		wdf = (void *)data;
1738 		wdf->height = sc->virt_y;
1739 		wdf->width = sc->virt_x;
1740 		wdf->depth = sc->bits_per_pixel;
1741 		wdf->cmsize = 256;
1742 		return 0;
1743 
1744 	case WSDISPLAYIO_GETCMAP:
1745 		return mach64_getcmap(sc,
1746 		    (struct wsdisplay_cmap *)data);
1747 
1748 	case WSDISPLAYIO_PUTCMAP:
1749 		return mach64_putcmap(sc,
1750 		    (struct wsdisplay_cmap *)data);
1751 
1752 	/* PCI config read/write passthrough. */
1753 	case PCI_IOC_CFGREAD:
1754 	case PCI_IOC_CFGWRITE:
1755 		return pci_devioctl(sc->sc_pc, sc->sc_pcitag,
1756 		    cmd, data, flag, l);
1757 
1758 	case WSDISPLAYIO_GET_BUSID:
1759 		return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc,
1760 		    sc->sc_pcitag, data);
1761 
1762 	case WSDISPLAYIO_SMODE: {
1763 		int new_mode = *(int*)data;
1764 		if (new_mode != sc->sc_mode) {
1765 			sc->sc_mode = new_mode;
1766 			if ((new_mode == WSDISPLAYIO_MODE_EMUL)
1767 			    && (ms != NULL))
1768 			{
1769 				/* restore initial video mode */
1770 				mach64_init(sc);
1771 				mach64_init_engine(sc);
1772 				mach64_init_lut(sc);
1773 				mach64_modeswitch(sc, sc->sc_my_mode);
1774 				vcons_redraw_screen(ms);
1775 			}
1776 		}
1777 		}
1778 		return 0;
1779 
1780 	}
1781 	return EPASSTHROUGH;
1782 }
1783 
1784 static paddr_t
1785 mach64_mmap(void *v, void *vs, off_t offset, int prot)
1786 {
1787 	struct vcons_data *vd = v;
1788 	struct mach64_softc *sc = vd->cookie;
1789 	paddr_t pa;
1790 	pcireg_t reg;
1791 
1792 #ifndef __sparc64__
1793 	/*
1794 	 *'regular' framebuffer mmap()ing
1795 	 * disabled on sparc64 because some ATI firmware likes to map some PCI
1796 	 * resources to addresses that would collide with this ( like some Rage
1797 	 * IIc which uses 0x2000 for the 2nd register block )
1798 	 * Other 64bit architectures might run into similar problems.
1799 	 */
1800 	if (offset<sc->sc_apersize) {
1801 		pa = bus_space_mmap(sc->sc_memt, sc->sc_aperbase, offset,
1802 		    prot, BUS_SPACE_MAP_LINEAR);
1803 		return pa;
1804 	}
1805 #endif
1806 
1807 	/*
1808 	 * restrict all other mappings to processes with superuser privileges
1809 	 * or the kernel itself
1810 	 */
1811 	if (kauth_authorize_generic(kauth_cred_get(), KAUTH_GENERIC_ISSUSER,
1812 	    NULL) != 0) {
1813 		return -1;
1814 	}
1815 
1816 	reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x18) & 0xffffff00);
1817 	if (reg != sc->sc_regphys) {
1818 #ifdef DIAGNOSTIC
1819 		printf("%s: BAR 0x18 changed! (%x %x)\n",
1820 		    device_xname(sc->sc_dev), (uint32_t)sc->sc_regphys,
1821 		    (uint32_t)reg);
1822 #endif
1823 		sc->sc_regphys = reg;
1824 	}
1825 
1826 	reg = (pci_conf_read(sc->sc_pc, sc->sc_pcitag, 0x10) & 0xffffff00);
1827 	if (reg != sc->sc_aperphys) {
1828 #ifdef DIAGNOSTIC
1829 		printf("%s: BAR 0x10 changed! (%x %x)\n",
1830 		    device_xname(sc->sc_dev), (uint32_t)sc->sc_aperphys,
1831 		    (uint32_t)reg);
1832 #endif
1833 		sc->sc_aperphys = reg;
1834 	}
1835 
1836 	if ((offset >= sc->sc_aperphys) &&
1837 	    (offset < (sc->sc_aperphys + sc->sc_apersize))) {
1838 		pa = bus_space_mmap(sc->sc_memt, offset, 0, prot,
1839 		    BUS_SPACE_MAP_LINEAR);
1840 		return pa;
1841 	}
1842 
1843 	if ((offset >= sc->sc_regphys) &&
1844 	    (offset < (sc->sc_regphys + sc->sc_regsize))) {
1845 		pa = bus_space_mmap(sc->sc_memt, offset, 0, prot,
1846 		    BUS_SPACE_MAP_LINEAR);
1847 		return pa;
1848 	}
1849 
1850 	if ((offset >= sc->sc_rom.vb_base) &&
1851 	    (offset < (sc->sc_rom.vb_base + sc->sc_rom.vb_size))) {
1852 		pa = bus_space_mmap(sc->sc_memt, offset, 0, prot,
1853 		    BUS_SPACE_MAP_LINEAR);
1854 		return pa;
1855 	}
1856 
1857 #ifdef PCI_MAGIC_IO_RANGE
1858 	if ((offset >= PCI_MAGIC_IO_RANGE) &&
1859 	    (offset <= PCI_MAGIC_IO_RANGE + 0x10000)) {
1860 	    	return bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE,
1861 	    	   0, prot, BUS_SPACE_MAP_LINEAR);
1862 	}
1863 #endif
1864 
1865 	return -1;
1866 }
1867 
1868 /* set ri->ri_bits according to fb, ri_xorigin and ri_yorigin */
1869 static void
1870 set_address(struct rasops_info *ri, void *fb)
1871 {
1872 #ifdef notdef
1873 	printf(" %d %d %d\n", ri->ri_xorigin, ri->ri_yorigin, ri->ri_stride);
1874 #endif
1875 	ri->ri_bits = (void *)((char *)fb + ri->ri_stride * ri->ri_yorigin +
1876 	    ri->ri_xorigin);
1877 }
1878 
1879 #if 0
1880 static int
1881 mach64_load_font(void *v, void *cookie, struct wsdisplay_font *data)
1882 {
1883 
1884 	return 0;
1885 }
1886 #endif
1887 
1888 void
1889 machfb_blank(struct mach64_softc *sc, int blank)
1890 {
1891 	uint32_t reg;
1892 
1893 #define MACH64_BLANK (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS)
1894 
1895 	switch (blank)
1896 	{
1897     		case 0:
1898 			reg = regr(sc, CRTC_GEN_CNTL);
1899 			regw(sc, CRTC_GEN_CNTL, reg & ~(MACH64_BLANK));
1900 			sc->sc_blanked = 0;
1901 			break;
1902 		case 1:
1903 			reg = regr(sc, CRTC_GEN_CNTL);
1904 			regw(sc, CRTC_GEN_CNTL, reg | (MACH64_BLANK));
1905 			sc->sc_blanked = 1;
1906 			break;
1907 		default:
1908         		break;
1909 	}
1910 }
1911 
1912 /* framebuffer device support */
1913 #ifdef __sparc__
1914 
1915 static void
1916 machfb_unblank(device_t dev)
1917 {
1918 	struct mach64_softc *sc = device_private(dev);
1919 
1920 	machfb_blank(sc, 0);
1921 }
1922 
1923 static void
1924 machfb_fbattach(struct mach64_softc *sc)
1925 {
1926 	struct fbdevice *fb = &sc->sc_fb;
1927 
1928 	fb->fb_device = sc->sc_dev;
1929 	fb->fb_driver = &machfb_fbdriver;
1930 
1931 	fb->fb_type.fb_cmsize = 256;
1932 	fb->fb_type.fb_size = sc->memsize;
1933 
1934 	fb->fb_type.fb_type = FBTYPE_GENERIC_PCI;
1935 	fb->fb_flags = sc->sc_dev->dv_cfdata->cf_flags & FB_USERMASK;
1936 	fb->fb_type.fb_depth = sc->bits_per_pixel;
1937 	fb->fb_type.fb_width = sc->virt_x;
1938 	fb->fb_type.fb_height = sc->virt_y;
1939 
1940 	fb->fb_pixels = sc->sc_aperture;
1941 	fb_attach(fb, sc->sc_console);
1942 }
1943 
1944 int
1945 machfb_fbopen(dev_t dev, int flags, int mode, struct lwp *l)
1946 {
1947 	struct mach64_softc *sc;
1948 
1949 	sc = device_lookup_private(&machfb_cd, minor(dev));
1950 	if (sc == NULL)
1951 		return ENXIO;
1952 	sc->sc_locked = 1;
1953 
1954 #ifdef MACHFB_DEBUG
1955 	printf("machfb_fbopen(%d)\n", minor(dev));
1956 #endif
1957 	return 0;
1958 }
1959 
1960 int
1961 machfb_fbclose(dev_t dev, int flags, int mode, struct lwp *l)
1962 {
1963 	struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev));
1964 
1965 #ifdef MACHFB_DEBUG
1966 	printf("machfb_fbclose()\n");
1967 #endif
1968 	mach64_init_engine(sc);
1969 	mach64_init_lut(sc);
1970 	sc->sc_locked = 0;
1971 	return 0;
1972 }
1973 
1974 int
1975 machfb_fbioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l)
1976 {
1977 	struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev));
1978 
1979 #ifdef MACHFB_DEBUG
1980 	printf("machfb_fbioctl(%d, %lx)\n", minor(dev), cmd);
1981 #endif
1982 	switch (cmd) {
1983 	case FBIOGTYPE:
1984 		*(struct fbtype *)data = sc->sc_fb.fb_type;
1985 		break;
1986 
1987 	case FBIOGATTR:
1988 #define fba ((struct fbgattr *)data)
1989 		fba->real_type = sc->sc_fb.fb_type.fb_type;
1990 		fba->owner = 0;		/* XXX ??? */
1991 		fba->fbtype = sc->sc_fb.fb_type;
1992 		fba->sattr.flags = 0;
1993 		fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type;
1994 		fba->sattr.dev_specific[0] = sc->sc_nbus;
1995 		fba->sattr.dev_specific[1] = sc->sc_ndev;
1996 		fba->sattr.dev_specific[2] = sc->sc_nfunc;
1997 		fba->sattr.dev_specific[3] = -1;
1998 		fba->emu_types[0] = sc->sc_fb.fb_type.fb_type;
1999 		fba->emu_types[1] = -1;
2000 #undef fba
2001 		break;
2002 
2003 #if 0
2004 	case FBIOGETCMAP:
2005 #define	p ((struct fbcmap *)data)
2006 		return bt_getcmap(p, &sc->sc_cmap, 256, 1);
2007 
2008 	case FBIOPUTCMAP:
2009 		/* copy to software map */
2010 		error = bt_putcmap(p, &sc->sc_cmap, 256, 1);
2011 		if (error)
2012 			return error;
2013 		/* now blast them into the chip */
2014 		/* XXX should use retrace interrupt */
2015 		cg6_loadcmap(sc, p->index, p->count);
2016 #undef p
2017 		break;
2018 #endif
2019 	case FBIOGVIDEO:
2020 		*(int *)data = sc->sc_blanked;
2021 		break;
2022 
2023 	case FBIOSVIDEO:
2024 		machfb_blank(sc, *(int *)data);
2025 		break;
2026 
2027 #if 0
2028 	case FBIOGCURSOR:
2029 		break;
2030 
2031 	case FBIOSCURSOR:
2032 		break;
2033 
2034 	case FBIOGCURPOS:
2035 		*(struct fbcurpos *)data = sc->sc_cursor.cc_pos;
2036 		break;
2037 
2038 	case FBIOSCURPOS:
2039 		sc->sc_cursor.cc_pos = *(struct fbcurpos *)data;
2040 		break;
2041 
2042 	case FBIOGCURMAX:
2043 		/* max cursor size is 32x32 */
2044 		((struct fbcurpos *)data)->x = 32;
2045 		((struct fbcurpos *)data)->y = 32;
2046 		break;
2047 #endif
2048 	case PCI_IOC_CFGREAD:
2049 	case PCI_IOC_CFGWRITE: {
2050 		int ret;
2051 		ret = pci_devioctl(sc->sc_pc, sc->sc_pcitag,
2052 		    cmd, data, flags, l);
2053 
2054 #ifdef MACHFB_DEBUG
2055 		printf("pci_devioctl: %d\n", ret);
2056 #endif
2057 		return ret;
2058 		}
2059 
2060 	case WSDISPLAYIO_GET_BUSID:
2061 		return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc,
2062 		    sc->sc_pcitag, data);
2063 
2064 	default:
2065 #ifdef MACHFB_DEBUG
2066 		log(LOG_NOTICE, "machfb_fbioctl(0x%lx) (%s[%d])\n", cmd,
2067 		    p->p_comm, p->p_pid);
2068 #endif
2069 		return ENOTTY;
2070 	}
2071 #ifdef MACHFB_DEBUG
2072 	printf("machfb_fbioctl done\n");
2073 #endif
2074 	return 0;
2075 }
2076 
2077 paddr_t
2078 machfb_fbmmap(dev_t dev, off_t off, int prot)
2079 {
2080 	struct mach64_softc *sc = device_lookup_private(&machfb_cd, minor(dev));
2081 
2082 	if (sc != NULL)
2083 		return mach64_mmap(&sc->vd, NULL, off, prot);
2084 
2085 	return 0;
2086 }
2087 
2088 #endif /* __sparc__ */
2089