xref: /netbsd-src/sys/dev/pci/jmide.c (revision 627f7eb200a4419d89b531d55fccd2ee3ffdcde0) 
1 /*	$NetBSD: jmide.c,v 1.23 2019/11/10 21:16:36 chs Exp $	*/
2 
3 /*
4  * Copyright (c) 2007 Manuel Bouyer.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  */
26 
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: jmide.c,v 1.23 2019/11/10 21:16:36 chs Exp $");
29 
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/malloc.h>
33 
34 #include <dev/pci/pcivar.h>
35 #include <dev/pci/pcidevs.h>
36 #include <dev/pci/pciidereg.h>
37 #include <dev/pci/pciidevar.h>
38 
39 #include <dev/pci/jmide_reg.h>
40 
41 #include <dev/ic/ahcisatavar.h>
42 
43 #include "jmide.h"
44 
45 static const struct jmide_product *jmide_lookup(pcireg_t);
46 
47 static int  jmide_match(device_t, cfdata_t, void *);
48 static void jmide_attach(device_t, device_t, void *);
49 static int  jmide_intr(void *);
50 
51 static void jmpata_chip_map(struct pciide_softc*,
52     const struct pci_attach_args*);
53 static void jmpata_setup_channel(struct ata_channel*);
54 
55 static int  jmahci_print(void *, const char *);
56 
57 struct jmide_product {
58 	u_int32_t jm_product;
59 	int jm_npata;
60 	int jm_nsata;
61 };
62 
63 static const struct jmide_product jm_products[] =  {
64 	{ PCI_PRODUCT_JMICRON_JMB360,
65 	  0,
66 	  1
67 	},
68 	{ PCI_PRODUCT_JMICRON_JMB361,
69 	  1,
70 	  1
71 	},
72 	{ PCI_PRODUCT_JMICRON_JMB362,
73 	  0,
74 	  2
75 	},
76 	{ PCI_PRODUCT_JMICRON_JMB363,
77 	  1,
78 	  2
79 	},
80 	{ PCI_PRODUCT_JMICRON_JMB365,
81 	  2,
82 	  1
83 	},
84 	{ PCI_PRODUCT_JMICRON_JMB366,
85 	  2,
86 	  2
87 	},
88 	{ PCI_PRODUCT_JMICRON_JMB368,
89 	  1,
90 	  0
91 	},
92 	{ 0,
93 	  0,
94 	  0
95 	}
96 };
97 
98 typedef enum {
99 	TYPE_INVALID = 0,
100 	TYPE_PATA,
101 	TYPE_SATA,
102 	TYPE_NONE
103 } jmchan_t;
104 
105 struct jmide_softc {
106 	struct pciide_softc sc_pciide;
107 	device_t sc_ahci;
108 	int sc_npata;
109 	int sc_nsata;
110 	jmchan_t sc_chan_type[PCIIDE_NUM_CHANNELS];
111 	int sc_chan_swap;
112 };
113 
114 struct jmahci_attach_args {
115 	const struct pci_attach_args *jma_pa;
116 	bus_space_tag_t jma_ahcit;
117 	bus_space_handle_t jma_ahcih;
118 };
119 
120 #define JM_NAME(sc) (device_xname(sc->sc_pciide.sc_wdcdev.sc_atac.atac_dev))
121 
122 CFATTACH_DECL_NEW(jmide, sizeof(struct jmide_softc),
123     jmide_match, jmide_attach, NULL, NULL);
124 
125 static const struct jmide_product *
126 jmide_lookup(pcireg_t id) {
127 	const struct jmide_product *jp;
128 
129 	for (jp = jm_products; jp->jm_product != 0; jp++) {
130 		if (jp->jm_product == PCI_PRODUCT(id))
131 			return jp;
132 	}
133 	return NULL;
134 }
135 
136 static int
137 jmide_match(device_t parent, cfdata_t match, void *aux)
138 {
139 	struct pci_attach_args *pa = aux;
140 
141 	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_JMICRON) {
142 		if (jmide_lookup(pa->pa_id))
143 			return (4); /* higher than ahcisata */
144 	}
145 	return (0);
146 }
147 
148 static void
149 jmide_attach(device_t parent, device_t self, void *aux)
150 {
151 	struct pci_attach_args *pa = aux;
152 	struct jmide_softc *sc = device_private(self);
153 	const struct jmide_product *jp;
154 	const char *intrstr;
155         pci_intr_handle_t intrhandle;
156 	u_int32_t pcictrl0 = pci_conf_read(pa->pa_pc, pa->pa_tag,
157 	    PCI_JM_CONTROL0);
158 	u_int32_t pcictrl1 = pci_conf_read(pa->pa_pc, pa->pa_tag,
159 	    PCI_JM_CONTROL1);
160 	struct pciide_product_desc *pp;
161 	int ahci_used = 0;
162 	char intrbuf[PCI_INTRSTR_LEN];
163 
164 	aprint_naive("\n");
165 	sc->sc_pciide.sc_wdcdev.sc_atac.atac_dev = self;
166 
167 	jp = jmide_lookup(pa->pa_id);
168 	if (jp == NULL) {
169 		aprint_error_dev(self, "jmide_attach: WTF?\n");
170 		return;
171 	}
172 	sc->sc_npata = jp->jm_npata;
173 	sc->sc_nsata = jp->jm_nsata;
174 
175         pci_aprint_devinfo(pa, "JMICRON PATA/SATA disk controller");
176 
177 	aprint_normal("%s: ", JM_NAME(sc));
178 	if (sc->sc_npata)
179 		aprint_normal("%d PATA port%s", sc->sc_npata,
180 		    (sc->sc_npata > 1) ? "s" : "");
181 	if (sc->sc_nsata)
182 		aprint_normal("%s%d SATA port%s", sc->sc_npata ? ", " : "",
183 		    sc->sc_nsata, (sc->sc_nsata > 1) ? "s" : "");
184 	aprint_normal("\n");
185 
186 	if (pci_intr_map(pa, &intrhandle) != 0) {
187                 aprint_error("%s: couldn't map interrupt\n", JM_NAME(sc));
188                 return;
189         }
190         intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf,
191 	    sizeof(intrbuf));
192         sc->sc_pciide.sc_pci_ih = pci_intr_establish_xname(pa->pa_pc,
193 	    intrhandle, IPL_BIO, jmide_intr, sc, device_xname(self));
194         if (sc->sc_pciide.sc_pci_ih == NULL) {
195                 aprint_error("%s: couldn't establish interrupt", JM_NAME(sc));
196                 return;
197         }
198         aprint_normal("%s: interrupting at %s\n", JM_NAME(sc),
199             intrstr ? intrstr : "unknown interrupt");
200 
201 	if (pcictrl0 & JM_CONTROL0_AHCI_EN) {
202 		bus_size_t size;
203 		struct jmahci_attach_args jma;
204 		u_int32_t saved_pcictrl0;
205 		/*
206 		 * ahci controller enabled; disable sata on pciide and
207 		 * enable on ahci
208 		 */
209 		saved_pcictrl0 = pcictrl0;
210 		pcictrl0 |= JM_CONTROL0_SATA0_AHCI | JM_CONTROL0_SATA1_AHCI;
211 		pcictrl0 &= ~(JM_CONTROL0_SATA0_IDE | JM_CONTROL0_SATA1_IDE);
212 		pci_conf_write(pa->pa_pc, pa->pa_tag,
213 		    PCI_JM_CONTROL0, pcictrl0);
214 		/* attach ahci controller if on the right function */
215 		if ((pa->pa_function == 0 &&
216 		      (pcictrl0 & JM_CONTROL0_AHCI_F1) == 0) ||
217 	    	    (pa->pa_function == 1 &&
218 		      (pcictrl0 & JM_CONTROL0_AHCI_F1) != 0)) {
219 			jma.jma_pa = pa;
220 			/* map registers */
221 			if (pci_mapreg_map(pa, AHCI_PCI_ABAR,
222 			    PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
223 			    &jma.jma_ahcit, &jma.jma_ahcih, NULL, &size) != 0) {
224 				aprint_error("%s: can't map ahci registers\n",
225 				    JM_NAME(sc));
226 			} else {
227 				sc->sc_ahci = config_found_ia(
228 				    sc->sc_pciide.sc_wdcdev.sc_atac.atac_dev,
229 				    "jmide_hl", &jma, jmahci_print);
230 			}
231 			/*
232 			 * if we couldn't attach an ahci, try to fall back
233 			 * to pciide. Note that this will not work if IDE
234 			 * is on function 0 and AHCI on function 1.
235 			 */
236 			if (sc->sc_ahci == NULL) {
237 				pcictrl0 = saved_pcictrl0 &
238 				    ~(JM_CONTROL0_SATA0_AHCI |
239 				      JM_CONTROL0_SATA1_AHCI |
240 				      JM_CONTROL0_AHCI_EN);
241 				pcictrl0 |= JM_CONTROL0_SATA1_IDE |
242 					JM_CONTROL0_SATA0_IDE;
243 				pci_conf_write(pa->pa_pc, pa->pa_tag,
244 				    PCI_JM_CONTROL0, pcictrl0);
245 			} else
246 				ahci_used = 1;
247 		}
248 	}
249 	sc->sc_chan_swap = ((pcictrl0 & JM_CONTROL0_PCIIDE_CS) != 0);
250 	/* compute the type of internal primary channel */
251 	if (pcictrl1 & JM_CONTROL1_PATA1_PRI) {
252 		if (sc->sc_npata > 1)
253 			sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_PATA;
254 		else
255 			sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_NONE;
256 	} else if (ahci_used == 0 && sc->sc_nsata > 0)
257 		sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_SATA;
258 	else
259 		sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_NONE;
260 	/* compute the type of internal secondary channel */
261 	if (sc->sc_nsata > 1 && ahci_used == 0 &&
262 	    (pcictrl0 & JM_CONTROL0_PCIIDE0_MS) == 0) {
263 		sc->sc_chan_type[sc->sc_chan_swap ? 0 : 1] = TYPE_SATA;
264 	} else {
265 		/* only a drive if first PATA enabled */
266 		if (sc->sc_npata > 0 && (pcictrl0 & JM_CONTROL0_PATA0_EN)
267 		    && (pcictrl0 &
268 		    (sc->sc_chan_swap ? JM_CONTROL0_PATA0_PRI: JM_CONTROL0_PATA0_SEC)))
269 			sc->sc_chan_type[sc->sc_chan_swap ? 0 : 1] = TYPE_PATA;
270 		else
271 			sc->sc_chan_type[sc->sc_chan_swap ? 0 : 1] = TYPE_NONE;
272 	}
273 
274 	if (sc->sc_chan_type[0] == TYPE_NONE &&
275 	    sc->sc_chan_type[1] == TYPE_NONE)
276 		return;
277 	if (pa->pa_function == 0 && (pcictrl0 & JM_CONTROL0_PCIIDE_F1))
278 		return;
279 	if (pa->pa_function == 1 && (pcictrl0 & JM_CONTROL0_PCIIDE_F1) == 0)
280 		return;
281 	pp = malloc(sizeof(struct pciide_product_desc), M_DEVBUF, M_WAITOK);
282 	aprint_normal("%s: PCI IDE interface used", JM_NAME(sc));
283 	pp->ide_product = 0;
284 	pp->ide_flags = 0;
285 	pp->ide_name = NULL;
286 	pp->chip_map = jmpata_chip_map;
287 	pciide_common_attach(&sc->sc_pciide, pa, pp);
288 }
289 
290 static int
291 jmide_intr(void *arg)
292 {
293 	struct jmide_softc *sc = arg;
294 	int ret = 0;
295 
296 #ifdef NJMAHCI
297 	if (sc->sc_ahci)
298 		ret |= ahci_intr(device_private(sc->sc_ahci));
299 #endif
300 	if (sc->sc_npata)
301 		ret |= pciide_pci_intr(&sc->sc_pciide);
302 	return ret;
303 }
304 
305 static void
306 jmpata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
307 {
308 	struct jmide_softc *jmidesc = (struct jmide_softc *)sc;
309 	int channel;
310 	pcireg_t interface;
311 	struct pciide_channel *cp;
312 
313 	if (pciide_chipen(sc, pa) == 0)
314 		return;
315 	aprint_verbose("%s: bus-master DMA support present", JM_NAME(jmidesc));
316 	pciide_mapreg_dma(sc, pa);
317 	aprint_verbose("\n");
318 	sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
319 	if (sc->sc_dma_ok) {
320 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
321 		sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
322 	}
323 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
324 	sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
325 	sc->sc_wdcdev.sc_atac.atac_set_modes = jmpata_setup_channel;
326 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
327 	sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
328 	sc->sc_wdcdev.wdc_maxdrives = 2;
329 	wdc_allocate_regs(&sc->sc_wdcdev);
330 	/*
331          * can't rely on the PCI_CLASS_REG content if the chip was in raid
332          * mode. We have to fake interface
333          */
334 	interface = PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
335 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
336 	    channel++) {
337 		cp = &sc->pciide_channels[channel];
338 		if (pciide_chansetup(sc, channel, interface) == 0)
339 			continue;
340 		aprint_normal("%s: %s channel is ", JM_NAME(jmidesc),
341 		    PCIIDE_CHANNEL_NAME(channel));
342 		switch(jmidesc->sc_chan_type[channel]) {
343 		case TYPE_PATA:
344 			aprint_normal("PATA");
345 			break;
346 		case TYPE_SATA:
347 			aprint_normal("SATA");
348 			break;
349 		case TYPE_NONE:
350 			aprint_normal("unused");
351 			break;
352 		default:
353 			aprint_normal("impossible");
354 			panic("jmide: wrong/uninitialised channel type");
355 		}
356 		aprint_normal("\n");
357 		if (jmidesc->sc_chan_type[channel] == TYPE_NONE) {
358 			cp->ata_channel.ch_flags |= ATACH_DISABLED;
359 			continue;
360 		}
361 		pciide_mapchan(pa, cp, interface, pciide_pci_intr);
362 	}
363 }
364 
365 static void
366 jmpata_setup_channel(struct ata_channel *chp)
367 {
368 	struct ata_drive_datas *drvp;
369 	int drive, s;
370 	u_int32_t idedma_ctl;
371 	struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
372 	struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
373 	struct jmide_softc *jmidesc = (struct jmide_softc *)sc;
374 	int ide80p;
375 
376 	/* setup DMA if needed */
377 	pciide_channel_dma_setup(cp);
378 
379 	idedma_ctl = 0;
380 
381 	/* cable type detect */
382 	ide80p = 1;
383 	if (chp->ch_channel == (jmidesc->sc_chan_swap ? 1 : 0)) {
384 		if (jmidesc->sc_chan_type[chp->ch_channel] == TYPE_PATA &&
385 		    (pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_JM_CONTROL1) &
386 		    JM_CONTROL1_PATA1_40P))
387 			ide80p = 0;
388 	} else {
389 		if (jmidesc->sc_chan_type[chp->ch_channel] == TYPE_PATA &&
390 		    (pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_JM_CONTROL0) &
391 		    JM_CONTROL0_PATA0_40P))
392 			ide80p = 0;
393 	}
394 
395 	for (drive = 0; drive < 2; drive++) {
396 		drvp = &chp->ch_drive[drive];
397 		/* If no drive, skip */
398 		if (drvp->drive_type == ATA_DRIVET_NONE)
399 			continue;
400 		if (drvp->drive_flags & ATA_DRIVE_UDMA) {
401 			/* use Ultra/DMA */
402 			s = splbio();
403 			drvp->drive_flags &= ~ATA_DRIVE_DMA;
404 			if (drvp->UDMA_mode > 2 && ide80p == 0)
405 				drvp->UDMA_mode = 2;
406 			splx(s);
407 			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
408 		} else if (drvp->drive_flags & ATA_DRIVE_DMA) {
409 			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
410 		}
411 	}
412 	/* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */
413 	if (idedma_ctl != 0) {
414 		/* Add software bits in status register */
415 		bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL],
416 		    0, idedma_ctl);
417 	}
418 }
419 
420 static int
421 jmahci_print(void *aux, const char *pnp)
422 {
423         if (pnp)
424                 aprint_normal("ahcisata at %s", pnp);
425 
426         return (UNCONF);
427 }
428 
429 
430 #ifdef NJMAHCI
431 static int  jmahci_match(device_t, cfdata_t, void *);
432 static void jmahci_attach(device_t, device_t, void *);
433 static int  jmahci_detach(device_t, int);
434 static bool jmahci_resume(device_t, const pmf_qual_t *);
435 
436 CFATTACH_DECL_NEW(jmahci, sizeof(struct ahci_softc),
437 	jmahci_match, jmahci_attach, jmahci_detach, NULL);
438 
439 static int
440 jmahci_match(device_t parent, cfdata_t match, void *aux)
441 {
442 	return 1;
443 }
444 
445 static void
446 jmahci_attach(device_t parent, device_t self, void *aux)
447 {
448 	struct jmahci_attach_args *jma = aux;
449 	const struct pci_attach_args *pa = jma->jma_pa;
450 	struct ahci_softc *sc = device_private(self);
451 	uint32_t ahci_cap;
452 
453 	aprint_naive(": AHCI disk controller\n");
454 	aprint_normal("\n");
455 
456 	sc->sc_atac.atac_dev = self;
457 	sc->sc_ahcit = jma->jma_ahcit;
458 	sc->sc_ahcih = jma->jma_ahcih;
459 
460 	ahci_cap = AHCI_READ(sc, AHCI_CAP);
461 
462 	if (pci_dma64_available(jma->jma_pa) && (ahci_cap & AHCI_CAP_64BIT))
463 		sc->sc_dmat = jma->jma_pa->pa_dmat64;
464 	else
465 		sc->sc_dmat = jma->jma_pa->pa_dmat;
466 
467 	if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
468 		sc->sc_atac_capflags = ATAC_CAP_RAID;
469 
470 	ahci_attach(sc);
471 
472 	if (!pmf_device_register(self, NULL, jmahci_resume))
473 	    aprint_error_dev(self, "couldn't establish power handler\n");
474 }
475 
476 static int
477 jmahci_detach(device_t dv, int flags)
478 {
479 	struct ahci_softc *sc;
480 	sc = device_private(dv);
481 
482 	int rv;
483 
484 	if ((rv = ahci_detach(sc, flags)))
485 		return rv;
486 
487 	return 0;
488 }
489 
490 static bool
491 jmahci_resume(device_t dv, const pmf_qual_t *qual)
492 {
493 	struct ahci_softc *sc;
494 	int s;
495 
496 	sc = device_private(dv);
497 
498 	s = splbio();
499 	ahci_resume(sc);
500 	splx(s);
501 
502 	return true;
503 }
504 #endif
505