xref: /netbsd-src/sys/dev/pci/jmide.c (revision 53b02e147d4ed531c0d2a5ca9b3e8026ba3e99b5) 
1 /*	$NetBSD: jmide.c,v 1.25 2021/08/07 16:19:14 thorpej Exp $	*/
2 
3 /*
4  * Copyright (c) 2007 Manuel Bouyer.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  */
26 
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: jmide.c,v 1.25 2021/08/07 16:19:14 thorpej Exp $");
29 
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/malloc.h>
33 
34 #include <dev/pci/pcivar.h>
35 #include <dev/pci/pcidevs.h>
36 #include <dev/pci/pciidereg.h>
37 #include <dev/pci/pciidevar.h>
38 
39 #include <dev/pci/jmide_reg.h>
40 
41 #include <dev/ic/ahcisatavar.h>
42 
43 #include "jmide.h"
44 
45 static const struct jmide_product *jmide_lookup(pcireg_t);
46 
47 static int  jmide_match(device_t, cfdata_t, void *);
48 static void jmide_attach(device_t, device_t, void *);
49 static int  jmide_intr(void *);
50 
51 static void jmpata_chip_map(struct pciide_softc*,
52     const struct pci_attach_args*);
53 static void jmpata_setup_channel(struct ata_channel*);
54 
55 static int  jmahci_print(void *, const char *);
56 
57 struct jmide_product {
58 	u_int32_t jm_product;
59 	int jm_npata;
60 	int jm_nsata;
61 };
62 
63 static const struct jmide_product jm_products[] =  {
64 	{ PCI_PRODUCT_JMICRON_JMB360,
65 	  0,
66 	  1
67 	},
68 	{ PCI_PRODUCT_JMICRON_JMB361,
69 	  1,
70 	  1
71 	},
72 	{ PCI_PRODUCT_JMICRON_JMB362,
73 	  0,
74 	  2
75 	},
76 	{ PCI_PRODUCT_JMICRON_JMB363,
77 	  1,
78 	  2
79 	},
80 	{ PCI_PRODUCT_JMICRON_JMB365,
81 	  2,
82 	  1
83 	},
84 	{ PCI_PRODUCT_JMICRON_JMB366,
85 	  2,
86 	  2
87 	},
88 	{ PCI_PRODUCT_JMICRON_JMB368,
89 	  1,
90 	  0
91 	},
92 	{ 0,
93 	  0,
94 	  0
95 	}
96 };
97 
98 typedef enum {
99 	TYPE_INVALID = 0,
100 	TYPE_PATA,
101 	TYPE_SATA,
102 	TYPE_NONE
103 } jmchan_t;
104 
105 struct jmide_softc {
106 	struct pciide_softc sc_pciide;
107 	device_t sc_ahci;
108 	int sc_npata;
109 	int sc_nsata;
110 	jmchan_t sc_chan_type[PCIIDE_NUM_CHANNELS];
111 	int sc_chan_swap;
112 };
113 
114 struct jmahci_attach_args {
115 	const struct pci_attach_args *jma_pa;
116 	bus_space_tag_t jma_ahcit;
117 	bus_space_handle_t jma_ahcih;
118 };
119 
120 #define JM_NAME(sc) (device_xname(sc->sc_pciide.sc_wdcdev.sc_atac.atac_dev))
121 
122 CFATTACH_DECL_NEW(jmide, sizeof(struct jmide_softc),
123     jmide_match, jmide_attach, NULL, NULL);
124 
125 static const struct jmide_product *
126 jmide_lookup(pcireg_t id) {
127 	const struct jmide_product *jp;
128 
129 	for (jp = jm_products; jp->jm_product != 0; jp++) {
130 		if (jp->jm_product == PCI_PRODUCT(id))
131 			return jp;
132 	}
133 	return NULL;
134 }
135 
136 static int
137 jmide_match(device_t parent, cfdata_t match, void *aux)
138 {
139 	struct pci_attach_args *pa = aux;
140 
141 	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_JMICRON) {
142 		if (jmide_lookup(pa->pa_id))
143 			return (4); /* higher than ahcisata */
144 	}
145 	return (0);
146 }
147 
148 static void
149 jmide_attach(device_t parent, device_t self, void *aux)
150 {
151 	struct pci_attach_args *pa = aux;
152 	struct jmide_softc *sc = device_private(self);
153 	const struct jmide_product *jp;
154 	const char *intrstr;
155         pci_intr_handle_t intrhandle;
156 	u_int32_t pcictrl0 = pci_conf_read(pa->pa_pc, pa->pa_tag,
157 	    PCI_JM_CONTROL0);
158 	u_int32_t pcictrl1 = pci_conf_read(pa->pa_pc, pa->pa_tag,
159 	    PCI_JM_CONTROL1);
160 	struct pciide_product_desc *pp;
161 	int ahci_used = 0;
162 	char intrbuf[PCI_INTRSTR_LEN];
163 
164 	aprint_naive("\n");
165 	sc->sc_pciide.sc_wdcdev.sc_atac.atac_dev = self;
166 
167 	jp = jmide_lookup(pa->pa_id);
168 	if (jp == NULL) {
169 		aprint_error_dev(self, "jmide_attach: WTF?\n");
170 		return;
171 	}
172 	sc->sc_npata = jp->jm_npata;
173 	sc->sc_nsata = jp->jm_nsata;
174 
175         pci_aprint_devinfo(pa, "JMICRON PATA/SATA disk controller");
176 
177 	aprint_normal("%s: ", JM_NAME(sc));
178 	if (sc->sc_npata)
179 		aprint_normal("%d PATA port%s", sc->sc_npata,
180 		    (sc->sc_npata > 1) ? "s" : "");
181 	if (sc->sc_nsata)
182 		aprint_normal("%s%d SATA port%s", sc->sc_npata ? ", " : "",
183 		    sc->sc_nsata, (sc->sc_nsata > 1) ? "s" : "");
184 	aprint_normal("\n");
185 
186 	if (pci_intr_map(pa, &intrhandle) != 0) {
187                 aprint_error("%s: couldn't map interrupt\n", JM_NAME(sc));
188                 return;
189         }
190         intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf,
191 	    sizeof(intrbuf));
192         sc->sc_pciide.sc_pci_ih = pci_intr_establish_xname(pa->pa_pc,
193 	    intrhandle, IPL_BIO, jmide_intr, sc, device_xname(self));
194         if (sc->sc_pciide.sc_pci_ih == NULL) {
195                 aprint_error("%s: couldn't establish interrupt", JM_NAME(sc));
196                 return;
197         }
198         aprint_normal("%s: interrupting at %s\n", JM_NAME(sc),
199             intrstr ? intrstr : "unknown interrupt");
200 
201 	if (pcictrl0 & JM_CONTROL0_AHCI_EN) {
202 		bus_size_t size;
203 		struct jmahci_attach_args jma;
204 		u_int32_t saved_pcictrl0;
205 		/*
206 		 * ahci controller enabled; disable sata on pciide and
207 		 * enable on ahci
208 		 */
209 		saved_pcictrl0 = pcictrl0;
210 		pcictrl0 |= JM_CONTROL0_SATA0_AHCI | JM_CONTROL0_SATA1_AHCI;
211 		pcictrl0 &= ~(JM_CONTROL0_SATA0_IDE | JM_CONTROL0_SATA1_IDE);
212 		pci_conf_write(pa->pa_pc, pa->pa_tag,
213 		    PCI_JM_CONTROL0, pcictrl0);
214 		/* attach ahci controller if on the right function */
215 		if ((pa->pa_function == 0 &&
216 		      (pcictrl0 & JM_CONTROL0_AHCI_F1) == 0) ||
217 	    	    (pa->pa_function == 1 &&
218 		      (pcictrl0 & JM_CONTROL0_AHCI_F1) != 0)) {
219 			jma.jma_pa = pa;
220 			/* map registers */
221 			if (pci_mapreg_map(pa, AHCI_PCI_ABAR,
222 			    PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
223 			    &jma.jma_ahcit, &jma.jma_ahcih, NULL, &size) != 0) {
224 				aprint_error("%s: can't map ahci registers\n",
225 				    JM_NAME(sc));
226 			} else {
227 				sc->sc_ahci = config_found(
228 				    sc->sc_pciide.sc_wdcdev.sc_atac.atac_dev,
229 				    &jma, jmahci_print,
230 				    CFARGS(.iattr = "jmide_hl"));
231 			}
232 			/*
233 			 * if we couldn't attach an ahci, try to fall back
234 			 * to pciide. Note that this will not work if IDE
235 			 * is on function 0 and AHCI on function 1.
236 			 */
237 			if (sc->sc_ahci == NULL) {
238 				pcictrl0 = saved_pcictrl0 &
239 				    ~(JM_CONTROL0_SATA0_AHCI |
240 				      JM_CONTROL0_SATA1_AHCI |
241 				      JM_CONTROL0_AHCI_EN);
242 				pcictrl0 |= JM_CONTROL0_SATA1_IDE |
243 					JM_CONTROL0_SATA0_IDE;
244 				pci_conf_write(pa->pa_pc, pa->pa_tag,
245 				    PCI_JM_CONTROL0, pcictrl0);
246 			} else
247 				ahci_used = 1;
248 		}
249 	}
250 	sc->sc_chan_swap = ((pcictrl0 & JM_CONTROL0_PCIIDE_CS) != 0);
251 	/* compute the type of internal primary channel */
252 	if (pcictrl1 & JM_CONTROL1_PATA1_PRI) {
253 		if (sc->sc_npata > 1)
254 			sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_PATA;
255 		else
256 			sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_NONE;
257 	} else if (ahci_used == 0 && sc->sc_nsata > 0)
258 		sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_SATA;
259 	else
260 		sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_NONE;
261 	/* compute the type of internal secondary channel */
262 	if (sc->sc_nsata > 1 && ahci_used == 0 &&
263 	    (pcictrl0 & JM_CONTROL0_PCIIDE0_MS) == 0) {
264 		sc->sc_chan_type[sc->sc_chan_swap ? 0 : 1] = TYPE_SATA;
265 	} else {
266 		/* only a drive if first PATA enabled */
267 		if (sc->sc_npata > 0 && (pcictrl0 & JM_CONTROL0_PATA0_EN)
268 		    && (pcictrl0 &
269 		    (sc->sc_chan_swap ? JM_CONTROL0_PATA0_PRI: JM_CONTROL0_PATA0_SEC)))
270 			sc->sc_chan_type[sc->sc_chan_swap ? 0 : 1] = TYPE_PATA;
271 		else
272 			sc->sc_chan_type[sc->sc_chan_swap ? 0 : 1] = TYPE_NONE;
273 	}
274 
275 	if (sc->sc_chan_type[0] == TYPE_NONE &&
276 	    sc->sc_chan_type[1] == TYPE_NONE)
277 		return;
278 	if (pa->pa_function == 0 && (pcictrl0 & JM_CONTROL0_PCIIDE_F1))
279 		return;
280 	if (pa->pa_function == 1 && (pcictrl0 & JM_CONTROL0_PCIIDE_F1) == 0)
281 		return;
282 	pp = malloc(sizeof(struct pciide_product_desc), M_DEVBUF, M_WAITOK);
283 	aprint_normal("%s: PCI IDE interface used", JM_NAME(sc));
284 	pp->ide_product = 0;
285 	pp->ide_flags = 0;
286 	pp->ide_name = NULL;
287 	pp->chip_map = jmpata_chip_map;
288 	pciide_common_attach(&sc->sc_pciide, pa, pp);
289 }
290 
291 static int
292 jmide_intr(void *arg)
293 {
294 	struct jmide_softc *sc = arg;
295 	int ret = 0;
296 
297 #ifdef NJMAHCI
298 	if (sc->sc_ahci)
299 		ret |= ahci_intr(device_private(sc->sc_ahci));
300 #endif
301 	if (sc->sc_npata)
302 		ret |= pciide_pci_intr(&sc->sc_pciide);
303 	return ret;
304 }
305 
306 static void
307 jmpata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
308 {
309 	struct jmide_softc *jmidesc = (struct jmide_softc *)sc;
310 	int channel;
311 	pcireg_t interface;
312 	struct pciide_channel *cp;
313 
314 	if (pciide_chipen(sc, pa) == 0)
315 		return;
316 	aprint_verbose("%s: bus-master DMA support present", JM_NAME(jmidesc));
317 	pciide_mapreg_dma(sc, pa);
318 	aprint_verbose("\n");
319 	sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
320 	if (sc->sc_dma_ok) {
321 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
322 		sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
323 	}
324 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
325 	sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
326 	sc->sc_wdcdev.sc_atac.atac_set_modes = jmpata_setup_channel;
327 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
328 	sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
329 	sc->sc_wdcdev.wdc_maxdrives = 2;
330 	wdc_allocate_regs(&sc->sc_wdcdev);
331 	/*
332          * can't rely on the PCI_CLASS_REG content if the chip was in raid
333          * mode. We have to fake interface
334          */
335 	interface = PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
336 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
337 	    channel++) {
338 		cp = &sc->pciide_channels[channel];
339 		if (pciide_chansetup(sc, channel, interface) == 0)
340 			continue;
341 		aprint_normal("%s: %s channel is ", JM_NAME(jmidesc),
342 		    PCIIDE_CHANNEL_NAME(channel));
343 		switch(jmidesc->sc_chan_type[channel]) {
344 		case TYPE_PATA:
345 			aprint_normal("PATA");
346 			break;
347 		case TYPE_SATA:
348 			aprint_normal("SATA");
349 			break;
350 		case TYPE_NONE:
351 			aprint_normal("unused");
352 			break;
353 		default:
354 			aprint_normal("impossible");
355 			panic("jmide: wrong/uninitialised channel type");
356 		}
357 		aprint_normal("\n");
358 		if (jmidesc->sc_chan_type[channel] == TYPE_NONE) {
359 			cp->ata_channel.ch_flags |= ATACH_DISABLED;
360 			continue;
361 		}
362 		pciide_mapchan(pa, cp, interface, pciide_pci_intr);
363 	}
364 }
365 
366 static void
367 jmpata_setup_channel(struct ata_channel *chp)
368 {
369 	struct ata_drive_datas *drvp;
370 	int drive, s;
371 	u_int32_t idedma_ctl;
372 	struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
373 	struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
374 	struct jmide_softc *jmidesc = (struct jmide_softc *)sc;
375 	int ide80p;
376 
377 	/* setup DMA if needed */
378 	pciide_channel_dma_setup(cp);
379 
380 	idedma_ctl = 0;
381 
382 	/* cable type detect */
383 	ide80p = 1;
384 	if (chp->ch_channel == (jmidesc->sc_chan_swap ? 1 : 0)) {
385 		if (jmidesc->sc_chan_type[chp->ch_channel] == TYPE_PATA &&
386 		    (pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_JM_CONTROL1) &
387 		    JM_CONTROL1_PATA1_40P))
388 			ide80p = 0;
389 	} else {
390 		if (jmidesc->sc_chan_type[chp->ch_channel] == TYPE_PATA &&
391 		    (pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_JM_CONTROL0) &
392 		    JM_CONTROL0_PATA0_40P))
393 			ide80p = 0;
394 	}
395 
396 	for (drive = 0; drive < 2; drive++) {
397 		drvp = &chp->ch_drive[drive];
398 		/* If no drive, skip */
399 		if (drvp->drive_type == ATA_DRIVET_NONE)
400 			continue;
401 		if (drvp->drive_flags & ATA_DRIVE_UDMA) {
402 			/* use Ultra/DMA */
403 			s = splbio();
404 			drvp->drive_flags &= ~ATA_DRIVE_DMA;
405 			if (drvp->UDMA_mode > 2 && ide80p == 0)
406 				drvp->UDMA_mode = 2;
407 			splx(s);
408 			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
409 		} else if (drvp->drive_flags & ATA_DRIVE_DMA) {
410 			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
411 		}
412 	}
413 	/* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */
414 	if (idedma_ctl != 0) {
415 		/* Add software bits in status register */
416 		bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL],
417 		    0, idedma_ctl);
418 	}
419 }
420 
421 static int
422 jmahci_print(void *aux, const char *pnp)
423 {
424         if (pnp)
425                 aprint_normal("ahcisata at %s", pnp);
426 
427         return (UNCONF);
428 }
429 
430 
431 #ifdef NJMAHCI
432 static int  jmahci_match(device_t, cfdata_t, void *);
433 static void jmahci_attach(device_t, device_t, void *);
434 static int  jmahci_detach(device_t, int);
435 static bool jmahci_resume(device_t, const pmf_qual_t *);
436 
437 CFATTACH_DECL_NEW(jmahci, sizeof(struct ahci_softc),
438 	jmahci_match, jmahci_attach, jmahci_detach, NULL);
439 
440 static int
441 jmahci_match(device_t parent, cfdata_t match, void *aux)
442 {
443 	return 1;
444 }
445 
446 static void
447 jmahci_attach(device_t parent, device_t self, void *aux)
448 {
449 	struct jmahci_attach_args *jma = aux;
450 	const struct pci_attach_args *pa = jma->jma_pa;
451 	struct ahci_softc *sc = device_private(self);
452 	uint32_t ahci_cap;
453 
454 	aprint_naive(": AHCI disk controller\n");
455 	aprint_normal("\n");
456 
457 	sc->sc_atac.atac_dev = self;
458 	sc->sc_ahcit = jma->jma_ahcit;
459 	sc->sc_ahcih = jma->jma_ahcih;
460 
461 	ahci_cap = AHCI_READ(sc, AHCI_CAP);
462 
463 	if (pci_dma64_available(jma->jma_pa) && (ahci_cap & AHCI_CAP_64BIT))
464 		sc->sc_dmat = jma->jma_pa->pa_dmat64;
465 	else
466 		sc->sc_dmat = jma->jma_pa->pa_dmat;
467 
468 	if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
469 		sc->sc_atac_capflags = ATAC_CAP_RAID;
470 
471 	ahci_attach(sc);
472 
473 	if (!pmf_device_register(self, NULL, jmahci_resume))
474 	    aprint_error_dev(self, "couldn't establish power handler\n");
475 }
476 
477 static int
478 jmahci_detach(device_t dv, int flags)
479 {
480 	struct ahci_softc *sc;
481 	sc = device_private(dv);
482 
483 	int rv;
484 
485 	if ((rv = ahci_detach(sc, flags)))
486 		return rv;
487 
488 	return 0;
489 }
490 
491 static bool
492 jmahci_resume(device_t dv, const pmf_qual_t *qual)
493 {
494 	struct ahci_softc *sc;
495 	int s;
496 
497 	sc = device_private(dv);
498 
499 	s = splbio();
500 	ahci_resume(sc);
501 	splx(s);
502 
503 	return true;
504 }
505 #endif
506