1 /* $NetBSD: ixgbe_phy.c,v 1.23 2020/08/31 11:19:54 msaitoh Exp $ */ 2 3 /****************************************************************************** 4 SPDX-License-Identifier: BSD-3-Clause 5 6 Copyright (c) 2001-2017, Intel Corporation 7 All rights reserved. 8 9 Redistribution and use in source and binary forms, with or without 10 modification, are permitted provided that the following conditions are met: 11 12 1. Redistributions of source code must retain the above copyright notice, 13 this list of conditions and the following disclaimer. 14 15 2. Redistributions in binary form must reproduce the above copyright 16 notice, this list of conditions and the following disclaimer in the 17 documentation and/or other materials provided with the distribution. 18 19 3. Neither the name of the Intel Corporation nor the names of its 20 contributors may be used to endorse or promote products derived from 21 this software without specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 27 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 POSSIBILITY OF SUCH DAMAGE. 34 35 ******************************************************************************/ 36 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.c 331224 2018-03-19 20:55:05Z erj $*/ 37 38 #include "ixgbe_api.h" 39 #include "ixgbe_common.h" 40 #include "ixgbe_phy.h" 41 42 #include <dev/mii/mdio.h> 43 44 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 45 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 46 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 47 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 48 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 49 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 50 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 51 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 52 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 53 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 54 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 55 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 56 u8 *sff8472_data); 57 58 /** 59 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 60 * @hw: pointer to the hardware structure 61 * @byte: byte to send 62 * 63 * Returns an error code on error. 64 */ 65 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 66 { 67 s32 status; 68 69 status = ixgbe_clock_out_i2c_byte(hw, byte); 70 if (status) 71 return status; 72 return ixgbe_get_i2c_ack(hw); 73 } 74 75 /** 76 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 77 * @hw: pointer to the hardware structure 78 * @byte: pointer to a u8 to receive the byte 79 * 80 * Returns an error code on error. 81 */ 82 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 83 { 84 s32 status; 85 86 status = ixgbe_clock_in_i2c_byte(hw, byte); 87 if (status) 88 return status; 89 /* ACK */ 90 return ixgbe_clock_out_i2c_bit(hw, FALSE); 91 } 92 93 /** 94 * ixgbe_ones_comp_byte_add - Perform one's complement addition 95 * @add1: addend 1 96 * @add2: addend 2 97 * 98 * Returns one's complement 8-bit sum. 99 */ 100 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 101 { 102 u16 sum = add1 + add2; 103 104 sum = (sum & 0xFF) + (sum >> 8); 105 return sum & 0xFF; 106 } 107 108 /** 109 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation 110 * @hw: pointer to the hardware structure 111 * @addr: I2C bus address to read from 112 * @reg: I2C device register to read from 113 * @val: pointer to location to receive read value 114 * @lock: TRUE if to take and release semaphore 115 * 116 * Returns an error code on error. 117 */ 118 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 119 u16 *val, bool lock) 120 { 121 u32 swfw_mask = hw->phy.phy_semaphore_mask; 122 int max_retry = 3; 123 int retry = 0; 124 u8 csum_byte; 125 u8 high_bits; 126 u8 low_bits; 127 u8 reg_high; 128 u8 csum; 129 130 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 131 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 132 csum = ~csum; 133 do { 134 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 135 return IXGBE_ERR_SWFW_SYNC; 136 ixgbe_i2c_start(hw); 137 /* Device Address and write indication */ 138 if (ixgbe_out_i2c_byte_ack(hw, addr)) 139 goto fail; 140 /* Write bits 14:8 */ 141 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 142 goto fail; 143 /* Write bits 7:0 */ 144 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 145 goto fail; 146 /* Write csum */ 147 if (ixgbe_out_i2c_byte_ack(hw, csum)) 148 goto fail; 149 /* Re-start condition */ 150 ixgbe_i2c_start(hw); 151 /* Device Address and read indication */ 152 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 153 goto fail; 154 /* Get upper bits */ 155 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 156 goto fail; 157 /* Get low bits */ 158 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 159 goto fail; 160 /* Get csum */ 161 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte)) 162 goto fail; 163 /* NACK */ 164 if (ixgbe_clock_out_i2c_bit(hw, FALSE)) 165 goto fail; 166 ixgbe_i2c_stop(hw); 167 if (lock) 168 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 169 *val = (high_bits << 8) | low_bits; 170 return 0; 171 172 fail: 173 ixgbe_i2c_bus_clear(hw); 174 if (lock) 175 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 176 retry++; 177 if (retry < max_retry) 178 DEBUGOUT("I2C byte read combined error - Retrying.\n"); 179 else 180 DEBUGOUT("I2C byte read combined error.\n"); 181 } while (retry < max_retry); 182 183 return IXGBE_ERR_I2C; 184 } 185 186 /** 187 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation 188 * @hw: pointer to the hardware structure 189 * @addr: I2C bus address to write to 190 * @reg: I2C device register to write to 191 * @val: value to write 192 * @lock: TRUE if to take and release semaphore 193 * 194 * Returns an error code on error. 195 */ 196 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 197 u16 val, bool lock) 198 { 199 u32 swfw_mask = hw->phy.phy_semaphore_mask; 200 int max_retry = 1; 201 int retry = 0; 202 u8 reg_high; 203 u8 csum; 204 205 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 206 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 207 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 208 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 209 csum = ~csum; 210 do { 211 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 212 return IXGBE_ERR_SWFW_SYNC; 213 ixgbe_i2c_start(hw); 214 /* Device Address and write indication */ 215 if (ixgbe_out_i2c_byte_ack(hw, addr)) 216 goto fail; 217 /* Write bits 14:8 */ 218 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 219 goto fail; 220 /* Write bits 7:0 */ 221 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 222 goto fail; 223 /* Write data 15:8 */ 224 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 225 goto fail; 226 /* Write data 7:0 */ 227 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 228 goto fail; 229 /* Write csum */ 230 if (ixgbe_out_i2c_byte_ack(hw, csum)) 231 goto fail; 232 ixgbe_i2c_stop(hw); 233 if (lock) 234 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 235 return 0; 236 237 fail: 238 ixgbe_i2c_bus_clear(hw); 239 if (lock) 240 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 241 retry++; 242 if (retry < max_retry) 243 DEBUGOUT("I2C byte write combined error - Retrying.\n"); 244 else 245 DEBUGOUT("I2C byte write combined error.\n"); 246 } while (retry < max_retry); 247 248 return IXGBE_ERR_I2C; 249 } 250 251 /** 252 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 253 * @hw: pointer to the hardware structure 254 * 255 * Initialize the function pointers. 256 **/ 257 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 258 { 259 struct ixgbe_phy_info *phy = &hw->phy; 260 261 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 262 263 /* PHY */ 264 phy->ops.identify = ixgbe_identify_phy_generic; 265 phy->ops.reset = ixgbe_reset_phy_generic; 266 phy->ops.read_reg = ixgbe_read_phy_reg_generic; 267 phy->ops.write_reg = ixgbe_write_phy_reg_generic; 268 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; 269 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; 270 phy->ops.setup_link = ixgbe_setup_phy_link_generic; 271 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic; 272 phy->ops.check_link = NULL; 273 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 274 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic; 275 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic; 276 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic; 277 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic; 278 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic; 279 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear; 280 phy->ops.identify_sfp = ixgbe_identify_module_generic; 281 phy->sfp_type = ixgbe_sfp_type_unknown; 282 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked; 283 phy->ops.write_i2c_byte_unlocked = 284 ixgbe_write_i2c_byte_generic_unlocked; 285 phy->ops.check_overtemp = ixgbe_tn_check_overtemp; 286 return IXGBE_SUCCESS; 287 } 288 289 /** 290 * ixgbe_probe_phy - Probe a single address for a PHY 291 * @hw: pointer to hardware structure 292 * @phy_addr: PHY address to probe 293 * 294 * Returns TRUE if PHY found 295 */ 296 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr) 297 { 298 u16 ext_ability = 0; 299 300 if (!ixgbe_validate_phy_addr(hw, phy_addr)) { 301 DEBUGOUT1("Unable to validate PHY address 0x%04X\n", 302 phy_addr); 303 return FALSE; 304 } 305 306 if (ixgbe_get_phy_id(hw)) 307 return FALSE; 308 309 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id); 310 311 if (hw->phy.type == ixgbe_phy_unknown) { 312 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 313 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 314 if (ext_ability & 315 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 316 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 317 hw->phy.type = ixgbe_phy_cu_unknown; 318 else 319 hw->phy.type = ixgbe_phy_generic; 320 } 321 322 return TRUE; 323 } 324 325 /** 326 * ixgbe_identify_phy_generic - Get physical layer module 327 * @hw: pointer to hardware structure 328 * 329 * Determines the physical layer module found on the current adapter. 330 **/ 331 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 332 { 333 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 334 u16 phy_addr; 335 336 DEBUGFUNC("ixgbe_identify_phy_generic"); 337 338 if (!hw->phy.phy_semaphore_mask) { 339 if (hw->bus.lan_id) 340 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 341 else 342 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 343 } 344 345 if (hw->phy.type != ixgbe_phy_unknown) 346 return IXGBE_SUCCESS; 347 348 if (hw->phy.nw_mng_if_sel) { 349 phy_addr = (hw->phy.nw_mng_if_sel & 350 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 351 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 352 if (ixgbe_probe_phy(hw, phy_addr)) 353 return IXGBE_SUCCESS; 354 else 355 return IXGBE_ERR_PHY_ADDR_INVALID; 356 } 357 358 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 359 if (ixgbe_probe_phy(hw, phy_addr)) { 360 status = IXGBE_SUCCESS; 361 break; 362 } 363 } 364 365 /* Certain media types do not have a phy so an address will not 366 * be found and the code will take this path. Caller has to 367 * decide if it is an error or not. 368 */ 369 if (status != IXGBE_SUCCESS) 370 hw->phy.addr = 0; 371 372 return status; 373 } 374 375 /** 376 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 377 * @hw: pointer to the hardware structure 378 * 379 * This function checks the MMNGC.MNG_VETO bit to see if there are 380 * any constraints on link from manageability. For MAC's that don't 381 * have this bit just return faluse since the link can not be blocked 382 * via this method. 383 **/ 384 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 385 { 386 u32 mmngc; 387 388 DEBUGFUNC("ixgbe_check_reset_blocked"); 389 390 /* If we don't have this bit, it can't be blocking */ 391 if (hw->mac.type == ixgbe_mac_82598EB) 392 return FALSE; 393 394 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 395 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 396 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 397 "MNG_VETO bit detected.\n"); 398 return TRUE; 399 } 400 401 return FALSE; 402 } 403 404 /** 405 * ixgbe_validate_phy_addr - Determines phy address is valid 406 * @hw: pointer to hardware structure 407 * @phy_addr: PHY address 408 * 409 **/ 410 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 411 { 412 u16 phy_id = 0; 413 bool valid = FALSE; 414 415 DEBUGFUNC("ixgbe_validate_phy_addr"); 416 417 hw->phy.addr = phy_addr; 418 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 419 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 420 421 if (phy_id != 0xFFFF && phy_id != 0x0) 422 valid = TRUE; 423 424 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id); 425 426 return valid; 427 } 428 429 /** 430 * ixgbe_get_phy_id - Get the phy type 431 * @hw: pointer to hardware structure 432 * 433 **/ 434 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 435 { 436 u32 status; 437 u16 phy_id_high = 0; 438 u16 phy_id_low = 0; 439 440 DEBUGFUNC("ixgbe_get_phy_id"); 441 442 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 443 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 444 &phy_id_high); 445 446 if (status == IXGBE_SUCCESS) { 447 hw->phy.id = (u32)(phy_id_high << 16); 448 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 449 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 450 &phy_id_low); 451 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 452 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 453 } 454 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n", 455 phy_id_high, phy_id_low); 456 457 return status; 458 } 459 460 /** 461 * ixgbe_get_phy_type_from_id - Get the phy type 462 * @phy_id: PHY ID information 463 * 464 **/ 465 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 466 { 467 enum ixgbe_phy_type phy_type; 468 469 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 470 471 switch (phy_id) { 472 case TN1010_PHY_ID: 473 phy_type = ixgbe_phy_tn; 474 break; 475 case X550_PHY_ID2: 476 case X550_PHY_ID3: 477 case X540_PHY_ID: 478 phy_type = ixgbe_phy_aq; 479 break; 480 case QT2022_PHY_ID: 481 phy_type = ixgbe_phy_qt; 482 break; 483 case ATH_PHY_ID: 484 phy_type = ixgbe_phy_nl; 485 break; 486 case X557_PHY_ID: 487 case X557_PHY_ID2: 488 phy_type = ixgbe_phy_x550em_ext_t; 489 break; 490 case IXGBE_M88E1500_E_PHY_ID: 491 case IXGBE_M88E1543_E_PHY_ID: 492 phy_type = ixgbe_phy_ext_1g_t; 493 break; 494 default: 495 phy_type = ixgbe_phy_unknown; 496 break; 497 } 498 return phy_type; 499 } 500 501 /** 502 * ixgbe_reset_phy_generic - Performs a PHY reset 503 * @hw: pointer to hardware structure 504 **/ 505 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 506 { 507 u32 i; 508 u16 ctrl = 0; 509 s32 status = IXGBE_SUCCESS; 510 511 DEBUGFUNC("ixgbe_reset_phy_generic"); 512 513 if (hw->phy.type == ixgbe_phy_unknown) 514 status = ixgbe_identify_phy_generic(hw); 515 516 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 517 goto out; 518 519 /* Don't reset PHY if it's shut down due to overtemp. */ 520 if (!hw->phy.reset_if_overtemp && 521 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 522 goto out; 523 524 /* Blocked by MNG FW so bail */ 525 if (ixgbe_check_reset_blocked(hw)) 526 goto out; 527 528 /* 529 * Perform soft PHY reset to the PHY_XS. 530 * This will cause a soft reset to the PHY 531 */ 532 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 533 IXGBE_MDIO_PHY_XS_DEV_TYPE, 534 IXGBE_MDIO_PHY_XS_RESET); 535 536 /* 537 * Poll for reset bit to self-clear indicating reset is complete. 538 * Some PHYs could take up to 3 seconds to complete and need about 539 * 1.7 usec delay after the reset is complete. 540 */ 541 for (i = 0; i < 30; i++) { 542 msec_delay(100); 543 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 544 status = hw->phy.ops.read_reg(hw, 545 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 546 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 547 &ctrl); 548 if (status != IXGBE_SUCCESS) 549 return status; 550 551 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 552 usec_delay(2); 553 break; 554 } 555 } else { 556 status = hw->phy.ops.read_reg(hw, 557 IXGBE_MDIO_PHY_XS_CONTROL, 558 IXGBE_MDIO_PHY_XS_DEV_TYPE, 559 &ctrl); 560 if (status != IXGBE_SUCCESS) 561 return status; 562 563 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 564 usec_delay(2); 565 break; 566 } 567 } 568 } 569 570 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 571 status = IXGBE_ERR_RESET_FAILED; 572 ERROR_REPORT1(IXGBE_ERROR_POLLING, 573 "PHY reset polling failed to complete.\n"); 574 } 575 576 out: 577 return status; 578 } 579 580 /** 581 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 582 * the SWFW lock 583 * @hw: pointer to hardware structure 584 * @reg_addr: 32 bit address of PHY register to read 585 * @device_type: 5 bit device type 586 * @phy_data: Pointer to read data from PHY register 587 **/ 588 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 589 u16 *phy_data) 590 { 591 u32 i, data, command; 592 593 /* Setup and write the address cycle command */ 594 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 595 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 596 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 597 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 598 599 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 600 601 /* 602 * Check every 10 usec to see if the address cycle completed. 603 * The MDI Command bit will clear when the operation is 604 * complete 605 */ 606 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 607 usec_delay(10); 608 609 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 610 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 611 break; 612 } 613 614 615 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 616 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 617 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n"); 618 return IXGBE_ERR_PHY; 619 } 620 621 /* 622 * Address cycle complete, setup and write the read 623 * command 624 */ 625 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 626 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 627 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 628 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 629 630 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 631 632 /* 633 * Check every 10 usec to see if the address cycle 634 * completed. The MDI Command bit will clear when the 635 * operation is complete 636 */ 637 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 638 usec_delay(10); 639 640 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 641 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 642 break; 643 } 644 645 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 646 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 647 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n"); 648 return IXGBE_ERR_PHY; 649 } 650 651 /* 652 * Read operation is complete. Get the data 653 * from MSRWD 654 */ 655 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 656 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 657 *phy_data = (u16)(data); 658 659 return IXGBE_SUCCESS; 660 } 661 662 /** 663 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 664 * using the SWFW lock - this function is needed in most cases 665 * @hw: pointer to hardware structure 666 * @reg_addr: 32 bit address of PHY register to read 667 * @device_type: 5 bit device type 668 * @phy_data: Pointer to read data from PHY register 669 **/ 670 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 671 u32 device_type, u16 *phy_data) 672 { 673 s32 status; 674 u32 gssr = hw->phy.phy_semaphore_mask; 675 676 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 677 678 if (hw->mac.ops.acquire_swfw_sync(hw, gssr)) 679 return IXGBE_ERR_SWFW_SYNC; 680 681 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 682 683 hw->mac.ops.release_swfw_sync(hw, gssr); 684 685 return status; 686 } 687 688 /** 689 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 690 * without SWFW lock 691 * @hw: pointer to hardware structure 692 * @reg_addr: 32 bit PHY register to write 693 * @device_type: 5 bit device type 694 * @phy_data: Data to write to the PHY register 695 **/ 696 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 697 u32 device_type, u16 phy_data) 698 { 699 u32 i, command; 700 701 /* Put the data in the MDI single read and write data register*/ 702 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 703 704 /* Setup and write the address cycle command */ 705 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 706 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 707 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 708 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 709 710 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 711 712 /* 713 * Check every 10 usec to see if the address cycle completed. 714 * The MDI Command bit will clear when the operation is 715 * complete 716 */ 717 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 718 usec_delay(10); 719 720 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 721 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 722 break; 723 } 724 725 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 726 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 727 return IXGBE_ERR_PHY; 728 } 729 730 /* 731 * Address cycle complete, setup and write the write 732 * command 733 */ 734 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 735 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 736 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 737 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 738 739 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 740 741 /* 742 * Check every 10 usec to see if the address cycle 743 * completed. The MDI Command bit will clear when the 744 * operation is complete 745 */ 746 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 747 usec_delay(10); 748 749 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 750 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 751 break; 752 } 753 754 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 755 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 756 return IXGBE_ERR_PHY; 757 } 758 759 return IXGBE_SUCCESS; 760 } 761 762 /** 763 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 764 * using SWFW lock- this function is needed in most cases 765 * @hw: pointer to hardware structure 766 * @reg_addr: 32 bit PHY register to write 767 * @device_type: 5 bit device type 768 * @phy_data: Data to write to the PHY register 769 **/ 770 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 771 u32 device_type, u16 phy_data) 772 { 773 s32 status; 774 u32 gssr = hw->phy.phy_semaphore_mask; 775 776 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 777 778 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 779 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type, 780 phy_data); 781 hw->mac.ops.release_swfw_sync(hw, gssr); 782 } else { 783 status = IXGBE_ERR_SWFW_SYNC; 784 } 785 786 return status; 787 } 788 789 /** 790 * ixgbe_setup_phy_link_generic - Set and restart auto-neg 791 * @hw: pointer to hardware structure 792 * 793 * Restart auto-negotiation and PHY and waits for completion. 794 **/ 795 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 796 { 797 s32 status = IXGBE_SUCCESS; 798 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 799 bool autoneg = FALSE; 800 ixgbe_link_speed speed; 801 802 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 803 804 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 805 806 /* Set or unset auto-negotiation 10G advertisement */ 807 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 808 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 809 &autoneg_reg); 810 811 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 812 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) && 813 (speed & IXGBE_LINK_SPEED_10GB_FULL)) 814 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 815 816 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 817 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 818 autoneg_reg); 819 820 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 821 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 822 &autoneg_reg); 823 824 if (hw->mac.type == ixgbe_mac_X550) { 825 /* Set or unset auto-negotiation 5G advertisement */ 826 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE; 827 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) && 828 (speed & IXGBE_LINK_SPEED_5GB_FULL)) 829 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE; 830 831 /* Set or unset auto-negotiation 2.5G advertisement */ 832 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE; 833 if ((hw->phy.autoneg_advertised & 834 IXGBE_LINK_SPEED_2_5GB_FULL) && 835 (speed & IXGBE_LINK_SPEED_2_5GB_FULL)) 836 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE; 837 } 838 839 /* Set or unset auto-negotiation 1G advertisement */ 840 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 841 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) && 842 (speed & IXGBE_LINK_SPEED_1GB_FULL)) 843 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 844 845 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 846 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 847 autoneg_reg); 848 849 /* Set or unset auto-negotiation 100M advertisement */ 850 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 851 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 852 &autoneg_reg); 853 854 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 855 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 856 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) && 857 (speed & IXGBE_LINK_SPEED_100_FULL)) 858 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 859 860 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 861 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 862 autoneg_reg); 863 864 if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_100_FULL) { 865 u16 ctrl; 866 867 /* Force 100Mbps */ 868 hw->phy.ops.read_reg(hw, MDIO_PMAPMD_CTRL1, MDIO_MMD_PMAPMD, 869 &ctrl); 870 ctrl &= ~PMAPMD_CTRL1_SPEED_MASK; 871 ctrl |= PMAPMD_CTRL1_SPEED_100; 872 hw->phy.ops.write_reg(hw, MDIO_PMAPMD_CTRL1,MDIO_MMD_PMAPMD, 873 ctrl); 874 875 /* Don't use auto-nego for 100Mbps */ 876 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 877 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 878 879 autoneg_reg &= ~AN_CTRL1_AUTOEN; 880 881 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 882 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 883 } else { 884 /* Blocked by MNG FW so don't reset PHY */ 885 if (ixgbe_check_reset_blocked(hw)) 886 return status; 887 888 /* Restart PHY auto-negotiation. */ 889 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 890 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 891 892 autoneg_reg |= IXGBE_MII_RESTART | AN_CTRL1_AUTOEN; 893 894 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 895 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 896 } 897 898 return status; 899 } 900 901 /** 902 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 903 * @hw: pointer to hardware structure 904 * @speed: new link speed 905 * @autoneg_wait_to_complete: unused 906 **/ 907 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 908 ixgbe_link_speed speed, 909 bool autoneg_wait_to_complete) 910 { 911 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 912 913 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 914 915 /* 916 * Clear autoneg_advertised and set new values based on input link 917 * speed. 918 */ 919 hw->phy.autoneg_advertised = 0; 920 921 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 922 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 923 924 if (speed & IXGBE_LINK_SPEED_5GB_FULL) 925 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL; 926 927 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) 928 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 929 930 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 931 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 932 933 if (speed & IXGBE_LINK_SPEED_100_FULL) 934 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 935 936 if (speed & IXGBE_LINK_SPEED_10_FULL) 937 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL; 938 939 /* Setup link based on the new speed settings */ 940 ixgbe_setup_phy_link(hw); 941 942 return IXGBE_SUCCESS; 943 } 944 945 /** 946 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy 947 * @hw: pointer to hardware structure 948 * 949 * Determines the supported link capabilities by reading the PHY auto 950 * negotiation register. 951 **/ 952 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw) 953 { 954 s32 status; 955 u16 speed_ability; 956 957 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 958 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 959 &speed_ability); 960 if (status) 961 return status; 962 963 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 964 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; 965 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 966 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; 967 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 968 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; 969 970 switch (hw->mac.type) { 971 case ixgbe_mac_X550: 972 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; 973 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; 974 break; 975 case ixgbe_mac_X550EM_x: 976 case ixgbe_mac_X550EM_a: 977 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL; 978 break; 979 default: 980 break; 981 } 982 983 return status; 984 } 985 986 /** 987 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 988 * @hw: pointer to hardware structure 989 * @speed: pointer to link speed 990 * @autoneg: boolean auto-negotiation value 991 **/ 992 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 993 ixgbe_link_speed *speed, 994 bool *autoneg) 995 { 996 s32 status = IXGBE_SUCCESS; 997 998 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 999 1000 *autoneg = TRUE; 1001 if (!hw->phy.speeds_supported) 1002 status = ixgbe_get_copper_speeds_supported(hw); 1003 1004 *speed = hw->phy.speeds_supported; 1005 return status; 1006 } 1007 1008 /** 1009 * ixgbe_check_phy_link_tnx - Determine link and speed status 1010 * @hw: pointer to hardware structure 1011 * @speed: current link speed 1012 * @link_up: TRUE is link is up, FALSE otherwise 1013 * 1014 * Reads the VS1 register to determine if link is up and the current speed for 1015 * the PHY. 1016 **/ 1017 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 1018 bool *link_up) 1019 { 1020 s32 status = IXGBE_SUCCESS; 1021 u32 time_out; 1022 u32 max_time_out = 10; 1023 u16 phy_link = 0; 1024 u16 phy_speed = 0; 1025 u16 phy_data = 0; 1026 1027 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 1028 1029 /* Initialize speed and link to default case */ 1030 *link_up = FALSE; 1031 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1032 1033 /* 1034 * Check current speed and link status of the PHY register. 1035 * This is a vendor specific register and may have to 1036 * be changed for other copper PHYs. 1037 */ 1038 for (time_out = 0; time_out < max_time_out; time_out++) { 1039 usec_delay(10); 1040 status = hw->phy.ops.read_reg(hw, 1041 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 1042 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1043 &phy_data); 1044 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 1045 phy_speed = phy_data & 1046 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 1047 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 1048 *link_up = TRUE; 1049 if (phy_speed == 1050 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 1051 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1052 break; 1053 } 1054 } 1055 1056 return status; 1057 } 1058 1059 /** 1060 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg 1061 * @hw: pointer to hardware structure 1062 * 1063 * Restart auto-negotiation and PHY and waits for completion. 1064 **/ 1065 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 1066 { 1067 s32 status = IXGBE_SUCCESS; 1068 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 1069 bool autoneg = FALSE; 1070 ixgbe_link_speed speed; 1071 1072 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 1073 1074 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 1075 1076 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 1077 /* Set or unset auto-negotiation 10G advertisement */ 1078 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1079 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1080 &autoneg_reg); 1081 1082 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 1083 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 1084 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 1085 1086 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1087 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1088 autoneg_reg); 1089 } 1090 1091 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 1092 /* Set or unset auto-negotiation 1G advertisement */ 1093 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1094 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1095 &autoneg_reg); 1096 1097 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1098 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1099 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1100 1101 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1102 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1103 autoneg_reg); 1104 } 1105 1106 if (speed & IXGBE_LINK_SPEED_100_FULL) { 1107 /* Set or unset auto-negotiation 100M advertisement */ 1108 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1109 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1110 &autoneg_reg); 1111 1112 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 1113 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 1114 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 1115 1116 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1117 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1118 autoneg_reg); 1119 } 1120 1121 /* Blocked by MNG FW so don't reset PHY */ 1122 if (ixgbe_check_reset_blocked(hw)) 1123 return status; 1124 1125 /* Restart PHY auto-negotiation. */ 1126 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1127 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 1128 1129 autoneg_reg |= IXGBE_MII_RESTART; 1130 1131 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1132 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 1133 1134 return status; 1135 } 1136 1137 /** 1138 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 1139 * @hw: pointer to hardware structure 1140 * @firmware_version: pointer to the PHY Firmware Version 1141 **/ 1142 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 1143 u16 *firmware_version) 1144 { 1145 s32 status; 1146 1147 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 1148 1149 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 1150 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1151 firmware_version); 1152 1153 return status; 1154 } 1155 1156 /** 1157 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 1158 * @hw: pointer to hardware structure 1159 * @firmware_version: pointer to the PHY Firmware Version 1160 **/ 1161 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 1162 u16 *firmware_version) 1163 { 1164 s32 status; 1165 1166 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 1167 1168 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 1169 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1170 firmware_version); 1171 1172 return status; 1173 } 1174 1175 /** 1176 * ixgbe_reset_phy_nl - Performs a PHY reset 1177 * @hw: pointer to hardware structure 1178 **/ 1179 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 1180 { 1181 u16 phy_offset, control, eword, edata, block_crc; 1182 bool end_data = FALSE; 1183 u16 list_offset, data_offset; 1184 u16 phy_data = 0; 1185 s32 ret_val = IXGBE_SUCCESS; 1186 u32 i; 1187 1188 DEBUGFUNC("ixgbe_reset_phy_nl"); 1189 1190 /* Blocked by MNG FW so bail */ 1191 if (ixgbe_check_reset_blocked(hw)) 1192 goto out; 1193 1194 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1195 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1196 1197 /* reset the PHY and poll for completion */ 1198 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1199 IXGBE_MDIO_PHY_XS_DEV_TYPE, 1200 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 1201 1202 for (i = 0; i < 100; i++) { 1203 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1204 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1205 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 1206 break; 1207 msec_delay(10); 1208 } 1209 1210 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 1211 DEBUGOUT("PHY reset did not complete.\n"); 1212 ret_val = IXGBE_ERR_PHY; 1213 goto out; 1214 } 1215 1216 /* Get init offsets */ 1217 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 1218 &data_offset); 1219 if (ret_val != IXGBE_SUCCESS) 1220 goto out; 1221 1222 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 1223 data_offset++; 1224 while (!end_data) { 1225 /* 1226 * Read control word from PHY init contents offset 1227 */ 1228 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1229 if (ret_val) 1230 goto err_eeprom; 1231 control = (eword & IXGBE_CONTROL_MASK_NL) >> 1232 IXGBE_CONTROL_SHIFT_NL; 1233 edata = eword & IXGBE_DATA_MASK_NL; 1234 switch (control) { 1235 case IXGBE_DELAY_NL: 1236 data_offset++; 1237 DEBUGOUT1("DELAY: %d MS\n", edata); 1238 msec_delay(edata); 1239 break; 1240 case IXGBE_DATA_NL: 1241 DEBUGOUT("DATA:\n"); 1242 data_offset++; 1243 ret_val = hw->eeprom.ops.read(hw, data_offset, 1244 &phy_offset); 1245 if (ret_val) 1246 goto err_eeprom; 1247 data_offset++; 1248 for (i = 0; i < edata; i++) { 1249 ret_val = hw->eeprom.ops.read(hw, data_offset, 1250 &eword); 1251 if (ret_val) 1252 goto err_eeprom; 1253 hw->phy.ops.write_reg(hw, phy_offset, 1254 IXGBE_TWINAX_DEV, eword); 1255 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 1256 phy_offset); 1257 data_offset++; 1258 phy_offset++; 1259 } 1260 break; 1261 case IXGBE_CONTROL_NL: 1262 data_offset++; 1263 DEBUGOUT("CONTROL:\n"); 1264 if (edata == IXGBE_CONTROL_EOL_NL) { 1265 DEBUGOUT("EOL\n"); 1266 end_data = TRUE; 1267 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1268 DEBUGOUT("SOL\n"); 1269 } else { 1270 DEBUGOUT("Bad control value\n"); 1271 ret_val = IXGBE_ERR_PHY; 1272 goto out; 1273 } 1274 break; 1275 default: 1276 DEBUGOUT("Bad control type\n"); 1277 ret_val = IXGBE_ERR_PHY; 1278 goto out; 1279 } 1280 } 1281 1282 out: 1283 return ret_val; 1284 1285 err_eeprom: 1286 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1287 "eeprom read at offset %d failed", data_offset); 1288 return IXGBE_ERR_PHY; 1289 } 1290 1291 /************************************************************************ 1292 * ixgbe_sfp_cage_full 1293 * 1294 * Determine if an SFP+ module is inserted to the cage. 1295 ************************************************************************/ 1296 bool 1297 ixgbe_sfp_cage_full(struct ixgbe_hw *hw) 1298 { 1299 uint32_t mask; 1300 int rv; 1301 1302 KASSERT(hw->mac.type != ixgbe_mac_82598EB); 1303 1304 if (hw->mac.type >= ixgbe_mac_X540) 1305 mask = IXGBE_ESDP_SDP0; 1306 else 1307 mask = IXGBE_ESDP_SDP2; 1308 1309 rv = IXGBE_READ_REG(hw, IXGBE_ESDP) & mask; 1310 if ((hw->quirks & IXGBE_QUIRK_MOD_ABS_INVERT) != 0) 1311 rv = !rv; 1312 1313 if (hw->mac.type == ixgbe_mac_X550EM_a) { 1314 /* X550EM_a's SDP0 is inverted than others. */ 1315 return !rv; 1316 } 1317 1318 return rv; 1319 } /* ixgbe_sfp_cage_full */ 1320 1321 /** 1322 * ixgbe_identify_module_generic - Identifies module type 1323 * @hw: pointer to hardware structure 1324 * 1325 * Determines HW type and calls appropriate function. 1326 **/ 1327 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1328 { 1329 s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 1330 1331 DEBUGFUNC("ixgbe_identify_module_generic"); 1332 1333 /* Lightweight way to check if the cage is not full. */ 1334 if (hw->mac.type != ixgbe_mac_82598EB) { 1335 if (!ixgbe_sfp_cage_full(hw)) { 1336 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1337 return IXGBE_ERR_SFP_NOT_PRESENT; 1338 } 1339 } 1340 1341 switch (hw->mac.ops.get_media_type(hw)) { 1342 case ixgbe_media_type_fiber: 1343 status = ixgbe_identify_sfp_module_generic(hw); 1344 break; 1345 1346 case ixgbe_media_type_fiber_qsfp: 1347 status = ixgbe_identify_qsfp_module_generic(hw); 1348 break; 1349 1350 default: 1351 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1352 status = IXGBE_ERR_SFP_NOT_PRESENT; 1353 break; 1354 } 1355 1356 return status; 1357 } 1358 1359 /** 1360 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1361 * @hw: pointer to hardware structure 1362 * 1363 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1364 **/ 1365 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1366 { 1367 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1368 u32 vendor_oui = 0; 1369 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1370 u8 identifier = 0; 1371 u8 comp_codes_1g = 0; 1372 u8 comp_codes_10g = 0; 1373 u8 oui_bytes[3] = {0, 0, 0}; 1374 u8 cable_tech = 0; 1375 u8 cable_spec = 0; 1376 u16 enforce_sfp = 0; 1377 1378 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1379 1380 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1381 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1382 status = IXGBE_ERR_SFP_NOT_PRESENT; 1383 goto out; 1384 } 1385 1386 /* LAN ID is needed for I2C access */ 1387 hw->mac.ops.set_lan_id(hw); 1388 1389 status = hw->phy.ops.read_i2c_eeprom(hw, 1390 IXGBE_SFF_IDENTIFIER, 1391 &identifier); 1392 1393 if (status != IXGBE_SUCCESS) 1394 goto err_read_i2c_eeprom; 1395 1396 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1397 if (hw->phy.type != ixgbe_phy_nl) 1398 hw->phy.type = ixgbe_phy_sfp_unsupported; 1399 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1400 } else { 1401 status = hw->phy.ops.read_i2c_eeprom(hw, 1402 IXGBE_SFF_1GBE_COMP_CODES, 1403 &comp_codes_1g); 1404 1405 if (status != IXGBE_SUCCESS) 1406 goto err_read_i2c_eeprom; 1407 1408 status = hw->phy.ops.read_i2c_eeprom(hw, 1409 IXGBE_SFF_10GBE_COMP_CODES, 1410 &comp_codes_10g); 1411 1412 if (status != IXGBE_SUCCESS) 1413 goto err_read_i2c_eeprom; 1414 status = hw->phy.ops.read_i2c_eeprom(hw, 1415 IXGBE_SFF_CABLE_TECHNOLOGY, 1416 &cable_tech); 1417 1418 if (status != IXGBE_SUCCESS) 1419 goto err_read_i2c_eeprom; 1420 1421 /* ID Module 1422 * ========= 1423 * 0 SFP_DA_CU 1424 * 1 SFP_SR 1425 * 2 SFP_LR 1426 * 3 SFP_DA_CORE0 - 82599-specific 1427 * 4 SFP_DA_CORE1 - 82599-specific 1428 * 5 SFP_SR/LR_CORE0 - 82599-specific 1429 * 6 SFP_SR/LR_CORE1 - 82599-specific 1430 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1431 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1432 * 9 SFP_1g_cu_CORE0 - 82599-specific 1433 * 10 SFP_1g_cu_CORE1 - 82599-specific 1434 * 11 SFP_1g_sx_CORE0 - 82599-specific 1435 * 12 SFP_1g_sx_CORE1 - 82599-specific 1436 */ 1437 if (hw->mac.type == ixgbe_mac_82598EB) { 1438 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1439 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1440 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1441 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1442 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1443 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1444 else 1445 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1446 } else { 1447 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1448 if (hw->bus.lan_id == 0) 1449 hw->phy.sfp_type = 1450 ixgbe_sfp_type_da_cu_core0; 1451 else 1452 hw->phy.sfp_type = 1453 ixgbe_sfp_type_da_cu_core1; 1454 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1455 hw->phy.ops.read_i2c_eeprom( 1456 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1457 &cable_spec); 1458 if (cable_spec & 1459 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1460 if (hw->bus.lan_id == 0) 1461 hw->phy.sfp_type = 1462 ixgbe_sfp_type_da_act_lmt_core0; 1463 else 1464 hw->phy.sfp_type = 1465 ixgbe_sfp_type_da_act_lmt_core1; 1466 } else { 1467 hw->phy.sfp_type = 1468 ixgbe_sfp_type_unknown; 1469 } 1470 } else if (comp_codes_10g & 1471 (IXGBE_SFF_10GBASESR_CAPABLE | 1472 IXGBE_SFF_10GBASELR_CAPABLE)) { 1473 if (hw->bus.lan_id == 0) 1474 hw->phy.sfp_type = 1475 ixgbe_sfp_type_srlr_core0; 1476 else 1477 hw->phy.sfp_type = 1478 ixgbe_sfp_type_srlr_core1; 1479 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1480 if (hw->bus.lan_id == 0) 1481 hw->phy.sfp_type = 1482 ixgbe_sfp_type_1g_cu_core0; 1483 else 1484 hw->phy.sfp_type = 1485 ixgbe_sfp_type_1g_cu_core1; 1486 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1487 if (hw->bus.lan_id == 0) 1488 hw->phy.sfp_type = 1489 ixgbe_sfp_type_1g_sx_core0; 1490 else 1491 hw->phy.sfp_type = 1492 ixgbe_sfp_type_1g_sx_core1; 1493 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1494 if (hw->bus.lan_id == 0) 1495 hw->phy.sfp_type = 1496 ixgbe_sfp_type_1g_lx_core0; 1497 else 1498 hw->phy.sfp_type = 1499 ixgbe_sfp_type_1g_lx_core1; 1500 } else { 1501 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1502 } 1503 } 1504 1505 if (hw->phy.sfp_type != stored_sfp_type) 1506 hw->phy.sfp_setup_needed = TRUE; 1507 1508 /* Determine if the SFP+ PHY is dual speed or not. */ 1509 hw->phy.multispeed_fiber = FALSE; 1510 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1511 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1512 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1513 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1514 hw->phy.multispeed_fiber = TRUE; 1515 1516 /* Determine PHY vendor */ 1517 if (hw->phy.type != ixgbe_phy_nl) { 1518 hw->phy.id = identifier; 1519 status = hw->phy.ops.read_i2c_eeprom(hw, 1520 IXGBE_SFF_VENDOR_OUI_BYTE0, 1521 &oui_bytes[0]); 1522 1523 if (status != IXGBE_SUCCESS) 1524 goto err_read_i2c_eeprom; 1525 1526 status = hw->phy.ops.read_i2c_eeprom(hw, 1527 IXGBE_SFF_VENDOR_OUI_BYTE1, 1528 &oui_bytes[1]); 1529 1530 if (status != IXGBE_SUCCESS) 1531 goto err_read_i2c_eeprom; 1532 1533 status = hw->phy.ops.read_i2c_eeprom(hw, 1534 IXGBE_SFF_VENDOR_OUI_BYTE2, 1535 &oui_bytes[2]); 1536 1537 if (status != IXGBE_SUCCESS) 1538 goto err_read_i2c_eeprom; 1539 1540 vendor_oui = 1541 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1542 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1543 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1544 1545 switch (vendor_oui) { 1546 case IXGBE_SFF_VENDOR_OUI_TYCO: 1547 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1548 hw->phy.type = 1549 ixgbe_phy_sfp_passive_tyco; 1550 break; 1551 case IXGBE_SFF_VENDOR_OUI_FTL: 1552 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1553 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1554 else 1555 hw->phy.type = ixgbe_phy_sfp_ftl; 1556 break; 1557 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1558 hw->phy.type = ixgbe_phy_sfp_avago; 1559 break; 1560 case IXGBE_SFF_VENDOR_OUI_INTEL: 1561 hw->phy.type = ixgbe_phy_sfp_intel; 1562 break; 1563 default: 1564 hw->phy.type = ixgbe_phy_sfp_unknown; 1565 break; 1566 } 1567 } 1568 1569 /* Allow any DA cable vendor */ 1570 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1571 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1572 status = IXGBE_SUCCESS; 1573 1574 /* Keep phy.type for ixgbe_phy_nl */ 1575 if (hw->phy.type == ixgbe_phy_nl) 1576 goto out; 1577 1578 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1579 hw->phy.type = ixgbe_phy_sfp_passive_unknown; 1580 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1581 hw->phy.type = ixgbe_phy_sfp_active_unknown; 1582 goto out; 1583 } 1584 1585 /* Verify supported 1G SFP modules */ 1586 if (comp_codes_10g == 0 && 1587 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1588 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1589 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1590 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1591 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1592 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1593 if (hw->phy.type != ixgbe_phy_nl) 1594 hw->phy.type = ixgbe_phy_sfp_unsupported; 1595 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1596 goto out; 1597 } 1598 1599 /* Anything else 82598-based is supported */ 1600 if (hw->mac.type == ixgbe_mac_82598EB) { 1601 status = IXGBE_SUCCESS; 1602 goto out; 1603 } 1604 1605 ixgbe_get_device_caps(hw, &enforce_sfp); 1606 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1607 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1608 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1609 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1610 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1611 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1612 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1613 /* Make sure we're a supported PHY type */ 1614 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1615 status = IXGBE_SUCCESS; 1616 } else { 1617 if (hw->allow_unsupported_sfp == TRUE) { 1618 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1619 status = IXGBE_SUCCESS; 1620 } else { 1621 DEBUGOUT("SFP+ module not supported\n"); 1622 if (hw->phy.type != ixgbe_phy_nl) 1623 hw->phy.type = 1624 ixgbe_phy_sfp_unsupported; 1625 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1626 } 1627 } 1628 } else { 1629 status = IXGBE_SUCCESS; 1630 } 1631 } 1632 1633 out: 1634 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1635 hw->need_unsupported_sfp_recovery = true; 1636 return status; 1637 1638 err_read_i2c_eeprom: 1639 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1640 if (hw->phy.type != ixgbe_phy_nl) { 1641 hw->phy.id = 0; 1642 hw->phy.type = ixgbe_phy_unknown; 1643 } 1644 return IXGBE_ERR_SFP_NOT_PRESENT; 1645 } 1646 1647 /** 1648 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type 1649 * @hw: pointer to hardware structure 1650 * 1651 * Determines physical layer capabilities of the current SFP. 1652 */ 1653 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw) 1654 { 1655 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1656 u8 comp_codes_10g = 0; 1657 u8 comp_codes_1g = 0; 1658 1659 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic"); 1660 1661 hw->phy.ops.identify_sfp(hw); 1662 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1663 return physical_layer; 1664 1665 switch (hw->phy.type) { 1666 case ixgbe_phy_sfp_passive_tyco: 1667 case ixgbe_phy_sfp_passive_unknown: 1668 case ixgbe_phy_qsfp_passive_unknown: 1669 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1670 break; 1671 case ixgbe_phy_sfp_ftl_active: 1672 case ixgbe_phy_sfp_active_unknown: 1673 case ixgbe_phy_qsfp_active_unknown: 1674 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1675 break; 1676 case ixgbe_phy_sfp_avago: 1677 case ixgbe_phy_sfp_ftl: 1678 case ixgbe_phy_sfp_intel: 1679 case ixgbe_phy_sfp_unknown: 1680 hw->phy.ops.read_i2c_eeprom(hw, 1681 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1682 hw->phy.ops.read_i2c_eeprom(hw, 1683 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1684 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1685 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1686 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1687 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1688 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1689 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1690 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) 1691 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX; 1692 break; 1693 case ixgbe_phy_qsfp_intel: 1694 case ixgbe_phy_qsfp_unknown: 1695 hw->phy.ops.read_i2c_eeprom(hw, 1696 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g); 1697 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1698 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1699 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1700 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1701 break; 1702 default: 1703 break; 1704 } 1705 1706 return physical_layer; 1707 } 1708 1709 /** 1710 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1711 * @hw: pointer to hardware structure 1712 * 1713 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1714 **/ 1715 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1716 { 1717 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1718 u32 vendor_oui = 0; 1719 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1720 u8 identifier = 0; 1721 u8 comp_codes_1g = 0; 1722 u8 comp_codes_10g = 0; 1723 u8 oui_bytes[3] = {0, 0, 0}; 1724 u16 enforce_sfp = 0; 1725 u8 connector = 0; 1726 u8 cable_length = 0; 1727 u8 device_tech = 0; 1728 bool active_cable = FALSE; 1729 1730 DEBUGFUNC("ixgbe_identify_qsfp_module_generic"); 1731 1732 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1733 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1734 status = IXGBE_ERR_SFP_NOT_PRESENT; 1735 goto out; 1736 } 1737 1738 /* LAN ID is needed for I2C access */ 1739 hw->mac.ops.set_lan_id(hw); 1740 1741 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1742 &identifier); 1743 1744 if (status != IXGBE_SUCCESS) 1745 goto err_read_i2c_eeprom; 1746 1747 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1748 hw->phy.type = ixgbe_phy_sfp_unsupported; 1749 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1750 goto out; 1751 } 1752 1753 hw->phy.id = identifier; 1754 1755 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1756 &comp_codes_10g); 1757 1758 if (status != IXGBE_SUCCESS) 1759 goto err_read_i2c_eeprom; 1760 1761 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1762 &comp_codes_1g); 1763 1764 if (status != IXGBE_SUCCESS) 1765 goto err_read_i2c_eeprom; 1766 1767 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1768 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1769 if (hw->bus.lan_id == 0) 1770 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1771 else 1772 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1773 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1774 IXGBE_SFF_10GBASELR_CAPABLE)) { 1775 if (hw->bus.lan_id == 0) 1776 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1777 else 1778 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1779 } else { 1780 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1781 active_cable = TRUE; 1782 1783 if (!active_cable) { 1784 /* check for active DA cables that pre-date 1785 * SFF-8436 v3.6 */ 1786 hw->phy.ops.read_i2c_eeprom(hw, 1787 IXGBE_SFF_QSFP_CONNECTOR, 1788 &connector); 1789 1790 hw->phy.ops.read_i2c_eeprom(hw, 1791 IXGBE_SFF_QSFP_CABLE_LENGTH, 1792 &cable_length); 1793 1794 hw->phy.ops.read_i2c_eeprom(hw, 1795 IXGBE_SFF_QSFP_DEVICE_TECH, 1796 &device_tech); 1797 1798 if ((connector == 1799 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1800 (cable_length > 0) && 1801 ((device_tech >> 4) == 1802 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1803 active_cable = TRUE; 1804 } 1805 1806 if (active_cable) { 1807 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1808 if (hw->bus.lan_id == 0) 1809 hw->phy.sfp_type = 1810 ixgbe_sfp_type_da_act_lmt_core0; 1811 else 1812 hw->phy.sfp_type = 1813 ixgbe_sfp_type_da_act_lmt_core1; 1814 } else { 1815 /* unsupported module type */ 1816 hw->phy.type = ixgbe_phy_sfp_unsupported; 1817 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1818 goto out; 1819 } 1820 } 1821 1822 if (hw->phy.sfp_type != stored_sfp_type) 1823 hw->phy.sfp_setup_needed = TRUE; 1824 1825 /* Determine if the QSFP+ PHY is dual speed or not. */ 1826 hw->phy.multispeed_fiber = FALSE; 1827 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1828 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1829 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1830 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1831 hw->phy.multispeed_fiber = TRUE; 1832 1833 /* Determine PHY vendor for optical modules */ 1834 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1835 IXGBE_SFF_10GBASELR_CAPABLE)) { 1836 status = hw->phy.ops.read_i2c_eeprom(hw, 1837 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1838 &oui_bytes[0]); 1839 1840 if (status != IXGBE_SUCCESS) 1841 goto err_read_i2c_eeprom; 1842 1843 status = hw->phy.ops.read_i2c_eeprom(hw, 1844 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1845 &oui_bytes[1]); 1846 1847 if (status != IXGBE_SUCCESS) 1848 goto err_read_i2c_eeprom; 1849 1850 status = hw->phy.ops.read_i2c_eeprom(hw, 1851 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1852 &oui_bytes[2]); 1853 1854 if (status != IXGBE_SUCCESS) 1855 goto err_read_i2c_eeprom; 1856 1857 vendor_oui = 1858 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1859 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1860 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1861 1862 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1863 hw->phy.type = ixgbe_phy_qsfp_intel; 1864 else 1865 hw->phy.type = ixgbe_phy_qsfp_unknown; 1866 1867 ixgbe_get_device_caps(hw, &enforce_sfp); 1868 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1869 /* Make sure we're a supported PHY type */ 1870 if (hw->phy.type == ixgbe_phy_qsfp_intel) { 1871 status = IXGBE_SUCCESS; 1872 } else { 1873 if (hw->allow_unsupported_sfp == TRUE) { 1874 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1875 status = IXGBE_SUCCESS; 1876 } else { 1877 DEBUGOUT("QSFP module not supported\n"); 1878 hw->phy.type = 1879 ixgbe_phy_sfp_unsupported; 1880 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1881 } 1882 } 1883 } else { 1884 status = IXGBE_SUCCESS; 1885 } 1886 } 1887 1888 out: 1889 if (hw->phy.type == ixgbe_phy_sfp_unsupported) 1890 hw->need_unsupported_sfp_recovery = true; 1891 return status; 1892 1893 err_read_i2c_eeprom: 1894 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1895 hw->phy.id = 0; 1896 hw->phy.type = ixgbe_phy_unknown; 1897 1898 return IXGBE_ERR_SFP_NOT_PRESENT; 1899 } 1900 1901 /** 1902 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1903 * @hw: pointer to hardware structure 1904 * @list_offset: offset to the SFP ID list 1905 * @data_offset: offset to the SFP data block 1906 * 1907 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1908 * so it returns the offsets to the phy init sequence block. 1909 **/ 1910 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1911 u16 *list_offset, 1912 u16 *data_offset) 1913 { 1914 u16 sfp_id; 1915 u16 sfp_type = hw->phy.sfp_type; 1916 1917 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1918 1919 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1920 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1921 1922 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1923 return IXGBE_ERR_SFP_NOT_PRESENT; 1924 1925 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1926 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1927 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1928 1929 /* 1930 * Limiting active cables and 1G Phys must be initialized as 1931 * SR modules 1932 */ 1933 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1934 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1935 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1936 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1937 sfp_type = ixgbe_sfp_type_srlr_core0; 1938 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1939 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1940 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1941 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1942 sfp_type = ixgbe_sfp_type_srlr_core1; 1943 1944 /* Read offset to PHY init contents */ 1945 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1946 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1947 "eeprom read at offset %d failed", 1948 IXGBE_PHY_INIT_OFFSET_NL); 1949 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1950 } 1951 1952 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1953 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1954 1955 /* Shift offset to first ID word */ 1956 (*list_offset)++; 1957 1958 /* 1959 * Find the matching SFP ID in the EEPROM 1960 * and program the init sequence 1961 */ 1962 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1963 goto err_phy; 1964 1965 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1966 if (sfp_id == sfp_type) { 1967 (*list_offset)++; 1968 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1969 goto err_phy; 1970 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1971 DEBUGOUT("SFP+ module not supported\n"); 1972 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1973 } else { 1974 break; 1975 } 1976 } else { 1977 (*list_offset) += 2; 1978 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1979 goto err_phy; 1980 } 1981 } 1982 1983 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1984 DEBUGOUT("No matching SFP+ module found\n"); 1985 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1986 } 1987 1988 return IXGBE_SUCCESS; 1989 1990 err_phy: 1991 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1992 "eeprom read at offset %d failed", *list_offset); 1993 return IXGBE_ERR_PHY; 1994 } 1995 1996 /** 1997 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1998 * @hw: pointer to hardware structure 1999 * @byte_offset: EEPROM byte offset to read 2000 * @eeprom_data: value read 2001 * 2002 * Performs byte read operation to SFP module's EEPROM over I2C interface. 2003 **/ 2004 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 2005 u8 *eeprom_data) 2006 { 2007 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 2008 2009 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 2010 IXGBE_I2C_EEPROM_DEV_ADDR, 2011 eeprom_data); 2012 } 2013 2014 /** 2015 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 2016 * @hw: pointer to hardware structure 2017 * @byte_offset: byte offset at address 0xA2 2018 * @sff8472_data: value read 2019 * 2020 * Performs byte read operation to SFP module's SFF-8472 data over I2C 2021 **/ 2022 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 2023 u8 *sff8472_data) 2024 { 2025 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 2026 IXGBE_I2C_EEPROM_DEV_ADDR2, 2027 sff8472_data); 2028 } 2029 2030 /** 2031 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 2032 * @hw: pointer to hardware structure 2033 * @byte_offset: EEPROM byte offset to write 2034 * @eeprom_data: value to write 2035 * 2036 * Performs byte write operation to SFP module's EEPROM over I2C interface. 2037 **/ 2038 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 2039 u8 eeprom_data) 2040 { 2041 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 2042 2043 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 2044 IXGBE_I2C_EEPROM_DEV_ADDR, 2045 eeprom_data); 2046 } 2047 2048 /** 2049 * ixgbe_is_sfp_probe - Returns TRUE if SFP is being detected 2050 * @hw: pointer to hardware structure 2051 * @offset: eeprom offset to be read 2052 * @addr: I2C address to be read 2053 */ 2054 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) 2055 { 2056 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR && 2057 offset == IXGBE_SFF_IDENTIFIER && 2058 hw->phy.sfp_type == ixgbe_sfp_type_not_present) 2059 return TRUE; 2060 return FALSE; 2061 } 2062 2063 /** 2064 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C 2065 * @hw: pointer to hardware structure 2066 * @byte_offset: byte offset to read 2067 * @dev_addr: address to read from 2068 * @data: value read 2069 * @lock: TRUE if to take and release semaphore 2070 * 2071 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2072 * a specified device address. 2073 **/ 2074 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2075 u8 dev_addr, u8 *data, bool lock) 2076 { 2077 s32 status; 2078 u32 max_retry = 10; 2079 u32 retry = 0; 2080 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2081 bool nack = 1; 2082 *data = 0; 2083 2084 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 2085 2086 if (hw->mac.type >= ixgbe_mac_X550) 2087 max_retry = 3; 2088 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) 2089 max_retry = IXGBE_SFP_DETECT_RETRIES; 2090 2091 do { 2092 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 2093 return IXGBE_ERR_SWFW_SYNC; 2094 2095 ixgbe_i2c_start(hw); 2096 2097 /* Device Address and write indication */ 2098 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2099 if (status != IXGBE_SUCCESS) 2100 goto fail; 2101 2102 status = ixgbe_get_i2c_ack(hw); 2103 if (status != IXGBE_SUCCESS) 2104 goto fail; 2105 2106 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2107 if (status != IXGBE_SUCCESS) 2108 goto fail; 2109 2110 status = ixgbe_get_i2c_ack(hw); 2111 if (status != IXGBE_SUCCESS) 2112 goto fail; 2113 2114 ixgbe_i2c_start(hw); 2115 2116 /* Device Address and read indication */ 2117 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 2118 if (status != IXGBE_SUCCESS) 2119 goto fail; 2120 2121 status = ixgbe_get_i2c_ack(hw); 2122 if (status != IXGBE_SUCCESS) 2123 goto fail; 2124 2125 status = ixgbe_clock_in_i2c_byte(hw, data); 2126 if (status != IXGBE_SUCCESS) 2127 goto fail; 2128 2129 status = ixgbe_clock_out_i2c_bit(hw, nack); 2130 if (status != IXGBE_SUCCESS) 2131 goto fail; 2132 2133 ixgbe_i2c_stop(hw); 2134 if (lock) 2135 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2136 return IXGBE_SUCCESS; 2137 2138 fail: 2139 ixgbe_i2c_bus_clear(hw); 2140 if (lock) { 2141 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2142 msec_delay(100); 2143 } 2144 retry++; 2145 if (retry < max_retry) 2146 DEBUGOUT("I2C byte read error - Retrying.\n"); 2147 else 2148 DEBUGOUT("I2C byte read error.\n"); 2149 2150 } while (retry < max_retry); 2151 2152 return status; 2153 } 2154 2155 /** 2156 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 2157 * @hw: pointer to hardware structure 2158 * @byte_offset: byte offset to read 2159 * @dev_addr: address to read from 2160 * @data: value read 2161 * 2162 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2163 * a specified device address. 2164 **/ 2165 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2166 u8 dev_addr, u8 *data) 2167 { 2168 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2169 data, TRUE); 2170 } 2171 2172 /** 2173 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C 2174 * @hw: pointer to hardware structure 2175 * @byte_offset: byte offset to read 2176 * @dev_addr: address to read from 2177 * @data: value read 2178 * 2179 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2180 * a specified device address. 2181 **/ 2182 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2183 u8 dev_addr, u8 *data) 2184 { 2185 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2186 data, FALSE); 2187 } 2188 2189 /** 2190 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C 2191 * @hw: pointer to hardware structure 2192 * @byte_offset: byte offset to write 2193 * @dev_addr: address to write to 2194 * @data: value to write 2195 * @lock: TRUE if to take and release semaphore 2196 * 2197 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2198 * a specified device address. 2199 **/ 2200 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2201 u8 dev_addr, u8 data, bool lock) 2202 { 2203 s32 status; 2204 u32 max_retry = 2; 2205 u32 retry = 0; 2206 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2207 2208 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 2209 2210 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 2211 IXGBE_SUCCESS) 2212 return IXGBE_ERR_SWFW_SYNC; 2213 2214 do { 2215 ixgbe_i2c_start(hw); 2216 2217 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2218 if (status != IXGBE_SUCCESS) 2219 goto fail; 2220 2221 status = ixgbe_get_i2c_ack(hw); 2222 if (status != IXGBE_SUCCESS) 2223 goto fail; 2224 2225 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2226 if (status != IXGBE_SUCCESS) 2227 goto fail; 2228 2229 status = ixgbe_get_i2c_ack(hw); 2230 if (status != IXGBE_SUCCESS) 2231 goto fail; 2232 2233 status = ixgbe_clock_out_i2c_byte(hw, data); 2234 if (status != IXGBE_SUCCESS) 2235 goto fail; 2236 2237 status = ixgbe_get_i2c_ack(hw); 2238 if (status != IXGBE_SUCCESS) 2239 goto fail; 2240 2241 ixgbe_i2c_stop(hw); 2242 if (lock) 2243 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2244 return IXGBE_SUCCESS; 2245 2246 fail: 2247 ixgbe_i2c_bus_clear(hw); 2248 retry++; 2249 if (retry < max_retry) 2250 DEBUGOUT("I2C byte write error - Retrying.\n"); 2251 else 2252 DEBUGOUT("I2C byte write error.\n"); 2253 } while (retry < max_retry); 2254 2255 if (lock) 2256 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2257 2258 return status; 2259 } 2260 2261 /** 2262 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 2263 * @hw: pointer to hardware structure 2264 * @byte_offset: byte offset to write 2265 * @dev_addr: address to write to 2266 * @data: value to write 2267 * 2268 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2269 * a specified device address. 2270 **/ 2271 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2272 u8 dev_addr, u8 data) 2273 { 2274 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2275 data, TRUE); 2276 } 2277 2278 /** 2279 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C 2280 * @hw: pointer to hardware structure 2281 * @byte_offset: byte offset to write 2282 * @dev_addr: address to write to 2283 * @data: value to write 2284 * 2285 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2286 * a specified device address. 2287 **/ 2288 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2289 u8 dev_addr, u8 data) 2290 { 2291 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2292 data, FALSE); 2293 } 2294 2295 /** 2296 * ixgbe_i2c_start - Sets I2C start condition 2297 * @hw: pointer to hardware structure 2298 * 2299 * Sets I2C start condition (High -> Low on SDA while SCL is High) 2300 * Set bit-bang mode on X550 hardware. 2301 **/ 2302 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 2303 { 2304 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2305 2306 DEBUGFUNC("ixgbe_i2c_start"); 2307 2308 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw); 2309 2310 /* Start condition must begin with data and clock high */ 2311 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2312 ixgbe_raise_i2c_clk(hw, &i2cctl); 2313 2314 /* Setup time for start condition (4.7us) */ 2315 usec_delay(IXGBE_I2C_T_SU_STA); 2316 2317 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2318 2319 /* Hold time for start condition (4us) */ 2320 usec_delay(IXGBE_I2C_T_HD_STA); 2321 2322 ixgbe_lower_i2c_clk(hw, &i2cctl); 2323 2324 /* Minimum low period of clock is 4.7 us */ 2325 usec_delay(IXGBE_I2C_T_LOW); 2326 2327 } 2328 2329 /** 2330 * ixgbe_i2c_stop - Sets I2C stop condition 2331 * @hw: pointer to hardware structure 2332 * 2333 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2334 * Disables bit-bang mode and negates data output enable on X550 2335 * hardware. 2336 **/ 2337 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 2338 { 2339 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2340 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2341 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2342 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw); 2343 2344 DEBUGFUNC("ixgbe_i2c_stop"); 2345 2346 /* Stop condition must begin with data low and clock high */ 2347 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2348 ixgbe_raise_i2c_clk(hw, &i2cctl); 2349 2350 /* Setup time for stop condition (4us) */ 2351 usec_delay(IXGBE_I2C_T_SU_STO); 2352 2353 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2354 2355 /* bus free time between stop and start (4.7us)*/ 2356 usec_delay(IXGBE_I2C_T_BUF); 2357 2358 if (bb_en_bit || data_oe_bit || clk_oe_bit) { 2359 i2cctl &= ~bb_en_bit; 2360 i2cctl |= data_oe_bit | clk_oe_bit; 2361 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2362 IXGBE_WRITE_FLUSH(hw); 2363 } 2364 } 2365 2366 /** 2367 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 2368 * @hw: pointer to hardware structure 2369 * @data: data byte to clock in 2370 * 2371 * Clocks in one byte data via I2C data/clock 2372 **/ 2373 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 2374 { 2375 s32 i; 2376 bool bit = 0; 2377 2378 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 2379 2380 *data = 0; 2381 for (i = 7; i >= 0; i--) { 2382 ixgbe_clock_in_i2c_bit(hw, &bit); 2383 *data |= bit << i; 2384 } 2385 2386 return IXGBE_SUCCESS; 2387 } 2388 2389 /** 2390 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 2391 * @hw: pointer to hardware structure 2392 * @data: data byte clocked out 2393 * 2394 * Clocks out one byte data via I2C data/clock 2395 **/ 2396 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 2397 { 2398 s32 status = IXGBE_SUCCESS; 2399 s32 i; 2400 u32 i2cctl; 2401 bool bit; 2402 2403 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 2404 2405 for (i = 7; i >= 0; i--) { 2406 bit = (data >> i) & 0x1; 2407 status = ixgbe_clock_out_i2c_bit(hw, bit); 2408 2409 if (status != IXGBE_SUCCESS) 2410 break; 2411 } 2412 2413 /* Release SDA line (set high) */ 2414 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2415 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2416 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2417 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2418 IXGBE_WRITE_FLUSH(hw); 2419 2420 return status; 2421 } 2422 2423 /** 2424 * ixgbe_get_i2c_ack - Polls for I2C ACK 2425 * @hw: pointer to hardware structure 2426 * 2427 * Clocks in/out one bit via I2C data/clock 2428 **/ 2429 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 2430 { 2431 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2432 s32 status = IXGBE_SUCCESS; 2433 u32 i = 0; 2434 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2435 u32 timeout = 10; 2436 bool ack = 1; 2437 2438 DEBUGFUNC("ixgbe_get_i2c_ack"); 2439 2440 if (data_oe_bit) { 2441 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2442 i2cctl |= data_oe_bit; 2443 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2444 IXGBE_WRITE_FLUSH(hw); 2445 } 2446 ixgbe_raise_i2c_clk(hw, &i2cctl); 2447 2448 /* Minimum high period of clock is 4us */ 2449 usec_delay(IXGBE_I2C_T_HIGH); 2450 2451 /* Poll for ACK. Note that ACK in I2C spec is 2452 * transition from 1 to 0 */ 2453 for (i = 0; i < timeout; i++) { 2454 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2455 ack = ixgbe_get_i2c_data(hw, &i2cctl); 2456 2457 usec_delay(1); 2458 if (!ack) 2459 break; 2460 } 2461 2462 if (ack) { 2463 DEBUGOUT("I2C ack was not received.\n"); 2464 status = IXGBE_ERR_I2C; 2465 } 2466 2467 ixgbe_lower_i2c_clk(hw, &i2cctl); 2468 2469 /* Minimum low period of clock is 4.7 us */ 2470 usec_delay(IXGBE_I2C_T_LOW); 2471 2472 return status; 2473 } 2474 2475 /** 2476 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 2477 * @hw: pointer to hardware structure 2478 * @data: read data value 2479 * 2480 * Clocks in one bit via I2C data/clock 2481 **/ 2482 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 2483 { 2484 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2485 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2486 2487 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 2488 2489 if (data_oe_bit) { 2490 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2491 i2cctl |= data_oe_bit; 2492 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2493 IXGBE_WRITE_FLUSH(hw); 2494 } 2495 ixgbe_raise_i2c_clk(hw, &i2cctl); 2496 2497 /* Minimum high period of clock is 4us */ 2498 usec_delay(IXGBE_I2C_T_HIGH); 2499 2500 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2501 *data = ixgbe_get_i2c_data(hw, &i2cctl); 2502 2503 ixgbe_lower_i2c_clk(hw, &i2cctl); 2504 2505 /* Minimum low period of clock is 4.7 us */ 2506 usec_delay(IXGBE_I2C_T_LOW); 2507 2508 return IXGBE_SUCCESS; 2509 } 2510 2511 /** 2512 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 2513 * @hw: pointer to hardware structure 2514 * @data: data value to write 2515 * 2516 * Clocks out one bit via I2C data/clock 2517 **/ 2518 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 2519 { 2520 s32 status; 2521 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2522 2523 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 2524 2525 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 2526 if (status == IXGBE_SUCCESS) { 2527 ixgbe_raise_i2c_clk(hw, &i2cctl); 2528 2529 /* Minimum high period of clock is 4us */ 2530 usec_delay(IXGBE_I2C_T_HIGH); 2531 2532 ixgbe_lower_i2c_clk(hw, &i2cctl); 2533 2534 /* Minimum low period of clock is 4.7 us. 2535 * This also takes care of the data hold time. 2536 */ 2537 usec_delay(IXGBE_I2C_T_LOW); 2538 } else { 2539 status = IXGBE_ERR_I2C; 2540 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2541 "I2C data was not set to %X\n", data); 2542 } 2543 2544 return status; 2545 } 2546 2547 /** 2548 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2549 * @hw: pointer to hardware structure 2550 * @i2cctl: Current value of I2CCTL register 2551 * 2552 * Raises the I2C clock line '0'->'1' 2553 * Negates the I2C clock output enable on X550 hardware. 2554 **/ 2555 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2556 { 2557 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2558 u32 i = 0; 2559 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2560 u32 i2cctl_r = 0; 2561 2562 DEBUGFUNC("ixgbe_raise_i2c_clk"); 2563 2564 if (clk_oe_bit) { 2565 *i2cctl |= clk_oe_bit; 2566 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2567 } 2568 2569 for (i = 0; i < timeout; i++) { 2570 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw); 2571 2572 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2573 IXGBE_WRITE_FLUSH(hw); 2574 /* SCL rise time (1000ns) */ 2575 usec_delay(IXGBE_I2C_T_RISE); 2576 2577 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2578 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw)) 2579 break; 2580 } 2581 } 2582 2583 /** 2584 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2585 * @hw: pointer to hardware structure 2586 * @i2cctl: Current value of I2CCTL register 2587 * 2588 * Lowers the I2C clock line '1'->'0' 2589 * Asserts the I2C clock output enable on X550 hardware. 2590 **/ 2591 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2592 { 2593 DEBUGFUNC("ixgbe_lower_i2c_clk"); 2594 2595 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw)); 2596 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2597 2598 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2599 IXGBE_WRITE_FLUSH(hw); 2600 2601 /* SCL fall time (300ns) */ 2602 usec_delay(IXGBE_I2C_T_FALL); 2603 } 2604 2605 /** 2606 * ixgbe_set_i2c_data - Sets the I2C data bit 2607 * @hw: pointer to hardware structure 2608 * @i2cctl: Current value of I2CCTL register 2609 * @data: I2C data value (0 or 1) to set 2610 * 2611 * Sets the I2C data bit 2612 * Asserts the I2C data output enable on X550 hardware. 2613 **/ 2614 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2615 { 2616 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2617 s32 status = IXGBE_SUCCESS; 2618 2619 DEBUGFUNC("ixgbe_set_i2c_data"); 2620 2621 if (data) 2622 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2623 else 2624 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw)); 2625 *i2cctl &= ~data_oe_bit; 2626 2627 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2628 IXGBE_WRITE_FLUSH(hw); 2629 2630 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2631 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2632 2633 if (!data) /* Can't verify data in this case */ 2634 return IXGBE_SUCCESS; 2635 if (data_oe_bit) { 2636 *i2cctl |= data_oe_bit; 2637 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2638 IXGBE_WRITE_FLUSH(hw); 2639 } 2640 2641 /* Verify data was set correctly */ 2642 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2643 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2644 status = IXGBE_ERR_I2C; 2645 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2646 "Error - I2C data was not set to %X.\n", 2647 data); 2648 } 2649 2650 return status; 2651 } 2652 2653 /** 2654 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2655 * @hw: pointer to hardware structure 2656 * @i2cctl: Current value of I2CCTL register 2657 * 2658 * Returns the I2C data bit value 2659 * Negates the I2C data output enable on X550 hardware. 2660 **/ 2661 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2662 { 2663 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2664 bool data; 2665 2666 DEBUGFUNC("ixgbe_get_i2c_data"); 2667 2668 if (data_oe_bit) { 2669 *i2cctl |= data_oe_bit; 2670 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2671 IXGBE_WRITE_FLUSH(hw); 2672 usec_delay(IXGBE_I2C_T_FALL); 2673 } 2674 2675 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw)) 2676 data = 1; 2677 else 2678 data = 0; 2679 2680 return data; 2681 } 2682 2683 /** 2684 * ixgbe_i2c_bus_clear - Clears the I2C bus 2685 * @hw: pointer to hardware structure 2686 * 2687 * Clears the I2C bus by sending nine clock pulses. 2688 * Used when data line is stuck low. 2689 **/ 2690 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2691 { 2692 u32 i2cctl; 2693 u32 i; 2694 2695 DEBUGFUNC("ixgbe_i2c_bus_clear"); 2696 2697 ixgbe_i2c_start(hw); 2698 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2699 2700 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2701 2702 for (i = 0; i < 9; i++) { 2703 ixgbe_raise_i2c_clk(hw, &i2cctl); 2704 2705 /* Min high period of clock is 4us */ 2706 usec_delay(IXGBE_I2C_T_HIGH); 2707 2708 ixgbe_lower_i2c_clk(hw, &i2cctl); 2709 2710 /* Min low period of clock is 4.7us*/ 2711 usec_delay(IXGBE_I2C_T_LOW); 2712 } 2713 2714 ixgbe_i2c_start(hw); 2715 2716 /* Put the i2c bus back to default state */ 2717 ixgbe_i2c_stop(hw); 2718 } 2719 2720 /** 2721 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2722 * @hw: pointer to hardware structure 2723 * 2724 * Checks if the LASI temp alarm status was triggered due to overtemp 2725 **/ 2726 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2727 { 2728 s32 status = IXGBE_SUCCESS; 2729 u16 phy_data = 0; 2730 2731 DEBUGFUNC("ixgbe_tn_check_overtemp"); 2732 2733 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2734 goto out; 2735 2736 /* Check that the LASI temp alarm status was triggered */ 2737 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2738 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 2739 2740 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2741 goto out; 2742 2743 status = IXGBE_ERR_OVERTEMP; 2744 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 2745 out: 2746 return status; 2747 } 2748 2749 /** 2750 * ixgbe_set_copper_phy_power - Control power for copper phy 2751 * @hw: pointer to hardware structure 2752 * @on: TRUE for on, FALSE for off 2753 */ 2754 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2755 { 2756 u32 status; 2757 u16 reg; 2758 2759 if (!on && ixgbe_mng_present(hw)) 2760 return 0; 2761 2762 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2763 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2764 ®); 2765 if (status) 2766 return status; 2767 2768 if (on) { 2769 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2770 } else { 2771 if (ixgbe_check_reset_blocked(hw)) 2772 return 0; 2773 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2774 } 2775 2776 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2777 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2778 reg); 2779 return status; 2780 } 2781