1 /****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_osdep.h,v 1.9 2010/11/26 22:46:32 jfv Exp $*/ 34 /*$NetBSD: ixgbe_osdep.h,v 1.3 2014/03/18 18:20:42 riastradh Exp $*/ 35 36 #ifndef _IXGBE_OS_H_ 37 #define _IXGBE_OS_H_ 38 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/mbuf.h> 43 #include <sys/protosw.h> 44 #include <sys/socket.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/cprng.h> 48 #include <sys/bus.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcireg.h> 51 #include <net/if.h> 52 #include <net/if_ether.h> 53 54 #define ASSERT(x) if(!(x)) panic("IXGBE: x") 55 56 /* The happy-fun DELAY macro is defined in /usr/src/sys/i386/include/clock.h */ 57 #define usec_delay(x) DELAY(x) 58 #define msec_delay(x) DELAY(1000*(x)) 59 60 #define DBG 0 61 #define MSGOUT(S, A, B) printf(S "\n", A, B) 62 #define DEBUGFUNC(F) DEBUGOUT(F); 63 #if DBG 64 #define DEBUGOUT(S) printf(S "\n") 65 #define DEBUGOUT1(S,A) printf(S "\n",A) 66 #define DEBUGOUT2(S,A,B) printf(S "\n",A,B) 67 #define DEBUGOUT3(S,A,B,C) printf(S "\n",A,B,C) 68 #define DEBUGOUT7(S,A,B,C,D,E,F,G) printf(S "\n",A,B,C,D,E,F,G) 69 #else 70 #define DEBUGOUT(S) do { } while (/*CONSTCOND*/false) 71 #define DEBUGOUT1(S,A) do { } while (/*CONSTCOND*/false) 72 #define DEBUGOUT2(S,A,B) do { } while (/*CONSTCOND*/false) 73 #define DEBUGOUT3(S,A,B,C) do { } while (/*CONSTCOND*/false) 74 #define DEBUGOUT6(S,A,B,C,D,E,F) \ 75 do { } while (/*CONSTCOND*/false) 76 #define DEBUGOUT7(S,A,B,C,D,E,F,G) \ 77 do { } while (/*CONSTCOND*/false) 78 #endif 79 80 #define FALSE 0 81 #define false 0 /* shared code requires this */ 82 #define TRUE 1 83 #define true 1 84 #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */ 85 #define PCI_COMMAND_REGISTER PCIR_COMMAND 86 #define UNREFERENCED_PARAMETER(_p) 87 88 89 #define IXGBE_NTOHL(_i) ntohl(_i) 90 #define IXGBE_NTOHS(_i) ntohs(_i) 91 92 typedef uint8_t u8; 93 typedef int8_t s8; 94 typedef uint16_t u16; 95 typedef uint32_t u32; 96 typedef int32_t s32; 97 typedef uint64_t u64; 98 99 #define le16_to_cpu 100 101 #if __FreeBSD_version < 800000 102 #if defined(__i386__) || defined(__amd64__) 103 #define mb() __asm volatile("mfence" ::: "memory") 104 #define wmb() __asm volatile("sfence" ::: "memory") 105 #define rmb() __asm volatile("lfence" ::: "memory") 106 #else 107 #define mb() 108 #define rmb() 109 #define wmb() 110 #endif 111 #endif 112 113 #if defined(__i386__) || defined(__amd64__) 114 static __inline 115 void prefetch(void *x) 116 { 117 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 118 } 119 #else 120 #define prefetch(x) 121 #endif 122 123 struct ixgbe_osdep 124 { 125 struct ethercom ec; 126 pci_chipset_tag_t pc; 127 pcitag_t tag; 128 bus_space_tag_t mem_bus_space_tag; 129 bus_space_handle_t mem_bus_space_handle; 130 bus_size_t mem_size; 131 bus_dma_tag_t dmat; 132 device_t dev; 133 pci_intr_handle_t ih; 134 void *intr; 135 }; 136 137 /* These routines are needed by the shared code */ 138 struct ixgbe_hw; 139 extern u16 ixgbe_read_pci_cfg(struct ixgbe_hw *, u32); 140 #define IXGBE_READ_PCIE_WORD ixgbe_read_pci_cfg 141 142 extern void ixgbe_write_pci_cfg(struct ixgbe_hw *, u32, u16); 143 #define IXGBE_WRITE_PCIE_WORD ixgbe_write_pci_cfg 144 145 #define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS) 146 147 #define IXGBE_READ_REG(a, reg) (\ 148 bus_space_read_4( ((a)->back)->mem_bus_space_tag, \ 149 ((a)->back)->mem_bus_space_handle, \ 150 reg)) 151 152 #define IXGBE_WRITE_REG(a, reg, value) (\ 153 bus_space_write_4( ((a)->back)->mem_bus_space_tag, \ 154 ((a)->back)->mem_bus_space_handle, \ 155 reg, value)) 156 157 158 #define IXGBE_READ_REG_ARRAY(a, reg, offset) (\ 159 bus_space_read_4( ((a)->back)->mem_bus_space_tag, \ 160 ((a)->back)->mem_bus_space_handle, \ 161 (reg + ((offset) << 2)))) 162 163 #define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) (\ 164 bus_space_write_4( ((a)->back)->mem_bus_space_tag, \ 165 ((a)->back)->mem_bus_space_handle, \ 166 (reg + ((offset) << 2)), value)) 167 168 169 #endif /* _IXGBE_OS_H_ */ 170