1 /****************************************************************************** 2 3 Copyright (c) 2001-2013, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_osdep.h 251964 2013-06-18 21:28:19Z jfv $*/ 34 /*$NetBSD: ixgbe_osdep.h,v 1.10 2015/08/13 04:56:43 msaitoh Exp $*/ 35 36 #ifndef _IXGBE_OS_H_ 37 #define _IXGBE_OS_H_ 38 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/endian.h> 42 #include <sys/systm.h> 43 #include <sys/mbuf.h> 44 #include <sys/protosw.h> 45 #include <sys/socket.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/cprng.h> 49 #include <sys/bus.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 #include <net/if.h> 53 #include <net/if_ether.h> 54 55 #define ASSERT(x) if(!(x)) panic("IXGBE: x") 56 #define EWARN(H, W, S) printf(W) 57 58 /* The happy-fun DELAY macro is defined in /usr/src/sys/i386/include/clock.h */ 59 #define usec_delay(x) DELAY(x) 60 #define msec_delay(x) DELAY(1000*(x)) 61 62 #define DBG 0 63 #define MSGOUT(S, A, B) printf(S "\n", A, B) 64 #define DEBUGFUNC(F) DEBUGOUT(F); 65 #if DBG 66 #define DEBUGOUT(S) printf(S "\n") 67 #define DEBUGOUT1(S,A) printf(S "\n",A) 68 #define DEBUGOUT2(S,A,B) printf(S "\n",A,B) 69 #define DEBUGOUT3(S,A,B,C) printf(S "\n",A,B,C) 70 #define DEBUGOUT4(S,A,B,C,D) printf(S "\n",A,B,C,D) 71 #define DEBUGOUT5(S,A,B,C,D,E) printf(S "\n",A,B,C,D,E) 72 #define DEBUGOUT6(S,A,B,C,D,E,F) printf(S "\n",A,B,C,D,E,F) 73 #define DEBUGOUT7(S,A,B,C,D,E,F,G) printf(S "\n",A,B,C,D,E,F,G) 74 #define ERROR_REPORT1(S,A) printf(S A "\n") 75 #define ERROR_REPORT2(S,A,B) printf(S A "\n",B) 76 #define ERROR_REPORT3(S,A,B,C) printf(S A "\n",B,C) 77 #else 78 #define DEBUGOUT(S) do { } while (/*CONSTCOND*/false) 79 #define DEBUGOUT1(S,A) do { } while (/*CONSTCOND*/false) 80 #define DEBUGOUT2(S,A,B) do { } while (/*CONSTCOND*/false) 81 #define DEBUGOUT3(S,A,B,C) do { } while (/*CONSTCOND*/false) 82 #define DEBUGOUT4(S,A,B,C,D) do { } while (/*CONSTCOND*/false) 83 #define DEBUGOUT5(S,A,B,C,D,E) do { } while (/*CONSTCOND*/false) 84 #define DEBUGOUT6(S,A,B,C,D,E,F) \ 85 do { } while (/*CONSTCOND*/false) 86 #define DEBUGOUT7(S,A,B,C,D,E,F,G) \ 87 do { } while (/*CONSTCOND*/false) 88 #define ERROR_REPORT1(S,A) do { } while (/*CONSTCOND*/false) 89 #define ERROR_REPORT2(S,A,B) do { } while (/*CONSTCOND*/false) 90 #define ERROR_REPORT3(S,A,B,C) do { } while (/*CONSTCOND*/false) 91 #endif 92 93 #define FALSE 0 94 #define false 0 /* shared code requires this */ 95 #define TRUE 1 96 #define true 1 97 #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */ 98 #define PCI_COMMAND_REGISTER PCIR_COMMAND 99 100 /* Shared code dropped this define.. */ 101 #define IXGBE_INTEL_VENDOR_ID 0x8086 102 103 /* Bunch of defines for shared code bogosity */ 104 #define UNREFERENCED_PARAMETER(_p) 105 #define UNREFERENCED_1PARAMETER(_p) 106 #define UNREFERENCED_2PARAMETER(_p, _q) 107 #define UNREFERENCED_3PARAMETER(_p, _q, _r) 108 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) 109 110 111 #define IXGBE_NTOHL(_i) ntohl(_i) 112 #define IXGBE_NTOHS(_i) ntohs(_i) 113 114 /* XXX these need to be revisited */ 115 #define IXGBE_CPU_TO_LE32 le32toh 116 #define IXGBE_LE32_TO_CPUS le32dec 117 118 typedef uint8_t u8; 119 typedef int8_t s8; 120 typedef uint16_t u16; 121 typedef int16_t s16; 122 typedef uint32_t u32; 123 typedef int32_t s32; 124 typedef uint64_t u64; 125 126 #define le16_to_cpu 127 128 #ifdef __HAVE_PCI_MSI_MSIX 129 #define NETBSD_MSI_OR_MSIX 130 /* 131 * This device driver divides interrupt to TX, RX and link state. 132 * Each MSI-X vector indexes are below. 133 */ 134 #define IXG_MSIX_NINTR 2 135 #define IXG_MSIX_TXRXINTR_IDX 0 136 #define IXG_MSIX_LINKINTR_IDX 1 137 #define IXG_MAX_NINTR IXG_MSIX_NINTR 138 #else 139 #define IXG_MAX_NINTR 1 140 #endif 141 142 #if __FreeBSD_version < 800000 143 #if defined(__i386__) || defined(__amd64__) 144 #define mb() __asm volatile("mfence" ::: "memory") 145 #define wmb() __asm volatile("sfence" ::: "memory") 146 #define rmb() __asm volatile("lfence" ::: "memory") 147 #else 148 #define mb() 149 #define rmb() 150 #define wmb() 151 #endif 152 #endif 153 154 #if defined(__i386__) || defined(__amd64__) 155 static __inline 156 void prefetch(void *x) 157 { 158 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 159 } 160 #else 161 #define prefetch(x) 162 #endif 163 164 /* 165 * Optimized bcopy thanks to Luigi Rizzo's investigative work. Assumes 166 * non-overlapping regions and 32-byte padding on both src and dst. 167 */ 168 static __inline int 169 ixgbe_bcopy(void *_src, void *_dst, int l) 170 { 171 uint64_t *src = _src; 172 uint64_t *dst = _dst; 173 174 for (; l > 0; l -= 32) { 175 *dst++ = *src++; 176 *dst++ = *src++; 177 *dst++ = *src++; 178 *dst++ = *src++; 179 } 180 return (0); 181 } 182 183 struct ixgbe_osdep 184 { 185 struct ethercom ec; 186 pci_chipset_tag_t pc; 187 pcitag_t tag; 188 bus_space_tag_t mem_bus_space_tag; 189 bus_space_handle_t mem_bus_space_handle; 190 bus_size_t mem_size; 191 bus_dma_tag_t dmat; 192 device_t dev; 193 pci_intr_handle_t *intrs; 194 int nintrs; 195 void *ihs[IXG_MAX_NINTR]; 196 bool attached; 197 }; 198 199 /* These routines are needed by the shared code */ 200 struct ixgbe_hw; 201 extern u16 ixgbe_read_pci_cfg(struct ixgbe_hw *, u32); 202 #define IXGBE_READ_PCIE_WORD ixgbe_read_pci_cfg 203 204 extern void ixgbe_write_pci_cfg(struct ixgbe_hw *, u32, u16); 205 #define IXGBE_WRITE_PCIE_WORD ixgbe_write_pci_cfg 206 207 #define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS) 208 209 #define IXGBE_READ_REG(a, reg) (\ 210 bus_space_read_4( ((a)->back)->mem_bus_space_tag, \ 211 ((a)->back)->mem_bus_space_handle, \ 212 reg)) 213 214 #define IXGBE_WRITE_REG(a, reg, value) (\ 215 bus_space_write_4( ((a)->back)->mem_bus_space_tag, \ 216 ((a)->back)->mem_bus_space_handle, \ 217 reg, value)) 218 219 220 #define IXGBE_READ_REG_ARRAY(a, reg, offset) (\ 221 bus_space_read_4( ((a)->back)->mem_bus_space_tag, \ 222 ((a)->back)->mem_bus_space_handle, \ 223 (reg + ((offset) << 2)))) 224 225 #define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) (\ 226 bus_space_write_4( ((a)->back)->mem_bus_space_tag, \ 227 ((a)->back)->mem_bus_space_handle, \ 228 (reg + ((offset) << 2)), value)) 229 230 231 #endif /* _IXGBE_OS_H_ */ 232