1 /* $NetBSD: ixgbe_common.c,v 1.22 2018/04/04 08:59:22 msaitoh Exp $ */ 2 3 /****************************************************************************** 4 SPDX-License-Identifier: BSD-3-Clause 5 6 Copyright (c) 2001-2017, Intel Corporation 7 All rights reserved. 8 9 Redistribution and use in source and binary forms, with or without 10 modification, are permitted provided that the following conditions are met: 11 12 1. Redistributions of source code must retain the above copyright notice, 13 this list of conditions and the following disclaimer. 14 15 2. Redistributions in binary form must reproduce the above copyright 16 notice, this list of conditions and the following disclaimer in the 17 documentation and/or other materials provided with the distribution. 18 19 3. Neither the name of the Intel Corporation nor the names of its 20 contributors may be used to endorse or promote products derived from 21 this software without specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 27 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 POSSIBILITY OF SUCH DAMAGE. 34 35 ******************************************************************************/ 36 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_common.c 331224 2018-03-19 20:55:05Z erj $*/ 37 38 #include "ixgbe_common.h" 39 #include "ixgbe_phy.h" 40 #include "ixgbe_dcb.h" 41 #include "ixgbe_dcb_82599.h" 42 #include "ixgbe_api.h" 43 44 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 45 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 46 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 47 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 48 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 49 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 50 u16 count); 51 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 52 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 53 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 54 static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 55 56 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 57 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 58 u16 *san_mac_offset); 59 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 60 u16 words, u16 *data); 61 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 62 u16 words, u16 *data); 63 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 64 u16 offset); 65 66 /** 67 * ixgbe_init_ops_generic - Inits function ptrs 68 * @hw: pointer to the hardware structure 69 * 70 * Initialize the function pointers. 71 **/ 72 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw) 73 { 74 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 75 struct ixgbe_mac_info *mac = &hw->mac; 76 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 77 78 DEBUGFUNC("ixgbe_init_ops_generic"); 79 80 /* EEPROM */ 81 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic; 82 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ 83 if (eec & IXGBE_EEC_PRES) { 84 eeprom->ops.read = ixgbe_read_eerd_generic; 85 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic; 86 } else { 87 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic; 88 eeprom->ops.read_buffer = 89 ixgbe_read_eeprom_buffer_bit_bang_generic; 90 } 91 eeprom->ops.write = ixgbe_write_eeprom_generic; 92 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic; 93 eeprom->ops.validate_checksum = 94 ixgbe_validate_eeprom_checksum_generic; 95 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic; 96 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic; 97 98 /* MAC */ 99 mac->ops.init_hw = ixgbe_init_hw_generic; 100 mac->ops.reset_hw = NULL; 101 mac->ops.start_hw = ixgbe_start_hw_generic; 102 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic; 103 mac->ops.get_media_type = NULL; 104 mac->ops.get_supported_physical_layer = NULL; 105 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic; 106 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic; 107 mac->ops.stop_adapter = ixgbe_stop_adapter_generic; 108 mac->ops.get_bus_info = ixgbe_get_bus_info_generic; 109 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie; 110 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync; 111 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync; 112 mac->ops.prot_autoc_read = prot_autoc_read_generic; 113 mac->ops.prot_autoc_write = prot_autoc_write_generic; 114 115 /* LEDs */ 116 mac->ops.led_on = ixgbe_led_on_generic; 117 mac->ops.led_off = ixgbe_led_off_generic; 118 mac->ops.blink_led_start = ixgbe_blink_led_start_generic; 119 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic; 120 mac->ops.init_led_link_act = ixgbe_init_led_link_act_generic; 121 122 /* RAR, Multicast, VLAN */ 123 mac->ops.set_rar = ixgbe_set_rar_generic; 124 mac->ops.clear_rar = ixgbe_clear_rar_generic; 125 mac->ops.insert_mac_addr = NULL; 126 mac->ops.set_vmdq = NULL; 127 mac->ops.clear_vmdq = NULL; 128 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic; 129 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic; 130 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic; 131 mac->ops.enable_mc = ixgbe_enable_mc_generic; 132 mac->ops.disable_mc = ixgbe_disable_mc_generic; 133 mac->ops.clear_vfta = NULL; 134 mac->ops.set_vfta = NULL; 135 mac->ops.set_vlvf = NULL; 136 mac->ops.init_uta_tables = NULL; 137 mac->ops.enable_rx = ixgbe_enable_rx_generic; 138 mac->ops.disable_rx = ixgbe_disable_rx_generic; 139 140 /* Flow Control */ 141 mac->ops.fc_enable = ixgbe_fc_enable_generic; 142 mac->ops.setup_fc = ixgbe_setup_fc_generic; 143 mac->ops.fc_autoneg = ixgbe_fc_autoneg; 144 145 /* Link */ 146 mac->ops.get_link_capabilities = NULL; 147 mac->ops.setup_link = NULL; 148 mac->ops.check_link = NULL; 149 mac->ops.dmac_config = NULL; 150 mac->ops.dmac_update_tcs = NULL; 151 mac->ops.dmac_config_tcs = NULL; 152 153 return IXGBE_SUCCESS; 154 } 155 156 /** 157 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation 158 * of flow control 159 * @hw: pointer to hardware structure 160 * 161 * This function returns TRUE if the device supports flow control 162 * autonegotiation, and FALSE if it does not. 163 * 164 **/ 165 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) 166 { 167 bool supported = FALSE; 168 ixgbe_link_speed speed; 169 bool link_up; 170 171 DEBUGFUNC("ixgbe_device_supports_autoneg_fc"); 172 173 switch (hw->phy.media_type) { 174 case ixgbe_media_type_fiber_fixed: 175 case ixgbe_media_type_fiber_qsfp: 176 case ixgbe_media_type_fiber: 177 /* flow control autoneg black list */ 178 switch (hw->device_id) { 179 case IXGBE_DEV_ID_X550EM_A_SFP: 180 case IXGBE_DEV_ID_X550EM_A_SFP_N: 181 case IXGBE_DEV_ID_X550EM_A_QSFP: 182 case IXGBE_DEV_ID_X550EM_A_QSFP_N: 183 supported = FALSE; 184 break; 185 default: 186 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 187 /* if link is down, assume supported */ 188 if (link_up) 189 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ? 190 TRUE : FALSE; 191 else 192 supported = TRUE; 193 } 194 195 break; 196 case ixgbe_media_type_backplane: 197 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI) 198 supported = FALSE; 199 else 200 supported = TRUE; 201 break; 202 case ixgbe_media_type_copper: 203 /* only some copper devices support flow control autoneg */ 204 switch (hw->device_id) { 205 case IXGBE_DEV_ID_82599_T3_LOM: 206 case IXGBE_DEV_ID_X540T: 207 case IXGBE_DEV_ID_X540T1: 208 case IXGBE_DEV_ID_X540_BYPASS: 209 case IXGBE_DEV_ID_X550T: 210 case IXGBE_DEV_ID_X550T1: 211 case IXGBE_DEV_ID_X550EM_X_10G_T: 212 case IXGBE_DEV_ID_X550EM_A_10G_T: 213 case IXGBE_DEV_ID_X550EM_A_1G_T: 214 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 215 supported = TRUE; 216 break; 217 default: 218 supported = FALSE; 219 } 220 default: 221 break; 222 } 223 224 if (!supported) 225 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 226 "Device %x does not support flow control autoneg", 227 hw->device_id); 228 229 return supported; 230 } 231 232 /** 233 * ixgbe_setup_fc_generic - Set up flow control 234 * @hw: pointer to hardware structure 235 * 236 * Called at init time to set up flow control. 237 **/ 238 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw) 239 { 240 s32 ret_val = IXGBE_SUCCESS; 241 u32 reg = 0, reg_bp = 0; 242 u16 reg_cu = 0; 243 bool locked = FALSE; 244 245 DEBUGFUNC("ixgbe_setup_fc_generic"); 246 247 /* Validate the requested mode */ 248 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 249 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 250 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 251 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 252 goto out; 253 } 254 255 /* 256 * 10gig parts do not have a word in the EEPROM to determine the 257 * default flow control setting, so we explicitly set it to full. 258 */ 259 if (hw->fc.requested_mode == ixgbe_fc_default) 260 hw->fc.requested_mode = ixgbe_fc_full; 261 262 /* 263 * Set up the 1G and 10G flow control advertisement registers so the 264 * HW will be able to do fc autoneg once the cable is plugged in. If 265 * we link at 10G, the 1G advertisement is harmless and vice versa. 266 */ 267 switch (hw->phy.media_type) { 268 case ixgbe_media_type_backplane: 269 /* some MAC's need RMW protection on AUTOC */ 270 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp); 271 if (ret_val != IXGBE_SUCCESS) 272 goto out; 273 274 /* fall through - only backplane uses autoc */ 275 case ixgbe_media_type_fiber_fixed: 276 case ixgbe_media_type_fiber_qsfp: 277 case ixgbe_media_type_fiber: 278 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 279 280 break; 281 case ixgbe_media_type_copper: 282 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 283 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu); 284 break; 285 default: 286 break; 287 } 288 289 /* 290 * The possible values of fc.requested_mode are: 291 * 0: Flow control is completely disabled 292 * 1: Rx flow control is enabled (we can receive pause frames, 293 * but not send pause frames). 294 * 2: Tx flow control is enabled (we can send pause frames but 295 * we do not support receiving pause frames). 296 * 3: Both Rx and Tx flow control (symmetric) are enabled. 297 * other: Invalid. 298 */ 299 switch (hw->fc.requested_mode) { 300 case ixgbe_fc_none: 301 /* Flow control completely disabled by software override. */ 302 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 303 if (hw->phy.media_type == ixgbe_media_type_backplane) 304 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE | 305 IXGBE_AUTOC_ASM_PAUSE); 306 else if (hw->phy.media_type == ixgbe_media_type_copper) 307 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); 308 break; 309 case ixgbe_fc_tx_pause: 310 /* 311 * Tx Flow control is enabled, and Rx Flow control is 312 * disabled by software override. 313 */ 314 reg |= IXGBE_PCS1GANA_ASM_PAUSE; 315 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE; 316 if (hw->phy.media_type == ixgbe_media_type_backplane) { 317 reg_bp |= IXGBE_AUTOC_ASM_PAUSE; 318 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE; 319 } else if (hw->phy.media_type == ixgbe_media_type_copper) { 320 reg_cu |= IXGBE_TAF_ASM_PAUSE; 321 reg_cu &= ~IXGBE_TAF_SYM_PAUSE; 322 } 323 break; 324 case ixgbe_fc_rx_pause: 325 /* 326 * Rx Flow control is enabled and Tx Flow control is 327 * disabled by software override. Since there really 328 * isn't a way to advertise that we are capable of RX 329 * Pause ONLY, we will advertise that we support both 330 * symmetric and asymmetric Rx PAUSE, as such we fall 331 * through to the fc_full statement. Later, we will 332 * disable the adapter's ability to send PAUSE frames. 333 */ 334 case ixgbe_fc_full: 335 /* Flow control (both Rx and Tx) is enabled by SW override. */ 336 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE; 337 if (hw->phy.media_type == ixgbe_media_type_backplane) 338 reg_bp |= IXGBE_AUTOC_SYM_PAUSE | 339 IXGBE_AUTOC_ASM_PAUSE; 340 else if (hw->phy.media_type == ixgbe_media_type_copper) 341 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE; 342 break; 343 default: 344 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 345 "Flow control param set incorrectly\n"); 346 ret_val = IXGBE_ERR_CONFIG; 347 goto out; 348 break; 349 } 350 351 if (hw->mac.type < ixgbe_mac_X540) { 352 /* 353 * Enable auto-negotiation between the MAC & PHY; 354 * the MAC will advertise clause 37 flow control. 355 */ 356 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 357 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 358 359 /* Disable AN timeout */ 360 if (hw->fc.strict_ieee) 361 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 362 363 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 364 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 365 } 366 367 /* 368 * AUTOC restart handles negotiation of 1G and 10G on backplane 369 * and copper. There is no need to set the PCS1GCTL register. 370 * 371 */ 372 if (hw->phy.media_type == ixgbe_media_type_backplane) { 373 reg_bp |= IXGBE_AUTOC_AN_RESTART; 374 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked); 375 if (ret_val) 376 goto out; 377 } else if ((hw->phy.media_type == ixgbe_media_type_copper) && 378 (ixgbe_device_supports_autoneg_fc(hw))) { 379 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 380 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu); 381 } 382 383 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 384 out: 385 return ret_val; 386 } 387 388 /** 389 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 390 * @hw: pointer to hardware structure 391 * 392 * Starts the hardware by filling the bus info structure and media type, clears 393 * all on chip counters, initializes receive address registers, multicast 394 * table, VLAN filter table, calls routine to set up link and flow control 395 * settings, and leaves transmit and receive units disabled and uninitialized 396 **/ 397 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 398 { 399 s32 ret_val; 400 u32 ctrl_ext; 401 u16 device_caps; 402 403 DEBUGFUNC("ixgbe_start_hw_generic"); 404 405 /* Set the media type */ 406 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 407 408 /* PHY ops initialization must be done in reset_hw() */ 409 410 /* Clear the VLAN filter table */ 411 hw->mac.ops.clear_vfta(hw); 412 413 /* Clear statistics registers */ 414 hw->mac.ops.clear_hw_cntrs(hw); 415 416 /* Set No Snoop Disable */ 417 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 418 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 419 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 420 IXGBE_WRITE_FLUSH(hw); 421 422 /* Setup flow control */ 423 ret_val = ixgbe_setup_fc(hw); 424 if (ret_val != IXGBE_SUCCESS && ret_val != IXGBE_NOT_IMPLEMENTED) { 425 DEBUGOUT1("Flow control setup failed, returning %d\n", ret_val); 426 return ret_val; 427 } 428 429 /* Cache bit indicating need for crosstalk fix */ 430 switch (hw->mac.type) { 431 case ixgbe_mac_82599EB: 432 case ixgbe_mac_X550EM_x: 433 case ixgbe_mac_X550EM_a: 434 hw->mac.ops.get_device_caps(hw, &device_caps); 435 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR) 436 hw->need_crosstalk_fix = FALSE; 437 else 438 hw->need_crosstalk_fix = TRUE; 439 break; 440 default: 441 hw->need_crosstalk_fix = FALSE; 442 break; 443 } 444 445 /* Clear adapter stopped flag */ 446 hw->adapter_stopped = FALSE; 447 448 return IXGBE_SUCCESS; 449 } 450 451 /** 452 * ixgbe_start_hw_gen2 - Init sequence for common device family 453 * @hw: pointer to hw structure 454 * 455 * Performs the init sequence common to the second generation 456 * of 10 GbE devices. 457 * Devices in the second generation: 458 * 82599 459 * X540 460 **/ 461 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 462 { 463 u32 i; 464 u32 regval; 465 466 /* Clear the rate limiters */ 467 for (i = 0; i < hw->mac.max_tx_queues; i++) { 468 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 469 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); 470 } 471 IXGBE_WRITE_FLUSH(hw); 472 473 /* Disable relaxed ordering */ 474 for (i = 0; i < hw->mac.max_tx_queues; i++) { 475 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 476 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 477 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 478 } 479 480 for (i = 0; i < hw->mac.max_rx_queues; i++) { 481 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 482 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | 483 IXGBE_DCA_RXCTRL_HEAD_WRO_EN); 484 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 485 } 486 487 return IXGBE_SUCCESS; 488 } 489 490 /** 491 * ixgbe_init_hw_generic - Generic hardware initialization 492 * @hw: pointer to hardware structure 493 * 494 * Initialize the hardware by resetting the hardware, filling the bus info 495 * structure and media type, clears all on chip counters, initializes receive 496 * address registers, multicast table, VLAN filter table, calls routine to set 497 * up link and flow control settings, and leaves transmit and receive units 498 * disabled and uninitialized 499 **/ 500 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 501 { 502 s32 status; 503 504 DEBUGFUNC("ixgbe_init_hw_generic"); 505 506 /* Reset the hardware */ 507 status = hw->mac.ops.reset_hw(hw); 508 509 if (status == IXGBE_SUCCESS || status == IXGBE_ERR_SFP_NOT_PRESENT) { 510 /* Start the HW */ 511 status = hw->mac.ops.start_hw(hw); 512 } 513 514 /* Initialize the LED link active for LED blink support */ 515 if (hw->mac.ops.init_led_link_act) 516 hw->mac.ops.init_led_link_act(hw); 517 518 if (status != IXGBE_SUCCESS) 519 DEBUGOUT1("Failed to initialize HW, STATUS = %d\n", status); 520 521 return status; 522 } 523 524 /** 525 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 526 * @hw: pointer to hardware structure 527 * 528 * Clears all hardware statistics counters by reading them from the hardware 529 * Statistics counters are clear on read. 530 **/ 531 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 532 { 533 u16 i = 0; 534 535 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic"); 536 537 IXGBE_READ_REG(hw, IXGBE_CRCERRS); 538 IXGBE_READ_REG(hw, IXGBE_ILLERRC); 539 IXGBE_READ_REG(hw, IXGBE_ERRBC); 540 IXGBE_READ_REG(hw, IXGBE_MSPDC); 541 if (hw->mac.type >= ixgbe_mac_X550) 542 IXGBE_READ_REG(hw, IXGBE_MBSDC); 543 for (i = 0; i < 8; i++) 544 IXGBE_READ_REG(hw, IXGBE_MPC(i)); 545 546 IXGBE_READ_REG(hw, IXGBE_MLFC); 547 IXGBE_READ_REG(hw, IXGBE_MRFC); 548 IXGBE_READ_REG(hw, IXGBE_RLEC); 549 IXGBE_READ_REG(hw, IXGBE_LXONTXC); 550 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 551 if (hw->mac.type >= ixgbe_mac_82599EB) { 552 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 553 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 554 } else { 555 IXGBE_READ_REG(hw, IXGBE_LXONRXC); 556 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 557 } 558 559 for (i = 0; i < 8; i++) { 560 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 561 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 562 if (hw->mac.type >= ixgbe_mac_82599EB) { 563 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 564 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 565 } else { 566 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 567 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 568 } 569 } 570 if (hw->mac.type >= ixgbe_mac_82599EB) 571 for (i = 0; i < 8; i++) 572 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 573 IXGBE_READ_REG(hw, IXGBE_PRC64); 574 IXGBE_READ_REG(hw, IXGBE_PRC127); 575 IXGBE_READ_REG(hw, IXGBE_PRC255); 576 IXGBE_READ_REG(hw, IXGBE_PRC511); 577 IXGBE_READ_REG(hw, IXGBE_PRC1023); 578 IXGBE_READ_REG(hw, IXGBE_PRC1522); 579 IXGBE_READ_REG(hw, IXGBE_GPRC); 580 IXGBE_READ_REG(hw, IXGBE_BPRC); 581 IXGBE_READ_REG(hw, IXGBE_MPRC); 582 IXGBE_READ_REG(hw, IXGBE_GPTC); 583 IXGBE_READ_REG(hw, IXGBE_GORCL); 584 IXGBE_READ_REG(hw, IXGBE_GORCH); 585 IXGBE_READ_REG(hw, IXGBE_GOTCL); 586 IXGBE_READ_REG(hw, IXGBE_GOTCH); 587 if (hw->mac.type == ixgbe_mac_82598EB) 588 for (i = 0; i < 8; i++) 589 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 590 IXGBE_READ_REG(hw, IXGBE_RUC); 591 IXGBE_READ_REG(hw, IXGBE_RFC); 592 IXGBE_READ_REG(hw, IXGBE_ROC); 593 IXGBE_READ_REG(hw, IXGBE_RJC); 594 IXGBE_READ_REG(hw, IXGBE_MNGPRC); 595 IXGBE_READ_REG(hw, IXGBE_MNGPDC); 596 IXGBE_READ_REG(hw, IXGBE_MNGPTC); 597 IXGBE_READ_REG(hw, IXGBE_TORL); 598 IXGBE_READ_REG(hw, IXGBE_TORH); 599 IXGBE_READ_REG(hw, IXGBE_TPR); 600 IXGBE_READ_REG(hw, IXGBE_TPT); 601 IXGBE_READ_REG(hw, IXGBE_PTC64); 602 IXGBE_READ_REG(hw, IXGBE_PTC127); 603 IXGBE_READ_REG(hw, IXGBE_PTC255); 604 IXGBE_READ_REG(hw, IXGBE_PTC511); 605 IXGBE_READ_REG(hw, IXGBE_PTC1023); 606 IXGBE_READ_REG(hw, IXGBE_PTC1522); 607 IXGBE_READ_REG(hw, IXGBE_MPTC); 608 IXGBE_READ_REG(hw, IXGBE_BPTC); 609 for (i = 0; i < 16; i++) { 610 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 611 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 612 if (hw->mac.type >= ixgbe_mac_82599EB) { 613 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 614 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); 615 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 616 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); 617 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 618 } else { 619 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 620 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 621 } 622 } 623 624 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) { 625 if (hw->phy.id == 0) 626 ixgbe_identify_phy(hw); 627 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, 628 IXGBE_MDIO_PCS_DEV_TYPE, &i); 629 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, 630 IXGBE_MDIO_PCS_DEV_TYPE, &i); 631 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, 632 IXGBE_MDIO_PCS_DEV_TYPE, &i); 633 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, 634 IXGBE_MDIO_PCS_DEV_TYPE, &i); 635 } 636 637 return IXGBE_SUCCESS; 638 } 639 640 /** 641 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM 642 * @hw: pointer to hardware structure 643 * @pba_num: stores the part number string from the EEPROM 644 * @pba_num_size: part number string buffer length 645 * 646 * Reads the part number string from the EEPROM. 647 **/ 648 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, 649 u32 pba_num_size) 650 { 651 s32 ret_val; 652 u16 data; 653 u16 pba_ptr; 654 u16 offset; 655 u16 length; 656 657 DEBUGFUNC("ixgbe_read_pba_string_generic"); 658 659 if (pba_num == NULL) { 660 DEBUGOUT("PBA string buffer was null\n"); 661 return IXGBE_ERR_INVALID_ARGUMENT; 662 } 663 664 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 665 if (ret_val) { 666 DEBUGOUT("NVM Read Error\n"); 667 return ret_val; 668 } 669 670 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); 671 if (ret_val) { 672 DEBUGOUT("NVM Read Error\n"); 673 return ret_val; 674 } 675 676 /* 677 * if data is not ptr guard the PBA must be in legacy format which 678 * means pba_ptr is actually our second data word for the PBA number 679 * and we can decode it into an ascii string 680 */ 681 if (data != IXGBE_PBANUM_PTR_GUARD) { 682 DEBUGOUT("NVM PBA number is not stored as string\n"); 683 684 /* we will need 11 characters to store the PBA */ 685 if (pba_num_size < 11) { 686 DEBUGOUT("PBA string buffer too small\n"); 687 return IXGBE_ERR_NO_SPACE; 688 } 689 690 /* extract hex string from data and pba_ptr */ 691 pba_num[0] = (data >> 12) & 0xF; 692 pba_num[1] = (data >> 8) & 0xF; 693 pba_num[2] = (data >> 4) & 0xF; 694 pba_num[3] = data & 0xF; 695 pba_num[4] = (pba_ptr >> 12) & 0xF; 696 pba_num[5] = (pba_ptr >> 8) & 0xF; 697 pba_num[6] = '-'; 698 pba_num[7] = 0; 699 pba_num[8] = (pba_ptr >> 4) & 0xF; 700 pba_num[9] = pba_ptr & 0xF; 701 702 /* put a null character on the end of our string */ 703 pba_num[10] = '\0'; 704 705 /* switch all the data but the '-' to hex char */ 706 for (offset = 0; offset < 10; offset++) { 707 if (pba_num[offset] < 0xA) 708 pba_num[offset] += '0'; 709 else if (pba_num[offset] < 0x10) 710 pba_num[offset] += 'A' - 0xA; 711 } 712 713 return IXGBE_SUCCESS; 714 } 715 716 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); 717 if (ret_val) { 718 DEBUGOUT("NVM Read Error\n"); 719 return ret_val; 720 } 721 722 if (length == 0xFFFF || length == 0) { 723 DEBUGOUT("NVM PBA number section invalid length\n"); 724 return IXGBE_ERR_PBA_SECTION; 725 } 726 727 /* check if pba_num buffer is big enough */ 728 if (pba_num_size < (((u32)length * 2) - 1)) { 729 DEBUGOUT("PBA string buffer too small\n"); 730 return IXGBE_ERR_NO_SPACE; 731 } 732 733 /* trim pba length from start of string */ 734 pba_ptr++; 735 length--; 736 737 for (offset = 0; offset < length; offset++) { 738 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); 739 if (ret_val) { 740 DEBUGOUT("NVM Read Error\n"); 741 return ret_val; 742 } 743 pba_num[offset * 2] = (u8)(data >> 8); 744 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF); 745 } 746 pba_num[offset * 2] = '\0'; 747 748 return IXGBE_SUCCESS; 749 } 750 751 /** 752 * ixgbe_read_pba_num_generic - Reads part number from EEPROM 753 * @hw: pointer to hardware structure 754 * @pba_num: stores the part number from the EEPROM 755 * 756 * Reads the part number from the EEPROM. 757 **/ 758 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) 759 { 760 s32 ret_val; 761 u16 data; 762 763 DEBUGFUNC("ixgbe_read_pba_num_generic"); 764 765 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 766 if (ret_val) { 767 DEBUGOUT("NVM Read Error\n"); 768 return ret_val; 769 } else if (data == IXGBE_PBANUM_PTR_GUARD) { 770 DEBUGOUT("NVM Not supported\n"); 771 return IXGBE_NOT_IMPLEMENTED; 772 } 773 *pba_num = (u32)(data << 16); 774 775 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); 776 if (ret_val) { 777 DEBUGOUT("NVM Read Error\n"); 778 return ret_val; 779 } 780 *pba_num |= data; 781 782 return IXGBE_SUCCESS; 783 } 784 785 /** 786 * ixgbe_read_pba_raw 787 * @hw: pointer to the HW structure 788 * @eeprom_buf: optional pointer to EEPROM image 789 * @eeprom_buf_size: size of EEPROM image in words 790 * @max_pba_block_size: PBA block size limit 791 * @pba: pointer to output PBA structure 792 * 793 * Reads PBA from EEPROM image when eeprom_buf is not NULL. 794 * Reads PBA from physical EEPROM device when eeprom_buf is NULL. 795 * 796 **/ 797 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, 798 u32 eeprom_buf_size, u16 max_pba_block_size, 799 struct ixgbe_pba *pba) 800 { 801 s32 ret_val; 802 u16 pba_block_size; 803 804 if (pba == NULL) 805 return IXGBE_ERR_PARAM; 806 807 if (eeprom_buf == NULL) { 808 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, 809 &pba->word[0]); 810 if (ret_val) 811 return ret_val; 812 } else { 813 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 814 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; 815 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; 816 } else { 817 return IXGBE_ERR_PARAM; 818 } 819 } 820 821 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { 822 if (pba->pba_block == NULL) 823 return IXGBE_ERR_PARAM; 824 825 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf, 826 eeprom_buf_size, 827 &pba_block_size); 828 if (ret_val) 829 return ret_val; 830 831 if (pba_block_size > max_pba_block_size) 832 return IXGBE_ERR_PARAM; 833 834 if (eeprom_buf == NULL) { 835 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1], 836 pba_block_size, 837 pba->pba_block); 838 if (ret_val) 839 return ret_val; 840 } else { 841 if (eeprom_buf_size > (u32)(pba->word[1] + 842 pba_block_size)) { 843 memcpy(pba->pba_block, 844 &eeprom_buf[pba->word[1]], 845 pba_block_size * sizeof(u16)); 846 } else { 847 return IXGBE_ERR_PARAM; 848 } 849 } 850 } 851 852 return IXGBE_SUCCESS; 853 } 854 855 /** 856 * ixgbe_write_pba_raw 857 * @hw: pointer to the HW structure 858 * @eeprom_buf: optional pointer to EEPROM image 859 * @eeprom_buf_size: size of EEPROM image in words 860 * @pba: pointer to PBA structure 861 * 862 * Writes PBA to EEPROM image when eeprom_buf is not NULL. 863 * Writes PBA to physical EEPROM device when eeprom_buf is NULL. 864 * 865 **/ 866 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, 867 u32 eeprom_buf_size, struct ixgbe_pba *pba) 868 { 869 s32 ret_val; 870 871 if (pba == NULL) 872 return IXGBE_ERR_PARAM; 873 874 if (eeprom_buf == NULL) { 875 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2, 876 &pba->word[0]); 877 if (ret_val) 878 return ret_val; 879 } else { 880 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 881 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0]; 882 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1]; 883 } else { 884 return IXGBE_ERR_PARAM; 885 } 886 } 887 888 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { 889 if (pba->pba_block == NULL) 890 return IXGBE_ERR_PARAM; 891 892 if (eeprom_buf == NULL) { 893 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1], 894 pba->pba_block[0], 895 pba->pba_block); 896 if (ret_val) 897 return ret_val; 898 } else { 899 if (eeprom_buf_size > (u32)(pba->word[1] + 900 pba->pba_block[0])) { 901 memcpy(&eeprom_buf[pba->word[1]], 902 pba->pba_block, 903 pba->pba_block[0] * sizeof(u16)); 904 } else { 905 return IXGBE_ERR_PARAM; 906 } 907 } 908 } 909 910 return IXGBE_SUCCESS; 911 } 912 913 /** 914 * ixgbe_get_pba_block_size 915 * @hw: pointer to the HW structure 916 * @eeprom_buf: optional pointer to EEPROM image 917 * @eeprom_buf_size: size of EEPROM image in words 918 * @pba_data_size: pointer to output variable 919 * 920 * Returns the size of the PBA block in words. Function operates on EEPROM 921 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical 922 * EEPROM device. 923 * 924 **/ 925 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf, 926 u32 eeprom_buf_size, u16 *pba_block_size) 927 { 928 s32 ret_val; 929 u16 pba_word[2]; 930 u16 length; 931 932 DEBUGFUNC("ixgbe_get_pba_block_size"); 933 934 if (eeprom_buf == NULL) { 935 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, 936 &pba_word[0]); 937 if (ret_val) 938 return ret_val; 939 } else { 940 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 941 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; 942 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; 943 } else { 944 return IXGBE_ERR_PARAM; 945 } 946 } 947 948 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) { 949 if (eeprom_buf == NULL) { 950 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0, 951 &length); 952 if (ret_val) 953 return ret_val; 954 } else { 955 if (eeprom_buf_size > pba_word[1]) 956 length = eeprom_buf[pba_word[1] + 0]; 957 else 958 return IXGBE_ERR_PARAM; 959 } 960 961 if (length == 0xFFFF || length == 0) 962 return IXGBE_ERR_PBA_SECTION; 963 } else { 964 /* PBA number in legacy format, there is no PBA Block. */ 965 length = 0; 966 } 967 968 if (pba_block_size != NULL) 969 *pba_block_size = length; 970 971 return IXGBE_SUCCESS; 972 } 973 974 /** 975 * ixgbe_get_mac_addr_generic - Generic get MAC address 976 * @hw: pointer to hardware structure 977 * @mac_addr: Adapter MAC address 978 * 979 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 980 * A reset of the adapter must be performed prior to calling this function 981 * in order for the MAC address to have been loaded from the EEPROM into RAR0 982 **/ 983 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 984 { 985 u32 rar_high; 986 u32 rar_low; 987 u16 i; 988 989 DEBUGFUNC("ixgbe_get_mac_addr_generic"); 990 991 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 992 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 993 994 for (i = 0; i < 4; i++) 995 mac_addr[i] = (u8)(rar_low >> (i*8)); 996 997 for (i = 0; i < 2; i++) 998 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 999 1000 return IXGBE_SUCCESS; 1001 } 1002 1003 /** 1004 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info 1005 * @hw: pointer to hardware structure 1006 * @link_status: the link status returned by the PCI config space 1007 * 1008 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure 1009 **/ 1010 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status) 1011 { 1012 struct ixgbe_mac_info *mac = &hw->mac; 1013 1014 if (hw->bus.type == ixgbe_bus_type_unknown) 1015 hw->bus.type = ixgbe_bus_type_pci_express; 1016 1017 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 1018 case IXGBE_PCI_LINK_WIDTH_1: 1019 hw->bus.width = ixgbe_bus_width_pcie_x1; 1020 break; 1021 case IXGBE_PCI_LINK_WIDTH_2: 1022 hw->bus.width = ixgbe_bus_width_pcie_x2; 1023 break; 1024 case IXGBE_PCI_LINK_WIDTH_4: 1025 hw->bus.width = ixgbe_bus_width_pcie_x4; 1026 break; 1027 case IXGBE_PCI_LINK_WIDTH_8: 1028 hw->bus.width = ixgbe_bus_width_pcie_x8; 1029 break; 1030 default: 1031 hw->bus.width = ixgbe_bus_width_unknown; 1032 break; 1033 } 1034 1035 switch (link_status & IXGBE_PCI_LINK_SPEED) { 1036 case IXGBE_PCI_LINK_SPEED_2500: 1037 hw->bus.speed = ixgbe_bus_speed_2500; 1038 break; 1039 case IXGBE_PCI_LINK_SPEED_5000: 1040 hw->bus.speed = ixgbe_bus_speed_5000; 1041 break; 1042 case IXGBE_PCI_LINK_SPEED_8000: 1043 hw->bus.speed = ixgbe_bus_speed_8000; 1044 break; 1045 default: 1046 hw->bus.speed = ixgbe_bus_speed_unknown; 1047 break; 1048 } 1049 1050 mac->ops.set_lan_id(hw); 1051 } 1052 1053 /** 1054 * ixgbe_get_bus_info_generic - Generic set PCI bus info 1055 * @hw: pointer to hardware structure 1056 * 1057 * Gets the PCI bus info (speed, width, type) then calls helper function to 1058 * store this data within the ixgbe_hw structure. 1059 **/ 1060 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 1061 { 1062 u16 link_status; 1063 1064 DEBUGFUNC("ixgbe_get_bus_info_generic"); 1065 1066 /* Get the negotiated link width and speed from PCI config space */ 1067 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS); 1068 1069 ixgbe_set_pci_config_data_generic(hw, link_status); 1070 1071 return IXGBE_SUCCESS; 1072 } 1073 1074 /** 1075 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 1076 * @hw: pointer to the HW structure 1077 * 1078 * Determines the LAN function id by reading memory-mapped registers and swaps 1079 * the port value if requested, and set MAC instance for devices that share 1080 * CS4227. 1081 **/ 1082 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 1083 { 1084 struct ixgbe_bus_info *bus = &hw->bus; 1085 u32 reg; 1086 u16 ee_ctrl_4; 1087 1088 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie"); 1089 1090 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 1091 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 1092 bus->lan_id = (u8)bus->func; 1093 1094 /* check for a port swap */ 1095 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw)); 1096 if (reg & IXGBE_FACTPS_LFS) 1097 bus->func ^= 0x1; 1098 1099 /* Get MAC instance from EEPROM for configuring CS4227 */ 1100 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) { 1101 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4); 1102 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >> 1103 IXGBE_EE_CTRL_4_INST_ID_SHIFT; 1104 } 1105 } 1106 1107 /** 1108 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 1109 * @hw: pointer to hardware structure 1110 * 1111 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 1112 * disables transmit and receive units. The adapter_stopped flag is used by 1113 * the shared code and drivers to determine if the adapter is in a stopped 1114 * state and should not touch the hardware. 1115 **/ 1116 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 1117 { 1118 u32 reg_val; 1119 u16 i; 1120 1121 DEBUGFUNC("ixgbe_stop_adapter_generic"); 1122 1123 /* 1124 * Set the adapter_stopped flag so other driver functions stop touching 1125 * the hardware 1126 */ 1127 hw->adapter_stopped = TRUE; 1128 1129 /* Disable the receive unit */ 1130 ixgbe_disable_rx(hw); 1131 1132 /* Clear interrupt mask to stop interrupts from being generated */ 1133 /* 1134 * XXX 1135 * This function is called in the state of both interrupt disabled 1136 * and interrupt enabled, e.g. 1137 * + interrupt disabled case: 1138 * - ixgbe_stop() 1139 * - ixgbe_disable_intr() // interrupt disabled here 1140 * - ixgbe_stop_adapter() 1141 * - hw->mac.ops.stop_adapter() 1142 * == this function 1143 * + interrupt enabled case: 1144 * - ixgbe_local_timer1() 1145 * - ixgbe_init_locked() 1146 * - ixgbe_stop_adapter() 1147 * - hw->mac.ops.stop_adapter() 1148 * == this function 1149 * Therefore, it causes nest status breaking to nest the status 1150 * (that is, que->im_nest++) at all times. So, this function must 1151 * use ixgbe_ensure_disabled_intr() instead of ixgbe_disable_intr(). 1152 */ 1153 ixgbe_ensure_disabled_intr(hw->back); 1154 1155 /* Clear any pending interrupts, flush previous writes */ 1156 IXGBE_READ_REG(hw, IXGBE_EICR); 1157 1158 /* Disable the transmit unit. Each queue must be disabled. */ 1159 for (i = 0; i < hw->mac.max_tx_queues; i++) 1160 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); 1161 1162 /* Disable the receive unit by stopping each queue */ 1163 for (i = 0; i < hw->mac.max_rx_queues; i++) { 1164 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 1165 reg_val &= ~IXGBE_RXDCTL_ENABLE; 1166 reg_val |= IXGBE_RXDCTL_SWFLSH; 1167 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 1168 } 1169 1170 /* flush all queues disables */ 1171 IXGBE_WRITE_FLUSH(hw); 1172 msec_delay(2); 1173 1174 /* 1175 * Prevent the PCI-E bus from hanging by disabling PCI-E master 1176 * access and verify no pending requests 1177 */ 1178 return ixgbe_disable_pcie_master(hw); 1179 } 1180 1181 /** 1182 * ixgbe_init_led_link_act_generic - Store the LED index link/activity. 1183 * @hw: pointer to hardware structure 1184 * 1185 * Store the index for the link active LED. This will be used to support 1186 * blinking the LED. 1187 **/ 1188 s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw) 1189 { 1190 struct ixgbe_mac_info *mac = &hw->mac; 1191 u32 led_reg, led_mode; 1192 u8 i; 1193 1194 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1195 1196 /* Get LED link active from the LEDCTL register */ 1197 for (i = 0; i < 4; i++) { 1198 led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i); 1199 1200 if ((led_mode & IXGBE_LED_MODE_MASK_BASE) == 1201 IXGBE_LED_LINK_ACTIVE) { 1202 mac->led_link_act = i; 1203 return IXGBE_SUCCESS; 1204 } 1205 } 1206 1207 /* 1208 * If LEDCTL register does not have the LED link active set, then use 1209 * known MAC defaults. 1210 */ 1211 switch (hw->mac.type) { 1212 case ixgbe_mac_X550EM_a: 1213 case ixgbe_mac_X550EM_x: 1214 mac->led_link_act = 1; 1215 break; 1216 default: 1217 mac->led_link_act = 2; 1218 } 1219 return IXGBE_SUCCESS; 1220 } 1221 1222 /** 1223 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 1224 * @hw: pointer to hardware structure 1225 * @index: led number to turn on 1226 **/ 1227 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 1228 { 1229 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1230 1231 DEBUGFUNC("ixgbe_led_on_generic"); 1232 1233 if (index > 3) 1234 return IXGBE_ERR_PARAM; 1235 1236 /* To turn on the LED, set mode to ON. */ 1237 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1238 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 1239 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1240 IXGBE_WRITE_FLUSH(hw); 1241 1242 return IXGBE_SUCCESS; 1243 } 1244 1245 /** 1246 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 1247 * @hw: pointer to hardware structure 1248 * @index: led number to turn off 1249 **/ 1250 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 1251 { 1252 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1253 1254 DEBUGFUNC("ixgbe_led_off_generic"); 1255 1256 if (index > 3) 1257 return IXGBE_ERR_PARAM; 1258 1259 /* To turn off the LED, set mode to OFF. */ 1260 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1261 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 1262 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1263 IXGBE_WRITE_FLUSH(hw); 1264 1265 return IXGBE_SUCCESS; 1266 } 1267 1268 /** 1269 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 1270 * @hw: pointer to hardware structure 1271 * 1272 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 1273 * ixgbe_hw struct in order to set up EEPROM access. 1274 **/ 1275 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 1276 { 1277 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 1278 u32 eec; 1279 u16 eeprom_size; 1280 1281 DEBUGFUNC("ixgbe_init_eeprom_params_generic"); 1282 1283 if (eeprom->type == ixgbe_eeprom_uninitialized) { 1284 eeprom->type = ixgbe_eeprom_none; 1285 /* Set default semaphore delay to 10ms which is a well 1286 * tested value */ 1287 eeprom->semaphore_delay = 10; 1288 /* Clear EEPROM page size, it will be initialized as needed */ 1289 eeprom->word_page_size = 0; 1290 1291 /* 1292 * Check for EEPROM present first. 1293 * If not present leave as none 1294 */ 1295 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1296 if (eec & IXGBE_EEC_PRES) { 1297 eeprom->type = ixgbe_eeprom_spi; 1298 1299 /* 1300 * SPI EEPROM is assumed here. This code would need to 1301 * change if a future EEPROM is not SPI. 1302 */ 1303 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 1304 IXGBE_EEC_SIZE_SHIFT); 1305 eeprom->word_size = 1 << (eeprom_size + 1306 IXGBE_EEPROM_WORD_SIZE_SHIFT); 1307 } 1308 1309 if (eec & IXGBE_EEC_ADDR_SIZE) 1310 eeprom->address_bits = 16; 1311 else 1312 eeprom->address_bits = 8; 1313 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: " 1314 "%d\n", eeprom->type, eeprom->word_size, 1315 eeprom->address_bits); 1316 } 1317 1318 return IXGBE_SUCCESS; 1319 } 1320 1321 /** 1322 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang 1323 * @hw: pointer to hardware structure 1324 * @offset: offset within the EEPROM to write 1325 * @words: number of word(s) 1326 * @data: 16 bit word(s) to write to EEPROM 1327 * 1328 * Reads 16 bit word(s) from EEPROM through bit-bang method 1329 **/ 1330 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1331 u16 words, u16 *data) 1332 { 1333 s32 status = IXGBE_SUCCESS; 1334 u16 i, count; 1335 1336 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic"); 1337 1338 hw->eeprom.ops.init_params(hw); 1339 1340 if (words == 0) { 1341 status = IXGBE_ERR_INVALID_ARGUMENT; 1342 goto out; 1343 } 1344 1345 if (offset + words > hw->eeprom.word_size) { 1346 status = IXGBE_ERR_EEPROM; 1347 goto out; 1348 } 1349 1350 /* 1351 * The EEPROM page size cannot be queried from the chip. We do lazy 1352 * initialization. It is worth to do that when we write large buffer. 1353 */ 1354 if ((hw->eeprom.word_page_size == 0) && 1355 (words > IXGBE_EEPROM_PAGE_SIZE_MAX)) 1356 ixgbe_detect_eeprom_page_size_generic(hw, offset); 1357 1358 /* 1359 * We cannot hold synchronization semaphores for too long 1360 * to avoid other entity starvation. However it is more efficient 1361 * to read in bursts than synchronizing access for each word. 1362 */ 1363 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1364 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1365 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1366 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, 1367 count, &data[i]); 1368 1369 if (status != IXGBE_SUCCESS) 1370 break; 1371 } 1372 1373 out: 1374 return status; 1375 } 1376 1377 /** 1378 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM 1379 * @hw: pointer to hardware structure 1380 * @offset: offset within the EEPROM to be written to 1381 * @words: number of word(s) 1382 * @data: 16 bit word(s) to be written to the EEPROM 1383 * 1384 * If ixgbe_eeprom_update_checksum is not called after this function, the 1385 * EEPROM will most likely contain an invalid checksum. 1386 **/ 1387 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1388 u16 words, u16 *data) 1389 { 1390 s32 status; 1391 u16 word; 1392 u16 page_size; 1393 u16 i; 1394 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 1395 1396 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang"); 1397 1398 /* Prepare the EEPROM for writing */ 1399 status = ixgbe_acquire_eeprom(hw); 1400 1401 if (status == IXGBE_SUCCESS) { 1402 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 1403 ixgbe_release_eeprom(hw); 1404 status = IXGBE_ERR_EEPROM; 1405 } 1406 } 1407 1408 if (status == IXGBE_SUCCESS) { 1409 for (i = 0; i < words; i++) { 1410 ixgbe_standby_eeprom(hw); 1411 1412 /* Send the WRITE ENABLE command (8 bit opcode ) */ 1413 ixgbe_shift_out_eeprom_bits(hw, 1414 IXGBE_EEPROM_WREN_OPCODE_SPI, 1415 IXGBE_EEPROM_OPCODE_BITS); 1416 1417 ixgbe_standby_eeprom(hw); 1418 1419 /* 1420 * Some SPI eeproms use the 8th address bit embedded 1421 * in the opcode 1422 */ 1423 if ((hw->eeprom.address_bits == 8) && 1424 ((offset + i) >= 128)) 1425 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1426 1427 /* Send the Write command (8-bit opcode + addr) */ 1428 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 1429 IXGBE_EEPROM_OPCODE_BITS); 1430 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1431 hw->eeprom.address_bits); 1432 1433 page_size = hw->eeprom.word_page_size; 1434 1435 /* Send the data in burst via SPI*/ 1436 do { 1437 word = data[i]; 1438 word = (word >> 8) | (word << 8); 1439 ixgbe_shift_out_eeprom_bits(hw, word, 16); 1440 1441 if (page_size == 0) 1442 break; 1443 1444 /* do not wrap around page */ 1445 if (((offset + i) & (page_size - 1)) == 1446 (page_size - 1)) 1447 break; 1448 } while (++i < words); 1449 1450 ixgbe_standby_eeprom(hw); 1451 msec_delay(10); 1452 } 1453 /* Done with writing - release the EEPROM */ 1454 ixgbe_release_eeprom(hw); 1455 } 1456 1457 return status; 1458 } 1459 1460 /** 1461 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 1462 * @hw: pointer to hardware structure 1463 * @offset: offset within the EEPROM to be written to 1464 * @data: 16 bit word to be written to the EEPROM 1465 * 1466 * If ixgbe_eeprom_update_checksum is not called after this function, the 1467 * EEPROM will most likely contain an invalid checksum. 1468 **/ 1469 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1470 { 1471 s32 status; 1472 1473 DEBUGFUNC("ixgbe_write_eeprom_generic"); 1474 1475 hw->eeprom.ops.init_params(hw); 1476 1477 if (offset >= hw->eeprom.word_size) { 1478 status = IXGBE_ERR_EEPROM; 1479 goto out; 1480 } 1481 1482 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); 1483 1484 out: 1485 return status; 1486 } 1487 1488 /** 1489 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang 1490 * @hw: pointer to hardware structure 1491 * @offset: offset within the EEPROM to be read 1492 * @data: read 16 bit words(s) from EEPROM 1493 * @words: number of word(s) 1494 * 1495 * Reads 16 bit word(s) from EEPROM through bit-bang method 1496 **/ 1497 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1498 u16 words, u16 *data) 1499 { 1500 s32 status = IXGBE_SUCCESS; 1501 u16 i, count; 1502 1503 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic"); 1504 1505 hw->eeprom.ops.init_params(hw); 1506 1507 if (words == 0) { 1508 status = IXGBE_ERR_INVALID_ARGUMENT; 1509 goto out; 1510 } 1511 1512 if (offset + words > hw->eeprom.word_size) { 1513 status = IXGBE_ERR_EEPROM; 1514 goto out; 1515 } 1516 1517 /* 1518 * We cannot hold synchronization semaphores for too long 1519 * to avoid other entity starvation. However it is more efficient 1520 * to read in bursts than synchronizing access for each word. 1521 */ 1522 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1523 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1524 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1525 1526 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, 1527 count, &data[i]); 1528 1529 if (status != IXGBE_SUCCESS) 1530 break; 1531 } 1532 1533 out: 1534 return status; 1535 } 1536 1537 /** 1538 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang 1539 * @hw: pointer to hardware structure 1540 * @offset: offset within the EEPROM to be read 1541 * @words: number of word(s) 1542 * @data: read 16 bit word(s) from EEPROM 1543 * 1544 * Reads 16 bit word(s) from EEPROM through bit-bang method 1545 **/ 1546 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1547 u16 words, u16 *data) 1548 { 1549 s32 status; 1550 u16 word_in; 1551 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 1552 u16 i; 1553 1554 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang"); 1555 1556 /* Prepare the EEPROM for reading */ 1557 status = ixgbe_acquire_eeprom(hw); 1558 1559 if (status == IXGBE_SUCCESS) { 1560 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 1561 ixgbe_release_eeprom(hw); 1562 status = IXGBE_ERR_EEPROM; 1563 } 1564 } 1565 1566 if (status == IXGBE_SUCCESS) { 1567 for (i = 0; i < words; i++) { 1568 ixgbe_standby_eeprom(hw); 1569 /* 1570 * Some SPI eeproms use the 8th address bit embedded 1571 * in the opcode 1572 */ 1573 if ((hw->eeprom.address_bits == 8) && 1574 ((offset + i) >= 128)) 1575 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1576 1577 /* Send the READ command (opcode + addr) */ 1578 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 1579 IXGBE_EEPROM_OPCODE_BITS); 1580 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1581 hw->eeprom.address_bits); 1582 1583 /* Read the data. */ 1584 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 1585 data[i] = (word_in >> 8) | (word_in << 8); 1586 } 1587 1588 /* End this read operation */ 1589 ixgbe_release_eeprom(hw); 1590 } 1591 1592 return status; 1593 } 1594 1595 /** 1596 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 1597 * @hw: pointer to hardware structure 1598 * @offset: offset within the EEPROM to be read 1599 * @data: read 16 bit value from EEPROM 1600 * 1601 * Reads 16 bit value from EEPROM through bit-bang method 1602 **/ 1603 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1604 u16 *data) 1605 { 1606 s32 status; 1607 1608 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic"); 1609 1610 hw->eeprom.ops.init_params(hw); 1611 1612 if (offset >= hw->eeprom.word_size) { 1613 status = IXGBE_ERR_EEPROM; 1614 goto out; 1615 } 1616 1617 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1618 1619 out: 1620 return status; 1621 } 1622 1623 /** 1624 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD 1625 * @hw: pointer to hardware structure 1626 * @offset: offset of word in the EEPROM to read 1627 * @words: number of word(s) 1628 * @data: 16 bit word(s) from the EEPROM 1629 * 1630 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 1631 **/ 1632 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1633 u16 words, u16 *data) 1634 { 1635 u32 eerd; 1636 s32 status = IXGBE_SUCCESS; 1637 u32 i; 1638 1639 DEBUGFUNC("ixgbe_read_eerd_buffer_generic"); 1640 1641 hw->eeprom.ops.init_params(hw); 1642 1643 if (words == 0) { 1644 status = IXGBE_ERR_INVALID_ARGUMENT; 1645 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words"); 1646 goto out; 1647 } 1648 1649 if (offset >= hw->eeprom.word_size) { 1650 status = IXGBE_ERR_EEPROM; 1651 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset"); 1652 goto out; 1653 } 1654 1655 for (i = 0; i < words; i++) { 1656 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1657 IXGBE_EEPROM_RW_REG_START; 1658 1659 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 1660 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 1661 1662 if (status == IXGBE_SUCCESS) { 1663 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 1664 IXGBE_EEPROM_RW_REG_DATA); 1665 } else { 1666 DEBUGOUT("Eeprom read timed out\n"); 1667 goto out; 1668 } 1669 } 1670 out: 1671 return status; 1672 } 1673 1674 /** 1675 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size 1676 * @hw: pointer to hardware structure 1677 * @offset: offset within the EEPROM to be used as a scratch pad 1678 * 1679 * Discover EEPROM page size by writing marching data at given offset. 1680 * This function is called only when we are writing a new large buffer 1681 * at given offset so the data would be overwritten anyway. 1682 **/ 1683 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 1684 u16 offset) 1685 { 1686 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX]; 1687 s32 status = IXGBE_SUCCESS; 1688 u16 i; 1689 1690 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic"); 1691 1692 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++) 1693 data[i] = i; 1694 1695 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; 1696 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1697 IXGBE_EEPROM_PAGE_SIZE_MAX, data); 1698 hw->eeprom.word_page_size = 0; 1699 if (status != IXGBE_SUCCESS) 1700 goto out; 1701 1702 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1703 if (status != IXGBE_SUCCESS) 1704 goto out; 1705 1706 /* 1707 * When writing in burst more than the actual page size 1708 * EEPROM address wraps around current page. 1709 */ 1710 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; 1711 1712 DEBUGOUT1("Detected EEPROM page size = %d words.", 1713 hw->eeprom.word_page_size); 1714 out: 1715 return status; 1716 } 1717 1718 /** 1719 * ixgbe_read_eerd_generic - Read EEPROM word using EERD 1720 * @hw: pointer to hardware structure 1721 * @offset: offset of word in the EEPROM to read 1722 * @data: word read from the EEPROM 1723 * 1724 * Reads a 16 bit word from the EEPROM using the EERD register. 1725 **/ 1726 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 1727 { 1728 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); 1729 } 1730 1731 /** 1732 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR 1733 * @hw: pointer to hardware structure 1734 * @offset: offset of word in the EEPROM to write 1735 * @words: number of word(s) 1736 * @data: word(s) write to the EEPROM 1737 * 1738 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 1739 **/ 1740 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1741 u16 words, u16 *data) 1742 { 1743 u32 eewr; 1744 s32 status = IXGBE_SUCCESS; 1745 u16 i; 1746 1747 DEBUGFUNC("ixgbe_write_eewr_generic"); 1748 1749 hw->eeprom.ops.init_params(hw); 1750 1751 if (words == 0) { 1752 status = IXGBE_ERR_INVALID_ARGUMENT; 1753 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words"); 1754 goto out; 1755 } 1756 1757 if (offset >= hw->eeprom.word_size) { 1758 status = IXGBE_ERR_EEPROM; 1759 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset"); 1760 goto out; 1761 } 1762 1763 for (i = 0; i < words; i++) { 1764 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1765 (data[i] << IXGBE_EEPROM_RW_REG_DATA) | 1766 IXGBE_EEPROM_RW_REG_START; 1767 1768 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1769 if (status != IXGBE_SUCCESS) { 1770 DEBUGOUT("Eeprom write EEWR timed out\n"); 1771 goto out; 1772 } 1773 1774 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); 1775 1776 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1777 if (status != IXGBE_SUCCESS) { 1778 DEBUGOUT("Eeprom write EEWR timed out\n"); 1779 goto out; 1780 } 1781 } 1782 1783 out: 1784 return status; 1785 } 1786 1787 /** 1788 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR 1789 * @hw: pointer to hardware structure 1790 * @offset: offset of word in the EEPROM to write 1791 * @data: word write to the EEPROM 1792 * 1793 * Write a 16 bit word to the EEPROM using the EEWR register. 1794 **/ 1795 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1796 { 1797 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); 1798 } 1799 1800 /** 1801 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 1802 * @hw: pointer to hardware structure 1803 * @ee_reg: EEPROM flag for polling 1804 * 1805 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the 1806 * read or write is done respectively. 1807 **/ 1808 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) 1809 { 1810 u32 i; 1811 u32 reg; 1812 s32 status = IXGBE_ERR_EEPROM; 1813 1814 DEBUGFUNC("ixgbe_poll_eerd_eewr_done"); 1815 1816 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { 1817 if (ee_reg == IXGBE_NVM_POLL_READ) 1818 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 1819 else 1820 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); 1821 1822 if (reg & IXGBE_EEPROM_RW_REG_DONE) { 1823 status = IXGBE_SUCCESS; 1824 break; 1825 } 1826 usec_delay(5); 1827 } 1828 1829 if (i == IXGBE_EERD_EEWR_ATTEMPTS) 1830 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1831 "EEPROM read/write done polling timed out"); 1832 1833 return status; 1834 } 1835 1836 /** 1837 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 1838 * @hw: pointer to hardware structure 1839 * 1840 * Prepares EEPROM for access using bit-bang method. This function should 1841 * be called before issuing a command to the EEPROM. 1842 **/ 1843 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 1844 { 1845 s32 status = IXGBE_SUCCESS; 1846 u32 eec; 1847 u32 i; 1848 1849 DEBUGFUNC("ixgbe_acquire_eeprom"); 1850 1851 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) 1852 != IXGBE_SUCCESS) 1853 status = IXGBE_ERR_SWFW_SYNC; 1854 1855 if (status == IXGBE_SUCCESS) { 1856 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1857 1858 /* Request EEPROM Access */ 1859 eec |= IXGBE_EEC_REQ; 1860 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1861 1862 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 1863 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1864 if (eec & IXGBE_EEC_GNT) 1865 break; 1866 usec_delay(5); 1867 } 1868 1869 /* Release if grant not acquired */ 1870 if (!(eec & IXGBE_EEC_GNT)) { 1871 eec &= ~IXGBE_EEC_REQ; 1872 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1873 DEBUGOUT("Could not acquire EEPROM grant\n"); 1874 1875 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1876 status = IXGBE_ERR_EEPROM; 1877 } 1878 1879 /* Setup EEPROM for Read/Write */ 1880 if (status == IXGBE_SUCCESS) { 1881 /* Clear CS and SK */ 1882 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 1883 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1884 IXGBE_WRITE_FLUSH(hw); 1885 usec_delay(1); 1886 } 1887 } 1888 return status; 1889 } 1890 1891 /** 1892 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 1893 * @hw: pointer to hardware structure 1894 * 1895 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 1896 **/ 1897 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 1898 { 1899 s32 status = IXGBE_ERR_EEPROM; 1900 u32 timeout = 2000; 1901 u32 i; 1902 u32 swsm; 1903 1904 DEBUGFUNC("ixgbe_get_eeprom_semaphore"); 1905 1906 1907 /* Get SMBI software semaphore between device drivers first */ 1908 for (i = 0; i < timeout; i++) { 1909 /* 1910 * If the SMBI bit is 0 when we read it, then the bit will be 1911 * set and we have the semaphore 1912 */ 1913 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1914 if (!(swsm & IXGBE_SWSM_SMBI)) { 1915 status = IXGBE_SUCCESS; 1916 break; 1917 } 1918 usec_delay(50); 1919 } 1920 1921 if (i == timeout) { 1922 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore " 1923 "not granted.\n"); 1924 /* 1925 * this release is particularly important because our attempts 1926 * above to get the semaphore may have succeeded, and if there 1927 * was a timeout, we should unconditionally clear the semaphore 1928 * bits to free the driver to make progress 1929 */ 1930 ixgbe_release_eeprom_semaphore(hw); 1931 1932 usec_delay(50); 1933 /* 1934 * one last try 1935 * If the SMBI bit is 0 when we read it, then the bit will be 1936 * set and we have the semaphore 1937 */ 1938 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1939 if (!(swsm & IXGBE_SWSM_SMBI)) 1940 status = IXGBE_SUCCESS; 1941 } 1942 1943 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 1944 if (status == IXGBE_SUCCESS) { 1945 for (i = 0; i < timeout; i++) { 1946 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1947 1948 /* Set the SW EEPROM semaphore bit to request access */ 1949 swsm |= IXGBE_SWSM_SWESMBI; 1950 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm); 1951 1952 /* 1953 * If we set the bit successfully then we got the 1954 * semaphore. 1955 */ 1956 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1957 if (swsm & IXGBE_SWSM_SWESMBI) 1958 break; 1959 1960 usec_delay(50); 1961 } 1962 1963 /* 1964 * Release semaphores and return error if SW EEPROM semaphore 1965 * was not granted because we don't have access to the EEPROM 1966 */ 1967 if (i >= timeout) { 1968 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1969 "SWESMBI Software EEPROM semaphore not granted.\n"); 1970 ixgbe_release_eeprom_semaphore(hw); 1971 status = IXGBE_ERR_EEPROM; 1972 } 1973 } else { 1974 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1975 "Software semaphore SMBI between device drivers " 1976 "not granted.\n"); 1977 } 1978 1979 return status; 1980 } 1981 1982 /** 1983 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 1984 * @hw: pointer to hardware structure 1985 * 1986 * This function clears hardware semaphore bits. 1987 **/ 1988 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 1989 { 1990 u32 swsm; 1991 1992 DEBUGFUNC("ixgbe_release_eeprom_semaphore"); 1993 1994 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1995 1996 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 1997 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 1998 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 1999 IXGBE_WRITE_FLUSH(hw); 2000 } 2001 2002 /** 2003 * ixgbe_ready_eeprom - Polls for EEPROM ready 2004 * @hw: pointer to hardware structure 2005 **/ 2006 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 2007 { 2008 s32 status = IXGBE_SUCCESS; 2009 u16 i; 2010 u8 spi_stat_reg; 2011 2012 DEBUGFUNC("ixgbe_ready_eeprom"); 2013 2014 /* 2015 * Read "Status Register" repeatedly until the LSB is cleared. The 2016 * EEPROM will signal that the command has been completed by clearing 2017 * bit 0 of the internal status register. If it's not cleared within 2018 * 5 milliseconds, then error out. 2019 */ 2020 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 2021 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 2022 IXGBE_EEPROM_OPCODE_BITS); 2023 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 2024 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 2025 break; 2026 2027 usec_delay(5); 2028 ixgbe_standby_eeprom(hw); 2029 } 2030 2031 /* 2032 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 2033 * devices (and only 0-5mSec on 5V devices) 2034 */ 2035 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 2036 DEBUGOUT("SPI EEPROM Status error\n"); 2037 status = IXGBE_ERR_EEPROM; 2038 } 2039 2040 return status; 2041 } 2042 2043 /** 2044 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 2045 * @hw: pointer to hardware structure 2046 **/ 2047 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 2048 { 2049 u32 eec; 2050 2051 DEBUGFUNC("ixgbe_standby_eeprom"); 2052 2053 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2054 2055 /* Toggle CS to flush commands */ 2056 eec |= IXGBE_EEC_CS; 2057 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2058 IXGBE_WRITE_FLUSH(hw); 2059 usec_delay(1); 2060 eec &= ~IXGBE_EEC_CS; 2061 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2062 IXGBE_WRITE_FLUSH(hw); 2063 usec_delay(1); 2064 } 2065 2066 /** 2067 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 2068 * @hw: pointer to hardware structure 2069 * @data: data to send to the EEPROM 2070 * @count: number of bits to shift out 2071 **/ 2072 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 2073 u16 count) 2074 { 2075 u32 eec; 2076 u32 mask; 2077 u32 i; 2078 2079 DEBUGFUNC("ixgbe_shift_out_eeprom_bits"); 2080 2081 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2082 2083 /* 2084 * Mask is used to shift "count" bits of "data" out to the EEPROM 2085 * one bit at a time. Determine the starting bit based on count 2086 */ 2087 mask = 0x01 << (count - 1); 2088 2089 for (i = 0; i < count; i++) { 2090 /* 2091 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 2092 * "1", and then raising and then lowering the clock (the SK 2093 * bit controls the clock input to the EEPROM). A "0" is 2094 * shifted out to the EEPROM by setting "DI" to "0" and then 2095 * raising and then lowering the clock. 2096 */ 2097 if (data & mask) 2098 eec |= IXGBE_EEC_DI; 2099 else 2100 eec &= ~IXGBE_EEC_DI; 2101 2102 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2103 IXGBE_WRITE_FLUSH(hw); 2104 2105 usec_delay(1); 2106 2107 ixgbe_raise_eeprom_clk(hw, &eec); 2108 ixgbe_lower_eeprom_clk(hw, &eec); 2109 2110 /* 2111 * Shift mask to signify next bit of data to shift in to the 2112 * EEPROM 2113 */ 2114 mask = mask >> 1; 2115 } 2116 2117 /* We leave the "DI" bit set to "0" when we leave this routine. */ 2118 eec &= ~IXGBE_EEC_DI; 2119 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2120 IXGBE_WRITE_FLUSH(hw); 2121 } 2122 2123 /** 2124 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 2125 * @hw: pointer to hardware structure 2126 * @count: number of bits to shift 2127 **/ 2128 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 2129 { 2130 u32 eec; 2131 u32 i; 2132 u16 data = 0; 2133 2134 DEBUGFUNC("ixgbe_shift_in_eeprom_bits"); 2135 2136 /* 2137 * In order to read a register from the EEPROM, we need to shift 2138 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 2139 * the clock input to the EEPROM (setting the SK bit), and then reading 2140 * the value of the "DO" bit. During this "shifting in" process the 2141 * "DI" bit should always be clear. 2142 */ 2143 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2144 2145 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 2146 2147 for (i = 0; i < count; i++) { 2148 data = data << 1; 2149 ixgbe_raise_eeprom_clk(hw, &eec); 2150 2151 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2152 2153 eec &= ~(IXGBE_EEC_DI); 2154 if (eec & IXGBE_EEC_DO) 2155 data |= 1; 2156 2157 ixgbe_lower_eeprom_clk(hw, &eec); 2158 } 2159 2160 return data; 2161 } 2162 2163 /** 2164 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 2165 * @hw: pointer to hardware structure 2166 * @eec: EEC register's current value 2167 **/ 2168 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 2169 { 2170 DEBUGFUNC("ixgbe_raise_eeprom_clk"); 2171 2172 /* 2173 * Raise the clock input to the EEPROM 2174 * (setting the SK bit), then delay 2175 */ 2176 *eec = *eec | IXGBE_EEC_SK; 2177 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec); 2178 IXGBE_WRITE_FLUSH(hw); 2179 usec_delay(1); 2180 } 2181 2182 /** 2183 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 2184 * @hw: pointer to hardware structure 2185 * @eec: EEC's current value 2186 **/ 2187 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 2188 { 2189 DEBUGFUNC("ixgbe_lower_eeprom_clk"); 2190 2191 /* 2192 * Lower the clock input to the EEPROM (clearing the SK bit), then 2193 * delay 2194 */ 2195 *eec = *eec & ~IXGBE_EEC_SK; 2196 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec); 2197 IXGBE_WRITE_FLUSH(hw); 2198 usec_delay(1); 2199 } 2200 2201 /** 2202 * ixgbe_release_eeprom - Release EEPROM, release semaphores 2203 * @hw: pointer to hardware structure 2204 **/ 2205 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 2206 { 2207 u32 eec; 2208 2209 DEBUGFUNC("ixgbe_release_eeprom"); 2210 2211 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2212 2213 eec |= IXGBE_EEC_CS; /* Pull CS high */ 2214 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 2215 2216 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2217 IXGBE_WRITE_FLUSH(hw); 2218 2219 usec_delay(1); 2220 2221 /* Stop requesting EEPROM access */ 2222 eec &= ~IXGBE_EEC_REQ; 2223 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2224 2225 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2226 2227 /* Delay before attempt to obtain semaphore again to allow FW access */ 2228 msec_delay(hw->eeprom.semaphore_delay); 2229 } 2230 2231 /** 2232 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum 2233 * @hw: pointer to hardware structure 2234 * 2235 * Returns a negative error code on error, or the 16-bit checksum 2236 **/ 2237 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) 2238 { 2239 u16 i; 2240 u16 j; 2241 u16 checksum = 0; 2242 u16 length = 0; 2243 u16 pointer = 0; 2244 u16 word = 0; 2245 2246 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic"); 2247 2248 /* Include 0x0-0x3F in the checksum */ 2249 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 2250 if (hw->eeprom.ops.read(hw, i, &word)) { 2251 DEBUGOUT("EEPROM read failed\n"); 2252 return IXGBE_ERR_EEPROM; 2253 } 2254 checksum += word; 2255 } 2256 2257 /* Include all data from pointers except for the fw pointer */ 2258 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 2259 if (hw->eeprom.ops.read(hw, i, &pointer)) { 2260 DEBUGOUT("EEPROM read failed\n"); 2261 return IXGBE_ERR_EEPROM; 2262 } 2263 2264 /* If the pointer seems invalid */ 2265 if (pointer == 0xFFFF || pointer == 0) 2266 continue; 2267 2268 if (hw->eeprom.ops.read(hw, pointer, &length)) { 2269 DEBUGOUT("EEPROM read failed\n"); 2270 return IXGBE_ERR_EEPROM; 2271 } 2272 2273 if (length == 0xFFFF || length == 0) 2274 continue; 2275 2276 for (j = pointer + 1; j <= pointer + length; j++) { 2277 if (hw->eeprom.ops.read(hw, j, &word)) { 2278 DEBUGOUT("EEPROM read failed\n"); 2279 return IXGBE_ERR_EEPROM; 2280 } 2281 checksum += word; 2282 } 2283 } 2284 2285 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 2286 2287 return (s32)checksum; 2288 } 2289 2290 /** 2291 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 2292 * @hw: pointer to hardware structure 2293 * @checksum_val: calculated checksum 2294 * 2295 * Performs checksum calculation and validates the EEPROM checksum. If the 2296 * caller does not need checksum_val, the value can be NULL. 2297 **/ 2298 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 2299 u16 *checksum_val) 2300 { 2301 s32 status; 2302 u16 checksum; 2303 u16 read_checksum = 0; 2304 2305 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic"); 2306 2307 /* Read the first word from the EEPROM. If this times out or fails, do 2308 * not continue or we could be in for a very long wait while every 2309 * EEPROM read fails 2310 */ 2311 status = hw->eeprom.ops.read(hw, 0, &checksum); 2312 if (status) { 2313 DEBUGOUT("EEPROM read failed\n"); 2314 return status; 2315 } 2316 2317 status = hw->eeprom.ops.calc_checksum(hw); 2318 if (status < 0) 2319 return status; 2320 2321 checksum = (u16)(status & 0xffff); 2322 2323 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 2324 if (status) { 2325 DEBUGOUT("EEPROM read failed\n"); 2326 return status; 2327 } 2328 2329 /* Verify read checksum from EEPROM is the same as 2330 * calculated checksum 2331 */ 2332 if (read_checksum != checksum) 2333 status = IXGBE_ERR_EEPROM_CHECKSUM; 2334 2335 /* If the user cares, return the calculated checksum */ 2336 if (checksum_val) 2337 *checksum_val = checksum; 2338 2339 return status; 2340 } 2341 2342 /** 2343 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 2344 * @hw: pointer to hardware structure 2345 **/ 2346 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 2347 { 2348 s32 status; 2349 u16 checksum; 2350 2351 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic"); 2352 2353 /* Read the first word from the EEPROM. If this times out or fails, do 2354 * not continue or we could be in for a very long wait while every 2355 * EEPROM read fails 2356 */ 2357 status = hw->eeprom.ops.read(hw, 0, &checksum); 2358 if (status) { 2359 DEBUGOUT("EEPROM read failed\n"); 2360 return status; 2361 } 2362 2363 status = hw->eeprom.ops.calc_checksum(hw); 2364 if (status < 0) 2365 return status; 2366 2367 checksum = (u16)(status & 0xffff); 2368 2369 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum); 2370 2371 return status; 2372 } 2373 2374 /** 2375 * ixgbe_validate_mac_addr - Validate MAC address 2376 * @mac_addr: pointer to MAC address. 2377 * 2378 * Tests a MAC address to ensure it is a valid Individual Address. 2379 **/ 2380 s32 ixgbe_validate_mac_addr(u8 *mac_addr) 2381 { 2382 s32 status = IXGBE_SUCCESS; 2383 2384 DEBUGFUNC("ixgbe_validate_mac_addr"); 2385 2386 /* Make sure it is not a multicast address */ 2387 if (IXGBE_IS_MULTICAST(mac_addr)) { 2388 status = IXGBE_ERR_INVALID_MAC_ADDR; 2389 /* Not a broadcast address */ 2390 } else if (IXGBE_IS_BROADCAST(mac_addr)) { 2391 status = IXGBE_ERR_INVALID_MAC_ADDR; 2392 /* Reject the zero address */ 2393 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 2394 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { 2395 status = IXGBE_ERR_INVALID_MAC_ADDR; 2396 } 2397 return status; 2398 } 2399 2400 /** 2401 * ixgbe_set_rar_generic - Set Rx address register 2402 * @hw: pointer to hardware structure 2403 * @index: Receive address register to write 2404 * @addr: Address to put into receive address register 2405 * @vmdq: VMDq "set" or "pool" index 2406 * @enable_addr: set flag that address is active 2407 * 2408 * Puts an ethernet address into a receive address register. 2409 **/ 2410 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 2411 u32 enable_addr) 2412 { 2413 u32 rar_low, rar_high; 2414 u32 rar_entries = hw->mac.num_rar_entries; 2415 2416 DEBUGFUNC("ixgbe_set_rar_generic"); 2417 2418 /* Make sure we are using a valid rar index range */ 2419 if (index >= rar_entries) { 2420 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 2421 "RAR index %d is out of range.\n", index); 2422 return IXGBE_ERR_INVALID_ARGUMENT; 2423 } 2424 2425 /* setup VMDq pool selection before this RAR gets enabled */ 2426 hw->mac.ops.set_vmdq(hw, index, vmdq); 2427 2428 /* 2429 * HW expects these in little endian so we reverse the byte 2430 * order from network order (big endian) to little endian 2431 */ 2432 rar_low = ((u32)addr[0] | 2433 ((u32)addr[1] << 8) | 2434 ((u32)addr[2] << 16) | 2435 ((u32)addr[3] << 24)); 2436 /* 2437 * Some parts put the VMDq setting in the extra RAH bits, 2438 * so save everything except the lower 16 bits that hold part 2439 * of the address and the address valid bit. 2440 */ 2441 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 2442 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 2443 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 2444 2445 if (enable_addr != 0) 2446 rar_high |= IXGBE_RAH_AV; 2447 2448 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 2449 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 2450 2451 return IXGBE_SUCCESS; 2452 } 2453 2454 /** 2455 * ixgbe_clear_rar_generic - Remove Rx address register 2456 * @hw: pointer to hardware structure 2457 * @index: Receive address register to write 2458 * 2459 * Clears an ethernet address from a receive address register. 2460 **/ 2461 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 2462 { 2463 u32 rar_high; 2464 u32 rar_entries = hw->mac.num_rar_entries; 2465 2466 DEBUGFUNC("ixgbe_clear_rar_generic"); 2467 2468 /* Make sure we are using a valid rar index range */ 2469 if (index >= rar_entries) { 2470 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 2471 "RAR index %d is out of range.\n", index); 2472 return IXGBE_ERR_INVALID_ARGUMENT; 2473 } 2474 2475 /* 2476 * Some parts put the VMDq setting in the extra RAH bits, 2477 * so save everything except the lower 16 bits that hold part 2478 * of the address and the address valid bit. 2479 */ 2480 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 2481 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 2482 2483 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 2484 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 2485 2486 /* clear VMDq pool/queue selection for this RAR */ 2487 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 2488 2489 return IXGBE_SUCCESS; 2490 } 2491 2492 /** 2493 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 2494 * @hw: pointer to hardware structure 2495 * 2496 * Places the MAC address in receive address register 0 and clears the rest 2497 * of the receive address registers. Clears the multicast table. Assumes 2498 * the receiver is in reset when the routine is called. 2499 **/ 2500 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 2501 { 2502 u32 i; 2503 u32 rar_entries = hw->mac.num_rar_entries; 2504 2505 DEBUGFUNC("ixgbe_init_rx_addrs_generic"); 2506 2507 /* 2508 * If the current mac address is valid, assume it is a software override 2509 * to the permanent address. 2510 * Otherwise, use the permanent address from the eeprom. 2511 */ 2512 if (ixgbe_validate_mac_addr(hw->mac.addr) == 2513 IXGBE_ERR_INVALID_MAC_ADDR) { 2514 /* Get the MAC address from the RAR0 for later reference */ 2515 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 2516 2517 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ", 2518 hw->mac.addr[0], hw->mac.addr[1], 2519 hw->mac.addr[2]); 2520 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 2521 hw->mac.addr[4], hw->mac.addr[5]); 2522 } else { 2523 /* Setup the receive address. */ 2524 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 2525 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 2526 hw->mac.addr[0], hw->mac.addr[1], 2527 hw->mac.addr[2]); 2528 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 2529 hw->mac.addr[4], hw->mac.addr[5]); 2530 2531 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 2532 } 2533 2534 /* clear VMDq pool/queue selection for RAR 0 */ 2535 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); 2536 2537 hw->addr_ctrl.overflow_promisc = 0; 2538 2539 hw->addr_ctrl.rar_used_count = 1; 2540 2541 /* Zero out the other receive addresses. */ 2542 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); 2543 for (i = 1; i < rar_entries; i++) { 2544 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 2545 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 2546 } 2547 2548 /* Clear the MTA */ 2549 hw->addr_ctrl.mta_in_use = 0; 2550 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2551 2552 DEBUGOUT(" Clearing MTA\n"); 2553 for (i = 0; i < hw->mac.mcft_size; i++) 2554 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 2555 2556 ixgbe_init_uta_tables(hw); 2557 2558 return IXGBE_SUCCESS; 2559 } 2560 2561 /** 2562 * ixgbe_add_uc_addr - Adds a secondary unicast address. 2563 * @hw: pointer to hardware structure 2564 * @addr: new address 2565 * @vmdq: VMDq "set" or "pool" index 2566 * 2567 * Adds it to unused receive address register or goes into promiscuous mode. 2568 **/ 2569 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 2570 { 2571 u32 rar_entries = hw->mac.num_rar_entries; 2572 u32 rar; 2573 2574 DEBUGFUNC("ixgbe_add_uc_addr"); 2575 2576 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", 2577 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 2578 2579 /* 2580 * Place this address in the RAR if there is room, 2581 * else put the controller into promiscuous mode 2582 */ 2583 if (hw->addr_ctrl.rar_used_count < rar_entries) { 2584 rar = hw->addr_ctrl.rar_used_count; 2585 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 2586 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar); 2587 hw->addr_ctrl.rar_used_count++; 2588 } else { 2589 hw->addr_ctrl.overflow_promisc++; 2590 } 2591 2592 DEBUGOUT("ixgbe_add_uc_addr Complete\n"); 2593 } 2594 2595 /** 2596 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses 2597 * @hw: pointer to hardware structure 2598 * @addr_list: the list of new addresses 2599 * @addr_count: number of addresses 2600 * @next: iterator function to walk the address list 2601 * 2602 * The given list replaces any existing list. Clears the secondary addrs from 2603 * receive address registers. Uses unused receive address registers for the 2604 * first secondary addresses, and falls back to promiscuous mode as needed. 2605 * 2606 * Drivers using secondary unicast addresses must set user_set_promisc when 2607 * manually putting the device into promiscuous mode. 2608 **/ 2609 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, 2610 u32 addr_count, ixgbe_mc_addr_itr next) 2611 { 2612 u8 *addr; 2613 u32 i; 2614 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; 2615 u32 uc_addr_in_use; 2616 u32 fctrl; 2617 u32 vmdq; 2618 2619 DEBUGFUNC("ixgbe_update_uc_addr_list_generic"); 2620 2621 /* 2622 * Clear accounting of old secondary address list, 2623 * don't count RAR[0] 2624 */ 2625 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1; 2626 hw->addr_ctrl.rar_used_count -= uc_addr_in_use; 2627 hw->addr_ctrl.overflow_promisc = 0; 2628 2629 /* Zero out the other receive addresses */ 2630 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1); 2631 for (i = 0; i < uc_addr_in_use; i++) { 2632 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0); 2633 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0); 2634 } 2635 2636 /* Add the new addresses */ 2637 for (i = 0; i < addr_count; i++) { 2638 DEBUGOUT(" Adding the secondary addresses:\n"); 2639 addr = next(hw, &addr_list, &vmdq); 2640 ixgbe_add_uc_addr(hw, addr, vmdq); 2641 } 2642 2643 if (hw->addr_ctrl.overflow_promisc) { 2644 /* enable promisc if not already in overflow or set by user */ 2645 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 2646 DEBUGOUT(" Entering address overflow promisc mode\n"); 2647 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 2648 fctrl |= IXGBE_FCTRL_UPE; 2649 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 2650 } 2651 } else { 2652 /* only disable if set by overflow, not by user */ 2653 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 2654 DEBUGOUT(" Leaving address overflow promisc mode\n"); 2655 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 2656 fctrl &= ~IXGBE_FCTRL_UPE; 2657 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 2658 } 2659 } 2660 2661 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n"); 2662 return IXGBE_SUCCESS; 2663 } 2664 2665 /** 2666 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 2667 * @hw: pointer to hardware structure 2668 * @mc_addr: the multicast address 2669 * 2670 * Extracts the 12 bits, from a multicast address, to determine which 2671 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 2672 * incoming rx multicast addresses, to determine the bit-vector to check in 2673 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 2674 * by the MO field of the MCSTCTRL. The MO field is set during initialization 2675 * to mc_filter_type. 2676 **/ 2677 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 2678 { 2679 u32 vector = 0; 2680 2681 DEBUGFUNC("ixgbe_mta_vector"); 2682 2683 switch (hw->mac.mc_filter_type) { 2684 case 0: /* use bits [47:36] of the address */ 2685 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 2686 break; 2687 case 1: /* use bits [46:35] of the address */ 2688 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 2689 break; 2690 case 2: /* use bits [45:34] of the address */ 2691 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 2692 break; 2693 case 3: /* use bits [43:32] of the address */ 2694 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 2695 break; 2696 default: /* Invalid mc_filter_type */ 2697 DEBUGOUT("MC filter type param set incorrectly\n"); 2698 ASSERT(0); 2699 break; 2700 } 2701 2702 /* vector can only be 12-bits or boundary will be exceeded */ 2703 vector &= 0xFFF; 2704 return vector; 2705 } 2706 2707 /** 2708 * ixgbe_set_mta - Set bit-vector in multicast table 2709 * @hw: pointer to hardware structure 2710 * @mc_addr: Multicast address 2711 * 2712 * Sets the bit-vector in the multicast table. 2713 **/ 2714 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 2715 { 2716 u32 vector; 2717 u32 vector_bit; 2718 u32 vector_reg; 2719 2720 DEBUGFUNC("ixgbe_set_mta"); 2721 2722 hw->addr_ctrl.mta_in_use++; 2723 2724 vector = ixgbe_mta_vector(hw, mc_addr); 2725 DEBUGOUT1(" bit-vector = 0x%03X\n", vector); 2726 2727 /* 2728 * The MTA is a register array of 128 32-bit registers. It is treated 2729 * like an array of 4096 bits. We want to set bit 2730 * BitArray[vector_value]. So we figure out what register the bit is 2731 * in, read it, OR in the new bit, then write back the new value. The 2732 * register is determined by the upper 7 bits of the vector value and 2733 * the bit within that register are determined by the lower 5 bits of 2734 * the value. 2735 */ 2736 vector_reg = (vector >> 5) & 0x7F; 2737 vector_bit = vector & 0x1F; 2738 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit); 2739 } 2740 2741 /** 2742 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 2743 * @hw: pointer to hardware structure 2744 * @mc_addr_list: the list of new multicast addresses 2745 * @mc_addr_count: number of addresses 2746 * @next: iterator function to walk the multicast address list 2747 * @clear: flag, when set clears the table beforehand 2748 * 2749 * When the clear flag is set, the given list replaces any existing list. 2750 * Hashes the given addresses into the multicast table. 2751 **/ 2752 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, 2753 u32 mc_addr_count, ixgbe_mc_addr_itr next, 2754 bool clear) 2755 { 2756 u32 i; 2757 u32 vmdq; 2758 2759 DEBUGFUNC("ixgbe_update_mc_addr_list_generic"); 2760 2761 /* 2762 * Set the new number of MC addresses that we are being requested to 2763 * use. 2764 */ 2765 hw->addr_ctrl.num_mc_addrs = mc_addr_count; 2766 hw->addr_ctrl.mta_in_use = 0; 2767 2768 /* Clear mta_shadow */ 2769 if (clear) { 2770 DEBUGOUT(" Clearing MTA\n"); 2771 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 2772 } 2773 2774 /* Update mta_shadow */ 2775 for (i = 0; i < mc_addr_count; i++) { 2776 DEBUGOUT(" Adding the multicast addresses:\n"); 2777 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); 2778 } 2779 2780 /* Enable mta */ 2781 for (i = 0; i < hw->mac.mcft_size; i++) 2782 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, 2783 hw->mac.mta_shadow[i]); 2784 2785 if (hw->addr_ctrl.mta_in_use > 0) 2786 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 2787 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 2788 2789 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n"); 2790 return IXGBE_SUCCESS; 2791 } 2792 2793 /** 2794 * ixgbe_enable_mc_generic - Enable multicast address in RAR 2795 * @hw: pointer to hardware structure 2796 * 2797 * Enables multicast address in RAR and the use of the multicast hash table. 2798 **/ 2799 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 2800 { 2801 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2802 2803 DEBUGFUNC("ixgbe_enable_mc_generic"); 2804 2805 if (a->mta_in_use > 0) 2806 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 2807 hw->mac.mc_filter_type); 2808 2809 return IXGBE_SUCCESS; 2810 } 2811 2812 /** 2813 * ixgbe_disable_mc_generic - Disable multicast address in RAR 2814 * @hw: pointer to hardware structure 2815 * 2816 * Disables multicast address in RAR and the use of the multicast hash table. 2817 **/ 2818 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 2819 { 2820 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2821 2822 DEBUGFUNC("ixgbe_disable_mc_generic"); 2823 2824 if (a->mta_in_use > 0) 2825 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2826 2827 return IXGBE_SUCCESS; 2828 } 2829 2830 /** 2831 * ixgbe_fc_enable_generic - Enable flow control 2832 * @hw: pointer to hardware structure 2833 * 2834 * Enable flow control according to the current settings. 2835 **/ 2836 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) 2837 { 2838 s32 ret_val = IXGBE_SUCCESS; 2839 u32 mflcn_reg, fccfg_reg; 2840 u32 reg; 2841 u32 fcrtl, fcrth; 2842 int i; 2843 2844 DEBUGFUNC("ixgbe_fc_enable_generic"); 2845 2846 /* Validate the water mark configuration */ 2847 if (!hw->fc.pause_time) { 2848 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2849 goto out; 2850 } 2851 2852 /* Low water mark of zero causes XOFF floods */ 2853 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 2854 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2855 hw->fc.high_water[i]) { 2856 if (!hw->fc.low_water[i] || 2857 hw->fc.low_water[i] >= hw->fc.high_water[i]) { 2858 DEBUGOUT("Invalid water mark configuration\n"); 2859 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2860 goto out; 2861 } 2862 } 2863 } 2864 2865 /* Negotiate the fc mode to use */ 2866 hw->mac.ops.fc_autoneg(hw); 2867 2868 /* Disable any previous flow control settings */ 2869 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2870 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); 2871 2872 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 2873 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 2874 2875 /* 2876 * The possible values of fc.current_mode are: 2877 * 0: Flow control is completely disabled 2878 * 1: Rx flow control is enabled (we can receive pause frames, 2879 * but not send pause frames). 2880 * 2: Tx flow control is enabled (we can send pause frames but 2881 * we do not support receiving pause frames). 2882 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2883 * other: Invalid. 2884 */ 2885 switch (hw->fc.current_mode) { 2886 case ixgbe_fc_none: 2887 /* 2888 * Flow control is disabled by software override or autoneg. 2889 * The code below will actually disable it in the HW. 2890 */ 2891 break; 2892 case ixgbe_fc_rx_pause: 2893 /* 2894 * Rx Flow control is enabled and Tx Flow control is 2895 * disabled by software override. Since there really 2896 * isn't a way to advertise that we are capable of RX 2897 * Pause ONLY, we will advertise that we support both 2898 * symmetric and asymmetric Rx PAUSE. Later, we will 2899 * disable the adapter's ability to send PAUSE frames. 2900 */ 2901 mflcn_reg |= IXGBE_MFLCN_RFCE; 2902 break; 2903 case ixgbe_fc_tx_pause: 2904 /* 2905 * Tx Flow control is enabled, and Rx Flow control is 2906 * disabled by software override. 2907 */ 2908 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2909 break; 2910 case ixgbe_fc_full: 2911 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2912 mflcn_reg |= IXGBE_MFLCN_RFCE; 2913 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2914 break; 2915 default: 2916 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 2917 "Flow control param set incorrectly\n"); 2918 ret_val = IXGBE_ERR_CONFIG; 2919 goto out; 2920 break; 2921 } 2922 2923 /* Set 802.3x based flow control settings. */ 2924 mflcn_reg |= IXGBE_MFLCN_DPF; 2925 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 2926 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 2927 2928 2929 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 2930 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 2931 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2932 hw->fc.high_water[i]) { 2933 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 2934 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); 2935 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 2936 } else { 2937 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 2938 /* 2939 * In order to prevent Tx hangs when the internal Tx 2940 * switch is enabled we must set the high water mark 2941 * to the Rx packet buffer size - 24KB. This allows 2942 * the Tx switch to function even under heavy Rx 2943 * workloads. 2944 */ 2945 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; 2946 } 2947 2948 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); 2949 } 2950 2951 /* Configure pause time (2 TCs per register) */ 2952 reg = hw->fc.pause_time * 0x00010001; 2953 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 2954 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 2955 2956 /* Configure flow control refresh threshold value */ 2957 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 2958 2959 out: 2960 return ret_val; 2961 } 2962 2963 /** 2964 * ixgbe_negotiate_fc - Negotiate flow control 2965 * @hw: pointer to hardware structure 2966 * @adv_reg: flow control advertised settings 2967 * @lp_reg: link partner's flow control settings 2968 * @adv_sym: symmetric pause bit in advertisement 2969 * @adv_asm: asymmetric pause bit in advertisement 2970 * @lp_sym: symmetric pause bit in link partner advertisement 2971 * @lp_asm: asymmetric pause bit in link partner advertisement 2972 * 2973 * Find the intersection between advertised settings and link partner's 2974 * advertised settings 2975 **/ 2976 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 2977 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) 2978 { 2979 if ((!(adv_reg)) || (!(lp_reg))) { 2980 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED, 2981 "Local or link partner's advertised flow control " 2982 "settings are NULL. Local: %x, link partner: %x\n", 2983 adv_reg, lp_reg); 2984 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2985 } 2986 2987 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) { 2988 /* 2989 * Now we need to check if the user selected Rx ONLY 2990 * of pause frames. In this case, we had to advertise 2991 * FULL flow control because we could not advertise RX 2992 * ONLY. Hence, we must now check to see if we need to 2993 * turn OFF the TRANSMISSION of PAUSE frames. 2994 */ 2995 if (hw->fc.requested_mode == ixgbe_fc_full) { 2996 hw->fc.current_mode = ixgbe_fc_full; 2997 DEBUGOUT("Flow Control = FULL.\n"); 2998 } else { 2999 hw->fc.current_mode = ixgbe_fc_rx_pause; 3000 DEBUGOUT("Flow Control=RX PAUSE frames only\n"); 3001 } 3002 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) && 3003 (lp_reg & lp_sym) && (lp_reg & lp_asm)) { 3004 hw->fc.current_mode = ixgbe_fc_tx_pause; 3005 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 3006 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) && 3007 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) { 3008 hw->fc.current_mode = ixgbe_fc_rx_pause; 3009 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 3010 } else { 3011 hw->fc.current_mode = ixgbe_fc_none; 3012 DEBUGOUT("Flow Control = NONE.\n"); 3013 } 3014 return IXGBE_SUCCESS; 3015 } 3016 3017 /** 3018 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber 3019 * @hw: pointer to hardware structure 3020 * 3021 * Enable flow control according on 1 gig fiber. 3022 **/ 3023 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) 3024 { 3025 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 3026 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 3027 3028 /* 3029 * On multispeed fiber at 1g, bail out if 3030 * - link is up but AN did not complete, or if 3031 * - link is up and AN completed but timed out 3032 */ 3033 3034 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 3035 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 3036 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { 3037 DEBUGOUT("Auto-Negotiation did not complete or timed out\n"); 3038 goto out; 3039 } 3040 3041 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 3042 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 3043 3044 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, 3045 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE, 3046 IXGBE_PCS1GANA_ASM_PAUSE, 3047 IXGBE_PCS1GANA_SYM_PAUSE, 3048 IXGBE_PCS1GANA_ASM_PAUSE); 3049 3050 out: 3051 return ret_val; 3052 } 3053 3054 /** 3055 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37 3056 * @hw: pointer to hardware structure 3057 * 3058 * Enable flow control according to IEEE clause 37. 3059 **/ 3060 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) 3061 { 3062 u32 links2, anlp1_reg, autoc_reg, links; 3063 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 3064 3065 /* 3066 * On backplane, bail out if 3067 * - backplane autoneg was not completed, or if 3068 * - we are 82599 and link partner is not AN enabled 3069 */ 3070 links = IXGBE_READ_REG(hw, IXGBE_LINKS); 3071 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) { 3072 DEBUGOUT("Auto-Negotiation did not complete\n"); 3073 goto out; 3074 } 3075 3076 if (hw->mac.type == ixgbe_mac_82599EB) { 3077 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 3078 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) { 3079 DEBUGOUT("Link partner is not AN enabled\n"); 3080 goto out; 3081 } 3082 } 3083 /* 3084 * Read the 10g AN autoc and LP ability registers and resolve 3085 * local flow control settings accordingly 3086 */ 3087 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 3088 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 3089 3090 ret_val = ixgbe_negotiate_fc(hw, autoc_reg, 3091 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE, 3092 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE); 3093 3094 out: 3095 return ret_val; 3096 } 3097 3098 /** 3099 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37 3100 * @hw: pointer to hardware structure 3101 * 3102 * Enable flow control according to IEEE clause 37. 3103 **/ 3104 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) 3105 { 3106 u16 technology_ability_reg = 0; 3107 u16 lp_technology_ability_reg = 0; 3108 3109 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 3110 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3111 &technology_ability_reg); 3112 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP, 3113 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3114 &lp_technology_ability_reg); 3115 3116 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, 3117 (u32)lp_technology_ability_reg, 3118 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE, 3119 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE); 3120 } 3121 3122 /** 3123 * ixgbe_fc_autoneg - Configure flow control 3124 * @hw: pointer to hardware structure 3125 * 3126 * Compares our advertised flow control capabilities to those advertised by 3127 * our link partner, and determines the proper flow control mode to use. 3128 **/ 3129 void ixgbe_fc_autoneg(struct ixgbe_hw *hw) 3130 { 3131 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 3132 ixgbe_link_speed speed; 3133 bool link_up; 3134 3135 DEBUGFUNC("ixgbe_fc_autoneg"); 3136 3137 /* 3138 * AN should have completed when the cable was plugged in. 3139 * Look for reasons to bail out. Bail out if: 3140 * - FC autoneg is disabled, or if 3141 * - link is not up. 3142 */ 3143 if (hw->fc.disable_fc_autoneg) { 3144 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 3145 "Flow control autoneg is disabled"); 3146 goto out; 3147 } 3148 3149 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 3150 if (!link_up) { 3151 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down"); 3152 goto out; 3153 } 3154 3155 switch (hw->phy.media_type) { 3156 /* Autoneg flow control on fiber adapters */ 3157 case ixgbe_media_type_fiber_fixed: 3158 case ixgbe_media_type_fiber_qsfp: 3159 case ixgbe_media_type_fiber: 3160 if (speed == IXGBE_LINK_SPEED_1GB_FULL) 3161 ret_val = ixgbe_fc_autoneg_fiber(hw); 3162 break; 3163 3164 /* Autoneg flow control on backplane adapters */ 3165 case ixgbe_media_type_backplane: 3166 ret_val = ixgbe_fc_autoneg_backplane(hw); 3167 break; 3168 3169 /* Autoneg flow control on copper adapters */ 3170 case ixgbe_media_type_copper: 3171 if (ixgbe_device_supports_autoneg_fc(hw)) 3172 ret_val = ixgbe_fc_autoneg_copper(hw); 3173 break; 3174 3175 default: 3176 break; 3177 } 3178 3179 out: 3180 if (ret_val == IXGBE_SUCCESS) { 3181 hw->fc.fc_was_autonegged = TRUE; 3182 } else { 3183 hw->fc.fc_was_autonegged = FALSE; 3184 hw->fc.current_mode = hw->fc.requested_mode; 3185 } 3186 } 3187 3188 /* 3189 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion 3190 * @hw: pointer to hardware structure 3191 * 3192 * System-wide timeout range is encoded in PCIe Device Control2 register. 3193 * 3194 * Add 10% to specified maximum and return the number of times to poll for 3195 * completion timeout, in units of 100 microsec. Never return less than 3196 * 800 = 80 millisec. 3197 */ 3198 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) 3199 { 3200 s16 devctl2; 3201 u32 pollcnt; 3202 3203 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2); 3204 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK; 3205 3206 switch (devctl2) { 3207 case IXGBE_PCIDEVCTRL2_65_130ms: 3208 pollcnt = 1300; /* 130 millisec */ 3209 break; 3210 case IXGBE_PCIDEVCTRL2_260_520ms: 3211 pollcnt = 5200; /* 520 millisec */ 3212 break; 3213 case IXGBE_PCIDEVCTRL2_1_2s: 3214 pollcnt = 20000; /* 2 sec */ 3215 break; 3216 case IXGBE_PCIDEVCTRL2_4_8s: 3217 pollcnt = 80000; /* 8 sec */ 3218 break; 3219 case IXGBE_PCIDEVCTRL2_17_34s: 3220 pollcnt = 34000; /* 34 sec */ 3221 break; 3222 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */ 3223 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */ 3224 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */ 3225 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */ 3226 default: 3227 pollcnt = 800; /* 80 millisec minimum */ 3228 break; 3229 } 3230 3231 /* add 10% to spec maximum */ 3232 return (pollcnt * 11) / 10; 3233 } 3234 3235 /** 3236 * ixgbe_disable_pcie_master - Disable PCI-express master access 3237 * @hw: pointer to hardware structure 3238 * 3239 * Disables PCI-Express master access and verifies there are no pending 3240 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 3241 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS 3242 * is returned signifying master requests disabled. 3243 **/ 3244 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 3245 { 3246 s32 status = IXGBE_SUCCESS; 3247 u32 i, poll; 3248 u16 value; 3249 3250 DEBUGFUNC("ixgbe_disable_pcie_master"); 3251 3252 /* Always set this bit to ensure any future transactions are blocked */ 3253 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); 3254 3255 /* Exit if master requests are blocked */ 3256 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || 3257 IXGBE_REMOVED(hw->hw_addr)) 3258 goto out; 3259 3260 /* Poll for master request bit to clear */ 3261 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 3262 usec_delay(100); 3263 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 3264 goto out; 3265 } 3266 3267 /* 3268 * Two consecutive resets are required via CTRL.RST per datasheet 3269 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine 3270 * of this need. The first reset prevents new master requests from 3271 * being issued by our device. We then must wait 1usec or more for any 3272 * remaining completions from the PCIe bus to trickle in, and then reset 3273 * again to clear out any effects they may have had on our device. 3274 */ 3275 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n"); 3276 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 3277 3278 if (hw->mac.type >= ixgbe_mac_X550) 3279 goto out; 3280 3281 /* 3282 * Before proceeding, make sure that the PCIe block does not have 3283 * transactions pending. 3284 */ 3285 poll = ixgbe_pcie_timeout_poll(hw); 3286 for (i = 0; i < poll; i++) { 3287 usec_delay(100); 3288 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); 3289 if (IXGBE_REMOVED(hw->hw_addr)) 3290 goto out; 3291 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 3292 goto out; 3293 } 3294 3295 ERROR_REPORT1(IXGBE_ERROR_POLLING, 3296 "PCIe transaction pending bit also did not clear.\n"); 3297 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 3298 3299 out: 3300 return status; 3301 } 3302 3303 /** 3304 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 3305 * @hw: pointer to hardware structure 3306 * @mask: Mask to specify which semaphore to acquire 3307 * 3308 * Acquires the SWFW semaphore through the GSSR register for the specified 3309 * function (CSR, PHY0, PHY1, EEPROM, Flash) 3310 **/ 3311 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) 3312 { 3313 u32 gssr = 0; 3314 u32 swmask = mask; 3315 u32 fwmask = mask << 5; 3316 u32 timeout = 200; 3317 u32 i; 3318 3319 DEBUGFUNC("ixgbe_acquire_swfw_sync"); 3320 3321 for (i = 0; i < timeout; i++) { 3322 /* 3323 * SW NVM semaphore bit is used for access to all 3324 * SW_FW_SYNC bits (not just NVM) 3325 */ 3326 if (ixgbe_get_eeprom_semaphore(hw)) 3327 return IXGBE_ERR_SWFW_SYNC; 3328 3329 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 3330 if (!(gssr & (fwmask | swmask))) { 3331 gssr |= swmask; 3332 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 3333 ixgbe_release_eeprom_semaphore(hw); 3334 return IXGBE_SUCCESS; 3335 } else { 3336 /* Resource is currently in use by FW or SW */ 3337 ixgbe_release_eeprom_semaphore(hw); 3338 msec_delay(5); 3339 } 3340 } 3341 3342 /* If time expired clear the bits holding the lock and retry */ 3343 if (gssr & (fwmask | swmask)) 3344 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); 3345 3346 msec_delay(5); 3347 return IXGBE_ERR_SWFW_SYNC; 3348 } 3349 3350 /** 3351 * ixgbe_release_swfw_sync - Release SWFW semaphore 3352 * @hw: pointer to hardware structure 3353 * @mask: Mask to specify which semaphore to release 3354 * 3355 * Releases the SWFW semaphore through the GSSR register for the specified 3356 * function (CSR, PHY0, PHY1, EEPROM, Flash) 3357 **/ 3358 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) 3359 { 3360 u32 gssr; 3361 u32 swmask = mask; 3362 3363 DEBUGFUNC("ixgbe_release_swfw_sync"); 3364 3365 ixgbe_get_eeprom_semaphore(hw); 3366 3367 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 3368 gssr &= ~swmask; 3369 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 3370 3371 ixgbe_release_eeprom_semaphore(hw); 3372 } 3373 3374 /** 3375 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path 3376 * @hw: pointer to hardware structure 3377 * 3378 * Stops the receive data path and waits for the HW to internally empty 3379 * the Rx security block 3380 **/ 3381 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw) 3382 { 3383 #define IXGBE_MAX_SECRX_POLL 4000 3384 3385 int i; 3386 int secrxreg; 3387 3388 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic"); 3389 3390 3391 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 3392 secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 3393 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 3394 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 3395 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 3396 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 3397 break; 3398 else 3399 /* Use interrupt-safe sleep just in case */ 3400 usec_delay(10); 3401 } 3402 3403 /* For informational purposes only */ 3404 if (i >= IXGBE_MAX_SECRX_POLL) 3405 DEBUGOUT("Rx unit being enabled before security " 3406 "path fully disabled. Continuing with init.\n"); 3407 3408 return IXGBE_SUCCESS; 3409 } 3410 3411 /** 3412 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read 3413 * @hw: pointer to hardware structure 3414 * @locked: bool to indicate whether the SW/FW lock was taken 3415 * @reg_val: Value we read from AUTOC 3416 * 3417 * The default case requires no protection so just to the register read. 3418 */ 3419 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) 3420 { 3421 *locked = FALSE; 3422 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 3423 return IXGBE_SUCCESS; 3424 } 3425 3426 /** 3427 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write 3428 * @hw: pointer to hardware structure 3429 * @reg_val: value to write to AUTOC 3430 * @locked: bool to indicate whether the SW/FW lock was already taken by 3431 * previous read. 3432 * 3433 * The default case requires no protection so just to the register write. 3434 */ 3435 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) 3436 { 3437 UNREFERENCED_1PARAMETER(locked); 3438 3439 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); 3440 return IXGBE_SUCCESS; 3441 } 3442 3443 /** 3444 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path 3445 * @hw: pointer to hardware structure 3446 * 3447 * Enables the receive data path. 3448 **/ 3449 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw) 3450 { 3451 u32 secrxreg; 3452 3453 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic"); 3454 3455 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 3456 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 3457 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 3458 IXGBE_WRITE_FLUSH(hw); 3459 3460 return IXGBE_SUCCESS; 3461 } 3462 3463 /** 3464 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 3465 * @hw: pointer to hardware structure 3466 * @regval: register value to write to RXCTRL 3467 * 3468 * Enables the Rx DMA unit 3469 **/ 3470 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 3471 { 3472 DEBUGFUNC("ixgbe_enable_rx_dma_generic"); 3473 3474 if (regval & IXGBE_RXCTRL_RXEN) 3475 ixgbe_enable_rx(hw); 3476 else 3477 ixgbe_disable_rx(hw); 3478 3479 return IXGBE_SUCCESS; 3480 } 3481 3482 /** 3483 * ixgbe_blink_led_start_generic - Blink LED based on index. 3484 * @hw: pointer to hardware structure 3485 * @index: led number to blink 3486 **/ 3487 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 3488 { 3489 ixgbe_link_speed speed = 0; 3490 bool link_up = 0; 3491 u32 autoc_reg = 0; 3492 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 3493 s32 ret_val = IXGBE_SUCCESS; 3494 bool locked = FALSE; 3495 3496 DEBUGFUNC("ixgbe_blink_led_start_generic"); 3497 3498 if (index > 3) 3499 return IXGBE_ERR_PARAM; 3500 3501 /* 3502 * Link must be up to auto-blink the LEDs; 3503 * Force it if link is down. 3504 */ 3505 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 3506 3507 if (!link_up) { 3508 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 3509 if (ret_val != IXGBE_SUCCESS) 3510 goto out; 3511 3512 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 3513 autoc_reg |= IXGBE_AUTOC_FLU; 3514 3515 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 3516 if (ret_val != IXGBE_SUCCESS) 3517 goto out; 3518 3519 IXGBE_WRITE_FLUSH(hw); 3520 msec_delay(10); 3521 } 3522 3523 led_reg &= ~IXGBE_LED_MODE_MASK(index); 3524 led_reg |= IXGBE_LED_BLINK(index); 3525 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 3526 IXGBE_WRITE_FLUSH(hw); 3527 3528 out: 3529 return ret_val; 3530 } 3531 3532 /** 3533 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 3534 * @hw: pointer to hardware structure 3535 * @index: led number to stop blinking 3536 **/ 3537 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 3538 { 3539 u32 autoc_reg = 0; 3540 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 3541 s32 ret_val = IXGBE_SUCCESS; 3542 bool locked = FALSE; 3543 3544 DEBUGFUNC("ixgbe_blink_led_stop_generic"); 3545 3546 if (index > 3) 3547 return IXGBE_ERR_PARAM; 3548 3549 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 3550 if (ret_val != IXGBE_SUCCESS) 3551 goto out; 3552 3553 autoc_reg &= ~IXGBE_AUTOC_FLU; 3554 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 3555 3556 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 3557 if (ret_val != IXGBE_SUCCESS) 3558 goto out; 3559 3560 led_reg &= ~IXGBE_LED_MODE_MASK(index); 3561 led_reg &= ~IXGBE_LED_BLINK(index); 3562 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 3563 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 3564 IXGBE_WRITE_FLUSH(hw); 3565 3566 out: 3567 return ret_val; 3568 } 3569 3570 /** 3571 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM 3572 * @hw: pointer to hardware structure 3573 * @san_mac_offset: SAN MAC address offset 3574 * 3575 * This function will read the EEPROM location for the SAN MAC address 3576 * pointer, and returns the value at that location. This is used in both 3577 * get and set mac_addr routines. 3578 **/ 3579 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 3580 u16 *san_mac_offset) 3581 { 3582 s32 ret_val; 3583 3584 DEBUGFUNC("ixgbe_get_san_mac_addr_offset"); 3585 3586 /* 3587 * First read the EEPROM pointer to see if the MAC addresses are 3588 * available. 3589 */ 3590 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, 3591 san_mac_offset); 3592 if (ret_val) { 3593 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 3594 "eeprom at offset %d failed", 3595 IXGBE_SAN_MAC_ADDR_PTR); 3596 } 3597 3598 return ret_val; 3599 } 3600 3601 /** 3602 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM 3603 * @hw: pointer to hardware structure 3604 * @san_mac_addr: SAN MAC address 3605 * 3606 * Reads the SAN MAC address from the EEPROM, if it's available. This is 3607 * per-port, so set_lan_id() must be called before reading the addresses. 3608 * set_lan_id() is called by identify_sfp(), but this cannot be relied 3609 * upon for non-SFP connections, so we must call it here. 3610 **/ 3611 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 3612 { 3613 u16 san_mac_data, san_mac_offset; 3614 u8 i; 3615 s32 ret_val; 3616 3617 DEBUGFUNC("ixgbe_get_san_mac_addr_generic"); 3618 3619 /* 3620 * First read the EEPROM pointer to see if the MAC addresses are 3621 * available. If they're not, no point in calling set_lan_id() here. 3622 */ 3623 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 3624 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 3625 goto san_mac_addr_out; 3626 3627 /* make sure we know which port we need to program */ 3628 hw->mac.ops.set_lan_id(hw); 3629 /* apply the port offset to the address offset */ 3630 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 3631 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 3632 for (i = 0; i < 3; i++) { 3633 ret_val = hw->eeprom.ops.read(hw, san_mac_offset, 3634 &san_mac_data); 3635 if (ret_val) { 3636 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 3637 "eeprom read at offset %d failed", 3638 san_mac_offset); 3639 goto san_mac_addr_out; 3640 } 3641 san_mac_addr[i * 2] = (u8)(san_mac_data); 3642 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 3643 san_mac_offset++; 3644 } 3645 return IXGBE_SUCCESS; 3646 3647 san_mac_addr_out: 3648 /* 3649 * No addresses available in this EEPROM. It's not an 3650 * error though, so just wipe the local address and return. 3651 */ 3652 for (i = 0; i < 6; i++) 3653 san_mac_addr[i] = 0xFF; 3654 return IXGBE_SUCCESS; 3655 } 3656 3657 /** 3658 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM 3659 * @hw: pointer to hardware structure 3660 * @san_mac_addr: SAN MAC address 3661 * 3662 * Write a SAN MAC address to the EEPROM. 3663 **/ 3664 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 3665 { 3666 s32 ret_val; 3667 u16 san_mac_data, san_mac_offset; 3668 u8 i; 3669 3670 DEBUGFUNC("ixgbe_set_san_mac_addr_generic"); 3671 3672 /* Look for SAN mac address pointer. If not defined, return */ 3673 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 3674 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 3675 return IXGBE_ERR_NO_SAN_ADDR_PTR; 3676 3677 /* Make sure we know which port we need to write */ 3678 hw->mac.ops.set_lan_id(hw); 3679 /* Apply the port offset to the address offset */ 3680 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 3681 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 3682 3683 for (i = 0; i < 3; i++) { 3684 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8); 3685 san_mac_data |= (u16)(san_mac_addr[i * 2]); 3686 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data); 3687 san_mac_offset++; 3688 } 3689 3690 return IXGBE_SUCCESS; 3691 } 3692 3693 /** 3694 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count 3695 * @hw: pointer to hardware structure 3696 * 3697 * Read PCIe configuration space, and get the MSI-X vector count from 3698 * the capabilities table. 3699 **/ 3700 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) 3701 { 3702 u16 msix_count = 1; 3703 u16 max_msix_count; 3704 u16 pcie_offset; 3705 3706 switch (hw->mac.type) { 3707 case ixgbe_mac_82598EB: 3708 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS; 3709 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598; 3710 break; 3711 case ixgbe_mac_82599EB: 3712 case ixgbe_mac_X540: 3713 case ixgbe_mac_X550: 3714 case ixgbe_mac_X550EM_x: 3715 case ixgbe_mac_X550EM_a: 3716 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS; 3717 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; 3718 break; 3719 default: 3720 return msix_count; 3721 } 3722 3723 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic"); 3724 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset); 3725 if (IXGBE_REMOVED(hw->hw_addr)) 3726 msix_count = 0; 3727 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 3728 3729 /* MSI-X count is zero-based in HW */ 3730 msix_count++; 3731 3732 if (msix_count > max_msix_count) 3733 msix_count = max_msix_count; 3734 3735 return msix_count; 3736 } 3737 3738 /** 3739 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address 3740 * @hw: pointer to hardware structure 3741 * @addr: Address to put into receive address register 3742 * @vmdq: VMDq pool to assign 3743 * 3744 * Puts an ethernet address into a receive address register, or 3745 * finds the rar that it is already in; adds to the pool list 3746 **/ 3747 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 3748 { 3749 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF; 3750 u32 first_empty_rar = NO_EMPTY_RAR_FOUND; 3751 u32 rar; 3752 u32 rar_low, rar_high; 3753 u32 addr_low, addr_high; 3754 3755 DEBUGFUNC("ixgbe_insert_mac_addr_generic"); 3756 3757 /* swap bytes for HW little endian */ 3758 addr_low = addr[0] | (addr[1] << 8) 3759 | (addr[2] << 16) 3760 | (addr[3] << 24); 3761 addr_high = addr[4] | (addr[5] << 8); 3762 3763 /* 3764 * Either find the mac_id in rar or find the first empty space. 3765 * rar_highwater points to just after the highest currently used 3766 * rar in order to shorten the search. It grows when we add a new 3767 * rar to the top. 3768 */ 3769 for (rar = 0; rar < hw->mac.rar_highwater; rar++) { 3770 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 3771 3772 if (((IXGBE_RAH_AV & rar_high) == 0) 3773 && first_empty_rar == NO_EMPTY_RAR_FOUND) { 3774 first_empty_rar = rar; 3775 } else if ((rar_high & 0xFFFF) == addr_high) { 3776 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar)); 3777 if (rar_low == addr_low) 3778 break; /* found it already in the rars */ 3779 } 3780 } 3781 3782 if (rar < hw->mac.rar_highwater) { 3783 /* already there so just add to the pool bits */ 3784 ixgbe_set_vmdq(hw, rar, vmdq); 3785 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) { 3786 /* stick it into first empty RAR slot we found */ 3787 rar = first_empty_rar; 3788 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 3789 } else if (rar == hw->mac.rar_highwater) { 3790 /* add it to the top of the list and inc the highwater mark */ 3791 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 3792 hw->mac.rar_highwater++; 3793 } else if (rar >= hw->mac.num_rar_entries) { 3794 return IXGBE_ERR_INVALID_MAC_ADDR; 3795 } 3796 3797 /* 3798 * If we found rar[0], make sure the default pool bit (we use pool 0) 3799 * remains cleared to be sure default pool packets will get delivered 3800 */ 3801 if (rar == 0) 3802 ixgbe_clear_vmdq(hw, rar, 0); 3803 3804 return rar; 3805 } 3806 3807 /** 3808 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address 3809 * @hw: pointer to hardware struct 3810 * @rar: receive address register index to disassociate 3811 * @vmdq: VMDq pool index to remove from the rar 3812 **/ 3813 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3814 { 3815 u32 mpsar_lo, mpsar_hi; 3816 u32 rar_entries = hw->mac.num_rar_entries; 3817 3818 DEBUGFUNC("ixgbe_clear_vmdq_generic"); 3819 3820 /* Make sure we are using a valid rar index range */ 3821 if (rar >= rar_entries) { 3822 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 3823 "RAR index %d is out of range.\n", rar); 3824 return IXGBE_ERR_INVALID_ARGUMENT; 3825 } 3826 3827 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3828 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3829 3830 if (IXGBE_REMOVED(hw->hw_addr)) 3831 goto done; 3832 3833 if (!mpsar_lo && !mpsar_hi) 3834 goto done; 3835 3836 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 3837 if (mpsar_lo) { 3838 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3839 mpsar_lo = 0; 3840 } 3841 if (mpsar_hi) { 3842 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3843 mpsar_hi = 0; 3844 } 3845 } else if (vmdq < 32) { 3846 mpsar_lo &= ~(1 << vmdq); 3847 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 3848 } else { 3849 mpsar_hi &= ~(1 << (vmdq - 32)); 3850 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 3851 } 3852 3853 /* was that the last pool using this rar? */ 3854 if (mpsar_lo == 0 && mpsar_hi == 0 && 3855 rar != 0 && rar != hw->mac.san_mac_rar_index) 3856 hw->mac.ops.clear_rar(hw, rar); 3857 done: 3858 return IXGBE_SUCCESS; 3859 } 3860 3861 /** 3862 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 3863 * @hw: pointer to hardware struct 3864 * @rar: receive address register index to associate with a VMDq index 3865 * @vmdq: VMDq pool index 3866 **/ 3867 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3868 { 3869 u32 mpsar; 3870 u32 rar_entries = hw->mac.num_rar_entries; 3871 3872 DEBUGFUNC("ixgbe_set_vmdq_generic"); 3873 3874 /* Make sure we are using a valid rar index range */ 3875 if (rar >= rar_entries) { 3876 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 3877 "RAR index %d is out of range.\n", rar); 3878 return IXGBE_ERR_INVALID_ARGUMENT; 3879 } 3880 3881 if (vmdq < 32) { 3882 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3883 mpsar |= 1 << vmdq; 3884 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 3885 } else { 3886 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3887 mpsar |= 1 << (vmdq - 32); 3888 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 3889 } 3890 return IXGBE_SUCCESS; 3891 } 3892 3893 /** 3894 * This function should only be involved in the IOV mode. 3895 * In IOV mode, Default pool is next pool after the number of 3896 * VFs advertized and not 0. 3897 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index] 3898 * 3899 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address 3900 * @hw: pointer to hardware struct 3901 * @vmdq: VMDq pool index 3902 **/ 3903 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) 3904 { 3905 u32 rar = hw->mac.san_mac_rar_index; 3906 3907 DEBUGFUNC("ixgbe_set_vmdq_san_mac"); 3908 3909 if (vmdq < 32) { 3910 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq); 3911 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3912 } else { 3913 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3914 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32)); 3915 } 3916 3917 return IXGBE_SUCCESS; 3918 } 3919 3920 /** 3921 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array 3922 * @hw: pointer to hardware structure 3923 **/ 3924 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 3925 { 3926 int i; 3927 3928 DEBUGFUNC("ixgbe_init_uta_tables_generic"); 3929 DEBUGOUT(" Clearing UTA\n"); 3930 3931 for (i = 0; i < 128; i++) 3932 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 3933 3934 return IXGBE_SUCCESS; 3935 } 3936 3937 /** 3938 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 3939 * @hw: pointer to hardware structure 3940 * @vlan: VLAN id to write to VLAN filter 3941 * @vlvf_bypass: TRUE to find vlanid only, FALSE returns first empty slot if 3942 * vlanid not found 3943 * 3944 * 3945 * return the VLVF index where this VLAN id should be placed 3946 * 3947 **/ 3948 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass) 3949 { 3950 s32 regindex, first_empty_slot; 3951 u32 bits; 3952 3953 /* short cut the special case */ 3954 if (vlan == 0) 3955 return 0; 3956 3957 /* if vlvf_bypass is set we don't want to use an empty slot, we 3958 * will simply bypass the VLVF if there are no entries present in the 3959 * VLVF that contain our VLAN 3960 */ 3961 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0; 3962 3963 /* add VLAN enable bit for comparison */ 3964 vlan |= IXGBE_VLVF_VIEN; 3965 3966 /* Search for the vlan id in the VLVF entries. Save off the first empty 3967 * slot found along the way. 3968 * 3969 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1 3970 */ 3971 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) { 3972 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 3973 if (bits == vlan) 3974 return regindex; 3975 if (!first_empty_slot && !bits) 3976 first_empty_slot = regindex; 3977 } 3978 3979 /* If we are here then we didn't find the VLAN. Return first empty 3980 * slot we found during our search, else error. 3981 */ 3982 if (!first_empty_slot) 3983 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "No space in VLVF.\n"); 3984 3985 return first_empty_slot ? first_empty_slot : IXGBE_ERR_NO_SPACE; 3986 } 3987 3988 /** 3989 * ixgbe_set_vfta_generic - Set VLAN filter table 3990 * @hw: pointer to hardware structure 3991 * @vlan: VLAN id to write to VLAN filter 3992 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 3993 * @vlan_on: boolean flag to turn on/off VLAN 3994 * @vlvf_bypass: boolean flag indicating updating default pool is okay 3995 * 3996 * Turn on/off specified VLAN in the VLAN filter table. 3997 **/ 3998 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 3999 bool vlan_on, bool vlvf_bypass) 4000 { 4001 u32 regidx, vfta_delta, vfta; 4002 s32 ret_val; 4003 4004 DEBUGFUNC("ixgbe_set_vfta_generic"); 4005 4006 if (vlan > 4095 || vind > 63) 4007 return IXGBE_ERR_PARAM; 4008 4009 /* 4010 * this is a 2 part operation - first the VFTA, then the 4011 * VLVF and VLVFB if VT Mode is set 4012 * We don't write the VFTA until we know the VLVF part succeeded. 4013 */ 4014 4015 /* Part 1 4016 * The VFTA is a bitstring made up of 128 32-bit registers 4017 * that enable the particular VLAN id, much like the MTA: 4018 * bits[11-5]: which register 4019 * bits[4-0]: which bit in the register 4020 */ 4021 regidx = vlan / 32; 4022 vfta_delta = 1 << (vlan % 32); 4023 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx)); 4024 4025 /* 4026 * vfta_delta represents the difference between the current value 4027 * of vfta and the value we want in the register. Since the diff 4028 * is an XOR mask we can just update the vfta using an XOR 4029 */ 4030 vfta_delta &= vlan_on ? ~vfta : vfta; 4031 vfta ^= vfta_delta; 4032 4033 /* Part 2 4034 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF 4035 */ 4036 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta, 4037 vfta, vlvf_bypass); 4038 if (ret_val != IXGBE_SUCCESS) { 4039 if (vlvf_bypass) 4040 goto vfta_update; 4041 return ret_val; 4042 } 4043 4044 vfta_update: 4045 /* Update VFTA now that we are ready for traffic */ 4046 if (vfta_delta) 4047 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); 4048 4049 return IXGBE_SUCCESS; 4050 } 4051 4052 /** 4053 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter 4054 * @hw: pointer to hardware structure 4055 * @vlan: VLAN id to write to VLAN filter 4056 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 4057 * @vlan_on: boolean flag to turn on/off VLAN in VLVF 4058 * @vfta_delta: pointer to the difference between the current value of VFTA 4059 * and the desired value 4060 * @vfta: the desired value of the VFTA 4061 * @vlvf_bypass: boolean flag indicating updating default pool is okay 4062 * 4063 * Turn on/off specified bit in VLVF table. 4064 **/ 4065 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 4066 bool vlan_on, u32 *vfta_delta, u32 vfta, 4067 bool vlvf_bypass) 4068 { 4069 u32 bits; 4070 s32 vlvf_index; 4071 4072 DEBUGFUNC("ixgbe_set_vlvf_generic"); 4073 4074 if (vlan > 4095 || vind > 63) 4075 return IXGBE_ERR_PARAM; 4076 4077 /* If VT Mode is set 4078 * Either vlan_on 4079 * make sure the vlan is in VLVF 4080 * set the vind bit in the matching VLVFB 4081 * Or !vlan_on 4082 * clear the pool bit and possibly the vind 4083 */ 4084 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE)) 4085 return IXGBE_SUCCESS; 4086 4087 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass); 4088 if (vlvf_index < 0) 4089 return vlvf_index; 4090 4091 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32)); 4092 4093 /* set the pool bit */ 4094 bits |= 1 << (vind % 32); 4095 if (vlan_on) 4096 goto vlvf_update; 4097 4098 /* clear the pool bit */ 4099 bits ^= 1 << (vind % 32); 4100 4101 if (!bits && 4102 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) { 4103 /* Clear VFTA first, then disable VLVF. Otherwise 4104 * we run the risk of stray packets leaking into 4105 * the PF via the default pool 4106 */ 4107 if (*vfta_delta) 4108 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta); 4109 4110 /* disable VLVF and clear remaining bit from pool */ 4111 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); 4112 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0); 4113 4114 return IXGBE_SUCCESS; 4115 } 4116 4117 /* If there are still bits set in the VLVFB registers 4118 * for the VLAN ID indicated we need to see if the 4119 * caller is requesting that we clear the VFTA entry bit. 4120 * If the caller has requested that we clear the VFTA 4121 * entry bit but there are still pools/VFs using this VLAN 4122 * ID entry then ignore the request. We're not worried 4123 * about the case where we're turning the VFTA VLAN ID 4124 * entry bit on, only when requested to turn it off as 4125 * there may be multiple pools and/or VFs using the 4126 * VLAN ID entry. In that case we cannot clear the 4127 * VFTA bit until all pools/VFs using that VLAN ID have also 4128 * been cleared. This will be indicated by "bits" being 4129 * zero. 4130 */ 4131 *vfta_delta = 0; 4132 4133 vlvf_update: 4134 /* record pool change and enable VLAN ID if not already enabled */ 4135 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits); 4136 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan); 4137 4138 return IXGBE_SUCCESS; 4139 } 4140 4141 /** 4142 * ixgbe_clear_vfta_generic - Clear VLAN filter table 4143 * @hw: pointer to hardware structure 4144 * 4145 * Clears the VLAN filer table, and the VMDq index associated with the filter 4146 **/ 4147 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 4148 { 4149 u32 offset; 4150 4151 DEBUGFUNC("ixgbe_clear_vfta_generic"); 4152 4153 for (offset = 0; offset < hw->mac.vft_size; offset++) 4154 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 4155 4156 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 4157 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 4158 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); 4159 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0); 4160 } 4161 4162 return IXGBE_SUCCESS; 4163 } 4164 4165 /** 4166 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix 4167 * @hw: pointer to hardware structure 4168 * 4169 * Contains the logic to identify if we need to verify link for the 4170 * crosstalk fix 4171 **/ 4172 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw) 4173 { 4174 4175 /* Does FW say we need the fix */ 4176 if (!hw->need_crosstalk_fix) 4177 return FALSE; 4178 4179 /* Only consider SFP+ PHYs i.e. media type fiber */ 4180 switch (hw->mac.ops.get_media_type(hw)) { 4181 case ixgbe_media_type_fiber: 4182 case ixgbe_media_type_fiber_qsfp: 4183 break; 4184 default: 4185 return FALSE; 4186 } 4187 4188 return TRUE; 4189 } 4190 4191 /** 4192 * ixgbe_check_mac_link_generic - Determine link and speed status 4193 * @hw: pointer to hardware structure 4194 * @speed: pointer to link speed 4195 * @link_up: TRUE when link is up 4196 * @link_up_wait_to_complete: bool used to wait for link up or not 4197 * 4198 * Reads the links register to determine if link is up and the current speed 4199 **/ 4200 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 4201 bool *link_up, bool link_up_wait_to_complete) 4202 { 4203 u32 links_reg, links_orig; 4204 u32 i; 4205 4206 DEBUGFUNC("ixgbe_check_mac_link_generic"); 4207 4208 /* If Crosstalk fix enabled do the sanity check of making sure 4209 * the SFP+ cage is full. 4210 */ 4211 if (ixgbe_need_crosstalk_fix(hw)) { 4212 u32 sfp_cage_full; 4213 4214 switch (hw->mac.type) { 4215 case ixgbe_mac_82599EB: 4216 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 4217 IXGBE_ESDP_SDP2; 4218 break; 4219 case ixgbe_mac_X550EM_x: 4220 case ixgbe_mac_X550EM_a: 4221 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 4222 IXGBE_ESDP_SDP0; 4223 break; 4224 default: 4225 /* sanity check - No SFP+ devices here */ 4226 sfp_cage_full = FALSE; 4227 break; 4228 } 4229 4230 if (!sfp_cage_full) { 4231 *link_up = FALSE; 4232 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4233 return IXGBE_SUCCESS; 4234 } 4235 } 4236 4237 /* clear the old state */ 4238 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); 4239 4240 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4241 4242 if (links_orig != links_reg) { 4243 DEBUGOUT2("LINKS changed from %08X to %08X\n", 4244 links_orig, links_reg); 4245 } 4246 4247 if (link_up_wait_to_complete) { 4248 for (i = 0; i < hw->mac.max_link_up_time; i++) { 4249 if (links_reg & IXGBE_LINKS_UP) { 4250 *link_up = TRUE; 4251 break; 4252 } else { 4253 *link_up = FALSE; 4254 } 4255 msec_delay(100); 4256 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4257 } 4258 } else { 4259 if (links_reg & IXGBE_LINKS_UP) 4260 *link_up = TRUE; 4261 else 4262 *link_up = FALSE; 4263 } 4264 4265 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 4266 case IXGBE_LINKS_SPEED_10G_82599: 4267 *speed = IXGBE_LINK_SPEED_10GB_FULL; 4268 if (hw->mac.type >= ixgbe_mac_X550) { 4269 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4270 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 4271 } 4272 break; 4273 case IXGBE_LINKS_SPEED_1G_82599: 4274 *speed = IXGBE_LINK_SPEED_1GB_FULL; 4275 break; 4276 case IXGBE_LINKS_SPEED_100_82599: 4277 *speed = IXGBE_LINK_SPEED_100_FULL; 4278 if (hw->mac.type >= ixgbe_mac_X550) { 4279 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4280 *speed = IXGBE_LINK_SPEED_5GB_FULL; 4281 } 4282 break; 4283 case IXGBE_LINKS_SPEED_10_X550EM_A: 4284 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4285 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 4286 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) 4287 *speed = IXGBE_LINK_SPEED_10_FULL; 4288 break; 4289 default: 4290 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4291 } 4292 4293 return IXGBE_SUCCESS; 4294 } 4295 4296 /** 4297 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from 4298 * the EEPROM 4299 * @hw: pointer to hardware structure 4300 * @wwnn_prefix: the alternative WWNN prefix 4301 * @wwpn_prefix: the alternative WWPN prefix 4302 * 4303 * This function will read the EEPROM from the alternative SAN MAC address 4304 * block to check the support for the alternative WWNN/WWPN prefix support. 4305 **/ 4306 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 4307 u16 *wwpn_prefix) 4308 { 4309 u16 offset, caps; 4310 u16 alt_san_mac_blk_offset; 4311 4312 DEBUGFUNC("ixgbe_get_wwn_prefix_generic"); 4313 4314 /* clear output first */ 4315 *wwnn_prefix = 0xFFFF; 4316 *wwpn_prefix = 0xFFFF; 4317 4318 /* check if alternative SAN MAC is supported */ 4319 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR; 4320 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) 4321 goto wwn_prefix_err; 4322 4323 if ((alt_san_mac_blk_offset == 0) || 4324 (alt_san_mac_blk_offset == 0xFFFF)) 4325 goto wwn_prefix_out; 4326 4327 /* check capability in alternative san mac address block */ 4328 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 4329 if (hw->eeprom.ops.read(hw, offset, &caps)) 4330 goto wwn_prefix_err; 4331 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) 4332 goto wwn_prefix_out; 4333 4334 /* get the corresponding prefix for WWNN/WWPN */ 4335 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 4336 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) { 4337 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 4338 "eeprom read at offset %d failed", offset); 4339 } 4340 4341 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 4342 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) 4343 goto wwn_prefix_err; 4344 4345 wwn_prefix_out: 4346 return IXGBE_SUCCESS; 4347 4348 wwn_prefix_err: 4349 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 4350 "eeprom read at offset %d failed", offset); 4351 return IXGBE_SUCCESS; 4352 } 4353 4354 /** 4355 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM 4356 * @hw: pointer to hardware structure 4357 * @bs: the fcoe boot status 4358 * 4359 * This function will read the FCOE boot status from the iSCSI FCOE block 4360 **/ 4361 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs) 4362 { 4363 u16 offset, caps, flags; 4364 s32 status; 4365 4366 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic"); 4367 4368 /* clear output first */ 4369 *bs = ixgbe_fcoe_bootstatus_unavailable; 4370 4371 /* check if FCOE IBA block is present */ 4372 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR; 4373 status = hw->eeprom.ops.read(hw, offset, &caps); 4374 if (status != IXGBE_SUCCESS) 4375 goto out; 4376 4377 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE)) 4378 goto out; 4379 4380 /* check if iSCSI FCOE block is populated */ 4381 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset); 4382 if (status != IXGBE_SUCCESS) 4383 goto out; 4384 4385 if ((offset == 0) || (offset == 0xFFFF)) 4386 goto out; 4387 4388 /* read fcoe flags in iSCSI FCOE block */ 4389 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET; 4390 status = hw->eeprom.ops.read(hw, offset, &flags); 4391 if (status != IXGBE_SUCCESS) 4392 goto out; 4393 4394 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE) 4395 *bs = ixgbe_fcoe_bootstatus_enabled; 4396 else 4397 *bs = ixgbe_fcoe_bootstatus_disabled; 4398 4399 out: 4400 return status; 4401 } 4402 4403 /** 4404 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing 4405 * @hw: pointer to hardware structure 4406 * @enable: enable or disable switch for MAC anti-spoofing 4407 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing 4408 * 4409 **/ 4410 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 4411 { 4412 int vf_target_reg = vf >> 3; 4413 int vf_target_shift = vf % 8; 4414 u32 pfvfspoof; 4415 4416 if (hw->mac.type == ixgbe_mac_82598EB) 4417 return; 4418 4419 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 4420 if (enable) 4421 pfvfspoof |= (1 << vf_target_shift); 4422 else 4423 pfvfspoof &= ~(1 << vf_target_shift); 4424 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 4425 } 4426 4427 /** 4428 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing 4429 * @hw: pointer to hardware structure 4430 * @enable: enable or disable switch for VLAN anti-spoofing 4431 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing 4432 * 4433 **/ 4434 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 4435 { 4436 int vf_target_reg = vf >> 3; 4437 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT; 4438 u32 pfvfspoof; 4439 4440 if (hw->mac.type == ixgbe_mac_82598EB) 4441 return; 4442 4443 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 4444 if (enable) 4445 pfvfspoof |= (1 << vf_target_shift); 4446 else 4447 pfvfspoof &= ~(1 << vf_target_shift); 4448 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 4449 } 4450 4451 /** 4452 * ixgbe_get_device_caps_generic - Get additional device capabilities 4453 * @hw: pointer to hardware structure 4454 * @device_caps: the EEPROM word with the extra device capabilities 4455 * 4456 * This function will read the EEPROM location for the device capabilities, 4457 * and return the word through device_caps. 4458 **/ 4459 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) 4460 { 4461 DEBUGFUNC("ixgbe_get_device_caps_generic"); 4462 4463 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); 4464 4465 return IXGBE_SUCCESS; 4466 } 4467 4468 /** 4469 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering 4470 * @hw: pointer to hardware structure 4471 * 4472 **/ 4473 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw) 4474 { 4475 u32 regval; 4476 u32 i; 4477 4478 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2"); 4479 4480 /* Enable relaxed ordering */ 4481 for (i = 0; i < hw->mac.max_tx_queues; i++) { 4482 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 4483 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN; 4484 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 4485 } 4486 4487 for (i = 0; i < hw->mac.max_rx_queues; i++) { 4488 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 4489 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN | 4490 IXGBE_DCA_RXCTRL_HEAD_WRO_EN; 4491 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 4492 } 4493 4494 } 4495 4496 /** 4497 * ixgbe_calculate_checksum - Calculate checksum for buffer 4498 * @buffer: pointer to EEPROM 4499 * @length: size of EEPROM to calculate a checksum for 4500 * Calculates the checksum for some buffer on a specified length. The 4501 * checksum calculated is returned. 4502 **/ 4503 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length) 4504 { 4505 u32 i; 4506 u8 sum = 0; 4507 4508 DEBUGFUNC("ixgbe_calculate_checksum"); 4509 4510 if (!buffer) 4511 return 0; 4512 4513 for (i = 0; i < length; i++) 4514 sum += buffer[i]; 4515 4516 return (u8) (0 - sum); 4517 } 4518 4519 /** 4520 * ixgbe_hic_unlocked - Issue command to manageability block unlocked 4521 * @hw: pointer to the HW structure 4522 * @buffer: command to write and where the return status will be placed 4523 * @length: length of buffer, must be multiple of 4 bytes 4524 * @timeout: time in ms to wait for command completion 4525 * 4526 * Communicates with the manageability block. On success return IXGBE_SUCCESS 4527 * else returns semaphore error when encountering an error acquiring 4528 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4529 * 4530 * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held 4531 * by the caller. 4532 **/ 4533 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length, 4534 u32 timeout) 4535 { 4536 u32 hicr, i, fwsts; 4537 u16 dword_len; 4538 4539 DEBUGFUNC("ixgbe_hic_unlocked"); 4540 4541 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 4542 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length); 4543 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4544 } 4545 4546 /* Set bit 9 of FWSTS clearing FW reset indication */ 4547 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); 4548 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); 4549 4550 /* Check that the host interface is enabled. */ 4551 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 4552 if (!(hicr & IXGBE_HICR_EN)) { 4553 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n"); 4554 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4555 } 4556 4557 /* Calculate length in DWORDs. We must be DWORD aligned */ 4558 if (length % sizeof(u32)) { 4559 DEBUGOUT("Buffer length failure, not aligned to dword"); 4560 return IXGBE_ERR_INVALID_ARGUMENT; 4561 } 4562 4563 dword_len = length >> 2; 4564 4565 /* The device driver writes the relevant command block 4566 * into the ram area. 4567 */ 4568 for (i = 0; i < dword_len; i++) 4569 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, 4570 i, IXGBE_CPU_TO_LE32(buffer[i])); 4571 4572 /* Setting this bit tells the ARC that a new command is pending. */ 4573 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); 4574 4575 for (i = 0; i < timeout; i++) { 4576 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 4577 if (!(hicr & IXGBE_HICR_C)) 4578 break; 4579 msec_delay(1); 4580 } 4581 4582 /* Check command completion */ 4583 if ((timeout && i == timeout) || 4584 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) { 4585 ERROR_REPORT1(IXGBE_ERROR_CAUTION, 4586 "Command has failed with no status valid.\n"); 4587 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4588 } 4589 4590 return IXGBE_SUCCESS; 4591 } 4592 4593 /** 4594 * ixgbe_host_interface_command - Issue command to manageability block 4595 * @hw: pointer to the HW structure 4596 * @buffer: contains the command to write and where the return status will 4597 * be placed 4598 * @length: length of buffer, must be multiple of 4 bytes 4599 * @timeout: time in ms to wait for command completion 4600 * @return_data: read and return data from the buffer (TRUE) or not (FALSE) 4601 * Needed because FW structures are big endian and decoding of 4602 * these fields can be 8 bit or 16 bit based on command. Decoding 4603 * is not easily understood without making a table of commands. 4604 * So we will leave this up to the caller to read back the data 4605 * in these cases. 4606 * 4607 * Communicates with the manageability block. On success return IXGBE_SUCCESS 4608 * else returns semaphore error when encountering an error acquiring 4609 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4610 **/ 4611 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, 4612 u32 length, u32 timeout, bool return_data) 4613 { 4614 u32 hdr_size = sizeof(struct ixgbe_hic_hdr); 4615 struct ixgbe_hic_hdr *resp = (struct ixgbe_hic_hdr *)buffer; 4616 u16 buf_len; 4617 s32 status; 4618 u32 bi; 4619 u32 dword_len; 4620 4621 DEBUGFUNC("ixgbe_host_interface_command"); 4622 4623 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 4624 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length); 4625 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4626 } 4627 4628 /* Take management host interface semaphore */ 4629 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 4630 if (status) 4631 return status; 4632 4633 status = ixgbe_hic_unlocked(hw, buffer, length, timeout); 4634 if (status) 4635 goto rel_out; 4636 4637 if (!return_data) 4638 goto rel_out; 4639 4640 /* Calculate length in DWORDs */ 4641 dword_len = hdr_size >> 2; 4642 4643 /* first pull in the header so we know the buffer length */ 4644 for (bi = 0; bi < dword_len; bi++) { 4645 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 4646 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4647 } 4648 4649 /* 4650 * If there is any thing in data position pull it in 4651 * Read Flash command requires reading buffer length from 4652 * two byes instead of one byte 4653 */ 4654 if (resp->cmd == 0x30) { 4655 for (; bi < dword_len + 2; bi++) { 4656 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, 4657 bi); 4658 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4659 } 4660 buf_len = (((u16)(resp->cmd_or_resp.ret_status) << 3) 4661 & 0xF00) | resp->buf_len; 4662 hdr_size += (2 << 2); 4663 } else { 4664 buf_len = resp->buf_len; 4665 } 4666 if (!buf_len) 4667 goto rel_out; 4668 4669 if (length < buf_len + hdr_size) { 4670 DEBUGOUT("Buffer not large enough for reply message.\n"); 4671 status = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4672 goto rel_out; 4673 } 4674 4675 /* Calculate length in DWORDs, add 3 for odd lengths */ 4676 dword_len = (buf_len + 3) >> 2; 4677 4678 /* Pull in the rest of the buffer (bi is where we left off) */ 4679 for (; bi <= dword_len; bi++) { 4680 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 4681 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4682 } 4683 4684 rel_out: 4685 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 4686 4687 return status; 4688 } 4689 4690 /** 4691 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware 4692 * @hw: pointer to the HW structure 4693 * @maj: driver version major number 4694 * @minr: driver version minor number 4695 * @build: driver version build number 4696 * @sub: driver version sub build number 4697 * @len: unused 4698 * @driver_ver: unused 4699 * 4700 * Sends driver version number to firmware through the manageability 4701 * block. On success return IXGBE_SUCCESS 4702 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 4703 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4704 **/ 4705 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 minr, 4706 u8 build, u8 sub, u16 len, 4707 const char *driver_ver) 4708 { 4709 struct ixgbe_hic_drv_info fw_cmd; 4710 int i; 4711 s32 ret_val = IXGBE_SUCCESS; 4712 4713 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic"); 4714 UNREFERENCED_2PARAMETER(len, driver_ver); 4715 4716 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 4717 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN; 4718 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 4719 fw_cmd.port_num = (u8)hw->bus.func; 4720 fw_cmd.ver_maj = maj; 4721 fw_cmd.ver_min = minr; 4722 fw_cmd.ver_build = build; 4723 fw_cmd.ver_sub = sub; 4724 fw_cmd.hdr.checksum = 0; 4725 fw_cmd.pad = 0; 4726 fw_cmd.pad2 = 0; 4727 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 4728 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 4729 4730 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 4731 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 4732 sizeof(fw_cmd), 4733 IXGBE_HI_COMMAND_TIMEOUT, 4734 TRUE); 4735 if (ret_val != IXGBE_SUCCESS) 4736 continue; 4737 4738 if (fw_cmd.hdr.cmd_or_resp.ret_status == 4739 FW_CEM_RESP_STATUS_SUCCESS) 4740 ret_val = IXGBE_SUCCESS; 4741 else 4742 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4743 4744 break; 4745 } 4746 4747 return ret_val; 4748 } 4749 4750 /** 4751 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer 4752 * @hw: pointer to hardware structure 4753 * @num_pb: number of packet buffers to allocate 4754 * @headroom: reserve n KB of headroom 4755 * @strategy: packet buffer allocation strategy 4756 **/ 4757 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom, 4758 int strategy) 4759 { 4760 u32 pbsize = hw->mac.rx_pb_size; 4761 int i = 0; 4762 u32 rxpktsize, txpktsize, txpbthresh; 4763 4764 /* Reserve headroom */ 4765 pbsize -= headroom; 4766 4767 if (!num_pb) 4768 num_pb = 1; 4769 4770 /* Divide remaining packet buffer space amongst the number of packet 4771 * buffers requested using supplied strategy. 4772 */ 4773 switch (strategy) { 4774 case PBA_STRATEGY_WEIGHTED: 4775 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet 4776 * buffer with 5/8 of the packet buffer space. 4777 */ 4778 rxpktsize = (pbsize * 5) / (num_pb * 4); 4779 pbsize -= rxpktsize * (num_pb / 2); 4780 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT; 4781 for (; i < (num_pb / 2); i++) 4782 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4783 /* fall through - configure remaining packet buffers */ 4784 case PBA_STRATEGY_EQUAL: 4785 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; 4786 for (; i < num_pb; i++) 4787 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4788 break; 4789 default: 4790 break; 4791 } 4792 4793 /* Only support an equally distributed Tx packet buffer strategy. */ 4794 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb; 4795 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX; 4796 for (i = 0; i < num_pb; i++) { 4797 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); 4798 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); 4799 } 4800 4801 /* Clear unused TCs, if any, to zero buffer size*/ 4802 for (; i < IXGBE_MAX_PB; i++) { 4803 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 4804 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); 4805 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); 4806 } 4807 } 4808 4809 /** 4810 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo 4811 * @hw: pointer to the hardware structure 4812 * 4813 * The 82599 and x540 MACs can experience issues if TX work is still pending 4814 * when a reset occurs. This function prevents this by flushing the PCIe 4815 * buffers on the system. 4816 **/ 4817 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) 4818 { 4819 u32 gcr_ext, hlreg0, i, poll; 4820 u16 value; 4821 4822 /* 4823 * If double reset is not requested then all transactions should 4824 * already be clear and as such there is no work to do 4825 */ 4826 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) 4827 return; 4828 4829 /* 4830 * Set loopback enable to prevent any transmits from being sent 4831 * should the link come up. This assumes that the RXCTRL.RXEN bit 4832 * has already been cleared. 4833 */ 4834 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4835 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); 4836 4837 /* Wait for a last completion before clearing buffers */ 4838 IXGBE_WRITE_FLUSH(hw); 4839 msec_delay(3); 4840 4841 /* 4842 * Before proceeding, make sure that the PCIe block does not have 4843 * transactions pending. 4844 */ 4845 poll = ixgbe_pcie_timeout_poll(hw); 4846 for (i = 0; i < poll; i++) { 4847 usec_delay(100); 4848 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); 4849 if (IXGBE_REMOVED(hw->hw_addr)) 4850 goto out; 4851 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 4852 goto out; 4853 } 4854 4855 out: 4856 /* initiate cleaning flow for buffers in the PCIe transaction layer */ 4857 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 4858 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, 4859 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR); 4860 4861 /* Flush all writes and allow 20usec for all transactions to clear */ 4862 IXGBE_WRITE_FLUSH(hw); 4863 usec_delay(20); 4864 4865 /* restore previous register values */ 4866 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4867 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4868 } 4869 4870 /** 4871 * ixgbe_bypass_rw_generic - Bit bang data into by_pass FW 4872 * 4873 * @hw: pointer to hardware structure 4874 * @cmd: Command we send to the FW 4875 * @status: The reply from the FW 4876 * 4877 * Bit-bangs the cmd to the by_pass FW status points to what is returned. 4878 **/ 4879 #define IXGBE_BYPASS_BB_WAIT 1 4880 s32 ixgbe_bypass_rw_generic(struct ixgbe_hw *hw, u32 cmd, u32 *status) 4881 { 4882 int i; 4883 u32 sck, sdi, sdo, dir_sck, dir_sdi, dir_sdo; 4884 u32 esdp; 4885 4886 if (!status) 4887 return IXGBE_ERR_PARAM; 4888 4889 *status = 0; 4890 4891 /* SDP vary by MAC type */ 4892 switch (hw->mac.type) { 4893 case ixgbe_mac_82599EB: 4894 sck = IXGBE_ESDP_SDP7; 4895 sdi = IXGBE_ESDP_SDP0; 4896 sdo = IXGBE_ESDP_SDP6; 4897 dir_sck = IXGBE_ESDP_SDP7_DIR; 4898 dir_sdi = IXGBE_ESDP_SDP0_DIR; 4899 dir_sdo = IXGBE_ESDP_SDP6_DIR; 4900 break; 4901 case ixgbe_mac_X540: 4902 sck = IXGBE_ESDP_SDP2; 4903 sdi = IXGBE_ESDP_SDP0; 4904 sdo = IXGBE_ESDP_SDP1; 4905 dir_sck = IXGBE_ESDP_SDP2_DIR; 4906 dir_sdi = IXGBE_ESDP_SDP0_DIR; 4907 dir_sdo = IXGBE_ESDP_SDP1_DIR; 4908 break; 4909 default: 4910 return IXGBE_ERR_DEVICE_NOT_SUPPORTED; 4911 } 4912 4913 /* Set SDP pins direction */ 4914 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 4915 esdp |= dir_sck; /* SCK as output */ 4916 esdp |= dir_sdi; /* SDI as output */ 4917 esdp &= ~dir_sdo; /* SDO as input */ 4918 esdp |= sck; 4919 esdp |= sdi; 4920 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4921 IXGBE_WRITE_FLUSH(hw); 4922 msec_delay(IXGBE_BYPASS_BB_WAIT); 4923 4924 /* Generate start condition */ 4925 esdp &= ~sdi; 4926 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4927 IXGBE_WRITE_FLUSH(hw); 4928 msec_delay(IXGBE_BYPASS_BB_WAIT); 4929 4930 esdp &= ~sck; 4931 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4932 IXGBE_WRITE_FLUSH(hw); 4933 msec_delay(IXGBE_BYPASS_BB_WAIT); 4934 4935 /* Clock out the new control word and clock in the status */ 4936 for (i = 0; i < 32; i++) { 4937 if ((cmd >> (31 - i)) & 0x01) { 4938 esdp |= sdi; 4939 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4940 } else { 4941 esdp &= ~sdi; 4942 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4943 } 4944 IXGBE_WRITE_FLUSH(hw); 4945 msec_delay(IXGBE_BYPASS_BB_WAIT); 4946 4947 esdp |= sck; 4948 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4949 IXGBE_WRITE_FLUSH(hw); 4950 msec_delay(IXGBE_BYPASS_BB_WAIT); 4951 4952 esdp &= ~sck; 4953 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4954 IXGBE_WRITE_FLUSH(hw); 4955 msec_delay(IXGBE_BYPASS_BB_WAIT); 4956 4957 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 4958 if (esdp & sdo) 4959 *status = (*status << 1) | 0x01; 4960 else 4961 *status = (*status << 1) | 0x00; 4962 msec_delay(IXGBE_BYPASS_BB_WAIT); 4963 } 4964 4965 /* stop condition */ 4966 esdp |= sck; 4967 esdp &= ~sdi; 4968 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4969 IXGBE_WRITE_FLUSH(hw); 4970 msec_delay(IXGBE_BYPASS_BB_WAIT); 4971 4972 esdp |= sdi; 4973 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4974 IXGBE_WRITE_FLUSH(hw); 4975 4976 /* set the page bits to match the cmd that the status it belongs to */ 4977 *status = (*status & 0x3fffffff) | (cmd & 0xc0000000); 4978 4979 return IXGBE_SUCCESS; 4980 } 4981 4982 /** 4983 * ixgbe_bypass_valid_rd_generic - Verify valid return from bit-bang. 4984 * 4985 * If we send a write we can't be sure it took until we can read back 4986 * that same register. It can be a problem as some of the feilds may 4987 * for valid reasons change inbetween the time wrote the register and 4988 * we read it again to verify. So this function check everything we 4989 * can check and then assumes it worked. 4990 * 4991 * @u32 in_reg - The register cmd for the bit-bang read. 4992 * @u32 out_reg - The register returned from a bit-bang read. 4993 **/ 4994 bool ixgbe_bypass_valid_rd_generic(u32 in_reg, u32 out_reg) 4995 { 4996 u32 mask; 4997 4998 /* Page must match for all control pages */ 4999 if ((in_reg & BYPASS_PAGE_M) != (out_reg & BYPASS_PAGE_M)) 5000 return FALSE; 5001 5002 switch (in_reg & BYPASS_PAGE_M) { 5003 case BYPASS_PAGE_CTL0: 5004 /* All the following can't change since the last write 5005 * - All the event actions 5006 * - The timeout value 5007 */ 5008 mask = BYPASS_AUX_ON_M | BYPASS_MAIN_ON_M | 5009 BYPASS_MAIN_OFF_M | BYPASS_AUX_OFF_M | 5010 BYPASS_WDTIMEOUT_M | 5011 BYPASS_WDT_VALUE_M; 5012 if ((out_reg & mask) != (in_reg & mask)) 5013 return FALSE; 5014 5015 /* 0x0 is never a valid value for bypass status */ 5016 if (!(out_reg & BYPASS_STATUS_OFF_M)) 5017 return FALSE; 5018 break; 5019 case BYPASS_PAGE_CTL1: 5020 /* All the following can't change since the last write 5021 * - time valid bit 5022 * - time we last sent 5023 */ 5024 mask = BYPASS_CTL1_VALID_M | BYPASS_CTL1_TIME_M; 5025 if ((out_reg & mask) != (in_reg & mask)) 5026 return FALSE; 5027 break; 5028 case BYPASS_PAGE_CTL2: 5029 /* All we can check in this page is control number 5030 * which is already done above. 5031 */ 5032 break; 5033 } 5034 5035 /* We are as sure as we can be return TRUE */ 5036 return TRUE; 5037 } 5038 5039 /** 5040 * ixgbe_bypass_set_generic - Set a bypass field in the FW CTRL Regiter. 5041 * 5042 * @hw: pointer to hardware structure 5043 * @cmd: The control word we are setting. 5044 * @event: The event we are setting in the FW. This also happens to 5045 * be the mask for the event we are setting (handy) 5046 * @action: The action we set the event to in the FW. This is in a 5047 * bit field that happens to be what we want to put in 5048 * the event spot (also handy) 5049 **/ 5050 s32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event, 5051 u32 action) 5052 { 5053 u32 by_ctl = 0; 5054 u32 cmd, verify; 5055 u32 count = 0; 5056 5057 /* Get current values */ 5058 cmd = ctrl; /* just reading only need control number */ 5059 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl)) 5060 return IXGBE_ERR_INVALID_ARGUMENT; 5061 5062 /* Set to new action */ 5063 cmd = (by_ctl & ~event) | BYPASS_WE | action; 5064 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl)) 5065 return IXGBE_ERR_INVALID_ARGUMENT; 5066 5067 /* Page 0 force a FW eeprom write which is slow so verify */ 5068 if ((cmd & BYPASS_PAGE_M) == BYPASS_PAGE_CTL0) { 5069 verify = BYPASS_PAGE_CTL0; 5070 do { 5071 if (count++ > 5) 5072 return IXGBE_BYPASS_FW_WRITE_FAILURE; 5073 5074 if (ixgbe_bypass_rw_generic(hw, verify, &by_ctl)) 5075 return IXGBE_ERR_INVALID_ARGUMENT; 5076 } while (!ixgbe_bypass_valid_rd_generic(cmd, by_ctl)); 5077 } else { 5078 /* We have give the FW time for the write to stick */ 5079 msec_delay(100); 5080 } 5081 5082 return IXGBE_SUCCESS; 5083 } 5084 5085 /** 5086 * ixgbe_bypass_rd_eep_generic - Read the bypass FW eeprom addres. 5087 * 5088 * @hw: pointer to hardware structure 5089 * @addr: The bypass eeprom address to read. 5090 * @value: The 8b of data at the address above. 5091 **/ 5092 s32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw *hw, u32 addr, u8 *value) 5093 { 5094 u32 cmd; 5095 u32 status; 5096 5097 5098 /* send the request */ 5099 cmd = BYPASS_PAGE_CTL2 | BYPASS_WE; 5100 cmd |= (addr << BYPASS_CTL2_OFFSET_SHIFT) & BYPASS_CTL2_OFFSET_M; 5101 if (ixgbe_bypass_rw_generic(hw, cmd, &status)) 5102 return IXGBE_ERR_INVALID_ARGUMENT; 5103 5104 /* We have give the FW time for the write to stick */ 5105 msec_delay(100); 5106 5107 /* now read the results */ 5108 cmd &= ~BYPASS_WE; 5109 if (ixgbe_bypass_rw_generic(hw, cmd, &status)) 5110 return IXGBE_ERR_INVALID_ARGUMENT; 5111 5112 *value = status & BYPASS_CTL2_DATA_M; 5113 5114 return IXGBE_SUCCESS; 5115 } 5116 5117 /** 5118 * ixgbe_get_orom_version - Return option ROM from EEPROM 5119 * 5120 * @hw: pointer to hardware structure 5121 * @nvm_ver: pointer to output structure 5122 * 5123 * if valid option ROM version, nvm_ver->or_valid set to TRUE 5124 * else nvm_ver->or_valid is FALSE. 5125 **/ 5126 void ixgbe_get_orom_version(struct ixgbe_hw *hw, 5127 struct ixgbe_nvm_version *nvm_ver) 5128 { 5129 u16 offset, eeprom_cfg_blkh, eeprom_cfg_blkl; 5130 5131 nvm_ver->or_valid = FALSE; 5132 /* Option Rom may or may not be present. Start with pointer */ 5133 hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset); 5134 5135 /* make sure offset is valid */ 5136 if ((offset == 0x0) || (offset == NVM_INVALID_PTR)) 5137 return; 5138 5139 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh); 5140 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl); 5141 5142 /* option rom exists and is valid */ 5143 if ((eeprom_cfg_blkl | eeprom_cfg_blkh) == 0x0 || 5144 eeprom_cfg_blkl == NVM_VER_INVALID || 5145 eeprom_cfg_blkh == NVM_VER_INVALID) 5146 return; 5147 5148 nvm_ver->or_valid = TRUE; 5149 nvm_ver->or_major = eeprom_cfg_blkl >> NVM_OROM_SHIFT; 5150 nvm_ver->or_build = (eeprom_cfg_blkl << NVM_OROM_SHIFT) | 5151 (eeprom_cfg_blkh >> NVM_OROM_SHIFT); 5152 nvm_ver->or_patch = eeprom_cfg_blkh & NVM_OROM_PATCH_MASK; 5153 } 5154 5155 /** 5156 * ixgbe_get_oem_prod_version - Return OEM Product version 5157 * 5158 * @hw: pointer to hardware structure 5159 * @nvm_ver: pointer to output structure 5160 * 5161 * if valid OEM product version, nvm_ver->oem_valid set to TRUE 5162 * else nvm_ver->oem_valid is FALSE. 5163 **/ 5164 void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw, 5165 struct ixgbe_nvm_version *nvm_ver) 5166 { 5167 u16 rel_num, prod_ver, mod_len, cap, offset; 5168 5169 nvm_ver->oem_valid = FALSE; 5170 hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset); 5171 5172 /* Return is offset to OEM Product Version block is invalid */ 5173 if (offset == 0x0 || offset == NVM_INVALID_PTR) 5174 return; 5175 5176 /* Read product version block */ 5177 hw->eeprom.ops.read(hw, offset, &mod_len); 5178 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap); 5179 5180 /* Return if OEM product version block is invalid */ 5181 if (mod_len != NVM_OEM_PROD_VER_MOD_LEN || 5182 (cap & NVM_OEM_PROD_VER_CAP_MASK) != 0x0) 5183 return; 5184 5185 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver); 5186 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num); 5187 5188 /* Return if version is invalid */ 5189 if ((rel_num | prod_ver) == 0x0 || 5190 rel_num == NVM_VER_INVALID || prod_ver == NVM_VER_INVALID) 5191 return; 5192 5193 nvm_ver->oem_major = prod_ver >> NVM_VER_SHIFT; 5194 nvm_ver->oem_minor = prod_ver & NVM_VER_MASK; 5195 nvm_ver->oem_release = rel_num; 5196 nvm_ver->oem_valid = TRUE; 5197 } 5198 5199 /** 5200 * ixgbe_get_etk_id - Return Etrack ID from EEPROM 5201 * 5202 * @hw: pointer to hardware structure 5203 * @nvm_ver: pointer to output structure 5204 * 5205 * word read errors will return 0xFFFF 5206 **/ 5207 void ixgbe_get_etk_id(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver) 5208 { 5209 u16 etk_id_l, etk_id_h; 5210 5211 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l)) 5212 etk_id_l = NVM_VER_INVALID; 5213 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h)) 5214 etk_id_h = NVM_VER_INVALID; 5215 5216 /* The word order for the version format is determined by high order 5217 * word bit 15. 5218 */ 5219 if ((etk_id_h & NVM_ETK_VALID) == 0) { 5220 nvm_ver->etk_id = etk_id_h; 5221 nvm_ver->etk_id |= (etk_id_l << NVM_ETK_SHIFT); 5222 } else { 5223 nvm_ver->etk_id = etk_id_l; 5224 nvm_ver->etk_id |= (etk_id_h << NVM_ETK_SHIFT); 5225 } 5226 } 5227 5228 5229 /** 5230 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg 5231 * @hw: pointer to hardware structure 5232 * @map: pointer to u8 arr for returning map 5233 * 5234 * Read the rtrup2tc HW register and resolve its content into map 5235 **/ 5236 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map) 5237 { 5238 u32 reg, i; 5239 5240 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 5241 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++) 5242 map[i] = IXGBE_RTRUP2TC_UP_MASK & 5243 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT)); 5244 return; 5245 } 5246 5247 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw) 5248 { 5249 u32 pfdtxgswc; 5250 u32 rxctrl; 5251 5252 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 5253 if (rxctrl & IXGBE_RXCTRL_RXEN) { 5254 if (hw->mac.type != ixgbe_mac_82598EB) { 5255 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 5256 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 5257 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 5258 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 5259 hw->mac.set_lben = TRUE; 5260 } else { 5261 hw->mac.set_lben = FALSE; 5262 } 5263 } 5264 rxctrl &= ~IXGBE_RXCTRL_RXEN; 5265 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 5266 } 5267 } 5268 5269 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw) 5270 { 5271 u32 pfdtxgswc; 5272 u32 rxctrl; 5273 5274 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 5275 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN)); 5276 5277 if (hw->mac.type != ixgbe_mac_82598EB) { 5278 if (hw->mac.set_lben) { 5279 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 5280 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN; 5281 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 5282 hw->mac.set_lben = FALSE; 5283 } 5284 } 5285 } 5286 5287 /** 5288 * ixgbe_mng_present - returns TRUE when management capability is present 5289 * @hw: pointer to hardware structure 5290 */ 5291 bool ixgbe_mng_present(struct ixgbe_hw *hw) 5292 { 5293 u32 fwsm; 5294 5295 if (hw->mac.type < ixgbe_mac_82599EB) 5296 return FALSE; 5297 5298 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)); 5299 return !!(fwsm & IXGBE_FWSM_FW_MODE_PT); 5300 } 5301 5302 /** 5303 * ixgbe_mng_enabled - Is the manageability engine enabled? 5304 * @hw: pointer to hardware structure 5305 * 5306 * Returns TRUE if the manageability engine is enabled. 5307 **/ 5308 bool ixgbe_mng_enabled(struct ixgbe_hw *hw) 5309 { 5310 u32 fwsm, manc, factps; 5311 5312 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)); 5313 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) 5314 return FALSE; 5315 5316 manc = IXGBE_READ_REG(hw, IXGBE_MANC); 5317 if (!(manc & IXGBE_MANC_RCV_TCO_EN)) 5318 return FALSE; 5319 5320 if (hw->mac.type <= ixgbe_mac_X540) { 5321 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw)); 5322 if (factps & IXGBE_FACTPS_MNGCG) 5323 return FALSE; 5324 } 5325 5326 return TRUE; 5327 } 5328 5329 /** 5330 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 5331 * @hw: pointer to hardware structure 5332 * @speed: new link speed 5333 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 5334 * 5335 * Set the link speed in the MAC and/or PHY register and restarts link. 5336 **/ 5337 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 5338 ixgbe_link_speed speed, 5339 bool autoneg_wait_to_complete) 5340 { 5341 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 5342 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 5343 s32 status = IXGBE_SUCCESS; 5344 u32 speedcnt = 0; 5345 u32 i = 0; 5346 bool autoneg, link_up = FALSE; 5347 5348 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber"); 5349 5350 /* Mask off requested but non-supported speeds */ 5351 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg); 5352 if (status != IXGBE_SUCCESS) 5353 return status; 5354 5355 speed &= link_speed; 5356 5357 /* Try each speed one by one, highest priority first. We do this in 5358 * software because 10Gb fiber doesn't support speed autonegotiation. 5359 */ 5360 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 5361 speedcnt++; 5362 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 5363 5364 /* Set the module link speed */ 5365 switch (hw->phy.media_type) { 5366 case ixgbe_media_type_fiber_fixed: 5367 case ixgbe_media_type_fiber: 5368 ixgbe_set_rate_select_speed(hw, 5369 IXGBE_LINK_SPEED_10GB_FULL); 5370 break; 5371 case ixgbe_media_type_fiber_qsfp: 5372 /* QSFP module automatically detects MAC link speed */ 5373 break; 5374 default: 5375 DEBUGOUT("Unexpected media type.\n"); 5376 break; 5377 } 5378 5379 /* Allow module to change analog characteristics (1G->10G) */ 5380 msec_delay(40); 5381 5382 status = ixgbe_setup_mac_link(hw, 5383 IXGBE_LINK_SPEED_10GB_FULL, 5384 autoneg_wait_to_complete); 5385 if (status != IXGBE_SUCCESS) 5386 return status; 5387 5388 /* Flap the Tx laser if it has not already been done */ 5389 ixgbe_flap_tx_laser(hw); 5390 5391 /* Wait for the controller to acquire link. Per IEEE 802.3ap, 5392 * Section 73.10.2, we may have to wait up to 500ms if KR is 5393 * attempted. 82599 uses the same timing for 10g SFI. 5394 */ 5395 for (i = 0; i < 5; i++) { 5396 /* Wait for the link partner to also set speed */ 5397 msec_delay(100); 5398 5399 /* If we have link, just jump out */ 5400 status = ixgbe_check_link(hw, &link_speed, 5401 &link_up, FALSE); 5402 if (status != IXGBE_SUCCESS) 5403 return status; 5404 5405 if (link_up) 5406 goto out; 5407 } 5408 } 5409 5410 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 5411 speedcnt++; 5412 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 5413 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 5414 5415 /* Set the module link speed */ 5416 switch (hw->phy.media_type) { 5417 case ixgbe_media_type_fiber_fixed: 5418 case ixgbe_media_type_fiber: 5419 ixgbe_set_rate_select_speed(hw, 5420 IXGBE_LINK_SPEED_1GB_FULL); 5421 break; 5422 case ixgbe_media_type_fiber_qsfp: 5423 /* QSFP module automatically detects link speed */ 5424 break; 5425 default: 5426 DEBUGOUT("Unexpected media type.\n"); 5427 break; 5428 } 5429 5430 /* Allow module to change analog characteristics (10G->1G) */ 5431 msec_delay(40); 5432 5433 status = ixgbe_setup_mac_link(hw, 5434 IXGBE_LINK_SPEED_1GB_FULL, 5435 autoneg_wait_to_complete); 5436 if (status != IXGBE_SUCCESS) 5437 return status; 5438 5439 /* Flap the Tx laser if it has not already been done */ 5440 ixgbe_flap_tx_laser(hw); 5441 5442 /* Wait for the link partner to also set speed */ 5443 msec_delay(100); 5444 5445 /* If we have link, just jump out */ 5446 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 5447 if (status != IXGBE_SUCCESS) 5448 return status; 5449 5450 if (link_up) 5451 goto out; 5452 } 5453 5454 if (speed == 0) { 5455 /* Disable the Tx laser for media none */ 5456 ixgbe_disable_tx_laser(hw); 5457 5458 goto out; 5459 } 5460 5461 /* We didn't get link. Configure back to the highest speed we tried, 5462 * (if there was more than one). We call ourselves back with just the 5463 * single highest speed that the user requested. 5464 */ 5465 if (speedcnt > 1) 5466 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 5467 highest_link_speed, 5468 autoneg_wait_to_complete); 5469 5470 out: 5471 /* Set autoneg_advertised value based on input link speed */ 5472 hw->phy.autoneg_advertised = 0; 5473 5474 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 5475 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 5476 5477 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 5478 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 5479 5480 return status; 5481 } 5482 5483 /** 5484 * ixgbe_set_soft_rate_select_speed - Set module link speed 5485 * @hw: pointer to hardware structure 5486 * @speed: link speed to set 5487 * 5488 * Set module link speed via the soft rate select. 5489 */ 5490 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, 5491 ixgbe_link_speed speed) 5492 { 5493 s32 status; 5494 u8 rs, eeprom_data; 5495 5496 switch (speed) { 5497 case IXGBE_LINK_SPEED_10GB_FULL: 5498 /* one bit mask same as setting on */ 5499 rs = IXGBE_SFF_SOFT_RS_SELECT_10G; 5500 break; 5501 case IXGBE_LINK_SPEED_1GB_FULL: 5502 rs = IXGBE_SFF_SOFT_RS_SELECT_1G; 5503 break; 5504 default: 5505 DEBUGOUT("Invalid fixed module speed\n"); 5506 return; 5507 } 5508 5509 /* Set RS0 */ 5510 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 5511 IXGBE_I2C_EEPROM_DEV_ADDR2, 5512 &eeprom_data); 5513 if (status) { 5514 DEBUGOUT("Failed to read Rx Rate Select RS0\n"); 5515 goto out; 5516 } 5517 5518 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 5519 5520 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 5521 IXGBE_I2C_EEPROM_DEV_ADDR2, 5522 eeprom_data); 5523 if (status) { 5524 DEBUGOUT("Failed to write Rx Rate Select RS0\n"); 5525 goto out; 5526 } 5527 5528 /* Set RS1 */ 5529 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 5530 IXGBE_I2C_EEPROM_DEV_ADDR2, 5531 &eeprom_data); 5532 if (status) { 5533 DEBUGOUT("Failed to read Rx Rate Select RS1\n"); 5534 goto out; 5535 } 5536 5537 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 5538 5539 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 5540 IXGBE_I2C_EEPROM_DEV_ADDR2, 5541 eeprom_data); 5542 if (status) { 5543 DEBUGOUT("Failed to write Rx Rate Select RS1\n"); 5544 goto out; 5545 } 5546 out: 5547 return; 5548 } 5549