1 /****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_common.c,v 1.12 2011/01/19 19:36:27 jfv Exp $*/ 34 /*$NetBSD: ixgbe_common.c,v 1.2 2014/04/17 15:33:40 christos Exp $*/ 35 36 #include "ixgbe_common.h" 37 #include "ixgbe_phy.h" 38 #include "ixgbe_api.h" 39 40 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 41 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 42 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 43 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 44 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 45 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 46 u16 count); 47 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 48 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 49 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 50 static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 51 52 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 53 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 54 u16 *san_mac_offset); 55 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw); 56 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw); 57 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw); 58 static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw); 59 static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 60 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm); 61 62 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan); 63 64 /** 65 * ixgbe_init_ops_generic - Inits function ptrs 66 * @hw: pointer to the hardware structure 67 * 68 * Initialize the function pointers. 69 **/ 70 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw) 71 { 72 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 73 struct ixgbe_mac_info *mac = &hw->mac; 74 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 75 76 DEBUGFUNC("ixgbe_init_ops_generic"); 77 78 /* EEPROM */ 79 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic; 80 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ 81 if (eec & (1 << 8)) 82 eeprom->ops.read = &ixgbe_read_eerd_generic; 83 else 84 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic; 85 eeprom->ops.write = &ixgbe_write_eeprom_generic; 86 eeprom->ops.validate_checksum = 87 &ixgbe_validate_eeprom_checksum_generic; 88 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic; 89 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic; 90 91 /* MAC */ 92 mac->ops.init_hw = &ixgbe_init_hw_generic; 93 mac->ops.reset_hw = NULL; 94 mac->ops.start_hw = &ixgbe_start_hw_generic; 95 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic; 96 mac->ops.get_media_type = NULL; 97 mac->ops.get_supported_physical_layer = NULL; 98 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic; 99 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic; 100 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic; 101 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic; 102 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie; 103 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync; 104 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync; 105 106 /* LEDs */ 107 mac->ops.led_on = &ixgbe_led_on_generic; 108 mac->ops.led_off = &ixgbe_led_off_generic; 109 mac->ops.blink_led_start = &ixgbe_blink_led_start_generic; 110 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic; 111 112 /* RAR, Multicast, VLAN */ 113 mac->ops.set_rar = &ixgbe_set_rar_generic; 114 mac->ops.clear_rar = &ixgbe_clear_rar_generic; 115 mac->ops.insert_mac_addr = NULL; 116 mac->ops.set_vmdq = NULL; 117 mac->ops.clear_vmdq = NULL; 118 mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic; 119 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic; 120 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic; 121 mac->ops.enable_mc = &ixgbe_enable_mc_generic; 122 mac->ops.disable_mc = &ixgbe_disable_mc_generic; 123 mac->ops.clear_vfta = NULL; 124 mac->ops.set_vfta = NULL; 125 mac->ops.init_uta_tables = NULL; 126 127 /* Flow Control */ 128 mac->ops.fc_enable = &ixgbe_fc_enable_generic; 129 130 /* Link */ 131 mac->ops.get_link_capabilities = NULL; 132 mac->ops.setup_link = NULL; 133 mac->ops.check_link = NULL; 134 135 return IXGBE_SUCCESS; 136 } 137 138 /** 139 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 140 * @hw: pointer to hardware structure 141 * 142 * Starts the hardware by filling the bus info structure and media type, clears 143 * all on chip counters, initializes receive address registers, multicast 144 * table, VLAN filter table, calls routine to set up link and flow control 145 * settings, and leaves transmit and receive units disabled and uninitialized 146 **/ 147 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 148 { 149 u32 ctrl_ext; 150 151 DEBUGFUNC("ixgbe_start_hw_generic"); 152 153 /* Set the media type */ 154 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 155 156 /* PHY ops initialization must be done in reset_hw() */ 157 158 /* Clear the VLAN filter table */ 159 hw->mac.ops.clear_vfta(hw); 160 161 /* Clear statistics registers */ 162 hw->mac.ops.clear_hw_cntrs(hw); 163 164 /* Set No Snoop Disable */ 165 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 166 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 167 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 168 IXGBE_WRITE_FLUSH(hw); 169 170 /* Setup flow control */ 171 ixgbe_setup_fc(hw, 0); 172 173 /* Clear adapter stopped flag */ 174 hw->adapter_stopped = FALSE; 175 176 return IXGBE_SUCCESS; 177 } 178 179 /** 180 * ixgbe_start_hw_gen2 - Init sequence for common device family 181 * @hw: pointer to hw structure 182 * 183 * Performs the init sequence common to the second generation 184 * of 10 GbE devices. 185 * Devices in the second generation: 186 * 82599 187 * X540 188 **/ 189 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 190 { 191 u32 i; 192 u32 regval; 193 194 /* Clear the rate limiters */ 195 for (i = 0; i < hw->mac.max_tx_queues; i++) { 196 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 197 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); 198 } 199 IXGBE_WRITE_FLUSH(hw); 200 201 /* Disable relaxed ordering */ 202 for (i = 0; i < hw->mac.max_tx_queues; i++) { 203 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 204 regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN; 205 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 206 } 207 208 for (i = 0; i < hw->mac.max_rx_queues; i++) { 209 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 210 regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN | 211 IXGBE_DCA_RXCTRL_DESC_HSRO_EN); 212 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 213 } 214 215 return IXGBE_SUCCESS; 216 } 217 218 /** 219 * ixgbe_init_hw_generic - Generic hardware initialization 220 * @hw: pointer to hardware structure 221 * 222 * Initialize the hardware by resetting the hardware, filling the bus info 223 * structure and media type, clears all on chip counters, initializes receive 224 * address registers, multicast table, VLAN filter table, calls routine to set 225 * up link and flow control settings, and leaves transmit and receive units 226 * disabled and uninitialized 227 **/ 228 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 229 { 230 s32 status; 231 232 DEBUGFUNC("ixgbe_init_hw_generic"); 233 234 /* Reset the hardware */ 235 status = hw->mac.ops.reset_hw(hw); 236 237 if (status == IXGBE_SUCCESS) { 238 /* Start the HW */ 239 status = hw->mac.ops.start_hw(hw); 240 } 241 242 return status; 243 } 244 245 /** 246 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 247 * @hw: pointer to hardware structure 248 * 249 * Clears all hardware statistics counters by reading them from the hardware 250 * Statistics counters are clear on read. 251 **/ 252 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 253 { 254 u16 i = 0; 255 256 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic"); 257 258 IXGBE_READ_REG(hw, IXGBE_CRCERRS); 259 IXGBE_READ_REG(hw, IXGBE_ILLERRC); 260 IXGBE_READ_REG(hw, IXGBE_ERRBC); 261 IXGBE_READ_REG(hw, IXGBE_MSPDC); 262 for (i = 0; i < 8; i++) 263 IXGBE_READ_REG(hw, IXGBE_MPC(i)); 264 265 IXGBE_READ_REG(hw, IXGBE_MLFC); 266 IXGBE_READ_REG(hw, IXGBE_MRFC); 267 IXGBE_READ_REG(hw, IXGBE_RLEC); 268 IXGBE_READ_REG(hw, IXGBE_LXONTXC); 269 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 270 if (hw->mac.type >= ixgbe_mac_82599EB) { 271 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 272 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 273 } else { 274 IXGBE_READ_REG(hw, IXGBE_LXONRXC); 275 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 276 } 277 278 for (i = 0; i < 8; i++) { 279 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 280 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 281 if (hw->mac.type >= ixgbe_mac_82599EB) { 282 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 283 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 284 } else { 285 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 286 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 287 } 288 } 289 if (hw->mac.type >= ixgbe_mac_82599EB) 290 for (i = 0; i < 8; i++) 291 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 292 IXGBE_READ_REG(hw, IXGBE_PRC64); 293 IXGBE_READ_REG(hw, IXGBE_PRC127); 294 IXGBE_READ_REG(hw, IXGBE_PRC255); 295 IXGBE_READ_REG(hw, IXGBE_PRC511); 296 IXGBE_READ_REG(hw, IXGBE_PRC1023); 297 IXGBE_READ_REG(hw, IXGBE_PRC1522); 298 IXGBE_READ_REG(hw, IXGBE_GPRC); 299 IXGBE_READ_REG(hw, IXGBE_BPRC); 300 IXGBE_READ_REG(hw, IXGBE_MPRC); 301 IXGBE_READ_REG(hw, IXGBE_GPTC); 302 IXGBE_READ_REG(hw, IXGBE_GORCL); 303 IXGBE_READ_REG(hw, IXGBE_GORCH); 304 IXGBE_READ_REG(hw, IXGBE_GOTCL); 305 IXGBE_READ_REG(hw, IXGBE_GOTCH); 306 for (i = 0; i < 8; i++) 307 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 308 IXGBE_READ_REG(hw, IXGBE_RUC); 309 IXGBE_READ_REG(hw, IXGBE_RFC); 310 IXGBE_READ_REG(hw, IXGBE_ROC); 311 IXGBE_READ_REG(hw, IXGBE_RJC); 312 IXGBE_READ_REG(hw, IXGBE_MNGPRC); 313 IXGBE_READ_REG(hw, IXGBE_MNGPDC); 314 IXGBE_READ_REG(hw, IXGBE_MNGPTC); 315 IXGBE_READ_REG(hw, IXGBE_TORL); 316 IXGBE_READ_REG(hw, IXGBE_TORH); 317 IXGBE_READ_REG(hw, IXGBE_TPR); 318 IXGBE_READ_REG(hw, IXGBE_TPT); 319 IXGBE_READ_REG(hw, IXGBE_PTC64); 320 IXGBE_READ_REG(hw, IXGBE_PTC127); 321 IXGBE_READ_REG(hw, IXGBE_PTC255); 322 IXGBE_READ_REG(hw, IXGBE_PTC511); 323 IXGBE_READ_REG(hw, IXGBE_PTC1023); 324 IXGBE_READ_REG(hw, IXGBE_PTC1522); 325 IXGBE_READ_REG(hw, IXGBE_MPTC); 326 IXGBE_READ_REG(hw, IXGBE_BPTC); 327 for (i = 0; i < 16; i++) { 328 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 329 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 330 if (hw->mac.type >= ixgbe_mac_82599EB) { 331 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 332 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); 333 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 334 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); 335 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 336 } else { 337 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 338 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 339 } 340 } 341 342 return IXGBE_SUCCESS; 343 } 344 345 /** 346 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM 347 * @hw: pointer to hardware structure 348 * @pba_num: stores the part number string from the EEPROM 349 * @pba_num_size: part number string buffer length 350 * 351 * Reads the part number string from the EEPROM. 352 **/ 353 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, 354 u32 pba_num_size) 355 { 356 s32 ret_val; 357 u16 data; 358 u16 pba_ptr; 359 u16 offset; 360 u16 length; 361 362 DEBUGFUNC("ixgbe_read_pba_string_generic"); 363 364 if (pba_num == NULL) { 365 DEBUGOUT("PBA string buffer was null\n"); 366 return IXGBE_ERR_INVALID_ARGUMENT; 367 } 368 369 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 370 if (ret_val) { 371 DEBUGOUT("NVM Read Error\n"); 372 return ret_val; 373 } 374 375 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); 376 if (ret_val) { 377 DEBUGOUT("NVM Read Error\n"); 378 return ret_val; 379 } 380 381 /* 382 * if data is not ptr guard the PBA must be in legacy format which 383 * means pba_ptr is actually our second data word for the PBA number 384 * and we can decode it into an ascii string 385 */ 386 if (data != IXGBE_PBANUM_PTR_GUARD) { 387 DEBUGOUT("NVM PBA number is not stored as string\n"); 388 389 /* we will need 11 characters to store the PBA */ 390 if (pba_num_size < 11) { 391 DEBUGOUT("PBA string buffer too small\n"); 392 return IXGBE_ERR_NO_SPACE; 393 } 394 395 /* extract hex string from data and pba_ptr */ 396 pba_num[0] = (data >> 12) & 0xF; 397 pba_num[1] = (data >> 8) & 0xF; 398 pba_num[2] = (data >> 4) & 0xF; 399 pba_num[3] = data & 0xF; 400 pba_num[4] = (pba_ptr >> 12) & 0xF; 401 pba_num[5] = (pba_ptr >> 8) & 0xF; 402 pba_num[6] = '-'; 403 pba_num[7] = 0; 404 pba_num[8] = (pba_ptr >> 4) & 0xF; 405 pba_num[9] = pba_ptr & 0xF; 406 407 /* put a null character on the end of our string */ 408 pba_num[10] = '\0'; 409 410 /* switch all the data but the '-' to hex char */ 411 for (offset = 0; offset < 10; offset++) { 412 if (pba_num[offset] < 0xA) 413 pba_num[offset] += '0'; 414 else if (pba_num[offset] < 0x10) 415 pba_num[offset] += 'A' - 0xA; 416 } 417 418 return IXGBE_SUCCESS; 419 } 420 421 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); 422 if (ret_val) { 423 DEBUGOUT("NVM Read Error\n"); 424 return ret_val; 425 } 426 427 if (length == 0xFFFF || length == 0) { 428 DEBUGOUT("NVM PBA number section invalid length\n"); 429 return IXGBE_ERR_PBA_SECTION; 430 } 431 432 /* check if pba_num buffer is big enough */ 433 if (pba_num_size < (((u32)length * 2) - 1)) { 434 DEBUGOUT("PBA string buffer too small\n"); 435 return IXGBE_ERR_NO_SPACE; 436 } 437 438 /* trim pba length from start of string */ 439 pba_ptr++; 440 length--; 441 442 for (offset = 0; offset < length; offset++) { 443 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); 444 if (ret_val) { 445 DEBUGOUT("NVM Read Error\n"); 446 return ret_val; 447 } 448 pba_num[offset * 2] = (u8)(data >> 8); 449 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF); 450 } 451 pba_num[offset * 2] = '\0'; 452 453 return IXGBE_SUCCESS; 454 } 455 456 /** 457 * ixgbe_read_pba_length_generic - Reads part number length from EEPROM 458 * @hw: pointer to hardware structure 459 * @pba_num_size: part number string buffer length 460 * 461 * Reads the part number length from the EEPROM. 462 * Returns expected buffer size in pba_num_size 463 **/ 464 s32 ixgbe_read_pba_length_generic(struct ixgbe_hw *hw, u32 *pba_num_size) 465 { 466 s32 ret_val; 467 u16 data; 468 u16 pba_ptr; 469 u16 length; 470 471 DEBUGFUNC("ixgbe_read_pba_length_generic"); 472 473 if (pba_num_size == NULL) { 474 DEBUGOUT("PBA buffer size was null\n"); 475 return IXGBE_ERR_INVALID_ARGUMENT; 476 } 477 478 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 479 if (ret_val) { 480 DEBUGOUT("NVM Read Error\n"); 481 return ret_val; 482 } 483 484 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); 485 if (ret_val) { 486 DEBUGOUT("NVM Read Error\n"); 487 return ret_val; 488 } 489 490 /* if data is not ptr guard the PBA must be in legacy format */ 491 if (data != IXGBE_PBANUM_PTR_GUARD) { 492 *pba_num_size = 11; 493 return IXGBE_SUCCESS; 494 } 495 496 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); 497 if (ret_val) { 498 DEBUGOUT("NVM Read Error\n"); 499 return ret_val; 500 } 501 502 if (length == 0xFFFF || length == 0) { 503 DEBUGOUT("NVM PBA number section invalid length\n"); 504 return IXGBE_ERR_PBA_SECTION; 505 } 506 507 /* 508 * Convert from length in u16 values to u8 chars, add 1 for NULL, 509 * and subtract 2 because length field is included in length. 510 */ 511 *pba_num_size = ((u32)length * 2) - 1; 512 513 return IXGBE_SUCCESS; 514 } 515 516 /** 517 * ixgbe_read_pba_num_generic - Reads part number from EEPROM 518 * @hw: pointer to hardware structure 519 * @pba_num: stores the part number from the EEPROM 520 * 521 * Reads the part number from the EEPROM. 522 **/ 523 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) 524 { 525 s32 ret_val; 526 u16 data; 527 528 DEBUGFUNC("ixgbe_read_pba_num_generic"); 529 530 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 531 if (ret_val) { 532 DEBUGOUT("NVM Read Error\n"); 533 return ret_val; 534 } else if (data == IXGBE_PBANUM_PTR_GUARD) { 535 DEBUGOUT("NVM Not supported\n"); 536 return IXGBE_NOT_IMPLEMENTED; 537 } 538 *pba_num = (u32)(data << 16); 539 540 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); 541 if (ret_val) { 542 DEBUGOUT("NVM Read Error\n"); 543 return ret_val; 544 } 545 *pba_num |= data; 546 547 return IXGBE_SUCCESS; 548 } 549 550 /** 551 * ixgbe_get_mac_addr_generic - Generic get MAC address 552 * @hw: pointer to hardware structure 553 * @mac_addr: Adapter MAC address 554 * 555 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 556 * A reset of the adapter must be performed prior to calling this function 557 * in order for the MAC address to have been loaded from the EEPROM into RAR0 558 **/ 559 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 560 { 561 u32 rar_high; 562 u32 rar_low; 563 u16 i; 564 565 DEBUGFUNC("ixgbe_get_mac_addr_generic"); 566 567 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 568 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 569 570 for (i = 0; i < 4; i++) 571 mac_addr[i] = (u8)(rar_low >> (i*8)); 572 573 for (i = 0; i < 2; i++) 574 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 575 576 return IXGBE_SUCCESS; 577 } 578 579 /** 580 * ixgbe_get_bus_info_generic - Generic set PCI bus info 581 * @hw: pointer to hardware structure 582 * 583 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 584 **/ 585 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 586 { 587 struct ixgbe_mac_info *mac = &hw->mac; 588 u16 link_status; 589 590 DEBUGFUNC("ixgbe_get_bus_info_generic"); 591 592 hw->bus.type = ixgbe_bus_type_pci_express; 593 594 /* Get the negotiated link width and speed from PCI config space */ 595 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS); 596 597 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 598 case IXGBE_PCI_LINK_WIDTH_1: 599 hw->bus.width = ixgbe_bus_width_pcie_x1; 600 break; 601 case IXGBE_PCI_LINK_WIDTH_2: 602 hw->bus.width = ixgbe_bus_width_pcie_x2; 603 break; 604 case IXGBE_PCI_LINK_WIDTH_4: 605 hw->bus.width = ixgbe_bus_width_pcie_x4; 606 break; 607 case IXGBE_PCI_LINK_WIDTH_8: 608 hw->bus.width = ixgbe_bus_width_pcie_x8; 609 break; 610 default: 611 hw->bus.width = ixgbe_bus_width_unknown; 612 break; 613 } 614 615 switch (link_status & IXGBE_PCI_LINK_SPEED) { 616 case IXGBE_PCI_LINK_SPEED_2500: 617 hw->bus.speed = ixgbe_bus_speed_2500; 618 break; 619 case IXGBE_PCI_LINK_SPEED_5000: 620 hw->bus.speed = ixgbe_bus_speed_5000; 621 break; 622 default: 623 hw->bus.speed = ixgbe_bus_speed_unknown; 624 break; 625 } 626 627 mac->ops.set_lan_id(hw); 628 629 return IXGBE_SUCCESS; 630 } 631 632 /** 633 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 634 * @hw: pointer to the HW structure 635 * 636 * Determines the LAN function id by reading memory-mapped registers 637 * and swaps the port value if requested. 638 **/ 639 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 640 { 641 struct ixgbe_bus_info *bus = &hw->bus; 642 u32 reg; 643 644 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie"); 645 646 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 647 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 648 bus->lan_id = bus->func; 649 650 /* check for a port swap */ 651 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS); 652 if (reg & IXGBE_FACTPS_LFS) 653 bus->func ^= 0x1; 654 } 655 656 /** 657 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 658 * @hw: pointer to hardware structure 659 * 660 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 661 * disables transmit and receive units. The adapter_stopped flag is used by 662 * the shared code and drivers to determine if the adapter is in a stopped 663 * state and should not touch the hardware. 664 **/ 665 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 666 { 667 u32 number_of_queues; 668 u32 reg_val; 669 u16 i; 670 671 DEBUGFUNC("ixgbe_stop_adapter_generic"); 672 673 /* 674 * Set the adapter_stopped flag so other driver functions stop touching 675 * the hardware 676 */ 677 hw->adapter_stopped = TRUE; 678 679 /* Disable the receive unit */ 680 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 681 reg_val &= ~(IXGBE_RXCTRL_RXEN); 682 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val); 683 IXGBE_WRITE_FLUSH(hw); 684 msec_delay(2); 685 686 /* Clear interrupt mask to stop from interrupts being generated */ 687 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 688 689 /* Clear any pending interrupts */ 690 IXGBE_READ_REG(hw, IXGBE_EICR); 691 692 /* Disable the transmit unit. Each queue must be disabled. */ 693 number_of_queues = hw->mac.max_tx_queues; 694 for (i = 0; i < number_of_queues; i++) { 695 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 696 if (reg_val & IXGBE_TXDCTL_ENABLE) { 697 reg_val &= ~IXGBE_TXDCTL_ENABLE; 698 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val); 699 } 700 } 701 702 /* 703 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 704 * access and verify no pending requests 705 */ 706 ixgbe_disable_pcie_master(hw); 707 708 return IXGBE_SUCCESS; 709 } 710 711 /** 712 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 713 * @hw: pointer to hardware structure 714 * @index: led number to turn on 715 **/ 716 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 717 { 718 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 719 720 DEBUGFUNC("ixgbe_led_on_generic"); 721 722 /* To turn on the LED, set mode to ON. */ 723 led_reg &= ~IXGBE_LED_MODE_MASK(index); 724 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 725 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 726 IXGBE_WRITE_FLUSH(hw); 727 728 return IXGBE_SUCCESS; 729 } 730 731 /** 732 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 733 * @hw: pointer to hardware structure 734 * @index: led number to turn off 735 **/ 736 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 737 { 738 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 739 740 DEBUGFUNC("ixgbe_led_off_generic"); 741 742 /* To turn off the LED, set mode to OFF. */ 743 led_reg &= ~IXGBE_LED_MODE_MASK(index); 744 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 745 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 746 IXGBE_WRITE_FLUSH(hw); 747 748 return IXGBE_SUCCESS; 749 } 750 751 /** 752 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 753 * @hw: pointer to hardware structure 754 * 755 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 756 * ixgbe_hw struct in order to set up EEPROM access. 757 **/ 758 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 759 { 760 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 761 u32 eec; 762 u16 eeprom_size; 763 764 DEBUGFUNC("ixgbe_init_eeprom_params_generic"); 765 766 if (eeprom->type == ixgbe_eeprom_uninitialized) { 767 eeprom->type = ixgbe_eeprom_none; 768 /* Set default semaphore delay to 10ms which is a well 769 * tested value */ 770 eeprom->semaphore_delay = 10; 771 772 /* 773 * Check for EEPROM present first. 774 * If not present leave as none 775 */ 776 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 777 if (eec & IXGBE_EEC_PRES) { 778 eeprom->type = ixgbe_eeprom_spi; 779 780 /* 781 * SPI EEPROM is assumed here. This code would need to 782 * change if a future EEPROM is not SPI. 783 */ 784 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 785 IXGBE_EEC_SIZE_SHIFT); 786 eeprom->word_size = 1 << (eeprom_size + 787 IXGBE_EEPROM_WORD_SIZE_BASE_SHIFT); 788 } 789 790 if (eec & IXGBE_EEC_ADDR_SIZE) 791 eeprom->address_bits = 16; 792 else 793 eeprom->address_bits = 8; 794 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: " 795 "%d\n", eeprom->type, eeprom->word_size, 796 eeprom->address_bits); 797 } 798 799 return IXGBE_SUCCESS; 800 } 801 802 /** 803 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 804 * @hw: pointer to hardware structure 805 * @offset: offset within the EEPROM to be written to 806 * @data: 16 bit word to be written to the EEPROM 807 * 808 * If ixgbe_eeprom_update_checksum is not called after this function, the 809 * EEPROM will most likely contain an invalid checksum. 810 **/ 811 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 812 { 813 s32 status; 814 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 815 816 DEBUGFUNC("ixgbe_write_eeprom_generic"); 817 818 hw->eeprom.ops.init_params(hw); 819 820 if (offset >= hw->eeprom.word_size) { 821 status = IXGBE_ERR_EEPROM; 822 goto out; 823 } 824 825 /* Prepare the EEPROM for writing */ 826 status = ixgbe_acquire_eeprom(hw); 827 828 if (status == IXGBE_SUCCESS) { 829 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 830 ixgbe_release_eeprom(hw); 831 status = IXGBE_ERR_EEPROM; 832 } 833 } 834 835 if (status == IXGBE_SUCCESS) { 836 ixgbe_standby_eeprom(hw); 837 838 /* Send the WRITE ENABLE command (8 bit opcode ) */ 839 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI, 840 IXGBE_EEPROM_OPCODE_BITS); 841 842 ixgbe_standby_eeprom(hw); 843 844 /* 845 * Some SPI eeproms use the 8th address bit embedded in the 846 * opcode 847 */ 848 if ((hw->eeprom.address_bits == 8) && (offset >= 128)) 849 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 850 851 /* Send the Write command (8-bit opcode + addr) */ 852 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 853 IXGBE_EEPROM_OPCODE_BITS); 854 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), 855 hw->eeprom.address_bits); 856 857 /* Send the data */ 858 data = (data >> 8) | (data << 8); 859 ixgbe_shift_out_eeprom_bits(hw, data, 16); 860 ixgbe_standby_eeprom(hw); 861 862 /* Done with writing - release the EEPROM */ 863 ixgbe_release_eeprom(hw); 864 } 865 866 out: 867 return status; 868 } 869 870 /** 871 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 872 * @hw: pointer to hardware structure 873 * @offset: offset within the EEPROM to be read 874 * @data: read 16 bit value from EEPROM 875 * 876 * Reads 16 bit value from EEPROM through bit-bang method 877 **/ 878 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 879 u16 *data) 880 { 881 s32 status; 882 u16 word_in; 883 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 884 885 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic"); 886 887 hw->eeprom.ops.init_params(hw); 888 889 if (offset >= hw->eeprom.word_size) { 890 status = IXGBE_ERR_EEPROM; 891 goto out; 892 } 893 894 /* Prepare the EEPROM for reading */ 895 status = ixgbe_acquire_eeprom(hw); 896 897 if (status == IXGBE_SUCCESS) { 898 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 899 ixgbe_release_eeprom(hw); 900 status = IXGBE_ERR_EEPROM; 901 } 902 } 903 904 if (status == IXGBE_SUCCESS) { 905 ixgbe_standby_eeprom(hw); 906 907 /* 908 * Some SPI eeproms use the 8th address bit embedded in the 909 * opcode 910 */ 911 if ((hw->eeprom.address_bits == 8) && (offset >= 128)) 912 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 913 914 /* Send the READ command (opcode + addr) */ 915 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 916 IXGBE_EEPROM_OPCODE_BITS); 917 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), 918 hw->eeprom.address_bits); 919 920 /* Read the data. */ 921 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 922 *data = (word_in >> 8) | (word_in << 8); 923 924 /* End this read operation */ 925 ixgbe_release_eeprom(hw); 926 } 927 928 out: 929 return status; 930 } 931 932 /** 933 * ixgbe_read_eerd_generic - Read EEPROM word using EERD 934 * @hw: pointer to hardware structure 935 * @offset: offset of word in the EEPROM to read 936 * @data: word read from the EEPROM 937 * 938 * Reads a 16 bit word from the EEPROM using the EERD register. 939 **/ 940 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 941 { 942 u32 eerd; 943 s32 status; 944 945 DEBUGFUNC("ixgbe_read_eerd_generic"); 946 947 hw->eeprom.ops.init_params(hw); 948 949 if (offset >= hw->eeprom.word_size) { 950 status = IXGBE_ERR_EEPROM; 951 goto out; 952 } 953 954 eerd = (offset << IXGBE_EEPROM_RW_ADDR_SHIFT) + 955 IXGBE_EEPROM_RW_REG_START; 956 957 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 958 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 959 960 if (status == IXGBE_SUCCESS) 961 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 962 IXGBE_EEPROM_RW_REG_DATA); 963 else 964 DEBUGOUT("Eeprom read timed out\n"); 965 966 out: 967 return status; 968 } 969 970 /** 971 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR 972 * @hw: pointer to hardware structure 973 * @offset: offset of word in the EEPROM to write 974 * @data: word write to the EEPROM 975 * 976 * Write a 16 bit word to the EEPROM using the EEWR register. 977 **/ 978 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 979 { 980 u32 eewr; 981 s32 status; 982 983 DEBUGFUNC("ixgbe_write_eewr_generic"); 984 985 hw->eeprom.ops.init_params(hw); 986 987 if (offset >= hw->eeprom.word_size) { 988 status = IXGBE_ERR_EEPROM; 989 goto out; 990 } 991 992 eewr = (offset << IXGBE_EEPROM_RW_ADDR_SHIFT) | 993 (data << IXGBE_EEPROM_RW_REG_DATA) | IXGBE_EEPROM_RW_REG_START; 994 995 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 996 if (status != IXGBE_SUCCESS) { 997 DEBUGOUT("Eeprom write EEWR timed out\n"); 998 goto out; 999 } 1000 1001 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); 1002 1003 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1004 if (status != IXGBE_SUCCESS) { 1005 DEBUGOUT("Eeprom write EEWR timed out\n"); 1006 goto out; 1007 } 1008 1009 out: 1010 return status; 1011 } 1012 1013 /** 1014 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 1015 * @hw: pointer to hardware structure 1016 * @ee_reg: EEPROM flag for polling 1017 * 1018 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the 1019 * read or write is done respectively. 1020 **/ 1021 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) 1022 { 1023 u32 i; 1024 u32 reg; 1025 s32 status = IXGBE_ERR_EEPROM; 1026 1027 DEBUGFUNC("ixgbe_poll_eerd_eewr_done"); 1028 1029 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { 1030 if (ee_reg == IXGBE_NVM_POLL_READ) 1031 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 1032 else 1033 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); 1034 1035 if (reg & IXGBE_EEPROM_RW_REG_DONE) { 1036 status = IXGBE_SUCCESS; 1037 break; 1038 } 1039 usec_delay(5); 1040 } 1041 return status; 1042 } 1043 1044 /** 1045 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 1046 * @hw: pointer to hardware structure 1047 * 1048 * Prepares EEPROM for access using bit-bang method. This function should 1049 * be called before issuing a command to the EEPROM. 1050 **/ 1051 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 1052 { 1053 s32 status = IXGBE_SUCCESS; 1054 u32 eec; 1055 u32 i; 1056 1057 DEBUGFUNC("ixgbe_acquire_eeprom"); 1058 1059 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != IXGBE_SUCCESS) 1060 status = IXGBE_ERR_SWFW_SYNC; 1061 1062 if (status == IXGBE_SUCCESS) { 1063 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1064 1065 /* Request EEPROM Access */ 1066 eec |= IXGBE_EEC_REQ; 1067 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1068 1069 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 1070 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1071 if (eec & IXGBE_EEC_GNT) 1072 break; 1073 usec_delay(5); 1074 } 1075 1076 /* Release if grant not acquired */ 1077 if (!(eec & IXGBE_EEC_GNT)) { 1078 eec &= ~IXGBE_EEC_REQ; 1079 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1080 DEBUGOUT("Could not acquire EEPROM grant\n"); 1081 1082 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1083 status = IXGBE_ERR_EEPROM; 1084 } 1085 1086 /* Setup EEPROM for Read/Write */ 1087 if (status == IXGBE_SUCCESS) { 1088 /* Clear CS and SK */ 1089 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 1090 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1091 IXGBE_WRITE_FLUSH(hw); 1092 usec_delay(1); 1093 } 1094 } 1095 return status; 1096 } 1097 1098 /** 1099 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 1100 * @hw: pointer to hardware structure 1101 * 1102 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 1103 **/ 1104 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 1105 { 1106 s32 status = IXGBE_ERR_EEPROM; 1107 u32 timeout = 2000; 1108 u32 i; 1109 u32 swsm; 1110 1111 DEBUGFUNC("ixgbe_get_eeprom_semaphore"); 1112 1113 1114 /* Get SMBI software semaphore between device drivers first */ 1115 for (i = 0; i < timeout; i++) { 1116 /* 1117 * If the SMBI bit is 0 when we read it, then the bit will be 1118 * set and we have the semaphore 1119 */ 1120 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1121 if (!(swsm & IXGBE_SWSM_SMBI)) { 1122 status = IXGBE_SUCCESS; 1123 break; 1124 } 1125 usec_delay(50); 1126 } 1127 1128 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 1129 if (status == IXGBE_SUCCESS) { 1130 for (i = 0; i < timeout; i++) { 1131 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1132 1133 /* Set the SW EEPROM semaphore bit to request access */ 1134 swsm |= IXGBE_SWSM_SWESMBI; 1135 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 1136 1137 /* 1138 * If we set the bit successfully then we got the 1139 * semaphore. 1140 */ 1141 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1142 if (swsm & IXGBE_SWSM_SWESMBI) 1143 break; 1144 1145 usec_delay(50); 1146 } 1147 1148 /* 1149 * Release semaphores and return error if SW EEPROM semaphore 1150 * was not granted because we don't have access to the EEPROM 1151 */ 1152 if (i >= timeout) { 1153 DEBUGOUT("SWESMBI Software EEPROM semaphore " 1154 "not granted.\n"); 1155 ixgbe_release_eeprom_semaphore(hw); 1156 status = IXGBE_ERR_EEPROM; 1157 } 1158 } else { 1159 DEBUGOUT("Software semaphore SMBI between device drivers " 1160 "not granted.\n"); 1161 } 1162 1163 return status; 1164 } 1165 1166 /** 1167 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 1168 * @hw: pointer to hardware structure 1169 * 1170 * This function clears hardware semaphore bits. 1171 **/ 1172 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 1173 { 1174 u32 swsm; 1175 1176 DEBUGFUNC("ixgbe_release_eeprom_semaphore"); 1177 1178 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1179 1180 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 1181 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 1182 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 1183 IXGBE_WRITE_FLUSH(hw); 1184 } 1185 1186 /** 1187 * ixgbe_ready_eeprom - Polls for EEPROM ready 1188 * @hw: pointer to hardware structure 1189 **/ 1190 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 1191 { 1192 s32 status = IXGBE_SUCCESS; 1193 u16 i; 1194 u8 spi_stat_reg; 1195 1196 DEBUGFUNC("ixgbe_ready_eeprom"); 1197 1198 /* 1199 * Read "Status Register" repeatedly until the LSB is cleared. The 1200 * EEPROM will signal that the command has been completed by clearing 1201 * bit 0 of the internal status register. If it's not cleared within 1202 * 5 milliseconds, then error out. 1203 */ 1204 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 1205 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 1206 IXGBE_EEPROM_OPCODE_BITS); 1207 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 1208 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 1209 break; 1210 1211 usec_delay(5); 1212 ixgbe_standby_eeprom(hw); 1213 }; 1214 1215 /* 1216 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 1217 * devices (and only 0-5mSec on 5V devices) 1218 */ 1219 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 1220 DEBUGOUT("SPI EEPROM Status error\n"); 1221 status = IXGBE_ERR_EEPROM; 1222 } 1223 1224 return status; 1225 } 1226 1227 /** 1228 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 1229 * @hw: pointer to hardware structure 1230 **/ 1231 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 1232 { 1233 u32 eec; 1234 1235 DEBUGFUNC("ixgbe_standby_eeprom"); 1236 1237 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1238 1239 /* Toggle CS to flush commands */ 1240 eec |= IXGBE_EEC_CS; 1241 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1242 IXGBE_WRITE_FLUSH(hw); 1243 usec_delay(1); 1244 eec &= ~IXGBE_EEC_CS; 1245 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1246 IXGBE_WRITE_FLUSH(hw); 1247 usec_delay(1); 1248 } 1249 1250 /** 1251 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 1252 * @hw: pointer to hardware structure 1253 * @data: data to send to the EEPROM 1254 * @count: number of bits to shift out 1255 **/ 1256 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 1257 u16 count) 1258 { 1259 u32 eec; 1260 u32 mask; 1261 u32 i; 1262 1263 DEBUGFUNC("ixgbe_shift_out_eeprom_bits"); 1264 1265 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1266 1267 /* 1268 * Mask is used to shift "count" bits of "data" out to the EEPROM 1269 * one bit at a time. Determine the starting bit based on count 1270 */ 1271 mask = 0x01 << (count - 1); 1272 1273 for (i = 0; i < count; i++) { 1274 /* 1275 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 1276 * "1", and then raising and then lowering the clock (the SK 1277 * bit controls the clock input to the EEPROM). A "0" is 1278 * shifted out to the EEPROM by setting "DI" to "0" and then 1279 * raising and then lowering the clock. 1280 */ 1281 if (data & mask) 1282 eec |= IXGBE_EEC_DI; 1283 else 1284 eec &= ~IXGBE_EEC_DI; 1285 1286 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1287 IXGBE_WRITE_FLUSH(hw); 1288 1289 usec_delay(1); 1290 1291 ixgbe_raise_eeprom_clk(hw, &eec); 1292 ixgbe_lower_eeprom_clk(hw, &eec); 1293 1294 /* 1295 * Shift mask to signify next bit of data to shift in to the 1296 * EEPROM 1297 */ 1298 mask = mask >> 1; 1299 }; 1300 1301 /* We leave the "DI" bit set to "0" when we leave this routine. */ 1302 eec &= ~IXGBE_EEC_DI; 1303 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1304 IXGBE_WRITE_FLUSH(hw); 1305 } 1306 1307 /** 1308 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 1309 * @hw: pointer to hardware structure 1310 **/ 1311 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 1312 { 1313 u32 eec; 1314 u32 i; 1315 u16 data = 0; 1316 1317 DEBUGFUNC("ixgbe_shift_in_eeprom_bits"); 1318 1319 /* 1320 * In order to read a register from the EEPROM, we need to shift 1321 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 1322 * the clock input to the EEPROM (setting the SK bit), and then reading 1323 * the value of the "DO" bit. During this "shifting in" process the 1324 * "DI" bit should always be clear. 1325 */ 1326 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1327 1328 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 1329 1330 for (i = 0; i < count; i++) { 1331 data = data << 1; 1332 ixgbe_raise_eeprom_clk(hw, &eec); 1333 1334 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1335 1336 eec &= ~(IXGBE_EEC_DI); 1337 if (eec & IXGBE_EEC_DO) 1338 data |= 1; 1339 1340 ixgbe_lower_eeprom_clk(hw, &eec); 1341 } 1342 1343 return data; 1344 } 1345 1346 /** 1347 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 1348 * @hw: pointer to hardware structure 1349 * @eec: EEC register's current value 1350 **/ 1351 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1352 { 1353 DEBUGFUNC("ixgbe_raise_eeprom_clk"); 1354 1355 /* 1356 * Raise the clock input to the EEPROM 1357 * (setting the SK bit), then delay 1358 */ 1359 *eec = *eec | IXGBE_EEC_SK; 1360 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1361 IXGBE_WRITE_FLUSH(hw); 1362 usec_delay(1); 1363 } 1364 1365 /** 1366 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 1367 * @hw: pointer to hardware structure 1368 * @eecd: EECD's current value 1369 **/ 1370 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1371 { 1372 DEBUGFUNC("ixgbe_lower_eeprom_clk"); 1373 1374 /* 1375 * Lower the clock input to the EEPROM (clearing the SK bit), then 1376 * delay 1377 */ 1378 *eec = *eec & ~IXGBE_EEC_SK; 1379 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1380 IXGBE_WRITE_FLUSH(hw); 1381 usec_delay(1); 1382 } 1383 1384 /** 1385 * ixgbe_release_eeprom - Release EEPROM, release semaphores 1386 * @hw: pointer to hardware structure 1387 **/ 1388 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 1389 { 1390 u32 eec; 1391 1392 DEBUGFUNC("ixgbe_release_eeprom"); 1393 1394 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1395 1396 eec |= IXGBE_EEC_CS; /* Pull CS high */ 1397 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 1398 1399 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1400 IXGBE_WRITE_FLUSH(hw); 1401 1402 usec_delay(1); 1403 1404 /* Stop requesting EEPROM access */ 1405 eec &= ~IXGBE_EEC_REQ; 1406 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1407 1408 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1409 1410 /* Delay before attempt to obtain semaphore again to allow FW access */ 1411 msec_delay(hw->eeprom.semaphore_delay); 1412 } 1413 1414 /** 1415 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum 1416 * @hw: pointer to hardware structure 1417 **/ 1418 u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) 1419 { 1420 u16 i; 1421 u16 j; 1422 u16 checksum = 0; 1423 u16 length = 0; 1424 u16 pointer = 0; 1425 u16 word = 0; 1426 1427 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic"); 1428 1429 /* Include 0x0-0x3F in the checksum */ 1430 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 1431 if (hw->eeprom.ops.read(hw, i, &word) != IXGBE_SUCCESS) { 1432 DEBUGOUT("EEPROM read failed\n"); 1433 break; 1434 } 1435 checksum += word; 1436 } 1437 1438 /* Include all data from pointers except for the fw pointer */ 1439 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 1440 hw->eeprom.ops.read(hw, i, &pointer); 1441 1442 /* Make sure the pointer seems valid */ 1443 if (pointer != 0xFFFF && pointer != 0) { 1444 hw->eeprom.ops.read(hw, pointer, &length); 1445 1446 if (length != 0xFFFF && length != 0) { 1447 for (j = pointer+1; j <= pointer+length; j++) { 1448 hw->eeprom.ops.read(hw, j, &word); 1449 checksum += word; 1450 } 1451 } 1452 } 1453 } 1454 1455 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1456 1457 return checksum; 1458 } 1459 1460 /** 1461 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 1462 * @hw: pointer to hardware structure 1463 * @checksum_val: calculated checksum 1464 * 1465 * Performs checksum calculation and validates the EEPROM checksum. If the 1466 * caller does not need checksum_val, the value can be NULL. 1467 **/ 1468 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 1469 u16 *checksum_val) 1470 { 1471 s32 status; 1472 u16 checksum; 1473 u16 read_checksum = 0; 1474 1475 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic"); 1476 1477 /* 1478 * Read the first word from the EEPROM. If this times out or fails, do 1479 * not continue or we could be in for a very long wait while every 1480 * EEPROM read fails 1481 */ 1482 status = hw->eeprom.ops.read(hw, 0, &checksum); 1483 1484 if (status == IXGBE_SUCCESS) { 1485 checksum = hw->eeprom.ops.calc_checksum(hw); 1486 1487 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 1488 1489 /* 1490 * Verify read checksum from EEPROM is the same as 1491 * calculated checksum 1492 */ 1493 if (read_checksum != checksum) 1494 status = IXGBE_ERR_EEPROM_CHECKSUM; 1495 1496 /* If the user cares, return the calculated checksum */ 1497 if (checksum_val) 1498 *checksum_val = checksum; 1499 } else { 1500 DEBUGOUT("EEPROM read failed\n"); 1501 } 1502 1503 return status; 1504 } 1505 1506 /** 1507 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 1508 * @hw: pointer to hardware structure 1509 **/ 1510 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 1511 { 1512 s32 status; 1513 u16 checksum; 1514 1515 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic"); 1516 1517 /* 1518 * Read the first word from the EEPROM. If this times out or fails, do 1519 * not continue or we could be in for a very long wait while every 1520 * EEPROM read fails 1521 */ 1522 status = hw->eeprom.ops.read(hw, 0, &checksum); 1523 1524 if (status == IXGBE_SUCCESS) { 1525 checksum = hw->eeprom.ops.calc_checksum(hw); 1526 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, 1527 checksum); 1528 } else { 1529 DEBUGOUT("EEPROM read failed\n"); 1530 } 1531 1532 return status; 1533 } 1534 1535 /** 1536 * ixgbe_validate_mac_addr - Validate MAC address 1537 * @mac_addr: pointer to MAC address. 1538 * 1539 * Tests a MAC address to ensure it is a valid Individual Address 1540 **/ 1541 s32 ixgbe_validate_mac_addr(u8 *mac_addr) 1542 { 1543 s32 status = IXGBE_SUCCESS; 1544 1545 DEBUGFUNC("ixgbe_validate_mac_addr"); 1546 1547 /* Make sure it is not a multicast address */ 1548 if (IXGBE_IS_MULTICAST(mac_addr)) { 1549 DEBUGOUT("MAC address is multicast\n"); 1550 status = IXGBE_ERR_INVALID_MAC_ADDR; 1551 /* Not a broadcast address */ 1552 } else if (IXGBE_IS_BROADCAST(mac_addr)) { 1553 DEBUGOUT("MAC address is broadcast\n"); 1554 status = IXGBE_ERR_INVALID_MAC_ADDR; 1555 /* Reject the zero address */ 1556 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 1557 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { 1558 DEBUGOUT("MAC address is all zeros\n"); 1559 status = IXGBE_ERR_INVALID_MAC_ADDR; 1560 } 1561 return status; 1562 } 1563 1564 /** 1565 * ixgbe_set_rar_generic - Set Rx address register 1566 * @hw: pointer to hardware structure 1567 * @index: Receive address register to write 1568 * @addr: Address to put into receive address register 1569 * @vmdq: VMDq "set" or "pool" index 1570 * @enable_addr: set flag that address is active 1571 * 1572 * Puts an ethernet address into a receive address register. 1573 **/ 1574 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 1575 u32 enable_addr) 1576 { 1577 u32 rar_low, rar_high; 1578 u32 rar_entries = hw->mac.num_rar_entries; 1579 1580 DEBUGFUNC("ixgbe_set_rar_generic"); 1581 1582 /* Make sure we are using a valid rar index range */ 1583 if (index >= rar_entries) { 1584 DEBUGOUT1("RAR index %d is out of range.\n", index); 1585 return IXGBE_ERR_INVALID_ARGUMENT; 1586 } 1587 1588 /* setup VMDq pool selection before this RAR gets enabled */ 1589 hw->mac.ops.set_vmdq(hw, index, vmdq); 1590 1591 /* 1592 * HW expects these in little endian so we reverse the byte 1593 * order from network order (big endian) to little endian 1594 */ 1595 rar_low = ((u32)addr[0] | 1596 ((u32)addr[1] << 8) | 1597 ((u32)addr[2] << 16) | 1598 ((u32)addr[3] << 24)); 1599 /* 1600 * Some parts put the VMDq setting in the extra RAH bits, 1601 * so save everything except the lower 16 bits that hold part 1602 * of the address and the address valid bit. 1603 */ 1604 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1605 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1606 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 1607 1608 if (enable_addr != 0) 1609 rar_high |= IXGBE_RAH_AV; 1610 1611 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 1612 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1613 1614 return IXGBE_SUCCESS; 1615 } 1616 1617 /** 1618 * ixgbe_clear_rar_generic - Remove Rx address register 1619 * @hw: pointer to hardware structure 1620 * @index: Receive address register to write 1621 * 1622 * Clears an ethernet address from a receive address register. 1623 **/ 1624 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 1625 { 1626 u32 rar_high; 1627 u32 rar_entries = hw->mac.num_rar_entries; 1628 1629 DEBUGFUNC("ixgbe_clear_rar_generic"); 1630 1631 /* Make sure we are using a valid rar index range */ 1632 if (index >= rar_entries) { 1633 DEBUGOUT1("RAR index %d is out of range.\n", index); 1634 return IXGBE_ERR_INVALID_ARGUMENT; 1635 } 1636 1637 /* 1638 * Some parts put the VMDq setting in the extra RAH bits, 1639 * so save everything except the lower 16 bits that hold part 1640 * of the address and the address valid bit. 1641 */ 1642 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1643 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1644 1645 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 1646 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1647 1648 /* clear VMDq pool/queue selection for this RAR */ 1649 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 1650 1651 return IXGBE_SUCCESS; 1652 } 1653 1654 /** 1655 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 1656 * @hw: pointer to hardware structure 1657 * 1658 * Places the MAC address in receive address register 0 and clears the rest 1659 * of the receive address registers. Clears the multicast table. Assumes 1660 * the receiver is in reset when the routine is called. 1661 **/ 1662 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 1663 { 1664 u32 i; 1665 u32 rar_entries = hw->mac.num_rar_entries; 1666 1667 DEBUGFUNC("ixgbe_init_rx_addrs_generic"); 1668 1669 /* 1670 * If the current mac address is valid, assume it is a software override 1671 * to the permanent address. 1672 * Otherwise, use the permanent address from the eeprom. 1673 */ 1674 if (ixgbe_validate_mac_addr(hw->mac.addr) == 1675 IXGBE_ERR_INVALID_MAC_ADDR) { 1676 /* Get the MAC address from the RAR0 for later reference */ 1677 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 1678 1679 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ", 1680 hw->mac.addr[0], hw->mac.addr[1], 1681 hw->mac.addr[2]); 1682 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 1683 hw->mac.addr[4], hw->mac.addr[5]); 1684 } else { 1685 /* Setup the receive address. */ 1686 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 1687 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 1688 hw->mac.addr[0], hw->mac.addr[1], 1689 hw->mac.addr[2]); 1690 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 1691 hw->mac.addr[4], hw->mac.addr[5]); 1692 1693 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 1694 1695 /* clear VMDq pool/queue selection for RAR 0 */ 1696 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); 1697 } 1698 hw->addr_ctrl.overflow_promisc = 0; 1699 1700 hw->addr_ctrl.rar_used_count = 1; 1701 1702 /* Zero out the other receive addresses. */ 1703 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); 1704 for (i = 1; i < rar_entries; i++) { 1705 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1706 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1707 } 1708 1709 /* Clear the MTA */ 1710 hw->addr_ctrl.mta_in_use = 0; 1711 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1712 1713 DEBUGOUT(" Clearing MTA\n"); 1714 for (i = 0; i < hw->mac.mcft_size; i++) 1715 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1716 1717 ixgbe_init_uta_tables(hw); 1718 1719 return IXGBE_SUCCESS; 1720 } 1721 1722 /** 1723 * ixgbe_add_uc_addr - Adds a secondary unicast address. 1724 * @hw: pointer to hardware structure 1725 * @addr: new address 1726 * 1727 * Adds it to unused receive address register or goes into promiscuous mode. 1728 **/ 1729 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 1730 { 1731 u32 rar_entries = hw->mac.num_rar_entries; 1732 u32 rar; 1733 1734 DEBUGFUNC("ixgbe_add_uc_addr"); 1735 1736 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", 1737 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 1738 1739 /* 1740 * Place this address in the RAR if there is room, 1741 * else put the controller into promiscuous mode 1742 */ 1743 if (hw->addr_ctrl.rar_used_count < rar_entries) { 1744 rar = hw->addr_ctrl.rar_used_count; 1745 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 1746 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar); 1747 hw->addr_ctrl.rar_used_count++; 1748 } else { 1749 hw->addr_ctrl.overflow_promisc++; 1750 } 1751 1752 DEBUGOUT("ixgbe_add_uc_addr Complete\n"); 1753 } 1754 1755 /** 1756 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses 1757 * @hw: pointer to hardware structure 1758 * @addr_list: the list of new addresses 1759 * @addr_count: number of addresses 1760 * @next: iterator function to walk the address list 1761 * 1762 * The given list replaces any existing list. Clears the secondary addrs from 1763 * receive address registers. Uses unused receive address registers for the 1764 * first secondary addresses, and falls back to promiscuous mode as needed. 1765 * 1766 * Drivers using secondary unicast addresses must set user_set_promisc when 1767 * manually putting the device into promiscuous mode. 1768 **/ 1769 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, 1770 u32 addr_count, ixgbe_mc_addr_itr next) 1771 { 1772 u8 *addr; 1773 u32 i; 1774 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; 1775 u32 uc_addr_in_use; 1776 u32 fctrl; 1777 u32 vmdq; 1778 1779 DEBUGFUNC("ixgbe_update_uc_addr_list_generic"); 1780 1781 /* 1782 * Clear accounting of old secondary address list, 1783 * don't count RAR[0] 1784 */ 1785 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1; 1786 hw->addr_ctrl.rar_used_count -= uc_addr_in_use; 1787 hw->addr_ctrl.overflow_promisc = 0; 1788 1789 /* Zero out the other receive addresses */ 1790 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1); 1791 for (i = 0; i < uc_addr_in_use; i++) { 1792 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0); 1793 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0); 1794 } 1795 1796 /* Add the new addresses */ 1797 for (i = 0; i < addr_count; i++) { 1798 DEBUGOUT(" Adding the secondary addresses:\n"); 1799 addr = next(hw, &addr_list, &vmdq); 1800 ixgbe_add_uc_addr(hw, addr, vmdq); 1801 } 1802 1803 if (hw->addr_ctrl.overflow_promisc) { 1804 /* enable promisc if not already in overflow or set by user */ 1805 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 1806 DEBUGOUT(" Entering address overflow promisc mode\n"); 1807 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1808 fctrl |= IXGBE_FCTRL_UPE; 1809 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 1810 } 1811 } else { 1812 /* only disable if set by overflow, not by user */ 1813 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 1814 DEBUGOUT(" Leaving address overflow promisc mode\n"); 1815 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1816 fctrl &= ~IXGBE_FCTRL_UPE; 1817 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 1818 } 1819 } 1820 1821 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n"); 1822 return IXGBE_SUCCESS; 1823 } 1824 1825 /** 1826 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 1827 * @hw: pointer to hardware structure 1828 * @mc_addr: the multicast address 1829 * 1830 * Extracts the 12 bits, from a multicast address, to determine which 1831 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 1832 * incoming rx multicast addresses, to determine the bit-vector to check in 1833 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 1834 * by the MO field of the MCSTCTRL. The MO field is set during initialization 1835 * to mc_filter_type. 1836 **/ 1837 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 1838 { 1839 u32 vector = 0; 1840 1841 DEBUGFUNC("ixgbe_mta_vector"); 1842 1843 switch (hw->mac.mc_filter_type) { 1844 case 0: /* use bits [47:36] of the address */ 1845 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 1846 break; 1847 case 1: /* use bits [46:35] of the address */ 1848 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 1849 break; 1850 case 2: /* use bits [45:34] of the address */ 1851 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 1852 break; 1853 case 3: /* use bits [43:32] of the address */ 1854 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 1855 break; 1856 default: /* Invalid mc_filter_type */ 1857 DEBUGOUT("MC filter type param set incorrectly\n"); 1858 ASSERT(0); 1859 break; 1860 } 1861 1862 /* vector can only be 12-bits or boundary will be exceeded */ 1863 vector &= 0xFFF; 1864 return vector; 1865 } 1866 1867 /** 1868 * ixgbe_set_mta - Set bit-vector in multicast table 1869 * @hw: pointer to hardware structure 1870 * @hash_value: Multicast address hash value 1871 * 1872 * Sets the bit-vector in the multicast table. 1873 **/ 1874 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 1875 { 1876 u32 vector; 1877 u32 vector_bit; 1878 u32 vector_reg; 1879 1880 DEBUGFUNC("ixgbe_set_mta"); 1881 1882 hw->addr_ctrl.mta_in_use++; 1883 1884 vector = ixgbe_mta_vector(hw, mc_addr); 1885 DEBUGOUT1(" bit-vector = 0x%03X\n", vector); 1886 1887 /* 1888 * The MTA is a register array of 128 32-bit registers. It is treated 1889 * like an array of 4096 bits. We want to set bit 1890 * BitArray[vector_value]. So we figure out what register the bit is 1891 * in, read it, OR in the new bit, then write back the new value. The 1892 * register is determined by the upper 7 bits of the vector value and 1893 * the bit within that register are determined by the lower 5 bits of 1894 * the value. 1895 */ 1896 vector_reg = (vector >> 5) & 0x7F; 1897 vector_bit = vector & 0x1F; 1898 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit); 1899 } 1900 1901 /** 1902 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 1903 * @hw: pointer to hardware structure 1904 * @mc_addr_list: the list of new multicast addresses 1905 * @mc_addr_count: number of addresses 1906 * @next: iterator function to walk the multicast address list 1907 * 1908 * The given list replaces any existing list. Clears the MC addrs from receive 1909 * address registers and the multicast table. Uses unused receive address 1910 * registers for the first multicast addresses, and hashes the rest into the 1911 * multicast table. 1912 **/ 1913 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, 1914 u32 mc_addr_count, ixgbe_mc_addr_itr next) 1915 { 1916 u32 i; 1917 u32 vmdq; 1918 1919 DEBUGFUNC("ixgbe_update_mc_addr_list_generic"); 1920 1921 /* 1922 * Set the new number of MC addresses that we are being requested to 1923 * use. 1924 */ 1925 hw->addr_ctrl.num_mc_addrs = mc_addr_count; 1926 hw->addr_ctrl.mta_in_use = 0; 1927 1928 /* Clear mta_shadow */ 1929 DEBUGOUT(" Clearing MTA\n"); 1930 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 1931 1932 /* Update mta_shadow */ 1933 for (i = 0; i < mc_addr_count; i++) { 1934 DEBUGOUT(" Adding the multicast addresses:\n"); 1935 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); 1936 } 1937 1938 /* Enable mta */ 1939 for (i = 0; i < hw->mac.mcft_size; i++) 1940 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, 1941 hw->mac.mta_shadow[i]); 1942 1943 if (hw->addr_ctrl.mta_in_use > 0) 1944 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 1945 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 1946 1947 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n"); 1948 return IXGBE_SUCCESS; 1949 } 1950 1951 /** 1952 * ixgbe_enable_mc_generic - Enable multicast address in RAR 1953 * @hw: pointer to hardware structure 1954 * 1955 * Enables multicast address in RAR and the use of the multicast hash table. 1956 **/ 1957 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 1958 { 1959 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1960 1961 DEBUGFUNC("ixgbe_enable_mc_generic"); 1962 1963 if (a->mta_in_use > 0) 1964 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 1965 hw->mac.mc_filter_type); 1966 1967 return IXGBE_SUCCESS; 1968 } 1969 1970 /** 1971 * ixgbe_disable_mc_generic - Disable multicast address in RAR 1972 * @hw: pointer to hardware structure 1973 * 1974 * Disables multicast address in RAR and the use of the multicast hash table. 1975 **/ 1976 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 1977 { 1978 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1979 1980 DEBUGFUNC("ixgbe_disable_mc_generic"); 1981 1982 if (a->mta_in_use > 0) 1983 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1984 1985 return IXGBE_SUCCESS; 1986 } 1987 1988 /** 1989 * ixgbe_fc_enable_generic - Enable flow control 1990 * @hw: pointer to hardware structure 1991 * @packetbuf_num: packet buffer number (0-7) 1992 * 1993 * Enable flow control according to the current settings. 1994 **/ 1995 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num) 1996 { 1997 s32 ret_val = IXGBE_SUCCESS; 1998 u32 mflcn_reg, fccfg_reg; 1999 u32 reg; 2000 u32 rx_pba_size; 2001 u32 fcrtl, fcrth; 2002 2003 DEBUGFUNC("ixgbe_fc_enable_generic"); 2004 2005 /* Negotiate the fc mode to use */ 2006 ret_val = ixgbe_fc_autoneg(hw); 2007 if (ret_val == IXGBE_ERR_FLOW_CONTROL) 2008 goto out; 2009 2010 /* Disable any previous flow control settings */ 2011 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2012 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE); 2013 2014 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 2015 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 2016 2017 /* 2018 * The possible values of fc.current_mode are: 2019 * 0: Flow control is completely disabled 2020 * 1: Rx flow control is enabled (we can receive pause frames, 2021 * but not send pause frames). 2022 * 2: Tx flow control is enabled (we can send pause frames but 2023 * we do not support receiving pause frames). 2024 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2025 * other: Invalid. 2026 */ 2027 switch (hw->fc.current_mode) { 2028 case ixgbe_fc_none: 2029 /* 2030 * Flow control is disabled by software override or autoneg. 2031 * The code below will actually disable it in the HW. 2032 */ 2033 break; 2034 case ixgbe_fc_rx_pause: 2035 /* 2036 * Rx Flow control is enabled and Tx Flow control is 2037 * disabled by software override. Since there really 2038 * isn't a way to advertise that we are capable of RX 2039 * Pause ONLY, we will advertise that we support both 2040 * symmetric and asymmetric Rx PAUSE. Later, we will 2041 * disable the adapter's ability to send PAUSE frames. 2042 */ 2043 mflcn_reg |= IXGBE_MFLCN_RFCE; 2044 break; 2045 case ixgbe_fc_tx_pause: 2046 /* 2047 * Tx Flow control is enabled, and Rx Flow control is 2048 * disabled by software override. 2049 */ 2050 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2051 break; 2052 case ixgbe_fc_full: 2053 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2054 mflcn_reg |= IXGBE_MFLCN_RFCE; 2055 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2056 break; 2057 default: 2058 DEBUGOUT("Flow control param set incorrectly\n"); 2059 ret_val = IXGBE_ERR_CONFIG; 2060 goto out; 2061 break; 2062 } 2063 2064 /* Set 802.3x based flow control settings. */ 2065 mflcn_reg |= IXGBE_MFLCN_DPF; 2066 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 2067 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 2068 2069 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num)); 2070 rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT; 2071 2072 fcrth = (rx_pba_size - hw->fc.high_water) << 10; 2073 fcrtl = (rx_pba_size - hw->fc.low_water) << 10; 2074 2075 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 2076 fcrth |= IXGBE_FCRTH_FCEN; 2077 if (hw->fc.send_xon) 2078 fcrtl |= IXGBE_FCRTL_XONE; 2079 } 2080 2081 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), fcrth); 2082 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), fcrtl); 2083 2084 /* Configure pause time (2 TCs per register) */ 2085 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2)); 2086 if ((packetbuf_num & 1) == 0) 2087 reg = (reg & 0xFFFF0000) | hw->fc.pause_time; 2088 else 2089 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16); 2090 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg); 2091 2092 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); 2093 2094 out: 2095 return ret_val; 2096 } 2097 2098 /** 2099 * ixgbe_fc_autoneg - Configure flow control 2100 * @hw: pointer to hardware structure 2101 * 2102 * Compares our advertised flow control capabilities to those advertised by 2103 * our link partner, and determines the proper flow control mode to use. 2104 **/ 2105 s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw) 2106 { 2107 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2108 ixgbe_link_speed speed; 2109 bool link_up; 2110 2111 DEBUGFUNC("ixgbe_fc_autoneg"); 2112 2113 if (hw->fc.disable_fc_autoneg) 2114 goto out; 2115 2116 /* 2117 * AN should have completed when the cable was plugged in. 2118 * Look for reasons to bail out. Bail out if: 2119 * - FC autoneg is disabled, or if 2120 * - link is not up. 2121 * 2122 * Since we're being called from an LSC, link is already known to be up. 2123 * So use link_up_wait_to_complete=FALSE. 2124 */ 2125 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 2126 if (!link_up) { 2127 ret_val = IXGBE_ERR_FLOW_CONTROL; 2128 goto out; 2129 } 2130 2131 switch (hw->phy.media_type) { 2132 /* Autoneg flow control on fiber adapters */ 2133 case ixgbe_media_type_fiber: 2134 if (speed == IXGBE_LINK_SPEED_1GB_FULL) 2135 ret_val = ixgbe_fc_autoneg_fiber(hw); 2136 break; 2137 2138 /* Autoneg flow control on backplane adapters */ 2139 case ixgbe_media_type_backplane: 2140 ret_val = ixgbe_fc_autoneg_backplane(hw); 2141 break; 2142 2143 /* Autoneg flow control on copper adapters */ 2144 case ixgbe_media_type_copper: 2145 if (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS) 2146 ret_val = ixgbe_fc_autoneg_copper(hw); 2147 break; 2148 2149 default: 2150 break; 2151 } 2152 2153 out: 2154 if (ret_val == IXGBE_SUCCESS) { 2155 hw->fc.fc_was_autonegged = TRUE; 2156 } else { 2157 hw->fc.fc_was_autonegged = FALSE; 2158 hw->fc.current_mode = hw->fc.requested_mode; 2159 } 2160 return ret_val; 2161 } 2162 2163 /** 2164 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber 2165 * @hw: pointer to hardware structure 2166 * @speed: 2167 * @link_up 2168 * 2169 * Enable flow control according on 1 gig fiber. 2170 **/ 2171 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) 2172 { 2173 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 2174 s32 ret_val; 2175 2176 /* 2177 * On multispeed fiber at 1g, bail out if 2178 * - link is up but AN did not complete, or if 2179 * - link is up and AN completed but timed out 2180 */ 2181 2182 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 2183 if (((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 2184 ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) != 0)) { 2185 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2186 goto out; 2187 } 2188 2189 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 2190 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 2191 2192 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, 2193 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE, 2194 IXGBE_PCS1GANA_ASM_PAUSE, 2195 IXGBE_PCS1GANA_SYM_PAUSE, 2196 IXGBE_PCS1GANA_ASM_PAUSE); 2197 2198 out: 2199 return ret_val; 2200 } 2201 2202 /** 2203 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37 2204 * @hw: pointer to hardware structure 2205 * 2206 * Enable flow control according to IEEE clause 37. 2207 **/ 2208 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) 2209 { 2210 u32 links2, anlp1_reg, autoc_reg, links; 2211 s32 ret_val; 2212 2213 /* 2214 * On backplane, bail out if 2215 * - backplane autoneg was not completed, or if 2216 * - we are 82599 and link partner is not AN enabled 2217 */ 2218 links = IXGBE_READ_REG(hw, IXGBE_LINKS); 2219 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) { 2220 hw->fc.fc_was_autonegged = FALSE; 2221 hw->fc.current_mode = hw->fc.requested_mode; 2222 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2223 goto out; 2224 } 2225 2226 if (hw->mac.type == ixgbe_mac_82599EB) { 2227 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 2228 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) { 2229 hw->fc.fc_was_autonegged = FALSE; 2230 hw->fc.current_mode = hw->fc.requested_mode; 2231 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2232 goto out; 2233 } 2234 } 2235 /* 2236 * Read the 10g AN autoc and LP ability registers and resolve 2237 * local flow control settings accordingly 2238 */ 2239 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2240 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 2241 2242 ret_val = ixgbe_negotiate_fc(hw, autoc_reg, 2243 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE, 2244 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE); 2245 2246 out: 2247 return ret_val; 2248 } 2249 2250 /** 2251 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37 2252 * @hw: pointer to hardware structure 2253 * 2254 * Enable flow control according to IEEE clause 37. 2255 **/ 2256 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) 2257 { 2258 u16 technology_ability_reg = 0; 2259 u16 lp_technology_ability_reg = 0; 2260 2261 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 2262 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2263 &technology_ability_reg); 2264 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP, 2265 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2266 &lp_technology_ability_reg); 2267 2268 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, 2269 (u32)lp_technology_ability_reg, 2270 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE, 2271 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE); 2272 } 2273 2274 /** 2275 * ixgbe_negotiate_fc - Negotiate flow control 2276 * @hw: pointer to hardware structure 2277 * @adv_reg: flow control advertised settings 2278 * @lp_reg: link partner's flow control settings 2279 * @adv_sym: symmetric pause bit in advertisement 2280 * @adv_asm: asymmetric pause bit in advertisement 2281 * @lp_sym: symmetric pause bit in link partner advertisement 2282 * @lp_asm: asymmetric pause bit in link partner advertisement 2283 * 2284 * Find the intersection between advertised settings and link partner's 2285 * advertised settings 2286 **/ 2287 static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 2288 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) 2289 { 2290 if ((!(adv_reg)) || (!(lp_reg))) 2291 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2292 2293 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) { 2294 /* 2295 * Now we need to check if the user selected Rx ONLY 2296 * of pause frames. In this case, we had to advertise 2297 * FULL flow control because we could not advertise RX 2298 * ONLY. Hence, we must now check to see if we need to 2299 * turn OFF the TRANSMISSION of PAUSE frames. 2300 */ 2301 if (hw->fc.requested_mode == ixgbe_fc_full) { 2302 hw->fc.current_mode = ixgbe_fc_full; 2303 DEBUGOUT("Flow Control = FULL.\n"); 2304 } else { 2305 hw->fc.current_mode = ixgbe_fc_rx_pause; 2306 DEBUGOUT("Flow Control=RX PAUSE frames only\n"); 2307 } 2308 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) && 2309 (lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2310 hw->fc.current_mode = ixgbe_fc_tx_pause; 2311 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 2312 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) && 2313 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2314 hw->fc.current_mode = ixgbe_fc_rx_pause; 2315 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2316 } else { 2317 hw->fc.current_mode = ixgbe_fc_none; 2318 DEBUGOUT("Flow Control = NONE.\n"); 2319 } 2320 return IXGBE_SUCCESS; 2321 } 2322 2323 /** 2324 * ixgbe_setup_fc - Set up flow control 2325 * @hw: pointer to hardware structure 2326 * 2327 * Called at init time to set up flow control. 2328 **/ 2329 s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num) 2330 { 2331 s32 ret_val = IXGBE_SUCCESS; 2332 u32 reg = 0, reg_bp = 0; 2333 u16 reg_cu = 0; 2334 2335 DEBUGFUNC("ixgbe_setup_fc"); 2336 2337 /* Validate the packetbuf configuration */ 2338 if (packetbuf_num < 0 || packetbuf_num > 7) { 2339 DEBUGOUT1("Invalid packet buffer number [%d], expected range is" 2340 " 0-7\n", packetbuf_num); 2341 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2342 goto out; 2343 } 2344 2345 /* 2346 * Validate the water mark configuration. Zero water marks are invalid 2347 * because it causes the controller to just blast out fc packets. 2348 */ 2349 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) { 2350 DEBUGOUT("Invalid water mark configuration\n"); 2351 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2352 goto out; 2353 } 2354 2355 /* 2356 * Validate the requested mode. Strict IEEE mode does not allow 2357 * ixgbe_fc_rx_pause because it will cause us to fail at UNH. 2358 */ 2359 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 2360 DEBUGOUT("ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 2361 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2362 goto out; 2363 } 2364 2365 /* 2366 * 10gig parts do not have a word in the EEPROM to determine the 2367 * default flow control setting, so we explicitly set it to full. 2368 */ 2369 if (hw->fc.requested_mode == ixgbe_fc_default) 2370 hw->fc.requested_mode = ixgbe_fc_full; 2371 2372 /* 2373 * Set up the 1G and 10G flow control advertisement registers so the 2374 * HW will be able to do fc autoneg once the cable is plugged in. If 2375 * we link at 10G, the 1G advertisement is harmless and vice versa. 2376 */ 2377 2378 switch (hw->phy.media_type) { 2379 case ixgbe_media_type_fiber: 2380 case ixgbe_media_type_backplane: 2381 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 2382 reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2383 break; 2384 2385 case ixgbe_media_type_copper: 2386 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 2387 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu); 2388 break; 2389 2390 default: 2391 ; 2392 } 2393 2394 /* 2395 * The possible values of fc.requested_mode are: 2396 * 0: Flow control is completely disabled 2397 * 1: Rx flow control is enabled (we can receive pause frames, 2398 * but not send pause frames). 2399 * 2: Tx flow control is enabled (we can send pause frames but 2400 * we do not support receiving pause frames). 2401 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2402 * other: Invalid. 2403 */ 2404 switch (hw->fc.requested_mode) { 2405 case ixgbe_fc_none: 2406 /* Flow control completely disabled by software override. */ 2407 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 2408 if (hw->phy.media_type == ixgbe_media_type_backplane) 2409 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE | 2410 IXGBE_AUTOC_ASM_PAUSE); 2411 else if (hw->phy.media_type == ixgbe_media_type_copper) 2412 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); 2413 break; 2414 case ixgbe_fc_rx_pause: 2415 /* 2416 * Rx Flow control is enabled and Tx Flow control is 2417 * disabled by software override. Since there really 2418 * isn't a way to advertise that we are capable of RX 2419 * Pause ONLY, we will advertise that we support both 2420 * symmetric and asymmetric Rx PAUSE. Later, we will 2421 * disable the adapter's ability to send PAUSE frames. 2422 */ 2423 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 2424 if (hw->phy.media_type == ixgbe_media_type_backplane) 2425 reg_bp |= (IXGBE_AUTOC_SYM_PAUSE | 2426 IXGBE_AUTOC_ASM_PAUSE); 2427 else if (hw->phy.media_type == ixgbe_media_type_copper) 2428 reg_cu |= (IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); 2429 break; 2430 case ixgbe_fc_tx_pause: 2431 /* 2432 * Tx Flow control is enabled, and Rx Flow control is 2433 * disabled by software override. 2434 */ 2435 reg |= (IXGBE_PCS1GANA_ASM_PAUSE); 2436 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE); 2437 if (hw->phy.media_type == ixgbe_media_type_backplane) { 2438 reg_bp |= (IXGBE_AUTOC_ASM_PAUSE); 2439 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE); 2440 } else if (hw->phy.media_type == ixgbe_media_type_copper) { 2441 reg_cu |= (IXGBE_TAF_ASM_PAUSE); 2442 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE); 2443 } 2444 break; 2445 case ixgbe_fc_full: 2446 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2447 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 2448 if (hw->phy.media_type == ixgbe_media_type_backplane) 2449 reg_bp |= (IXGBE_AUTOC_SYM_PAUSE | 2450 IXGBE_AUTOC_ASM_PAUSE); 2451 else if (hw->phy.media_type == ixgbe_media_type_copper) 2452 reg_cu |= (IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); 2453 break; 2454 default: 2455 DEBUGOUT("Flow control param set incorrectly\n"); 2456 ret_val = IXGBE_ERR_CONFIG; 2457 goto out; 2458 break; 2459 } 2460 2461 /* 2462 * Enable auto-negotiation between the MAC & PHY; 2463 * the MAC will advertise clause 37 flow control. 2464 */ 2465 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 2466 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 2467 2468 /* Disable AN timeout */ 2469 if (hw->fc.strict_ieee) 2470 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 2471 2472 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 2473 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 2474 2475 /* 2476 * AUTOC restart handles negotiation of 1G and 10G on backplane 2477 * and copper. There is no need to set the PCS1GCTL register. 2478 * 2479 */ 2480 if (hw->phy.media_type == ixgbe_media_type_backplane) { 2481 reg_bp |= IXGBE_AUTOC_AN_RESTART; 2482 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp); 2483 } else if ((hw->phy.media_type == ixgbe_media_type_copper) && 2484 (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)) { 2485 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 2486 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu); 2487 } 2488 2489 DEBUGOUT1("Set up FC; IXGBE_AUTOC = 0x%08X\n", reg); 2490 out: 2491 return ret_val; 2492 } 2493 2494 /** 2495 * ixgbe_disable_pcie_master - Disable PCI-express master access 2496 * @hw: pointer to hardware structure 2497 * 2498 * Disables PCI-Express master access and verifies there are no pending 2499 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 2500 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS 2501 * is returned signifying master requests disabled. 2502 **/ 2503 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 2504 { 2505 u32 i; 2506 u32 reg_val; 2507 u32 number_of_queues; 2508 s32 status = IXGBE_SUCCESS; 2509 2510 DEBUGFUNC("ixgbe_disable_pcie_master"); 2511 2512 /* Just jump out if bus mastering is already disabled */ 2513 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 2514 goto out; 2515 2516 /* Disable the receive unit by stopping each queue */ 2517 number_of_queues = hw->mac.max_rx_queues; 2518 for (i = 0; i < number_of_queues; i++) { 2519 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 2520 if (reg_val & IXGBE_RXDCTL_ENABLE) { 2521 reg_val &= ~IXGBE_RXDCTL_ENABLE; 2522 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 2523 } 2524 } 2525 2526 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL); 2527 reg_val |= IXGBE_CTRL_GIO_DIS; 2528 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val); 2529 2530 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2531 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 2532 goto check_device_status; 2533 usec_delay(100); 2534 } 2535 2536 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n"); 2537 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 2538 2539 /* 2540 * Before proceeding, make sure that the PCIe block does not have 2541 * transactions pending. 2542 */ 2543 check_device_status: 2544 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2545 if (!(IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS) & 2546 IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 2547 break; 2548 usec_delay(100); 2549 } 2550 2551 if (i == IXGBE_PCI_MASTER_DISABLE_TIMEOUT) 2552 DEBUGOUT("PCIe transaction pending bit also did not clear.\n"); 2553 else 2554 goto out; 2555 2556 /* 2557 * Two consecutive resets are required via CTRL.RST per datasheet 2558 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine 2559 * of this need. The first reset prevents new master requests from 2560 * being issued by our device. We then must wait 1usec for any 2561 * remaining completions from the PCIe bus to trickle in, and then reset 2562 * again to clear out any effects they may have had on our device. 2563 */ 2564 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 2565 2566 out: 2567 return status; 2568 } 2569 2570 2571 /** 2572 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 2573 * @hw: pointer to hardware structure 2574 * @mask: Mask to specify which semaphore to acquire 2575 * 2576 * Acquires the SWFW semaphore thought the GSSR register for the specified 2577 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2578 **/ 2579 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) 2580 { 2581 u32 gssr; 2582 u32 swmask = mask; 2583 u32 fwmask = mask << 5; 2584 s32 timeout = 200; 2585 2586 DEBUGFUNC("ixgbe_acquire_swfw_sync"); 2587 2588 while (timeout) { 2589 /* 2590 * SW EEPROM semaphore bit is used for access to all 2591 * SW_FW_SYNC/GSSR bits (not just EEPROM) 2592 */ 2593 if (ixgbe_get_eeprom_semaphore(hw)) 2594 return IXGBE_ERR_SWFW_SYNC; 2595 2596 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2597 if (!(gssr & (fwmask | swmask))) 2598 break; 2599 2600 /* 2601 * Firmware currently using resource (fwmask) or other software 2602 * thread currently using resource (swmask) 2603 */ 2604 ixgbe_release_eeprom_semaphore(hw); 2605 msec_delay(5); 2606 timeout--; 2607 } 2608 2609 if (!timeout) { 2610 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 2611 return IXGBE_ERR_SWFW_SYNC; 2612 } 2613 2614 gssr |= swmask; 2615 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2616 2617 ixgbe_release_eeprom_semaphore(hw); 2618 return IXGBE_SUCCESS; 2619 } 2620 2621 /** 2622 * ixgbe_release_swfw_sync - Release SWFW semaphore 2623 * @hw: pointer to hardware structure 2624 * @mask: Mask to specify which semaphore to release 2625 * 2626 * Releases the SWFW semaphore thought the GSSR register for the specified 2627 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2628 **/ 2629 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask) 2630 { 2631 u32 gssr; 2632 u32 swmask = mask; 2633 2634 DEBUGFUNC("ixgbe_release_swfw_sync"); 2635 2636 ixgbe_get_eeprom_semaphore(hw); 2637 2638 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2639 gssr &= ~swmask; 2640 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2641 2642 ixgbe_release_eeprom_semaphore(hw); 2643 } 2644 2645 /** 2646 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 2647 * @hw: pointer to hardware structure 2648 * @regval: register value to write to RXCTRL 2649 * 2650 * Enables the Rx DMA unit 2651 **/ 2652 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 2653 { 2654 DEBUGFUNC("ixgbe_enable_rx_dma_generic"); 2655 2656 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); 2657 2658 return IXGBE_SUCCESS; 2659 } 2660 2661 /** 2662 * ixgbe_blink_led_start_generic - Blink LED based on index. 2663 * @hw: pointer to hardware structure 2664 * @index: led number to blink 2665 **/ 2666 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 2667 { 2668 ixgbe_link_speed speed = 0; 2669 bool link_up = 0; 2670 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2671 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2672 2673 DEBUGFUNC("ixgbe_blink_led_start_generic"); 2674 2675 /* 2676 * Link must be up to auto-blink the LEDs; 2677 * Force it if link is down. 2678 */ 2679 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 2680 2681 if (!link_up) { 2682 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2683 autoc_reg |= IXGBE_AUTOC_FLU; 2684 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2685 msec_delay(10); 2686 } 2687 2688 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2689 led_reg |= IXGBE_LED_BLINK(index); 2690 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2691 IXGBE_WRITE_FLUSH(hw); 2692 2693 return IXGBE_SUCCESS; 2694 } 2695 2696 /** 2697 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 2698 * @hw: pointer to hardware structure 2699 * @index: led number to stop blinking 2700 **/ 2701 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 2702 { 2703 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2704 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2705 2706 DEBUGFUNC("ixgbe_blink_led_stop_generic"); 2707 2708 2709 autoc_reg &= ~IXGBE_AUTOC_FLU; 2710 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2711 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2712 2713 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2714 led_reg &= ~IXGBE_LED_BLINK(index); 2715 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 2716 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2717 IXGBE_WRITE_FLUSH(hw); 2718 2719 return IXGBE_SUCCESS; 2720 } 2721 2722 /** 2723 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM 2724 * @hw: pointer to hardware structure 2725 * @san_mac_offset: SAN MAC address offset 2726 * 2727 * This function will read the EEPROM location for the SAN MAC address 2728 * pointer, and returns the value at that location. This is used in both 2729 * get and set mac_addr routines. 2730 **/ 2731 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 2732 u16 *san_mac_offset) 2733 { 2734 DEBUGFUNC("ixgbe_get_san_mac_addr_offset"); 2735 2736 /* 2737 * First read the EEPROM pointer to see if the MAC addresses are 2738 * available. 2739 */ 2740 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset); 2741 2742 return IXGBE_SUCCESS; 2743 } 2744 2745 /** 2746 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM 2747 * @hw: pointer to hardware structure 2748 * @san_mac_addr: SAN MAC address 2749 * 2750 * Reads the SAN MAC address from the EEPROM, if it's available. This is 2751 * per-port, so set_lan_id() must be called before reading the addresses. 2752 * set_lan_id() is called by identify_sfp(), but this cannot be relied 2753 * upon for non-SFP connections, so we must call it here. 2754 **/ 2755 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 2756 { 2757 u16 san_mac_data, san_mac_offset; 2758 u8 i; 2759 2760 DEBUGFUNC("ixgbe_get_san_mac_addr_generic"); 2761 2762 /* 2763 * First read the EEPROM pointer to see if the MAC addresses are 2764 * available. If they're not, no point in calling set_lan_id() here. 2765 */ 2766 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 2767 2768 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) { 2769 /* 2770 * No addresses available in this EEPROM. It's not an 2771 * error though, so just wipe the local address and return. 2772 */ 2773 for (i = 0; i < 6; i++) 2774 san_mac_addr[i] = 0xFF; 2775 2776 goto san_mac_addr_out; 2777 } 2778 2779 /* make sure we know which port we need to program */ 2780 hw->mac.ops.set_lan_id(hw); 2781 /* apply the port offset to the address offset */ 2782 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 2783 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 2784 for (i = 0; i < 3; i++) { 2785 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data); 2786 san_mac_addr[i * 2] = (u8)(san_mac_data); 2787 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 2788 san_mac_offset++; 2789 } 2790 2791 san_mac_addr_out: 2792 return IXGBE_SUCCESS; 2793 } 2794 2795 /** 2796 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM 2797 * @hw: pointer to hardware structure 2798 * @san_mac_addr: SAN MAC address 2799 * 2800 * Write a SAN MAC address to the EEPROM. 2801 **/ 2802 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 2803 { 2804 s32 status = IXGBE_SUCCESS; 2805 u16 san_mac_data, san_mac_offset; 2806 u8 i; 2807 2808 DEBUGFUNC("ixgbe_set_san_mac_addr_generic"); 2809 2810 /* Look for SAN mac address pointer. If not defined, return */ 2811 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 2812 2813 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) { 2814 status = IXGBE_ERR_NO_SAN_ADDR_PTR; 2815 goto san_mac_addr_out; 2816 } 2817 2818 /* Make sure we know which port we need to write */ 2819 hw->mac.ops.set_lan_id(hw); 2820 /* Apply the port offset to the address offset */ 2821 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 2822 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 2823 2824 for (i = 0; i < 3; i++) { 2825 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8); 2826 san_mac_data |= (u16)(san_mac_addr[i * 2]); 2827 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data); 2828 san_mac_offset++; 2829 } 2830 2831 san_mac_addr_out: 2832 return status; 2833 } 2834 2835 /** 2836 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count 2837 * @hw: pointer to hardware structure 2838 * 2839 * Read PCIe configuration space, and get the MSI-X vector count from 2840 * the capabilities table. 2841 **/ 2842 u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) 2843 { 2844 u32 msix_count = 64; 2845 2846 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic"); 2847 if (hw->mac.msix_vectors_from_pcie) { 2848 msix_count = IXGBE_READ_PCIE_WORD(hw, 2849 IXGBE_PCIE_MSIX_82599_CAPS); 2850 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 2851 2852 /* MSI-X count is zero-based in HW, so increment to give 2853 * proper value */ 2854 msix_count++; 2855 } 2856 2857 return msix_count; 2858 } 2859 2860 /** 2861 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address 2862 * @hw: pointer to hardware structure 2863 * @addr: Address to put into receive address register 2864 * @vmdq: VMDq pool to assign 2865 * 2866 * Puts an ethernet address into a receive address register, or 2867 * finds the rar that it is aleady in; adds to the pool list 2868 **/ 2869 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 2870 { 2871 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF; 2872 u32 first_empty_rar = NO_EMPTY_RAR_FOUND; 2873 u32 rar; 2874 u32 rar_low, rar_high; 2875 u32 addr_low, addr_high; 2876 2877 DEBUGFUNC("ixgbe_insert_mac_addr_generic"); 2878 2879 /* swap bytes for HW little endian */ 2880 addr_low = addr[0] | (addr[1] << 8) 2881 | (addr[2] << 16) 2882 | (addr[3] << 24); 2883 addr_high = addr[4] | (addr[5] << 8); 2884 2885 /* 2886 * Either find the mac_id in rar or find the first empty space. 2887 * rar_highwater points to just after the highest currently used 2888 * rar in order to shorten the search. It grows when we add a new 2889 * rar to the top. 2890 */ 2891 for (rar = 0; rar < hw->mac.rar_highwater; rar++) { 2892 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 2893 2894 if (((IXGBE_RAH_AV & rar_high) == 0) 2895 && first_empty_rar == NO_EMPTY_RAR_FOUND) { 2896 first_empty_rar = rar; 2897 } else if ((rar_high & 0xFFFF) == addr_high) { 2898 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar)); 2899 if (rar_low == addr_low) 2900 break; /* found it already in the rars */ 2901 } 2902 } 2903 2904 if (rar < hw->mac.rar_highwater) { 2905 /* already there so just add to the pool bits */ 2906 ixgbe_set_vmdq(hw, rar, vmdq); 2907 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) { 2908 /* stick it into first empty RAR slot we found */ 2909 rar = first_empty_rar; 2910 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 2911 } else if (rar == hw->mac.rar_highwater) { 2912 /* add it to the top of the list and inc the highwater mark */ 2913 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 2914 hw->mac.rar_highwater++; 2915 } else if (rar >= hw->mac.num_rar_entries) { 2916 return IXGBE_ERR_INVALID_MAC_ADDR; 2917 } 2918 2919 /* 2920 * If we found rar[0], make sure the default pool bit (we use pool 0) 2921 * remains cleared to be sure default pool packets will get delivered 2922 */ 2923 if (rar == 0) 2924 ixgbe_clear_vmdq(hw, rar, 0); 2925 2926 return rar; 2927 } 2928 2929 /** 2930 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address 2931 * @hw: pointer to hardware struct 2932 * @rar: receive address register index to disassociate 2933 * @vmdq: VMDq pool index to remove from the rar 2934 **/ 2935 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 2936 { 2937 u32 mpsar_lo, mpsar_hi; 2938 u32 rar_entries = hw->mac.num_rar_entries; 2939 2940 DEBUGFUNC("ixgbe_clear_vmdq_generic"); 2941 2942 /* Make sure we are using a valid rar index range */ 2943 if (rar >= rar_entries) { 2944 DEBUGOUT1("RAR index %d is out of range.\n", rar); 2945 return IXGBE_ERR_INVALID_ARGUMENT; 2946 } 2947 2948 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 2949 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 2950 2951 if (!mpsar_lo && !mpsar_hi) 2952 goto done; 2953 2954 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 2955 if (mpsar_lo) { 2956 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 2957 mpsar_lo = 0; 2958 } 2959 if (mpsar_hi) { 2960 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 2961 mpsar_hi = 0; 2962 } 2963 } else if (vmdq < 32) { 2964 mpsar_lo &= ~(1 << vmdq); 2965 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 2966 } else { 2967 mpsar_hi &= ~(1 << (vmdq - 32)); 2968 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 2969 } 2970 2971 /* was that the last pool using this rar? */ 2972 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0) 2973 hw->mac.ops.clear_rar(hw, rar); 2974 done: 2975 return IXGBE_SUCCESS; 2976 } 2977 2978 /** 2979 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 2980 * @hw: pointer to hardware struct 2981 * @rar: receive address register index to associate with a VMDq index 2982 * @vmdq: VMDq pool index 2983 **/ 2984 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 2985 { 2986 u32 mpsar; 2987 u32 rar_entries = hw->mac.num_rar_entries; 2988 2989 DEBUGFUNC("ixgbe_set_vmdq_generic"); 2990 2991 /* Make sure we are using a valid rar index range */ 2992 if (rar >= rar_entries) { 2993 DEBUGOUT1("RAR index %d is out of range.\n", rar); 2994 return IXGBE_ERR_INVALID_ARGUMENT; 2995 } 2996 2997 if (vmdq < 32) { 2998 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 2999 mpsar |= 1 << vmdq; 3000 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 3001 } else { 3002 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3003 mpsar |= 1 << (vmdq - 32); 3004 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 3005 } 3006 return IXGBE_SUCCESS; 3007 } 3008 3009 /** 3010 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array 3011 * @hw: pointer to hardware structure 3012 **/ 3013 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 3014 { 3015 int i; 3016 3017 DEBUGFUNC("ixgbe_init_uta_tables_generic"); 3018 DEBUGOUT(" Clearing UTA\n"); 3019 3020 for (i = 0; i < 128; i++) 3021 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 3022 3023 return IXGBE_SUCCESS; 3024 } 3025 3026 /** 3027 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 3028 * @hw: pointer to hardware structure 3029 * @vlan: VLAN id to write to VLAN filter 3030 * 3031 * return the VLVF index where this VLAN id should be placed 3032 * 3033 **/ 3034 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan) 3035 { 3036 u32 bits = 0; 3037 u32 first_empty_slot = 0; 3038 s32 regindex; 3039 3040 /* short cut the special case */ 3041 if (vlan == 0) 3042 return 0; 3043 3044 /* 3045 * Search for the vlan id in the VLVF entries. Save off the first empty 3046 * slot found along the way 3047 */ 3048 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) { 3049 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 3050 if (!bits && !(first_empty_slot)) 3051 first_empty_slot = regindex; 3052 else if ((bits & 0x0FFF) == vlan) 3053 break; 3054 } 3055 3056 /* 3057 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan 3058 * in the VLVF. Else use the first empty VLVF register for this 3059 * vlan id. 3060 */ 3061 if (regindex >= IXGBE_VLVF_ENTRIES) { 3062 if (first_empty_slot) 3063 regindex = first_empty_slot; 3064 else { 3065 DEBUGOUT("No space in VLVF.\n"); 3066 regindex = IXGBE_ERR_NO_SPACE; 3067 } 3068 } 3069 3070 return regindex; 3071 } 3072 3073 /** 3074 * ixgbe_set_vfta_generic - Set VLAN filter table 3075 * @hw: pointer to hardware structure 3076 * @vlan: VLAN id to write to VLAN filter 3077 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 3078 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 3079 * 3080 * Turn on/off specified VLAN in the VLAN filter table. 3081 **/ 3082 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 3083 bool vlan_on) 3084 { 3085 s32 regindex; 3086 u32 bitindex; 3087 u32 vfta; 3088 u32 bits; 3089 u32 vt; 3090 u32 targetbit; 3091 bool vfta_changed = FALSE; 3092 3093 DEBUGFUNC("ixgbe_set_vfta_generic"); 3094 3095 if (vlan > 4095) 3096 return IXGBE_ERR_PARAM; 3097 3098 /* 3099 * this is a 2 part operation - first the VFTA, then the 3100 * VLVF and VLVFB if VT Mode is set 3101 * We don't write the VFTA until we know the VLVF part succeeded. 3102 */ 3103 3104 /* Part 1 3105 * The VFTA is a bitstring made up of 128 32-bit registers 3106 * that enable the particular VLAN id, much like the MTA: 3107 * bits[11-5]: which register 3108 * bits[4-0]: which bit in the register 3109 */ 3110 regindex = (vlan >> 5) & 0x7F; 3111 bitindex = vlan & 0x1F; 3112 targetbit = (1 << bitindex); 3113 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 3114 3115 if (vlan_on) { 3116 if (!(vfta & targetbit)) { 3117 vfta |= targetbit; 3118 vfta_changed = TRUE; 3119 } 3120 } else { 3121 if ((vfta & targetbit)) { 3122 vfta &= ~targetbit; 3123 vfta_changed = TRUE; 3124 } 3125 } 3126 3127 /* Part 2 3128 * If VT Mode is set 3129 * Either vlan_on 3130 * make sure the vlan is in VLVF 3131 * set the vind bit in the matching VLVFB 3132 * Or !vlan_on 3133 * clear the pool bit and possibly the vind 3134 */ 3135 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 3136 if (vt & IXGBE_VT_CTL_VT_ENABLE) { 3137 s32 vlvf_index; 3138 3139 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan); 3140 if (vlvf_index < 0) 3141 return vlvf_index; 3142 3143 if (vlan_on) { 3144 /* set the pool bit */ 3145 if (vind < 32) { 3146 bits = IXGBE_READ_REG(hw, 3147 IXGBE_VLVFB(vlvf_index*2)); 3148 bits |= (1 << vind); 3149 IXGBE_WRITE_REG(hw, 3150 IXGBE_VLVFB(vlvf_index*2), 3151 bits); 3152 } else { 3153 bits = IXGBE_READ_REG(hw, 3154 IXGBE_VLVFB((vlvf_index*2)+1)); 3155 bits |= (1 << (vind-32)); 3156 IXGBE_WRITE_REG(hw, 3157 IXGBE_VLVFB((vlvf_index*2)+1), 3158 bits); 3159 } 3160 } else { 3161 /* clear the pool bit */ 3162 if (vind < 32) { 3163 bits = IXGBE_READ_REG(hw, 3164 IXGBE_VLVFB(vlvf_index*2)); 3165 bits &= ~(1 << vind); 3166 IXGBE_WRITE_REG(hw, 3167 IXGBE_VLVFB(vlvf_index*2), 3168 bits); 3169 bits |= IXGBE_READ_REG(hw, 3170 IXGBE_VLVFB((vlvf_index*2)+1)); 3171 } else { 3172 bits = IXGBE_READ_REG(hw, 3173 IXGBE_VLVFB((vlvf_index*2)+1)); 3174 bits &= ~(1 << (vind-32)); 3175 IXGBE_WRITE_REG(hw, 3176 IXGBE_VLVFB((vlvf_index*2)+1), 3177 bits); 3178 bits |= IXGBE_READ_REG(hw, 3179 IXGBE_VLVFB(vlvf_index*2)); 3180 } 3181 } 3182 3183 /* 3184 * If there are still bits set in the VLVFB registers 3185 * for the VLAN ID indicated we need to see if the 3186 * caller is requesting that we clear the VFTA entry bit. 3187 * If the caller has requested that we clear the VFTA 3188 * entry bit but there are still pools/VFs using this VLAN 3189 * ID entry then ignore the request. We're not worried 3190 * about the case where we're turning the VFTA VLAN ID 3191 * entry bit on, only when requested to turn it off as 3192 * there may be multiple pools and/or VFs using the 3193 * VLAN ID entry. In that case we cannot clear the 3194 * VFTA bit until all pools/VFs using that VLAN ID have also 3195 * been cleared. This will be indicated by "bits" being 3196 * zero. 3197 */ 3198 if (bits) { 3199 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 3200 (IXGBE_VLVF_VIEN | vlan)); 3201 if (!vlan_on) { 3202 /* someone wants to clear the vfta entry 3203 * but some pools/VFs are still using it. 3204 * Ignore it. */ 3205 vfta_changed = FALSE; 3206 } 3207 } 3208 else 3209 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); 3210 } 3211 3212 if (vfta_changed) 3213 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta); 3214 3215 return IXGBE_SUCCESS; 3216 } 3217 3218 /** 3219 * ixgbe_clear_vfta_generic - Clear VLAN filter table 3220 * @hw: pointer to hardware structure 3221 * 3222 * Clears the VLAN filer table, and the VMDq index associated with the filter 3223 **/ 3224 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 3225 { 3226 u32 offset; 3227 3228 DEBUGFUNC("ixgbe_clear_vfta_generic"); 3229 3230 for (offset = 0; offset < hw->mac.vft_size; offset++) 3231 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 3232 3233 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 3234 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 3235 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0); 3236 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0); 3237 } 3238 3239 return IXGBE_SUCCESS; 3240 } 3241 3242 /** 3243 * ixgbe_check_mac_link_generic - Determine link and speed status 3244 * @hw: pointer to hardware structure 3245 * @speed: pointer to link speed 3246 * @link_up: TRUE when link is up 3247 * @link_up_wait_to_complete: bool used to wait for link up or not 3248 * 3249 * Reads the links register to determine if link is up and the current speed 3250 **/ 3251 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 3252 bool *link_up, bool link_up_wait_to_complete) 3253 { 3254 u32 links_reg, links_orig; 3255 u32 i; 3256 3257 DEBUGFUNC("ixgbe_check_mac_link_generic"); 3258 3259 /* clear the old state */ 3260 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); 3261 3262 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 3263 3264 if (links_orig != links_reg) { 3265 DEBUGOUT2("LINKS changed from %08X to %08X\n", 3266 links_orig, links_reg); 3267 } 3268 3269 if (link_up_wait_to_complete) { 3270 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 3271 if (links_reg & IXGBE_LINKS_UP) { 3272 *link_up = TRUE; 3273 break; 3274 } else { 3275 *link_up = FALSE; 3276 } 3277 msec_delay(100); 3278 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 3279 } 3280 } else { 3281 if (links_reg & IXGBE_LINKS_UP) 3282 *link_up = TRUE; 3283 else 3284 *link_up = FALSE; 3285 } 3286 3287 if ((links_reg & IXGBE_LINKS_SPEED_82599) == 3288 IXGBE_LINKS_SPEED_10G_82599) 3289 *speed = IXGBE_LINK_SPEED_10GB_FULL; 3290 else if ((links_reg & IXGBE_LINKS_SPEED_82599) == 3291 IXGBE_LINKS_SPEED_1G_82599) 3292 *speed = IXGBE_LINK_SPEED_1GB_FULL; 3293 else if ((links_reg & IXGBE_LINKS_SPEED_82599) == 3294 IXGBE_LINKS_SPEED_100_82599) 3295 *speed = IXGBE_LINK_SPEED_100_FULL; 3296 else 3297 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3298 3299 /* if link is down, zero out the current_mode */ 3300 if (*link_up == FALSE) { 3301 hw->fc.current_mode = ixgbe_fc_none; 3302 hw->fc.fc_was_autonegged = FALSE; 3303 } 3304 3305 return IXGBE_SUCCESS; 3306 } 3307 3308 /** 3309 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from 3310 * the EEPROM 3311 * @hw: pointer to hardware structure 3312 * @wwnn_prefix: the alternative WWNN prefix 3313 * @wwpn_prefix: the alternative WWPN prefix 3314 * 3315 * This function will read the EEPROM from the alternative SAN MAC address 3316 * block to check the support for the alternative WWNN/WWPN prefix support. 3317 **/ 3318 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 3319 u16 *wwpn_prefix) 3320 { 3321 u16 offset, caps; 3322 u16 alt_san_mac_blk_offset; 3323 3324 DEBUGFUNC("ixgbe_get_wwn_prefix_generic"); 3325 3326 /* clear output first */ 3327 *wwnn_prefix = 0xFFFF; 3328 *wwpn_prefix = 0xFFFF; 3329 3330 /* check if alternative SAN MAC is supported */ 3331 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR, 3332 &alt_san_mac_blk_offset); 3333 3334 if ((alt_san_mac_blk_offset == 0) || 3335 (alt_san_mac_blk_offset == 0xFFFF)) 3336 goto wwn_prefix_out; 3337 3338 /* check capability in alternative san mac address block */ 3339 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 3340 hw->eeprom.ops.read(hw, offset, &caps); 3341 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) 3342 goto wwn_prefix_out; 3343 3344 /* get the corresponding prefix for WWNN/WWPN */ 3345 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 3346 hw->eeprom.ops.read(hw, offset, wwnn_prefix); 3347 3348 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 3349 hw->eeprom.ops.read(hw, offset, wwpn_prefix); 3350 3351 wwn_prefix_out: 3352 return IXGBE_SUCCESS; 3353 } 3354 3355 /** 3356 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM 3357 * @hw: pointer to hardware structure 3358 * @bs: the fcoe boot status 3359 * 3360 * This function will read the FCOE boot status from the iSCSI FCOE block 3361 **/ 3362 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs) 3363 { 3364 u16 offset, caps, flags; 3365 s32 status; 3366 3367 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic"); 3368 3369 /* clear output first */ 3370 *bs = ixgbe_fcoe_bootstatus_unavailable; 3371 3372 /* check if FCOE IBA block is present */ 3373 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR; 3374 status = hw->eeprom.ops.read(hw, offset, &caps); 3375 if (status != IXGBE_SUCCESS) 3376 goto out; 3377 3378 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE)) 3379 goto out; 3380 3381 /* check if iSCSI FCOE block is populated */ 3382 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset); 3383 if (status != IXGBE_SUCCESS) 3384 goto out; 3385 3386 if ((offset == 0) || (offset == 0xFFFF)) 3387 goto out; 3388 3389 /* read fcoe flags in iSCSI FCOE block */ 3390 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET; 3391 status = hw->eeprom.ops.read(hw, offset, &flags); 3392 if (status != IXGBE_SUCCESS) 3393 goto out; 3394 3395 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE) 3396 *bs = ixgbe_fcoe_bootstatus_enabled; 3397 else 3398 *bs = ixgbe_fcoe_bootstatus_disabled; 3399 3400 out: 3401 return status; 3402 } 3403 3404 /** 3405 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow 3406 * control 3407 * @hw: pointer to hardware structure 3408 * 3409 * There are several phys that do not support autoneg flow control. This 3410 * function check the device id to see if the associated phy supports 3411 * autoneg flow control. 3412 **/ 3413 static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) 3414 { 3415 3416 DEBUGFUNC("ixgbe_device_supports_autoneg_fc"); 3417 3418 switch (hw->device_id) { 3419 case IXGBE_DEV_ID_82599_T3_LOM: 3420 return IXGBE_SUCCESS; 3421 default: 3422 return IXGBE_ERR_FC_NOT_SUPPORTED; 3423 } 3424 } 3425 3426 /** 3427 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing 3428 * @hw: pointer to hardware structure 3429 * @enable: enable or disable switch for anti-spoofing 3430 * @pf: Physical Function pool - do not enable anti-spoofing for the PF 3431 * 3432 **/ 3433 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf) 3434 { 3435 int j; 3436 int pf_target_reg = pf >> 3; 3437 int pf_target_shift = pf % 8; 3438 u32 pfvfspoof = 0; 3439 3440 if (hw->mac.type == ixgbe_mac_82598EB) 3441 return; 3442 3443 if (enable) 3444 pfvfspoof = IXGBE_SPOOF_MACAS_MASK; 3445 3446 /* 3447 * PFVFSPOOF register array is size 8 with 8 bits assigned to 3448 * MAC anti-spoof enables in each register array element. 3449 */ 3450 for (j = 0; j < IXGBE_PFVFSPOOF_REG_COUNT; j++) 3451 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof); 3452 3453 /* If not enabling anti-spoofing then done */ 3454 if (!enable) 3455 return; 3456 3457 /* 3458 * The PF should be allowed to spoof so that it can support 3459 * emulation mode NICs. Reset the bit assigned to the PF 3460 */ 3461 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg)); 3462 pfvfspoof ^= (1 << pf_target_shift); 3463 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg), pfvfspoof); 3464 } 3465 3466 /** 3467 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing 3468 * @hw: pointer to hardware structure 3469 * @enable: enable or disable switch for VLAN anti-spoofing 3470 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing 3471 * 3472 **/ 3473 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 3474 { 3475 int vf_target_reg = vf >> 3; 3476 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT; 3477 u32 pfvfspoof; 3478 3479 if (hw->mac.type == ixgbe_mac_82598EB) 3480 return; 3481 3482 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3483 if (enable) 3484 pfvfspoof |= (1 << vf_target_shift); 3485 else 3486 pfvfspoof &= ~(1 << vf_target_shift); 3487 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3488 } 3489 3490 /** 3491 * ixgbe_get_device_caps_generic - Get additional device capabilities 3492 * @hw: pointer to hardware structure 3493 * @device_caps: the EEPROM word with the extra device capabilities 3494 * 3495 * This function will read the EEPROM location for the device capabilities, 3496 * and return the word through device_caps. 3497 **/ 3498 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) 3499 { 3500 DEBUGFUNC("ixgbe_get_device_caps_generic"); 3501 3502 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); 3503 3504 return IXGBE_SUCCESS; 3505 } 3506 3507 /** 3508 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering 3509 * @hw: pointer to hardware structure 3510 * 3511 **/ 3512 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw) 3513 { 3514 u32 regval; 3515 u32 i; 3516 3517 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2"); 3518 3519 /* Enable relaxed ordering */ 3520 for (i = 0; i < hw->mac.max_tx_queues; i++) { 3521 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 3522 regval |= IXGBE_DCA_TXCTRL_TX_WB_RO_EN; 3523 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 3524 } 3525 3526 for (i = 0; i < hw->mac.max_rx_queues; i++) { 3527 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 3528 regval |= (IXGBE_DCA_RXCTRL_DESC_WRO_EN | 3529 IXGBE_DCA_RXCTRL_DESC_HSRO_EN); 3530 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 3531 } 3532 3533 } 3534