1 /****************************************************************************** 2 3 Copyright (c) 2001-2012, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_api.c 238149 2012-07-05 20:51:44Z jfv $*/ 34 /*$NetBSD: ixgbe_api.c,v 1.6 2015/04/02 09:26:55 msaitoh Exp $*/ 35 36 #include "ixgbe_api.h" 37 #include "ixgbe_common.h" 38 39 /** 40 * ixgbe_init_shared_code - Initialize the shared code 41 * @hw: pointer to hardware structure 42 * 43 * This will assign function pointers and assign the MAC type and PHY code. 44 * Does not touch the hardware. This function must be called prior to any 45 * other function in the shared code. The ixgbe_hw structure should be 46 * memset to 0 prior to calling this function. The following fields in 47 * hw structure should be filled in prior to calling this function: 48 * back, device_id, vendor_id, subsystem_device_id, 49 * subsystem_vendor_id, and revision_id 50 **/ 51 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw) 52 { 53 s32 status; 54 55 DEBUGFUNC("ixgbe_init_shared_code"); 56 57 /* 58 * Set the mac type 59 */ 60 ixgbe_set_mac_type(hw); 61 62 switch (hw->mac.type) { 63 case ixgbe_mac_82598EB: 64 status = ixgbe_init_ops_82598(hw); 65 break; 66 case ixgbe_mac_82599EB: 67 status = ixgbe_init_ops_82599(hw); 68 break; 69 case ixgbe_mac_82599_vf: 70 case ixgbe_mac_X540_vf: 71 status = ixgbe_init_ops_vf(hw); 72 break; 73 case ixgbe_mac_X540: 74 status = ixgbe_init_ops_X540(hw); 75 break; 76 default: 77 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 78 break; 79 } 80 81 return status; 82 } 83 84 /** 85 * ixgbe_set_mac_type - Sets MAC type 86 * @hw: pointer to the HW structure 87 * 88 * This function sets the mac type of the adapter based on the 89 * vendor ID and device ID stored in the hw structure. 90 **/ 91 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw) 92 { 93 s32 ret_val = IXGBE_SUCCESS; 94 95 DEBUGFUNC("ixgbe_set_mac_type\n"); 96 97 if (hw->vendor_id == IXGBE_INTEL_VENDOR_ID) { 98 switch (hw->device_id) { 99 case IXGBE_DEV_ID_82598: 100 case IXGBE_DEV_ID_82598_BX: 101 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 102 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 103 case IXGBE_DEV_ID_82598AT: 104 case IXGBE_DEV_ID_82598AT2: 105 case IXGBE_DEV_ID_82598EB_CX4: 106 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 107 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 108 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 109 case IXGBE_DEV_ID_82598EB_XF_LR: 110 case IXGBE_DEV_ID_82598EB_SFP_LOM: 111 hw->mac.type = ixgbe_mac_82598EB; 112 break; 113 case IXGBE_DEV_ID_82599_KX4: 114 case IXGBE_DEV_ID_82599_KX4_MEZZ: 115 case IXGBE_DEV_ID_82599_XAUI_LOM: 116 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 117 case IXGBE_DEV_ID_82599_KR: 118 case IXGBE_DEV_ID_82599_SFP: 119 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 120 case IXGBE_DEV_ID_82599_SFP_FCOE: 121 case IXGBE_DEV_ID_82599_SFP_EM: 122 case IXGBE_DEV_ID_82599_SFP_SF2: 123 case IXGBE_DEV_ID_82599_SFP_SF_QP: 124 case IXGBE_DEV_ID_82599EN_SFP: 125 case IXGBE_DEV_ID_82599_CX4: 126 case IXGBE_DEV_ID_82599_T3_LOM: 127 hw->mac.type = ixgbe_mac_82599EB; 128 break; 129 case IXGBE_DEV_ID_82599_VF: 130 hw->mac.type = ixgbe_mac_82599_vf; 131 break; 132 case IXGBE_DEV_ID_X540_VF: 133 hw->mac.type = ixgbe_mac_X540_vf; 134 break; 135 case IXGBE_DEV_ID_X540T: 136 case IXGBE_DEV_ID_X540T1: 137 hw->mac.type = ixgbe_mac_X540; 138 break; 139 default: 140 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 141 break; 142 } 143 } else { 144 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 145 } 146 147 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n", 148 hw->mac.type, ret_val); 149 return ret_val; 150 } 151 152 /** 153 * ixgbe_init_hw - Initialize the hardware 154 * @hw: pointer to hardware structure 155 * 156 * Initialize the hardware by resetting and then starting the hardware 157 **/ 158 s32 ixgbe_init_hw(struct ixgbe_hw *hw) 159 { 160 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), 161 IXGBE_NOT_IMPLEMENTED); 162 } 163 164 /** 165 * ixgbe_reset_hw - Performs a hardware reset 166 * @hw: pointer to hardware structure 167 * 168 * Resets the hardware by resetting the transmit and receive units, masks and 169 * clears all interrupts, performs a PHY reset, and performs a MAC reset 170 **/ 171 s32 ixgbe_reset_hw(struct ixgbe_hw *hw) 172 { 173 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), 174 IXGBE_NOT_IMPLEMENTED); 175 } 176 177 /** 178 * ixgbe_start_hw - Prepares hardware for Rx/Tx 179 * @hw: pointer to hardware structure 180 * 181 * Starts the hardware by filling the bus info structure and media type, 182 * clears all on chip counters, initializes receive address registers, 183 * multicast table, VLAN filter table, calls routine to setup link and 184 * flow control settings, and leaves transmit and receive units disabled 185 * and uninitialized. 186 **/ 187 s32 ixgbe_start_hw(struct ixgbe_hw *hw) 188 { 189 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), 190 IXGBE_NOT_IMPLEMENTED); 191 } 192 193 /** 194 * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering, 195 * which is disabled by default in ixgbe_start_hw(); 196 * 197 * @hw: pointer to hardware structure 198 * 199 * Enable relaxed ordering; 200 **/ 201 void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw) 202 { 203 if (hw->mac.ops.enable_relaxed_ordering) 204 hw->mac.ops.enable_relaxed_ordering(hw); 205 } 206 207 /** 208 * ixgbe_clear_hw_cntrs - Clear hardware counters 209 * @hw: pointer to hardware structure 210 * 211 * Clears all hardware statistics counters by reading them from the hardware 212 * Statistics counters are clear on read. 213 **/ 214 s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) 215 { 216 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw), 217 IXGBE_NOT_IMPLEMENTED); 218 } 219 220 /** 221 * ixgbe_get_media_type - Get media type 222 * @hw: pointer to hardware structure 223 * 224 * Returns the media type (fiber, copper, backplane) 225 **/ 226 enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw) 227 { 228 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw), 229 ixgbe_media_type_unknown); 230 } 231 232 /** 233 * ixgbe_get_mac_addr - Get MAC address 234 * @hw: pointer to hardware structure 235 * @mac_addr: Adapter MAC address 236 * 237 * Reads the adapter's MAC address from the first Receive Address Register 238 * (RAR0) A reset of the adapter must have been performed prior to calling 239 * this function in order for the MAC address to have been loaded from the 240 * EEPROM into RAR0 241 **/ 242 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) 243 { 244 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr, 245 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED); 246 } 247 248 /** 249 * ixgbe_get_san_mac_addr - Get SAN MAC address 250 * @hw: pointer to hardware structure 251 * @san_mac_addr: SAN MAC address 252 * 253 * Reads the SAN MAC address from the EEPROM, if it's available. This is 254 * per-port, so set_lan_id() must be called before reading the addresses. 255 **/ 256 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 257 { 258 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr, 259 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 260 } 261 262 /** 263 * ixgbe_set_san_mac_addr - Write a SAN MAC address 264 * @hw: pointer to hardware structure 265 * @san_mac_addr: SAN MAC address 266 * 267 * Writes A SAN MAC address to the EEPROM. 268 **/ 269 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 270 { 271 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr, 272 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 273 } 274 275 /** 276 * ixgbe_get_device_caps - Get additional device capabilities 277 * @hw: pointer to hardware structure 278 * @device_caps: the EEPROM word for device capabilities 279 * 280 * Reads the extra device capabilities from the EEPROM 281 **/ 282 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps) 283 { 284 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps, 285 (hw, device_caps), IXGBE_NOT_IMPLEMENTED); 286 } 287 288 /** 289 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM 290 * @hw: pointer to hardware structure 291 * @wwnn_prefix: the alternative WWNN prefix 292 * @wwpn_prefix: the alternative WWPN prefix 293 * 294 * This function will read the EEPROM from the alternative SAN MAC address 295 * block to check the support for the alternative WWNN/WWPN prefix support. 296 **/ 297 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, 298 u16 *wwpn_prefix) 299 { 300 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix, 301 (hw, wwnn_prefix, wwpn_prefix), 302 IXGBE_NOT_IMPLEMENTED); 303 } 304 305 /** 306 * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM 307 * @hw: pointer to hardware structure 308 * @bs: the fcoe boot status 309 * 310 * This function will read the FCOE boot status from the iSCSI FCOE block 311 **/ 312 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs) 313 { 314 return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status, 315 (hw, bs), 316 IXGBE_NOT_IMPLEMENTED); 317 } 318 319 /** 320 * ixgbe_get_bus_info - Set PCI bus info 321 * @hw: pointer to hardware structure 322 * 323 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 324 **/ 325 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw) 326 { 327 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), 328 IXGBE_NOT_IMPLEMENTED); 329 } 330 331 /** 332 * ixgbe_get_num_of_tx_queues - Get Tx queues 333 * @hw: pointer to hardware structure 334 * 335 * Returns the number of transmit queues for the given adapter. 336 **/ 337 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw) 338 { 339 return hw->mac.max_tx_queues; 340 } 341 342 /** 343 * ixgbe_get_num_of_rx_queues - Get Rx queues 344 * @hw: pointer to hardware structure 345 * 346 * Returns the number of receive queues for the given adapter. 347 **/ 348 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw) 349 { 350 return hw->mac.max_rx_queues; 351 } 352 353 /** 354 * ixgbe_stop_adapter - Disable Rx/Tx units 355 * @hw: pointer to hardware structure 356 * 357 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 358 * disables transmit and receive units. The adapter_stopped flag is used by 359 * the shared code and drivers to determine if the adapter is in a stopped 360 * state and should not touch the hardware. 361 **/ 362 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw) 363 { 364 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), 365 IXGBE_NOT_IMPLEMENTED); 366 } 367 368 /** 369 * ixgbe_read_pba_string - Reads part number string from EEPROM 370 * @hw: pointer to hardware structure 371 * @pba_num: stores the part number string from the EEPROM 372 * @pba_num_size: part number string buffer length 373 * 374 * Reads the part number string from the EEPROM. 375 **/ 376 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size) 377 { 378 return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size); 379 } 380 381 /** 382 * ixgbe_read_pba_num - Reads part number from EEPROM 383 * @hw: pointer to hardware structure 384 * @pba_num: stores the part number from the EEPROM 385 * 386 * Reads the part number from the EEPROM. 387 **/ 388 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num) 389 { 390 return ixgbe_read_pba_num_generic(hw, pba_num); 391 } 392 393 /** 394 * ixgbe_identify_phy - Get PHY type 395 * @hw: pointer to hardware structure 396 * 397 * Determines the physical layer module found on the current adapter. 398 **/ 399 s32 ixgbe_identify_phy(struct ixgbe_hw *hw) 400 { 401 s32 status = IXGBE_SUCCESS; 402 403 if (hw->phy.type == ixgbe_phy_unknown) { 404 status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw), 405 IXGBE_NOT_IMPLEMENTED); 406 } 407 408 return status; 409 } 410 411 /** 412 * ixgbe_reset_phy - Perform a PHY reset 413 * @hw: pointer to hardware structure 414 **/ 415 s32 ixgbe_reset_phy(struct ixgbe_hw *hw) 416 { 417 s32 status = IXGBE_SUCCESS; 418 419 if (hw->phy.type == ixgbe_phy_unknown) { 420 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) 421 status = IXGBE_ERR_PHY; 422 } 423 424 if (status == IXGBE_SUCCESS) { 425 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), 426 IXGBE_NOT_IMPLEMENTED); 427 } 428 return status; 429 } 430 431 /** 432 * ixgbe_get_phy_firmware_version - 433 * @hw: pointer to hardware structure 434 * @firmware_version: pointer to firmware version 435 **/ 436 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version) 437 { 438 s32 status = IXGBE_SUCCESS; 439 440 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version, 441 (hw, firmware_version), 442 IXGBE_NOT_IMPLEMENTED); 443 return status; 444 } 445 446 /** 447 * ixgbe_read_phy_reg - Read PHY register 448 * @hw: pointer to hardware structure 449 * @reg_addr: 32 bit address of PHY register to read 450 * @phy_data: Pointer to read data from PHY register 451 * 452 * Reads a value from a specified PHY register 453 **/ 454 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 455 u16 *phy_data) 456 { 457 if (hw->phy.id == 0) 458 ixgbe_identify_phy(hw); 459 460 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, 461 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 462 } 463 464 /** 465 * ixgbe_write_phy_reg - Write PHY register 466 * @hw: pointer to hardware structure 467 * @reg_addr: 32 bit PHY register to write 468 * @phy_data: Data to write to the PHY register 469 * 470 * Writes a value to specified PHY register 471 **/ 472 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 473 u16 phy_data) 474 { 475 if (hw->phy.id == 0) 476 ixgbe_identify_phy(hw); 477 478 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, 479 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 480 } 481 482 /** 483 * ixgbe_setup_phy_link - Restart PHY autoneg 484 * @hw: pointer to hardware structure 485 * 486 * Restart autonegotiation and PHY and waits for completion. 487 **/ 488 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw) 489 { 490 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), 491 IXGBE_NOT_IMPLEMENTED); 492 } 493 494 /** 495 * ixgbe_check_phy_link - Determine link and speed status 496 * @hw: pointer to hardware structure 497 * 498 * Reads a PHY register to determine if link is up and the current speed for 499 * the PHY. 500 **/ 501 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 502 bool *link_up) 503 { 504 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed, 505 link_up), IXGBE_NOT_IMPLEMENTED); 506 } 507 508 /** 509 * ixgbe_setup_phy_link_speed - Set auto advertise 510 * @hw: pointer to hardware structure 511 * @speed: new link speed 512 * @autoneg: TRUE if autonegotiation enabled 513 * 514 * Sets the auto advertised capabilities 515 **/ 516 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, 517 bool autoneg, 518 bool autoneg_wait_to_complete) 519 { 520 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, 521 autoneg, autoneg_wait_to_complete), 522 IXGBE_NOT_IMPLEMENTED); 523 } 524 525 /** 526 * ixgbe_check_link - Get link and speed status 527 * @hw: pointer to hardware structure 528 * 529 * Reads the links register to determine if link is up and the current speed 530 **/ 531 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 532 bool *link_up, bool link_up_wait_to_complete) 533 { 534 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed, 535 link_up, link_up_wait_to_complete), 536 IXGBE_NOT_IMPLEMENTED); 537 } 538 539 /** 540 * ixgbe_disable_tx_laser - Disable Tx laser 541 * @hw: pointer to hardware structure 542 * 543 * If the driver needs to disable the laser on SFI optics. 544 **/ 545 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw) 546 { 547 if (hw->mac.ops.disable_tx_laser) 548 hw->mac.ops.disable_tx_laser(hw); 549 } 550 551 /** 552 * ixgbe_enable_tx_laser - Enable Tx laser 553 * @hw: pointer to hardware structure 554 * 555 * If the driver needs to enable the laser on SFI optics. 556 **/ 557 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw) 558 { 559 if (hw->mac.ops.enable_tx_laser) 560 hw->mac.ops.enable_tx_laser(hw); 561 } 562 563 /** 564 * ixgbe_flap_tx_laser - flap Tx laser to start autotry process 565 * @hw: pointer to hardware structure 566 * 567 * When the driver changes the link speeds that it can support then 568 * flap the tx laser to alert the link partner to start autotry 569 * process on its end. 570 **/ 571 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw) 572 { 573 if (hw->mac.ops.flap_tx_laser) 574 hw->mac.ops.flap_tx_laser(hw); 575 } 576 577 /** 578 * ixgbe_setup_link - Set link speed 579 * @hw: pointer to hardware structure 580 * @speed: new link speed 581 * @autoneg: TRUE if autonegotiation enabled 582 * 583 * Configures link settings. Restarts the link. 584 * Performs autonegotiation if needed. 585 **/ 586 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 587 bool autoneg, 588 bool autoneg_wait_to_complete) 589 { 590 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed, 591 autoneg, autoneg_wait_to_complete), 592 IXGBE_NOT_IMPLEMENTED); 593 } 594 595 /** 596 * ixgbe_get_link_capabilities - Returns link capabilities 597 * @hw: pointer to hardware structure 598 * 599 * Determines the link capabilities of the current configuration. 600 **/ 601 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 602 bool *autoneg) 603 { 604 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw, 605 speed, autoneg), IXGBE_NOT_IMPLEMENTED); 606 } 607 608 /** 609 * ixgbe_led_on - Turn on LEDs 610 * @hw: pointer to hardware structure 611 * @index: led number to turn on 612 * 613 * Turns on the software controllable LEDs. 614 **/ 615 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) 616 { 617 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index), 618 IXGBE_NOT_IMPLEMENTED); 619 } 620 621 /** 622 * ixgbe_led_off - Turn off LEDs 623 * @hw: pointer to hardware structure 624 * @index: led number to turn off 625 * 626 * Turns off the software controllable LEDs. 627 **/ 628 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) 629 { 630 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index), 631 IXGBE_NOT_IMPLEMENTED); 632 } 633 634 /** 635 * ixgbe_blink_led_start - Blink LEDs 636 * @hw: pointer to hardware structure 637 * @index: led number to blink 638 * 639 * Blink LED based on index. 640 **/ 641 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index) 642 { 643 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index), 644 IXGBE_NOT_IMPLEMENTED); 645 } 646 647 /** 648 * ixgbe_blink_led_stop - Stop blinking LEDs 649 * @hw: pointer to hardware structure 650 * 651 * Stop blinking LED based on index. 652 **/ 653 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index) 654 { 655 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index), 656 IXGBE_NOT_IMPLEMENTED); 657 } 658 659 /** 660 * ixgbe_init_eeprom_params - Initialize EEPROM parameters 661 * @hw: pointer to hardware structure 662 * 663 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 664 * ixgbe_hw struct in order to set up EEPROM access. 665 **/ 666 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw) 667 { 668 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw), 669 IXGBE_NOT_IMPLEMENTED); 670 } 671 672 673 /** 674 * ixgbe_write_eeprom - Write word to EEPROM 675 * @hw: pointer to hardware structure 676 * @offset: offset within the EEPROM to be written to 677 * @data: 16 bit word to be written to the EEPROM 678 * 679 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not 680 * called after this function, the EEPROM will most likely contain an 681 * invalid checksum. 682 **/ 683 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data) 684 { 685 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data), 686 IXGBE_NOT_IMPLEMENTED); 687 } 688 689 /** 690 * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM 691 * @hw: pointer to hardware structure 692 * @offset: offset within the EEPROM to be written to 693 * @data: 16 bit word(s) to be written to the EEPROM 694 * @words: number of words 695 * 696 * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not 697 * called after this function, the EEPROM will most likely contain an 698 * invalid checksum. 699 **/ 700 s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words, 701 u16 *data) 702 { 703 return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer, 704 (hw, offset, words, data), 705 IXGBE_NOT_IMPLEMENTED); 706 } 707 708 /** 709 * ixgbe_read_eeprom - Read word from EEPROM 710 * @hw: pointer to hardware structure 711 * @offset: offset within the EEPROM to be read 712 * @data: read 16 bit value from EEPROM 713 * 714 * Reads 16 bit value from EEPROM 715 **/ 716 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) 717 { 718 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data), 719 IXGBE_NOT_IMPLEMENTED); 720 } 721 722 /** 723 * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM 724 * @hw: pointer to hardware structure 725 * @offset: offset within the EEPROM to be read 726 * @data: read 16 bit word(s) from EEPROM 727 * @words: number of words 728 * 729 * Reads 16 bit word(s) from EEPROM 730 **/ 731 s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, 732 u16 words, u16 *data) 733 { 734 return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer, 735 (hw, offset, words, data), 736 IXGBE_NOT_IMPLEMENTED); 737 } 738 739 /** 740 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum 741 * @hw: pointer to hardware structure 742 * @checksum_val: calculated checksum 743 * 744 * Performs checksum calculation and validates the EEPROM checksum 745 **/ 746 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) 747 { 748 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum, 749 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED); 750 } 751 752 /** 753 * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum 754 * @hw: pointer to hardware structure 755 **/ 756 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw) 757 { 758 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw), 759 IXGBE_NOT_IMPLEMENTED); 760 } 761 762 /** 763 * ixgbe_insert_mac_addr - Find a RAR for this mac address 764 * @hw: pointer to hardware structure 765 * @addr: Address to put into receive address register 766 * @vmdq: VMDq pool to assign 767 * 768 * Puts an ethernet address into a receive address register, or 769 * finds the rar that it is aleady in; adds to the pool list 770 **/ 771 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 772 { 773 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr, 774 (hw, addr, vmdq), 775 IXGBE_NOT_IMPLEMENTED); 776 } 777 778 /** 779 * ixgbe_set_rar - Set Rx address register 780 * @hw: pointer to hardware structure 781 * @index: Receive address register to write 782 * @addr: Address to put into receive address register 783 * @vmdq: VMDq "set" 784 * @enable_addr: set flag that address is active 785 * 786 * Puts an ethernet address into a receive address register. 787 **/ 788 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 789 u32 enable_addr) 790 { 791 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq, 792 enable_addr), IXGBE_NOT_IMPLEMENTED); 793 } 794 795 /** 796 * ixgbe_clear_rar - Clear Rx address register 797 * @hw: pointer to hardware structure 798 * @index: Receive address register to write 799 * 800 * Puts an ethernet address into a receive address register. 801 **/ 802 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index) 803 { 804 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index), 805 IXGBE_NOT_IMPLEMENTED); 806 } 807 808 /** 809 * ixgbe_set_vmdq - Associate a VMDq index with a receive address 810 * @hw: pointer to hardware structure 811 * @rar: receive address register index to associate with VMDq index 812 * @vmdq: VMDq set or pool index 813 **/ 814 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 815 { 816 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq), 817 IXGBE_NOT_IMPLEMENTED); 818 819 } 820 821 /** 822 * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address 823 * @hw: pointer to hardware structure 824 * @vmdq: VMDq default pool index 825 **/ 826 s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq) 827 { 828 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac, 829 (hw, vmdq), IXGBE_NOT_IMPLEMENTED); 830 } 831 832 /** 833 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address 834 * @hw: pointer to hardware structure 835 * @rar: receive address register index to disassociate with VMDq index 836 * @vmdq: VMDq set or pool index 837 **/ 838 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 839 { 840 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq), 841 IXGBE_NOT_IMPLEMENTED); 842 } 843 844 /** 845 * ixgbe_init_rx_addrs - Initializes receive address filters. 846 * @hw: pointer to hardware structure 847 * 848 * Places the MAC address in receive address register 0 and clears the rest 849 * of the receive address registers. Clears the multicast table. Assumes 850 * the receiver is in reset when the routine is called. 851 **/ 852 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) 853 { 854 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw), 855 IXGBE_NOT_IMPLEMENTED); 856 } 857 858 /** 859 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries. 860 * @hw: pointer to hardware structure 861 **/ 862 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw) 863 { 864 return hw->mac.num_rar_entries; 865 } 866 867 /** 868 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses 869 * @hw: pointer to hardware structure 870 * @addr_list: the list of new multicast addresses 871 * @addr_count: number of addresses 872 * @func: iterator function to walk the multicast address list 873 * 874 * The given list replaces any existing list. Clears the secondary addrs from 875 * receive address registers. Uses unused receive address registers for the 876 * first secondary addresses, and falls back to promiscuous mode as needed. 877 **/ 878 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, 879 u32 addr_count, ixgbe_mc_addr_itr func) 880 { 881 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw, 882 addr_list, addr_count, func), 883 IXGBE_NOT_IMPLEMENTED); 884 } 885 886 /** 887 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses 888 * @hw: pointer to hardware structure 889 * @mc_addr_list: the list of new multicast addresses 890 * @mc_addr_count: number of addresses 891 * @func: iterator function to walk the multicast address list 892 * 893 * The given list replaces any existing list. Clears the MC addrs from receive 894 * address registers and the multicast table. Uses unused receive address 895 * registers for the first multicast addresses, and hashes the rest into the 896 * multicast table. 897 **/ 898 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, 899 u32 mc_addr_count, ixgbe_mc_addr_itr func, 900 bool clear) 901 { 902 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw, 903 mc_addr_list, mc_addr_count, func, clear), 904 IXGBE_NOT_IMPLEMENTED); 905 } 906 907 /** 908 * ixgbe_enable_mc - Enable multicast address in RAR 909 * @hw: pointer to hardware structure 910 * 911 * Enables multicast address in RAR and the use of the multicast hash table. 912 **/ 913 s32 ixgbe_enable_mc(struct ixgbe_hw *hw) 914 { 915 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), 916 IXGBE_NOT_IMPLEMENTED); 917 } 918 919 /** 920 * ixgbe_disable_mc - Disable multicast address in RAR 921 * @hw: pointer to hardware structure 922 * 923 * Disables multicast address in RAR and the use of the multicast hash table. 924 **/ 925 s32 ixgbe_disable_mc(struct ixgbe_hw *hw) 926 { 927 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw), 928 IXGBE_NOT_IMPLEMENTED); 929 } 930 931 /** 932 * ixgbe_clear_vfta - Clear VLAN filter table 933 * @hw: pointer to hardware structure 934 * 935 * Clears the VLAN filer table, and the VMDq index associated with the filter 936 **/ 937 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw) 938 { 939 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw), 940 IXGBE_NOT_IMPLEMENTED); 941 } 942 943 /** 944 * ixgbe_set_vfta - Set VLAN filter table 945 * @hw: pointer to hardware structure 946 * @vlan: VLAN id to write to VLAN filter 947 * @vind: VMDq output index that maps queue to VLAN id in VFTA 948 * @vlan_on: boolean flag to turn on/off VLAN in VFTA 949 * 950 * Turn on/off specified VLAN in the VLAN filter table. 951 **/ 952 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on) 953 { 954 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind, 955 vlan_on), IXGBE_NOT_IMPLEMENTED); 956 } 957 958 /** 959 * ixgbe_set_vlvf - Set VLAN Pool Filter 960 * @hw: pointer to hardware structure 961 * @vlan: VLAN id to write to VLAN filter 962 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 963 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 964 * @vfta_changed: pointer to boolean flag which indicates whether VFTA 965 * should be changed 966 * 967 * Turn on/off specified bit in VLVF table. 968 **/ 969 s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 970 bool *vfta_changed) 971 { 972 return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind, 973 vlan_on, vfta_changed), IXGBE_NOT_IMPLEMENTED); 974 } 975 976 /** 977 * ixgbe_fc_enable - Enable flow control 978 * @hw: pointer to hardware structure 979 * 980 * Configures the flow control settings based on SW configuration. 981 **/ 982 s32 ixgbe_fc_enable(struct ixgbe_hw *hw) 983 { 984 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw), 985 IXGBE_NOT_IMPLEMENTED); 986 } 987 988 /** 989 * ixgbe_set_fw_drv_ver - Try to send the driver version number FW 990 * @hw: pointer to hardware structure 991 * @maj: driver major number to be sent to firmware 992 * @min: driver minor number to be sent to firmware 993 * @build: driver build number to be sent to firmware 994 * @ver: driver version number to be sent to firmware 995 **/ 996 s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build, 997 u8 ver) 998 { 999 return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min, 1000 build, ver), IXGBE_NOT_IMPLEMENTED); 1001 } 1002 1003 1004 /** 1005 * ixgbe_read_analog_reg8 - Reads 8 bit analog register 1006 * @hw: pointer to hardware structure 1007 * @reg: analog register to read 1008 * @val: read value 1009 * 1010 * Performs write operation to analog register specified. 1011 **/ 1012 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) 1013 { 1014 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg, 1015 val), IXGBE_NOT_IMPLEMENTED); 1016 } 1017 1018 /** 1019 * ixgbe_write_analog_reg8 - Writes 8 bit analog register 1020 * @hw: pointer to hardware structure 1021 * @reg: analog register to write 1022 * @val: value to write 1023 * 1024 * Performs write operation to Atlas analog register specified. 1025 **/ 1026 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) 1027 { 1028 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg, 1029 val), IXGBE_NOT_IMPLEMENTED); 1030 } 1031 1032 /** 1033 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays. 1034 * @hw: pointer to hardware structure 1035 * 1036 * Initializes the Unicast Table Arrays to zero on device load. This 1037 * is part of the Rx init addr execution path. 1038 **/ 1039 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw) 1040 { 1041 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw), 1042 IXGBE_NOT_IMPLEMENTED); 1043 } 1044 1045 /** 1046 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address 1047 * @hw: pointer to hardware structure 1048 * @byte_offset: byte offset to read 1049 * @data: value read 1050 * 1051 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1052 **/ 1053 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1054 u8 *data) 1055 { 1056 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset, 1057 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1058 } 1059 1060 /** 1061 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C 1062 * @hw: pointer to hardware structure 1063 * @byte_offset: byte offset to write 1064 * @data: value to write 1065 * 1066 * Performs byte write operation to SFP module's EEPROM over I2C interface 1067 * at a specified device address. 1068 **/ 1069 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1070 u8 data) 1071 { 1072 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset, 1073 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1074 } 1075 1076 /** 1077 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface 1078 * @hw: pointer to hardware structure 1079 * @byte_offset: EEPROM byte offset to write 1080 * @eeprom_data: value to write 1081 * 1082 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1083 **/ 1084 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, 1085 u8 byte_offset, u8 eeprom_data) 1086 { 1087 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom, 1088 (hw, byte_offset, eeprom_data), 1089 IXGBE_NOT_IMPLEMENTED); 1090 } 1091 1092 /** 1093 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface 1094 * @hw: pointer to hardware structure 1095 * @byte_offset: EEPROM byte offset to read 1096 * @eeprom_data: value read 1097 * 1098 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1099 **/ 1100 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data) 1101 { 1102 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom, 1103 (hw, byte_offset, eeprom_data), 1104 IXGBE_NOT_IMPLEMENTED); 1105 } 1106 1107 /** 1108 * ixgbe_get_supported_physical_layer - Returns physical layer type 1109 * @hw: pointer to hardware structure 1110 * 1111 * Determines physical layer capabilities of the current configuration. 1112 **/ 1113 u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw) 1114 { 1115 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer, 1116 (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN); 1117 } 1118 1119 /** 1120 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics 1121 * @hw: pointer to hardware structure 1122 * @regval: bitfield to write to the Rx DMA register 1123 * 1124 * Enables the Rx DMA unit of the device. 1125 **/ 1126 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) 1127 { 1128 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma, 1129 (hw, regval), IXGBE_NOT_IMPLEMENTED); 1130 } 1131 1132 /** 1133 * ixgbe_disable_sec_rx_path - Stops the receive data path 1134 * @hw: pointer to hardware structure 1135 * 1136 * Stops the receive data path. 1137 **/ 1138 s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw) 1139 { 1140 return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path, 1141 (hw), IXGBE_NOT_IMPLEMENTED); 1142 } 1143 1144 /** 1145 * ixgbe_enable_sec_rx_path - Enables the receive data path 1146 * @hw: pointer to hardware structure 1147 * 1148 * Enables the receive data path. 1149 **/ 1150 s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw) 1151 { 1152 return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path, 1153 (hw), IXGBE_NOT_IMPLEMENTED); 1154 } 1155 1156 /** 1157 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore 1158 * @hw: pointer to hardware structure 1159 * @mask: Mask to specify which semaphore to acquire 1160 * 1161 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified 1162 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1163 **/ 1164 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask) 1165 { 1166 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, 1167 (hw, mask), IXGBE_NOT_IMPLEMENTED); 1168 } 1169 1170 /** 1171 * ixgbe_release_swfw_semaphore - Release SWFW semaphore 1172 * @hw: pointer to hardware structure 1173 * @mask: Mask to specify which semaphore to release 1174 * 1175 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified 1176 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1177 **/ 1178 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask) 1179 { 1180 if (hw->mac.ops.release_swfw_sync) 1181 hw->mac.ops.release_swfw_sync(hw, mask); 1182 } 1183 1184